Index: include/llvm/IR/IntrinsicsPowerPC.td =================================================================== --- include/llvm/IR/IntrinsicsPowerPC.td +++ include/llvm/IR/IntrinsicsPowerPC.td @@ -613,6 +613,9 @@ def int_ppc_altivec_vbpermq : GCCBuiltin<"__builtin_altivec_vbpermq">, Intrinsic<[llvm_v2i64_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>; + def int_ppc_altivec_vbpermd : GCCBuiltin<"__builtin_altivec_vbpermd">, + Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], + [IntrNoMem]>; } def int_ppc_altivec_vexptefp : PowerPC_Vec_FF_Intrinsic<"vexptefp">; Index: lib/Target/PowerPC/PPCInstrAltivec.td =================================================================== --- lib/Target/PowerPC/PPCInstrAltivec.td +++ lib/Target/PowerPC/PPCInstrAltivec.td @@ -1213,3 +1213,29 @@ int_ppc_altivec_crypto_vncipherlast, v2i64>; def VSBOX : VXBX_Int_Ty<1480, "vsbox", int_ppc_altivec_crypto_vsbox, v2i64>; } // HasP8Crypto + +def HasP9Altivec : Predicate<"PPCSubTarget->hasP9Altivec()">; +let Predicates = [HasP9Altivec] in { + +def VBPERMD : VX1_Int_Ty<1484, "vbpermd", int_ppc_altivec_vbpermd, v2i64>; + +// Vector Count Leading/Trailing Zero LSB, dest register is gpr +class VCZLSB xo, bits<5> eo, string opc> + : VXForm_EO; + +def VCLZLSBB : VCZLSB<1538, 0, "vclzlsbb">; +def VCTZLSBB : VCZLSB<1538, 1, "vctzlsbb">; + +// Vector Count Trailing Zeros +class VCTZ xo, bits<5> eo, string opc, ValueType Ty> + : VXForm_EO; + +def VCTZB : VCTZ<1538, 28, "vctzb", v16i8>; +def VCTZH : VCTZ<1538, 29, "vctzh", v8i16>; +def VCTZW : VCTZ<1538, 30, "vctzw", v4i32>; +def VCTZD : VCTZ<1538, 31, "vctzd", v2i64>; +} // end HasP9Altivec Index: lib/Target/PowerPC/PPCInstrFormats.td =================================================================== --- lib/Target/PowerPC/PPCInstrFormats.td +++ lib/Target/PowerPC/PPCInstrFormats.td @@ -1571,6 +1571,21 @@ let Inst{21-31} = xo; } +/// VXForm_EO - [PO, VRT, EO, VRB, XO] +class VXForm_EO xo, bits<5> eo, dag OOL, dag IOL, string asmstr, + InstrItinClass itin, list pattern> + : I<4, OOL, IOL, asmstr, itin> { + bits<5> RD; + bits<5> VB; + + let Pattern = pattern; + + let Inst{6-10} = RD; + let Inst{11-15} = eo; + let Inst{16-20} = VB; + let Inst{21-31} = xo; +} + /// VXForm_CR - VX crypto instructions with "VRT, VRA, ST, SIX" class VXForm_CR xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list pattern> Index: lib/Target/PowerPC/PPCSubtarget.h =================================================================== --- lib/Target/PowerPC/PPCSubtarget.h +++ lib/Target/PowerPC/PPCSubtarget.h @@ -92,6 +92,7 @@ bool HasP8Vector; bool HasP8Altivec; bool HasP8Crypto; + bool HasP9Altivec; bool HasFCPSGN; bool HasFSQRT; bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES; @@ -229,6 +230,7 @@ bool hasP8Vector() const { return HasP8Vector; } bool hasP8Altivec() const { return HasP8Altivec; } bool hasP8Crypto() const { return HasP8Crypto; } + bool hasP9Altivec() const { return HasP9Altivec; } bool hasMFOCRF() const { return HasMFOCRF; } bool hasISEL() const { return HasISEL; } bool hasPOPCNTD() const { return HasPOPCNTD; } Index: lib/Target/PowerPC/PPCSubtarget.cpp =================================================================== --- lib/Target/PowerPC/PPCSubtarget.cpp +++ lib/Target/PowerPC/PPCSubtarget.cpp @@ -70,6 +70,7 @@ HasP8Vector = false; HasP8Altivec = false; HasP8Crypto = false; + HasP9Altivec = false; HasFCPSGN = false; HasFSQRT = false; HasFRE = false; Index: test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt =================================================================== --- test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt +++ test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt @@ -642,6 +642,9 @@ # CHECK: vbpermq 2, 5, 17 0x10 0x45 0x8d 0x4c +# CHECK: vbpermd 2, 5, 17 +0x10 0x45 0x8d 0xcc + # CHECK: vclzb 2, 3 0x10 0x40 0x1f 0x02 @@ -654,6 +657,24 @@ # CHECK: vclzd 2, 3 0x10 0x40 0x1f 0xc2 +# CHECK: vclzlsbb 2, 3 +0x10 0x40 0x1e 0x02 + +# CHECK: vctzlsbb 2, 3 +0x10 0x41 0x1e 0x02 + +# CHECK: vctzb 2, 3 +0x10 0x5c 0x1e 0x02 + +# CHECK: vctzh 2, 3 +0x10 0x5d 0x1e 0x02 + +# CHECK: vctzw 2, 3 +0x10 0x5e 0x1e 0x02 + +# CHECK: vctzd 2, 3 +0x10 0x5f 0x1e 0x02 + # CHECK: vpopcntb 2, 3 0x10 0x40 0x1f 0x03 Index: test/MC/PowerPC/ppc64-encoding-vmx.s =================================================================== --- test/MC/PowerPC/ppc64-encoding-vmx.s +++ test/MC/PowerPC/ppc64-encoding-vmx.s @@ -698,6 +698,9 @@ # CHECK-BE: vbpermq 2, 5, 17 # encoding: [0x10,0x45,0x8d,0x4c] # CHECK-LE: vbpermq 2, 5, 17 # encoding: [0x4c,0x8d,0x45,0x10] vbpermq 2, 5, 17 +# CHECK-BE: vbpermd 2, 5, 17 # encoding: [0x10,0x45,0x8d,0xcc] +# CHECK-LE: vbpermd 2, 5, 17 # encoding: [0xcc,0x8d,0x45,0x10] + vbpermd 2, 5, 17 # Vector count leading zero instructions # CHECK-BE: vclzb 2, 3 # encoding: [0x10,0x40,0x1f,0x02] @@ -716,6 +719,29 @@ # CHECK-LE: vclzd 2, 3 # encoding: [0xc2,0x1f,0x40,0x10] vclzd 2, 3 +# Vector count trailing zero instructions +# CHECK-BE: vctzb 2, 3 # encoding: [0x10,0x5c,0x1e,0x02] +# CHECK-LE: vctzb 2, 3 # encoding: [0x02,0x1e,0x5c,0x10] + vctzb 2, 3 +# CHECK-BE: vctzh 2, 3 # encoding: [0x10,0x5d,0x1e,0x02] +# CHECK-LE: vctzh 2, 3 # encoding: [0x02,0x1e,0x5d,0x10] + vctzh 2, 3 +# CHECK-BE: vctzw 2, 3 # encoding: [0x10,0x5e,0x1e,0x02] +# CHECK-LE: vctzw 2, 3 # encoding: [0x02,0x1e,0x5e,0x10] + vctzw 2, 3 +# CHECK-BE: vctzd 2, 3 # encoding: [0x10,0x5f,0x1e,0x02] +# CHECK-LE: vctzd 2, 3 # encoding: [0x02,0x1e,0x5f,0x10] + vctzd 2, 3 + +# LSB version of vector count leading/trailing zero instructions +# CHECK-BE: vclzlsbb 2, 3 # encoding: [0x10,0x40,0x1e,0x02] +# CHECK-LE: vclzlsbb 2, 3 # encoding: [0x02,0x1e,0x40,0x10] + vclzlsbb 2, 3 + +# CHECK-BE: vctzlsbb 2, 3 # encoding: [0x10,0x41,0x1e,0x02] +# CHECK-LE: vctzlsbb 2, 3 # encoding: [0x02,0x1e,0x41,0x10] + vctzlsbb 2, 3 + # Vector population count instructions # CHECK-BE: vpopcntb 2, 3 # encoding: [0x10,0x40,0x1f,0x03] # CHECK-LE: vpopcntb 2, 3 # encoding: [0x03,0x1f,0x40,0x10]