diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -1164,6 +1164,20 @@
     Known = KnownScl.trunc(BitWidth);
     break;
   }
+  case ISD::SPLAT_VECTOR_PARTS: {
+    unsigned NumSclBits = Op.getOperand(0).getScalarValueSizeInBits();
+    assert(NumSclBits * Op.getNumOperands() == BitWidth &&
+           "Expected SPLAT_VECTOR_PARTS scalars to cover element width");
+    for (auto [I, Scl] : enumerate(Op->ops())) {
+      APInt DemandedSclBits =
+          DemandedBits.extractBits(NumSclBits, NumSclBits * I);
+      KnownBits KnownScl;
+      if (SimplifyDemandedBits(Scl, DemandedSclBits, KnownScl, TLO, Depth + 1))
+        return true;
+      Known.insertBits(KnownScl, NumSclBits * I);
+    }
+    break;
+  }
   case ISD::LOAD: {
     auto *LD = cast<LoadSDNode>(Op);
     if (getTargetConstantFromLoad(LD)) {
diff --git a/llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll
@@ -634,27 +634,11 @@
 }
 
 define <vscale x 1 x i16> @vnsrl_wx_i64_nxv1i16(<vscale x 1 x i32> %va, i64 %b) {
-; RV32-LABEL: vnsrl_wx_i64_nxv1i16:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
-; RV32-NEXT:    vlse64.v v9, (a0), zero
-; RV32-NEXT:    vnsrl.wi v9, v9, 0
-; RV32-NEXT:    vsrl.vv v8, v8, v9
-; RV32-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
-; RV32-NEXT:    vnsrl.wi v8, v8, 0
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vnsrl_wx_i64_nxv1i16:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
-; RV64-NEXT:    vnsrl.wx v8, v8, a0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vnsrl_wx_i64_nxv1i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
+; CHECK-NEXT:    vnsrl.wx v8, v8, a0
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
   %vb = trunc <vscale x 1 x i64> %splat to <vscale x 1 x i32>
@@ -664,29 +648,11 @@
 }
 
 define <vscale x 1 x i8> @vnsrl_wx_i64_nxv1i8(<vscale x 1 x i16> %va, i64 %b) {
-; RV32-LABEL: vnsrl_wx_i64_nxv1i8:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
-; RV32-NEXT:    vlse64.v v9, (a0), zero
-; RV32-NEXT:    vnsrl.wi v9, v9, 0
-; RV32-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
-; RV32-NEXT:    vnsrl.wi v9, v9, 0
-; RV32-NEXT:    vsrl.vv v8, v8, v9
-; RV32-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
-; RV32-NEXT:    vnsrl.wi v8, v8, 0
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vnsrl_wx_i64_nxv1i8:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma
-; RV64-NEXT:    vnsrl.wx v8, v8, a0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vnsrl_wx_i64_nxv1i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma
+; CHECK-NEXT:    vnsrl.wx v8, v8, a0
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
   %vb = trunc <vscale x 1 x i64> %splat to <vscale x 1 x i16>
@@ -694,3 +660,6 @@
   %y = trunc <vscale x 1 x i16> %x to <vscale x 1 x i8>
   ret <vscale x 1 x i8> %y
 }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; RV32: {{.*}}
+; RV64: {{.*}}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll
@@ -287,52 +287,22 @@
 }
 
 define <vscale x 4 x i32> @vwsll_vx_i64_nxv4i32(<vscale x 4 x i16> %a, i64 %b) {
-; CHECK-RV32-LABEL: vwsll_vx_i64_nxv4i32:
-; CHECK-RV32:       # %bb.0:
-; CHECK-RV32-NEXT:    addi sp, sp, -16
-; CHECK-RV32-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-RV32-NEXT:    sw a1, 12(sp)
-; CHECK-RV32-NEXT:    sw a0, 8(sp)
-; CHECK-RV32-NEXT:    addi a0, sp, 8
-; CHECK-RV32-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
-; CHECK-RV32-NEXT:    vlse64.v v12, (a0), zero
-; CHECK-RV32-NEXT:    vzext.vf2 v10, v8
-; CHECK-RV32-NEXT:    vnsrl.wi v8, v12, 0
-; CHECK-RV32-NEXT:    vsll.vv v8, v10, v8
-; CHECK-RV32-NEXT:    addi sp, sp, 16
-; CHECK-RV32-NEXT:    ret
-;
-; CHECK-RV64-LABEL: vwsll_vx_i64_nxv4i32:
-; CHECK-RV64:       # %bb.0:
-; CHECK-RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
-; CHECK-RV64-NEXT:    vmv.v.x v12, a0
-; CHECK-RV64-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
-; CHECK-RV64-NEXT:    vzext.vf2 v10, v8
-; CHECK-RV64-NEXT:    vnsrl.wi v8, v12, 0
-; CHECK-RV64-NEXT:    vsll.vv v8, v10, v8
-; CHECK-RV64-NEXT:    ret
-;
-; CHECK-ZVBB32-LABEL: vwsll_vx_i64_nxv4i32:
-; CHECK-ZVBB32:       # %bb.0:
-; CHECK-ZVBB32-NEXT:    addi sp, sp, -16
-; CHECK-ZVBB32-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-ZVBB32-NEXT:    sw a1, 12(sp)
-; CHECK-ZVBB32-NEXT:    sw a0, 8(sp)
-; CHECK-ZVBB32-NEXT:    addi a0, sp, 8
-; CHECK-ZVBB32-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
-; CHECK-ZVBB32-NEXT:    vlse64.v v12, (a0), zero
-; CHECK-ZVBB32-NEXT:    vzext.vf2 v10, v8
-; CHECK-ZVBB32-NEXT:    vnsrl.wi v8, v12, 0
-; CHECK-ZVBB32-NEXT:    vsll.vv v8, v10, v8
-; CHECK-ZVBB32-NEXT:    addi sp, sp, 16
-; CHECK-ZVBB32-NEXT:    ret
+; CHECK-LABEL: vwsll_vx_i64_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
+; CHECK-NEXT:    vmv.v.x v12, a0
+; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT:    vzext.vf2 v10, v8
+; CHECK-NEXT:    vnsrl.wi v8, v12, 0
+; CHECK-NEXT:    vsll.vv v8, v10, v8
+; CHECK-NEXT:    ret
 ;
-; CHECK-ZVBB64-LABEL: vwsll_vx_i64_nxv4i32:
-; CHECK-ZVBB64:       # %bb.0:
-; CHECK-ZVBB64-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
-; CHECK-ZVBB64-NEXT:    vwsll.vx v10, v8, a0
-; CHECK-ZVBB64-NEXT:    vmv2r.v v8, v10
-; CHECK-ZVBB64-NEXT:    ret
+; CHECK-ZVBB-LABEL: vwsll_vx_i64_nxv4i32:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
+; CHECK-ZVBB-NEXT:    vwsll.vx v10, v8, a0
+; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
+; CHECK-ZVBB-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
   %x = zext <vscale x 4 x i16> %a to <vscale x 4 x i32>
@@ -528,61 +498,25 @@
 }
 
 define <vscale x 8 x i16> @vwsll_vx_i64_nxv8i16(<vscale x 8 x i8> %a, i64 %b) {
-; CHECK-RV32-LABEL: vwsll_vx_i64_nxv8i16:
-; CHECK-RV32:       # %bb.0:
-; CHECK-RV32-NEXT:    addi sp, sp, -16
-; CHECK-RV32-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-RV32-NEXT:    sw a1, 12(sp)
-; CHECK-RV32-NEXT:    sw a0, 8(sp)
-; CHECK-RV32-NEXT:    addi a0, sp, 8
-; CHECK-RV32-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
-; CHECK-RV32-NEXT:    vlse64.v v16, (a0), zero
-; CHECK-RV32-NEXT:    vzext.vf2 v10, v8
-; CHECK-RV32-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
-; CHECK-RV32-NEXT:    vnsrl.wi v12, v16, 0
-; CHECK-RV32-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
-; CHECK-RV32-NEXT:    vnsrl.wi v8, v12, 0
-; CHECK-RV32-NEXT:    vsll.vv v8, v10, v8
-; CHECK-RV32-NEXT:    addi sp, sp, 16
-; CHECK-RV32-NEXT:    ret
-;
-; CHECK-RV64-LABEL: vwsll_vx_i64_nxv8i16:
-; CHECK-RV64:       # %bb.0:
-; CHECK-RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
-; CHECK-RV64-NEXT:    vmv.v.x v16, a0
-; CHECK-RV64-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
-; CHECK-RV64-NEXT:    vzext.vf2 v10, v8
-; CHECK-RV64-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
-; CHECK-RV64-NEXT:    vnsrl.wi v12, v16, 0
-; CHECK-RV64-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
-; CHECK-RV64-NEXT:    vnsrl.wi v8, v12, 0
-; CHECK-RV64-NEXT:    vsll.vv v8, v10, v8
-; CHECK-RV64-NEXT:    ret
-;
-; CHECK-ZVBB32-LABEL: vwsll_vx_i64_nxv8i16:
-; CHECK-ZVBB32:       # %bb.0:
-; CHECK-ZVBB32-NEXT:    addi sp, sp, -16
-; CHECK-ZVBB32-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-ZVBB32-NEXT:    sw a1, 12(sp)
-; CHECK-ZVBB32-NEXT:    sw a0, 8(sp)
-; CHECK-ZVBB32-NEXT:    addi a0, sp, 8
-; CHECK-ZVBB32-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
-; CHECK-ZVBB32-NEXT:    vlse64.v v16, (a0), zero
-; CHECK-ZVBB32-NEXT:    vzext.vf2 v10, v8
-; CHECK-ZVBB32-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
-; CHECK-ZVBB32-NEXT:    vnsrl.wi v12, v16, 0
-; CHECK-ZVBB32-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
-; CHECK-ZVBB32-NEXT:    vnsrl.wi v8, v12, 0
-; CHECK-ZVBB32-NEXT:    vsll.vv v8, v10, v8
-; CHECK-ZVBB32-NEXT:    addi sp, sp, 16
-; CHECK-ZVBB32-NEXT:    ret
+; CHECK-LABEL: vwsll_vx_i64_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
+; CHECK-NEXT:    vmv.v.x v16, a0
+; CHECK-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT:    vzext.vf2 v10, v8
+; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
+; CHECK-NEXT:    vnsrl.wi v12, v16, 0
+; CHECK-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT:    vnsrl.wi v8, v12, 0
+; CHECK-NEXT:    vsll.vv v8, v10, v8
+; CHECK-NEXT:    ret
 ;
-; CHECK-ZVBB64-LABEL: vwsll_vx_i64_nxv8i16:
-; CHECK-ZVBB64:       # %bb.0:
-; CHECK-ZVBB64-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
-; CHECK-ZVBB64-NEXT:    vwsll.vx v10, v8, a0
-; CHECK-ZVBB64-NEXT:    vmv2r.v v8, v10
-; CHECK-ZVBB64-NEXT:    ret
+; CHECK-ZVBB-LABEL: vwsll_vx_i64_nxv8i16:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
+; CHECK-ZVBB-NEXT:    vwsll.vx v10, v8, a0
+; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
+; CHECK-ZVBB-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 8 x i32> zeroinitializer
   %x = zext <vscale x 8 x i8> %a to <vscale x 8 x i16>
@@ -705,3 +639,8 @@
   %z = shl <vscale x 8 x i16> %x, shufflevector(<vscale x 8 x i16> insertelement(<vscale x 8 x i16> poison, i16 2, i32 0), <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer)
   ret <vscale x 8 x i16> %z
 }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK-RV32: {{.*}}
+; CHECK-RV64: {{.*}}
+; CHECK-ZVBB32: {{.*}}
+; CHECK-ZVBB64: {{.*}}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwsll-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vwsll-vp.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vwsll-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vwsll-vp.ll
@@ -320,18 +320,13 @@
 define <vscale x 4 x i32> @vwsll_vx_i64_nxv4i32(<vscale x 4 x i16> %a, i64 %b, <vscale x 4 x i1> %m, i32 zeroext %vl) {
 ; CHECK-RV32-LABEL: vwsll_vx_i64_nxv4i32:
 ; CHECK-RV32:       # %bb.0:
-; CHECK-RV32-NEXT:    addi sp, sp, -16
-; CHECK-RV32-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-RV32-NEXT:    sw a1, 12(sp)
-; CHECK-RV32-NEXT:    sw a0, 8(sp)
-; CHECK-RV32-NEXT:    addi a0, sp, 8
-; CHECK-RV32-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
-; CHECK-RV32-NEXT:    vlse64.v v12, (a0), zero
+; CHECK-RV32-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
+; CHECK-RV32-NEXT:    vmv.v.x v12, a0
+; CHECK-RV32-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; CHECK-RV32-NEXT:    vzext.vf2 v10, v8
 ; CHECK-RV32-NEXT:    vnsrl.wi v8, v12, 0
 ; CHECK-RV32-NEXT:    vsetvli zero, a2, e32, m2, ta, ma
 ; CHECK-RV32-NEXT:    vsll.vv v8, v10, v8, v0.t
-; CHECK-RV32-NEXT:    addi sp, sp, 16
 ; CHECK-RV32-NEXT:    ret
 ;
 ; CHECK-RV64-LABEL: vwsll_vx_i64_nxv4i32:
@@ -347,18 +342,9 @@
 ;
 ; CHECK-ZVBB32-LABEL: vwsll_vx_i64_nxv4i32:
 ; CHECK-ZVBB32:       # %bb.0:
-; CHECK-ZVBB32-NEXT:    addi sp, sp, -16
-; CHECK-ZVBB32-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-ZVBB32-NEXT:    sw a1, 12(sp)
-; CHECK-ZVBB32-NEXT:    sw a0, 8(sp)
-; CHECK-ZVBB32-NEXT:    addi a0, sp, 8
-; CHECK-ZVBB32-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
-; CHECK-ZVBB32-NEXT:    vlse64.v v12, (a0), zero
-; CHECK-ZVBB32-NEXT:    vzext.vf2 v10, v8
-; CHECK-ZVBB32-NEXT:    vnsrl.wi v8, v12, 0
-; CHECK-ZVBB32-NEXT:    vsetvli zero, a2, e32, m2, ta, ma
-; CHECK-ZVBB32-NEXT:    vsll.vv v8, v10, v8, v0.t
-; CHECK-ZVBB32-NEXT:    addi sp, sp, 16
+; CHECK-ZVBB32-NEXT:    vsetvli zero, a2, e16, m1, ta, ma
+; CHECK-ZVBB32-NEXT:    vwsll.vx v10, v8, a0, v0.t
+; CHECK-ZVBB32-NEXT:    vmv2r.v v8, v10
 ; CHECK-ZVBB32-NEXT:    ret
 ;
 ; CHECK-ZVBB64-LABEL: vwsll_vx_i64_nxv4i32:
@@ -575,13 +561,9 @@
 define <vscale x 8 x i16> @vwsll_vx_i64_nxv8i16(<vscale x 8 x i8> %a, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %vl) {
 ; CHECK-RV32-LABEL: vwsll_vx_i64_nxv8i16:
 ; CHECK-RV32:       # %bb.0:
-; CHECK-RV32-NEXT:    addi sp, sp, -16
-; CHECK-RV32-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-RV32-NEXT:    sw a1, 12(sp)
-; CHECK-RV32-NEXT:    sw a0, 8(sp)
-; CHECK-RV32-NEXT:    addi a0, sp, 8
-; CHECK-RV32-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
-; CHECK-RV32-NEXT:    vlse64.v v16, (a0), zero
+; CHECK-RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
+; CHECK-RV32-NEXT:    vmv.v.x v16, a0
+; CHECK-RV32-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
 ; CHECK-RV32-NEXT:    vzext.vf2 v10, v8
 ; CHECK-RV32-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
 ; CHECK-RV32-NEXT:    vnsrl.wi v12, v16, 0
@@ -589,7 +571,6 @@
 ; CHECK-RV32-NEXT:    vnsrl.wi v8, v12, 0
 ; CHECK-RV32-NEXT:    vsetvli zero, a2, e16, m2, ta, ma
 ; CHECK-RV32-NEXT:    vsll.vv v8, v10, v8, v0.t
-; CHECK-RV32-NEXT:    addi sp, sp, 16
 ; CHECK-RV32-NEXT:    ret
 ;
 ; CHECK-RV64-LABEL: vwsll_vx_i64_nxv8i16:
@@ -608,21 +589,9 @@
 ;
 ; CHECK-ZVBB32-LABEL: vwsll_vx_i64_nxv8i16:
 ; CHECK-ZVBB32:       # %bb.0:
-; CHECK-ZVBB32-NEXT:    addi sp, sp, -16
-; CHECK-ZVBB32-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-ZVBB32-NEXT:    sw a1, 12(sp)
-; CHECK-ZVBB32-NEXT:    sw a0, 8(sp)
-; CHECK-ZVBB32-NEXT:    addi a0, sp, 8
-; CHECK-ZVBB32-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
-; CHECK-ZVBB32-NEXT:    vlse64.v v16, (a0), zero
-; CHECK-ZVBB32-NEXT:    vzext.vf2 v10, v8
-; CHECK-ZVBB32-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
-; CHECK-ZVBB32-NEXT:    vnsrl.wi v12, v16, 0
-; CHECK-ZVBB32-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
-; CHECK-ZVBB32-NEXT:    vnsrl.wi v8, v12, 0
-; CHECK-ZVBB32-NEXT:    vsetvli zero, a2, e16, m2, ta, ma
-; CHECK-ZVBB32-NEXT:    vsll.vv v8, v10, v8, v0.t
-; CHECK-ZVBB32-NEXT:    addi sp, sp, 16
+; CHECK-ZVBB32-NEXT:    vsetvli zero, a2, e8, m1, ta, ma
+; CHECK-ZVBB32-NEXT:    vwsll.vx v10, v8, a0, v0.t
+; CHECK-ZVBB32-NEXT:    vmv2r.v v8, v10
 ; CHECK-ZVBB32-NEXT:    ret
 ;
 ; CHECK-ZVBB64-LABEL: vwsll_vx_i64_nxv8i16: