diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -3203,7 +3203,7 @@ .addOperand(Inst.getOperand(1)) .addOperand(Inst.getOperand(2)) .addOperand(Inst.getOperand(3)) - .addOperand(Inst.getOperand(4))); + .addReg(RISCV::NoRegister)); emitToStreamer(Out, MCInstBuilder(RISCV::VMANDN_MM) .addOperand(Inst.getOperand(0)) .addOperand(Inst.getOperand(0)) diff --git a/llvm/test/MC/RISCV/rvv/compare.s b/llvm/test/MC/RISCV/rvv/compare.s --- a/llvm/test/MC/RISCV/rvv/compare.s +++ b/llvm/test/MC/RISCV/rvv/compare.s @@ -420,21 +420,21 @@ # CHECK-UNKNOWN: 57 24 80 6e vmsgeu.vx v0, v4, a0, v0.t, v2 -# CHECK-INST: vmsltu.vx v2, v4, a0, v0.t +# CHECK-INST: vmsltu.vx v2, v4, a0 # CHECK-INST: vmandn.mm v0, v0, v2 -# CHECK-ENCODING: [0x57,0x41,0x45,0x68] +# CHECK-ENCODING: [0x57,0x41,0x45,0x6a] # CHECK-ENCODING: [0x57,0x20,0x01,0x62] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 41 45 68 +# CHECK-UNKNOWN: 57 41 45 6a # CHECK-UNKNOWN: 57 20 01 62 vmsge.vx v0, v4, a0, v0.t, v2 -# CHECK-INST: vmslt.vx v2, v4, a0, v0.t +# CHECK-INST: vmslt.vx v2, v4, a0 # CHECK-INST: vmandn.mm v0, v0, v2 -# CHECK-ENCODING: [0x57,0x41,0x45,0x6c] +# CHECK-ENCODING: [0x57,0x41,0x45,0x6e] # CHECK-ENCODING: [0x57,0x20,0x01,0x62] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 41 45 6c +# CHECK-UNKNOWN: 57 41 45 6e # CHECK-UNKNOWN: 57 20 01 62 vmsgeu.vx v9, v4, a0, v0.t, v2