diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
@@ -1,9 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 
-; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,LMULMAX1
-; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,LMULMAX1
-; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,LMULMAX2
-; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,LMULMAX2
+; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfh,+f,+d -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfh,+f,+d -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
 
 ; Tests that a floating-point build_vector doesn't try and generate a VID
 ; instruction
@@ -33,33 +31,20 @@
 ; expanded to 4 EXTRACT_VECTOR_ELTs and a BUILD_VECTOR. This then triggers the
 ; loop when expanded.
 define <4 x float> @hang_when_merging_stores_after_legalization(<8 x float> %x, <8 x float> %y) optsize {
-; LMULMAX1-LABEL: hang_when_merging_stores_after_legalization:
-; LMULMAX1:       # %bb.0:
-; LMULMAX1-NEXT:    vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT:    vmv.v.i v0, 2
-; LMULMAX1-NEXT:    vrgather.vi v12, v8, 0
-; LMULMAX1-NEXT:    vrgather.vi v12, v9, 3, v0.t
-; LMULMAX1-NEXT:    vsetivli zero, 3, e32, m1, tu, ma
-; LMULMAX1-NEXT:    vslideup.vi v11, v10, 2
-; LMULMAX1-NEXT:    vsetivli zero, 2, e32, m1, tu, ma
-; LMULMAX1-NEXT:    vmv.v.v v11, v12
-; LMULMAX1-NEXT:    vmv1r.v v8, v11
-; LMULMAX1-NEXT:    ret
-;
-; LMULMAX2-LABEL: hang_when_merging_stores_after_legalization:
-; LMULMAX2:       # %bb.0:
-; LMULMAX2-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
-; LMULMAX2-NEXT:    vid.v v12
-; LMULMAX2-NEXT:    li a0, 7
-; LMULMAX2-NEXT:    vmul.vx v14, v12, a0
-; LMULMAX2-NEXT:    vrgather.vv v12, v8, v14
-; LMULMAX2-NEXT:    vadd.vi v8, v14, -14
-; LMULMAX2-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma
-; LMULMAX2-NEXT:    vmv.v.i v0, 12
-; LMULMAX2-NEXT:    vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-NEXT:    vrgather.vv v12, v10, v8, v0.t
-; LMULMAX2-NEXT:    vmv1r.v v8, v12
-; LMULMAX2-NEXT:    ret
+; CHECK-LABEL: hang_when_merging_stores_after_legalization:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT:    vid.v v12
+; CHECK-NEXT:    li a0, 7
+; CHECK-NEXT:    vmul.vx v14, v12, a0
+; CHECK-NEXT:    vrgather.vv v12, v8, v14
+; CHECK-NEXT:    vadd.vi v8, v14, -14
+; CHECK-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma
+; CHECK-NEXT:    vmv.v.i v0, 12
+; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, mu
+; CHECK-NEXT:    vrgather.vv v12, v10, v8, v0.t
+; CHECK-NEXT:    vmv1r.v v8, v12
+; CHECK-NEXT:    ret
   %z = shufflevector <8 x float> %x, <8 x float> %y, <4 x i32> <i32 0, i32 7, i32 8, i32 15>
   ret <4 x float> %z
 }
@@ -192,19 +177,12 @@
 }
 
 define <8 x float> @splat_c5_v8f32(<8 x float> %v) {
-; LMULMAX1-LABEL: splat_c5_v8f32:
-; LMULMAX1:       # %bb.0:
-; LMULMAX1-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
-; LMULMAX1-NEXT:    vrgather.vi v8, v9, 1
-; LMULMAX1-NEXT:    vmv.v.v v9, v8
-; LMULMAX1-NEXT:    ret
-;
-; LMULMAX2-LABEL: splat_c5_v8f32:
-; LMULMAX2:       # %bb.0:
-; LMULMAX2-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
-; LMULMAX2-NEXT:    vrgather.vi v10, v8, 5
-; LMULMAX2-NEXT:    vmv.v.v v8, v10
-; LMULMAX2-NEXT:    ret
+; CHECK-LABEL: splat_c5_v8f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT:    vrgather.vi v10, v8, 5
+; CHECK-NEXT:    vmv.v.v v8, v10
+; CHECK-NEXT:    ret
   %x = extractelement <8 x float> %v, i32 5
   %ins = insertelement <8 x float> poison, float %x, i32 0
   %splat = shufflevector <8 x float> %ins, <8 x float> poison, <8 x i32> zeroinitializer
@@ -212,29 +190,13 @@
 }
 
 define <8 x float> @splat_idx_v8f32(<8 x float> %v, i64 %idx) {
-; LMULMAX1-LABEL: splat_idx_v8f32:
-; LMULMAX1:       # %bb.0:
-; LMULMAX1-NEXT:    addi sp, sp, -32
-; LMULMAX1-NEXT:    .cfi_def_cfa_offset 32
-; LMULMAX1-NEXT:    andi a0, a0, 7
-; LMULMAX1-NEXT:    slli a0, a0, 2
-; LMULMAX1-NEXT:    mv a1, sp
-; LMULMAX1-NEXT:    add a0, a1, a0
-; LMULMAX1-NEXT:    addi a2, sp, 16
-; LMULMAX1-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
-; LMULMAX1-NEXT:    vse32.v v9, (a2)
-; LMULMAX1-NEXT:    vse32.v v8, (a1)
-; LMULMAX1-NEXT:    vlse32.v v8, (a0), zero
-; LMULMAX1-NEXT:    vmv.v.v v9, v8
-; LMULMAX1-NEXT:    addi sp, sp, 32
-; LMULMAX1-NEXT:    ret
 ;
-; LMULMAX2-LABEL: splat_idx_v8f32:
-; LMULMAX2:       # %bb.0:
-; LMULMAX2-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
-; LMULMAX2-NEXT:    vrgather.vx v10, v8, a0
-; LMULMAX2-NEXT:    vmv.v.v v8, v10
-; LMULMAX2-NEXT:    ret
+; CHECK-LABEL: splat_idx_v8f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT:    vrgather.vx v10, v8, a0
+; CHECK-NEXT:    vmv.v.v v8, v10
+; CHECK-NEXT:    ret
   %x = extractelement <8 x float> %v, i64 %idx
   %ins = insertelement <8 x float> poison, float %x, i32 0
   %splat = shufflevector <8 x float> %ins, <8 x float> poison, <8 x i32> zeroinitializer