diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -5042,6 +5042,9 @@
   /// Expand fminnum/fmaxnum into fminnum_ieee/fmaxnum_ieee with quieted inputs.
   SDValue expandFMINNUM_FMAXNUM(SDNode *N, SelectionDAG &DAG) const;
 
+  /// Expand fminimum/fmaximum into multiple comparison with selects.
+  SDValue expandFMINIMUM_FMAXIMUM(SDNode *N, SelectionDAG &DAG) const;
+
   /// Expand FP_TO_[US]INT_SAT into FP_TO_[US]INT and selects or min/max.
   /// \param N Node to expand
   /// \returns The expansion result
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -3523,6 +3523,12 @@
       Results.push_back(Expanded);
     break;
   }
+  case ISD::FMINIMUM:
+  case ISD::FMAXIMUM: {
+    if (SDValue Expanded = TLI.expandFMINIMUM_FMAXIMUM(Node, DAG))
+      Results.push_back(Expanded);
+    break;
+  }
   case ISD::FSIN:
   case ISD::FCOS: {
     EVT VT = Node->getValueType(0);
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -8128,6 +8128,64 @@
   return SDValue();
 }
 
+SDValue TargetLowering::expandFMINIMUM_FMAXIMUM(SDNode *N,
+                                                SelectionDAG &DAG) const {
+  SDLoc DL(N);
+  SDValue LHS = N->getOperand(0);
+  SDValue RHS = N->getOperand(1);
+  unsigned Opc = N->getOpcode();
+  EVT VT = N->getValueType(0);
+  EVT CCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
+  bool NoNaN = (N->getFlags().hasNoNaNs() ||
+                (DAG.isKnownNeverNaN(LHS) && DAG.isKnownNeverNaN(RHS)));
+  bool NoZeroSign =
+      (N->getFlags().hasNoSignedZeros() || DAG.isKnownNeverZeroFloat(LHS) ||
+       DAG.isKnownNeverZeroFloat(RHS));
+  bool IsMax = Opc == ISD::FMAXIMUM;
+
+  SDValue MinMax;
+  if (isOperationLegalOrCustom(IsMax ? ISD::FMAXNUM_IEEE : ISD::FMINNUM_IEEE, VT)) {
+    MinMax = DAG.getNode(IsMax ? ISD::FMAXNUM_IEEE : ISD::FMINNUM_IEEE, DL, VT, LHS, RHS);
+  } else if (isOperationLegalOrCustom(IsMax ? ISD::FMAXNUM : ISD::FMINNUM, VT)) {
+    MinMax = DAG.getNode(IsMax ? ISD::FMAXNUM : ISD::FMINNUM, DL, VT, LHS, RHS);
+  } else {
+    SDValue FPCmp =
+        DAG.getSetCC(DL, CCVT, LHS, RHS, IsMax ? ISD::SETGT : ISD::SETLT);
+    MinMax = DAG.getSelect(DL, VT, FPCmp, LHS, RHS);
+  }
+
+  // Propagate any NaN of both operands
+  if (!NoNaN) {
+    ConstantFP *FPNaN = ConstantFP::get(
+        *DAG.getContext(), APFloat::getNaN(DAG.EVTToAPFloatSemantics(VT)));
+    MinMax = DAG.getSelect(DL, VT, DAG.getSetCC(DL, CCVT, LHS, RHS, ISD::SETUO),
+                           DAG.getConstantFP(*FPNaN, DL, VT), MinMax);
+  }
+
+  // fminimum/fmaximum requires -0.0 less than +0.0
+  if (!NoZeroSign) {
+    SDValue IsZero = DAG.getSetCC(DL, CCVT, MinMax,
+                                  DAG.getConstantFP(0.0, DL, VT), ISD::SETEQ);
+    SDValue Pos0Neg1 = DAG.getNode(
+        ISD::AND, DL, CCVT,
+        DAG.getNode(ISD::IS_FPCLASS, DL, CCVT, LHS,
+                    DAG.getTargetConstant(fcPosZero, DL, MVT::i32)),
+        DAG.getNode(ISD::IS_FPCLASS, DL, CCVT, RHS,
+                    DAG.getTargetConstant(fcNegZero, DL, MVT::i32)));
+    SDValue Neg0Pos1 = DAG.getNode(
+        ISD::AND, DL, CCVT,
+        DAG.getNode(ISD::IS_FPCLASS, DL, CCVT, LHS,
+                    DAG.getTargetConstant(fcNegZero, DL, MVT::i32)),
+        DAG.getNode(ISD::IS_FPCLASS, DL, CCVT, RHS,
+                    DAG.getTargetConstant(fcPosZero, DL, MVT::i32)));
+    SDValue Pos0 = DAG.getSelect(DL, VT, Pos0Neg1, IsMax ? LHS : RHS, MinMax);
+    SDValue Pos1 = DAG.getSelect(DL, VT, Neg0Pos1, IsMax ? RHS : LHS, Pos0);
+    MinMax = DAG.getSelect(DL, VT, IsZero, Pos1, MinMax);
+  }
+
+  return MinMax;
+}
+
 /// Returns a true value if if this FPClassTest can be performed with an ordered
 /// fcmp to 0, and a false value if it's an unordered fcmp to 0. Returns
 /// std::nullopt if it cannot be performed as a compare with 0.
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -440,6 +440,8 @@
 
     if (!Subtarget.hasStdExtZfa())
       setOperationAction({ISD::FMAXIMUM, ISD::FMINIMUM}, MVT::f16, Custom);
+    else
+      setOperationAction({ISD::FMAXIMUM, ISD::FMINIMUM}, MVT::f16, Legal);
   }
 
   if (Subtarget.hasStdExtFOrZfinx()) {
@@ -462,9 +464,10 @@
     setOperationAction(ISD::FP_TO_FP16, MVT::f32, Custom);
     setOperationAction(ISD::FP16_TO_FP, MVT::f32, Custom);
 
-    if (Subtarget.hasStdExtZfa())
+    if (Subtarget.hasStdExtZfa()) {
       setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
-    else
+      setOperationAction({ISD::FMAXIMUM, ISD::FMINIMUM}, MVT::f32, Legal);
+    } else
       setOperationAction({ISD::FMAXIMUM, ISD::FMINIMUM}, MVT::f32, Custom);
   }
 
@@ -479,6 +482,7 @@
       setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
       setOperationAction(ISD::BITCAST, MVT::i64, Custom);
       setOperationAction(ISD::BITCAST, MVT::f64, Custom);
+      setOperationAction({ISD::FMAXIMUM, ISD::FMINIMUM}, MVT::f64, Legal);
     } else {
       if (Subtarget.is64Bit())
         setOperationAction(FPRndMode, MVT::f64, Custom);
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-minmax.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-minmax.ll
--- a/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-minmax.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-minmax.ll
@@ -48,7 +48,7 @@
 define void @fmaxnm_v32f16(ptr %a, ptr %b) #0 {
 ; VBITS_EQ_256-LABEL: fmaxnm_v32f16:
 ; VBITS_EQ_256:       // %bb.0:
-; VBITS_EQ_256-NEXT:    mov x8, #16
+; VBITS_EQ_256-NEXT:    mov x8, #16 // =0x10
 ; VBITS_EQ_256-NEXT:    ptrue p0.h, vl16
 ; VBITS_EQ_256-NEXT:    ld1h { z0.h }, p0/z, [x0, x8, lsl #1]
 ; VBITS_EQ_256-NEXT:    ld1h { z1.h }, p0/z, [x0]
@@ -146,7 +146,7 @@
 define void @fmaxnm_v16f32(ptr %a, ptr %b) #0 {
 ; VBITS_EQ_256-LABEL: fmaxnm_v16f32:
 ; VBITS_EQ_256:       // %bb.0:
-; VBITS_EQ_256-NEXT:    mov x8, #8
+; VBITS_EQ_256-NEXT:    mov x8, #8 // =0x8
 ; VBITS_EQ_256-NEXT:    ptrue p0.s, vl8
 ; VBITS_EQ_256-NEXT:    ld1w { z0.s }, p0/z, [x0, x8, lsl #2]
 ; VBITS_EQ_256-NEXT:    ld1w { z1.s }, p0/z, [x0]
@@ -244,7 +244,7 @@
 define void @fmaxnm_v8f64(ptr %a, ptr %b) #0 {
 ; VBITS_EQ_256-LABEL: fmaxnm_v8f64:
 ; VBITS_EQ_256:       // %bb.0:
-; VBITS_EQ_256-NEXT:    mov x8, #4
+; VBITS_EQ_256-NEXT:    mov x8, #4 // =0x4
 ; VBITS_EQ_256-NEXT:    ptrue p0.d, vl4
 ; VBITS_EQ_256-NEXT:    ld1d { z0.d }, p0/z, [x0, x8, lsl #3]
 ; VBITS_EQ_256-NEXT:    ld1d { z1.d }, p0/z, [x0]
@@ -346,7 +346,7 @@
 define void @fminnm_v32f16(ptr %a, ptr %b) #0 {
 ; VBITS_EQ_256-LABEL: fminnm_v32f16:
 ; VBITS_EQ_256:       // %bb.0:
-; VBITS_EQ_256-NEXT:    mov x8, #16
+; VBITS_EQ_256-NEXT:    mov x8, #16 // =0x10
 ; VBITS_EQ_256-NEXT:    ptrue p0.h, vl16
 ; VBITS_EQ_256-NEXT:    ld1h { z0.h }, p0/z, [x0, x8, lsl #1]
 ; VBITS_EQ_256-NEXT:    ld1h { z1.h }, p0/z, [x0]
@@ -444,7 +444,7 @@
 define void @fminnm_v16f32(ptr %a, ptr %b) #0 {
 ; VBITS_EQ_256-LABEL: fminnm_v16f32:
 ; VBITS_EQ_256:       // %bb.0:
-; VBITS_EQ_256-NEXT:    mov x8, #8
+; VBITS_EQ_256-NEXT:    mov x8, #8 // =0x8
 ; VBITS_EQ_256-NEXT:    ptrue p0.s, vl8
 ; VBITS_EQ_256-NEXT:    ld1w { z0.s }, p0/z, [x0, x8, lsl #2]
 ; VBITS_EQ_256-NEXT:    ld1w { z1.s }, p0/z, [x0]
@@ -542,7 +542,7 @@
 define void @fminnm_v8f64(ptr %a, ptr %b) #0 {
 ; VBITS_EQ_256-LABEL: fminnm_v8f64:
 ; VBITS_EQ_256:       // %bb.0:
-; VBITS_EQ_256-NEXT:    mov x8, #4
+; VBITS_EQ_256-NEXT:    mov x8, #4 // =0x4
 ; VBITS_EQ_256-NEXT:    ptrue p0.d, vl4
 ; VBITS_EQ_256-NEXT:    ld1d { z0.d }, p0/z, [x0, x8, lsl #3]
 ; VBITS_EQ_256-NEXT:    ld1d { z1.d }, p0/z, [x0]
@@ -644,7 +644,7 @@
 define void @fmax_v32f16(ptr %a, ptr %b) #0 {
 ; VBITS_EQ_256-LABEL: fmax_v32f16:
 ; VBITS_EQ_256:       // %bb.0:
-; VBITS_EQ_256-NEXT:    mov x8, #16
+; VBITS_EQ_256-NEXT:    mov x8, #16 // =0x10
 ; VBITS_EQ_256-NEXT:    ptrue p0.h, vl16
 ; VBITS_EQ_256-NEXT:    ld1h { z0.h }, p0/z, [x0, x8, lsl #1]
 ; VBITS_EQ_256-NEXT:    ld1h { z1.h }, p0/z, [x0]
@@ -742,7 +742,7 @@
 define void @fmax_v16f32(ptr %a, ptr %b) #0 {
 ; VBITS_EQ_256-LABEL: fmax_v16f32:
 ; VBITS_EQ_256:       // %bb.0:
-; VBITS_EQ_256-NEXT:    mov x8, #8
+; VBITS_EQ_256-NEXT:    mov x8, #8 // =0x8
 ; VBITS_EQ_256-NEXT:    ptrue p0.s, vl8
 ; VBITS_EQ_256-NEXT:    ld1w { z0.s }, p0/z, [x0, x8, lsl #2]
 ; VBITS_EQ_256-NEXT:    ld1w { z1.s }, p0/z, [x0]
@@ -840,7 +840,7 @@
 define void @fmax_v8f64(ptr %a, ptr %b) #0 {
 ; VBITS_EQ_256-LABEL: fmax_v8f64:
 ; VBITS_EQ_256:       // %bb.0:
-; VBITS_EQ_256-NEXT:    mov x8, #4
+; VBITS_EQ_256-NEXT:    mov x8, #4 // =0x4
 ; VBITS_EQ_256-NEXT:    ptrue p0.d, vl4
 ; VBITS_EQ_256-NEXT:    ld1d { z0.d }, p0/z, [x0, x8, lsl #3]
 ; VBITS_EQ_256-NEXT:    ld1d { z1.d }, p0/z, [x0]
@@ -942,7 +942,7 @@
 define void @fmin_v32f16(ptr %a, ptr %b) #0 {
 ; VBITS_EQ_256-LABEL: fmin_v32f16:
 ; VBITS_EQ_256:       // %bb.0:
-; VBITS_EQ_256-NEXT:    mov x8, #16
+; VBITS_EQ_256-NEXT:    mov x8, #16 // =0x10
 ; VBITS_EQ_256-NEXT:    ptrue p0.h, vl16
 ; VBITS_EQ_256-NEXT:    ld1h { z0.h }, p0/z, [x0, x8, lsl #1]
 ; VBITS_EQ_256-NEXT:    ld1h { z1.h }, p0/z, [x0]
@@ -1040,7 +1040,7 @@
 define void @fmin_v16f32(ptr %a, ptr %b) #0 {
 ; VBITS_EQ_256-LABEL: fmin_v16f32:
 ; VBITS_EQ_256:       // %bb.0:
-; VBITS_EQ_256-NEXT:    mov x8, #8
+; VBITS_EQ_256-NEXT:    mov x8, #8 // =0x8
 ; VBITS_EQ_256-NEXT:    ptrue p0.s, vl8
 ; VBITS_EQ_256-NEXT:    ld1w { z0.s }, p0/z, [x0, x8, lsl #2]
 ; VBITS_EQ_256-NEXT:    ld1w { z1.s }, p0/z, [x0]
@@ -1138,7 +1138,7 @@
 define void @fmin_v8f64(ptr %a, ptr %b) #0 {
 ; VBITS_EQ_256-LABEL: fmin_v8f64:
 ; VBITS_EQ_256:       // %bb.0:
-; VBITS_EQ_256-NEXT:    mov x8, #4
+; VBITS_EQ_256-NEXT:    mov x8, #4 // =0x4
 ; VBITS_EQ_256-NEXT:    ptrue p0.d, vl4
 ; VBITS_EQ_256-NEXT:    ld1d { z0.d }, p0/z, [x0, x8, lsl #3]
 ; VBITS_EQ_256-NEXT:    ld1d { z1.d }, p0/z, [x0]
diff --git a/llvm/test/CodeGen/ARM/fminmax-folds.ll b/llvm/test/CodeGen/ARM/fminmax-folds.ll
--- a/llvm/test/CodeGen/ARM/fminmax-folds.ll
+++ b/llvm/test/CodeGen/ARM/fminmax-folds.ll
@@ -77,13 +77,22 @@
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    vldr s0, .LCPI6_0
 ; CHECK-NEXT:    vmov s2, r0
-; CHECK-NEXT:    vmax.f32 d0, d1, d0
+; CHECK-NEXT:    mov r1, #0
+; CHECK-NEXT:    vldr s4, .LCPI6_1
+; CHECK-NEXT:    vcmp.f32 s2, s0
+; CHECK-NEXT:    vmaxnm.f32 s6, s2, s0
+; CHECK-NEXT:    vmrs APSR_nzcv, fpscr
+; CHECK-NEXT:    movwvs r1, #1
+; CHECK-NEXT:    cmp r1, #0
+; CHECK-NEXT:    vseleq.f32 s0, s6, s4
 ; CHECK-NEXT:    vmov r0, s0
 ; CHECK-NEXT:    bx lr
 ; CHECK-NEXT:    .p2align 2
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI6_0:
 ; CHECK-NEXT:    .long 0x7f800000 @ float +Inf
+; CHECK-NEXT:  .LCPI6_1:
+; CHECK-NEXT:    .long 0x7fc00000 @ float NaN
   %r = call float @llvm.maximum.f32(float %x, float 0x7ff0000000000000)
   ret float %r
 }
@@ -135,13 +144,22 @@
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    vldr s0, .LCPI11_0
 ; CHECK-NEXT:    vmov s2, r0
-; CHECK-NEXT:    vmin.f32 d0, d1, d0
+; CHECK-NEXT:    mov r1, #0
+; CHECK-NEXT:    vldr s4, .LCPI11_1
+; CHECK-NEXT:    vcmp.f32 s2, s0
+; CHECK-NEXT:    vminnm.f32 s6, s2, s0
+; CHECK-NEXT:    vmrs APSR_nzcv, fpscr
+; CHECK-NEXT:    movwvs r1, #1
+; CHECK-NEXT:    cmp r1, #0
+; CHECK-NEXT:    vseleq.f32 s0, s6, s4
 ; CHECK-NEXT:    vmov r0, s0
 ; CHECK-NEXT:    bx lr
 ; CHECK-NEXT:    .p2align 2
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI11_0:
 ; CHECK-NEXT:    .long 0xff800000 @ float -Inf
+; CHECK-NEXT:  .LCPI11_1:
+; CHECK-NEXT:    .long 0x7fc00000 @ float NaN
   %r = call float @llvm.minimum.f32(float %x, float 0xfff0000000000000)
   ret float %r
 }
@@ -337,13 +355,22 @@
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    vldr s0, .LCPI30_0
 ; CHECK-NEXT:    vmov s2, r0
-; CHECK-NEXT:    vmax.f32 d0, d1, d0
+; CHECK-NEXT:    mov r1, #0
+; CHECK-NEXT:    vldr s4, .LCPI30_1
+; CHECK-NEXT:    vcmp.f32 s2, s0
+; CHECK-NEXT:    vmaxnm.f32 s6, s2, s0
+; CHECK-NEXT:    vmrs APSR_nzcv, fpscr
+; CHECK-NEXT:    movwvs r1, #1
+; CHECK-NEXT:    cmp r1, #0
+; CHECK-NEXT:    vseleq.f32 s0, s6, s4
 ; CHECK-NEXT:    vmov r0, s0
 ; CHECK-NEXT:    bx lr
 ; CHECK-NEXT:    .p2align 2
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI30_0:
 ; CHECK-NEXT:    .long 0x7f7fffff @ float 3.40282347E+38
+; CHECK-NEXT:  .LCPI30_1:
+; CHECK-NEXT:    .long 0x7fc00000 @ float NaN
   %r = call float @llvm.maximum.f32(float %x, float 0x47efffffe0000000)
   ret float %r
 }
@@ -353,13 +380,22 @@
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    vldr s0, .LCPI31_0
 ; CHECK-NEXT:    vmov s2, r0
-; CHECK-NEXT:    vmin.f32 d0, d1, d0
+; CHECK-NEXT:    mov r1, #0
+; CHECK-NEXT:    vldr s4, .LCPI31_1
+; CHECK-NEXT:    vcmp.f32 s2, s0
+; CHECK-NEXT:    vminnm.f32 s6, s2, s0
+; CHECK-NEXT:    vmrs APSR_nzcv, fpscr
+; CHECK-NEXT:    movwvs r1, #1
+; CHECK-NEXT:    cmp r1, #0
+; CHECK-NEXT:    vseleq.f32 s0, s6, s4
 ; CHECK-NEXT:    vmov r0, s0
 ; CHECK-NEXT:    bx lr
 ; CHECK-NEXT:    .p2align 2
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI31_0:
 ; CHECK-NEXT:    .long 0x7f7fffff @ float 3.40282347E+38
+; CHECK-NEXT:  .LCPI31_1:
+; CHECK-NEXT:    .long 0x7fc00000 @ float NaN
   %r = call float @llvm.minimum.f32(float %x, float 0x47efffffe0000000)
   ret float %r
 }
@@ -401,13 +437,22 @@
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    vldr s0, .LCPI34_0
 ; CHECK-NEXT:    vmov s2, r0
-; CHECK-NEXT:    vmax.f32 d0, d1, d0
+; CHECK-NEXT:    mov r1, #0
+; CHECK-NEXT:    vldr s4, .LCPI34_1
+; CHECK-NEXT:    vcmp.f32 s2, s0
+; CHECK-NEXT:    vmaxnm.f32 s6, s2, s0
+; CHECK-NEXT:    vmrs APSR_nzcv, fpscr
+; CHECK-NEXT:    movwvs r1, #1
+; CHECK-NEXT:    cmp r1, #0
+; CHECK-NEXT:    vseleq.f32 s0, s6, s4
 ; CHECK-NEXT:    vmov r0, s0
 ; CHECK-NEXT:    bx lr
 ; CHECK-NEXT:    .p2align 2
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI34_0:
 ; CHECK-NEXT:    .long 0xff7fffff @ float -3.40282347E+38
+; CHECK-NEXT:  .LCPI34_1:
+; CHECK-NEXT:    .long 0x7fc00000 @ float NaN
   %r = call float @llvm.maximum.f32(float %x, float 0xc7efffffe0000000)
   ret float %r
 }
@@ -417,13 +462,22 @@
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    vldr s0, .LCPI35_0
 ; CHECK-NEXT:    vmov s2, r0
-; CHECK-NEXT:    vmin.f32 d0, d1, d0
+; CHECK-NEXT:    mov r1, #0
+; CHECK-NEXT:    vldr s4, .LCPI35_1
+; CHECK-NEXT:    vcmp.f32 s2, s0
+; CHECK-NEXT:    vminnm.f32 s6, s2, s0
+; CHECK-NEXT:    vmrs APSR_nzcv, fpscr
+; CHECK-NEXT:    movwvs r1, #1
+; CHECK-NEXT:    cmp r1, #0
+; CHECK-NEXT:    vseleq.f32 s0, s6, s4
 ; CHECK-NEXT:    vmov r0, s0
 ; CHECK-NEXT:    bx lr
 ; CHECK-NEXT:    .p2align 2
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI35_0:
 ; CHECK-NEXT:    .long 0xff7fffff @ float -3.40282347E+38
+; CHECK-NEXT:  .LCPI35_1:
+; CHECK-NEXT:    .long 0x7fc00000 @ float NaN
   %r = call float @llvm.minimum.f32(float %x, float 0xc7efffffe0000000)
   ret float %r
 }
@@ -459,13 +513,22 @@
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    vldr s0, .LCPI38_0
 ; CHECK-NEXT:    vmov s2, r0
-; CHECK-NEXT:    vmax.f32 d0, d1, d0
+; CHECK-NEXT:    mov r1, #0
+; CHECK-NEXT:    vldr s4, .LCPI38_1
+; CHECK-NEXT:    vcmp.f32 s2, s0
+; CHECK-NEXT:    vmaxnm.f32 s6, s2, s0
+; CHECK-NEXT:    vmrs APSR_nzcv, fpscr
+; CHECK-NEXT:    movwvs r1, #1
+; CHECK-NEXT:    cmp r1, #0
+; CHECK-NEXT:    vseleq.f32 s0, s6, s4
 ; CHECK-NEXT:    vmov r0, s0
 ; CHECK-NEXT:    bx lr
 ; CHECK-NEXT:    .p2align 2
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI38_0:
 ; CHECK-NEXT:    .long 0x7f7fffff @ float 3.40282347E+38
+; CHECK-NEXT:  .LCPI38_1:
+; CHECK-NEXT:    .long 0x7fc00000 @ float NaN
   %r = call ninf float @llvm.maximum.f32(float %x, float 0x47efffffe0000000)
   ret float %r
 }
@@ -516,13 +579,22 @@
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    vldr s0, .LCPI43_0
 ; CHECK-NEXT:    vmov s2, r0
-; CHECK-NEXT:    vmin.f32 d0, d1, d0
+; CHECK-NEXT:    mov r1, #0
+; CHECK-NEXT:    vldr s4, .LCPI43_1
+; CHECK-NEXT:    vcmp.f32 s2, s0
+; CHECK-NEXT:    vminnm.f32 s6, s2, s0
+; CHECK-NEXT:    vmrs APSR_nzcv, fpscr
+; CHECK-NEXT:    movwvs r1, #1
+; CHECK-NEXT:    cmp r1, #0
+; CHECK-NEXT:    vseleq.f32 s0, s6, s4
 ; CHECK-NEXT:    vmov r0, s0
 ; CHECK-NEXT:    bx lr
 ; CHECK-NEXT:    .p2align 2
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI43_0:
 ; CHECK-NEXT:    .long 0xff7fffff @ float -3.40282347E+38
+; CHECK-NEXT:  .LCPI43_1:
+; CHECK-NEXT:    .long 0x7fc00000 @ float NaN
   %r = call ninf float @llvm.minimum.f32(float %x, float 0xc7efffffe0000000)
   ret float %r
 }
diff --git a/llvm/test/CodeGen/PowerPC/fminimum-fmaximum-f128.ll b/llvm/test/CodeGen/PowerPC/fminimum-fmaximum-f128.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/fminimum-fmaximum-f128.ll
@@ -0,0 +1,105 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck %s
+
+define fp128 @f128_minimum(fp128 %a, fp128 %b) {
+; CHECK-LABEL: f128_minimum:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xscmpuqp 0, 2, 3
+; CHECK-NEXT:    vmr 4, 2
+; CHECK-NEXT:    bge 0, .LBB0_3
+; CHECK-NEXT:  # %bb.1: # %entry
+; CHECK-NEXT:    bun 0, .LBB0_4
+; CHECK-NEXT:  .LBB0_2: # %entry
+; CHECK-NEXT:    xststdcqp 0, 3, 4
+; CHECK-NEXT:    bc 12, 2, .LBB0_5
+; CHECK-NEXT:    b .LBB0_6
+; CHECK-NEXT:  .LBB0_3: # %entry
+; CHECK-NEXT:    vmr 4, 3
+; CHECK-NEXT:    bnu 0, .LBB0_2
+; CHECK-NEXT:  .LBB0_4:
+; CHECK-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
+; CHECK-NEXT:    addi 3, 3, .LCPI0_0@toc@l
+; CHECK-NEXT:    lxv 36, 0(3)
+; CHECK-NEXT:    xststdcqp 0, 3, 4
+; CHECK-NEXT:    bc 4, 2, .LBB0_6
+; CHECK-NEXT:  .LBB0_5: # %entry
+; CHECK-NEXT:    xststdcqp 0, 2, 8
+; CHECK-NEXT:    xxlor 0, 35, 35
+; CHECK-NEXT:    bc 12, 2, .LBB0_7
+; CHECK-NEXT:  .LBB0_6: # %entry
+; CHECK-NEXT:    xxlor 0, 36, 36
+; CHECK-NEXT:  .LBB0_7: # %entry
+; CHECK-NEXT:    xststdcqp 0, 3, 8
+; CHECK-NEXT:    bc 4, 2, .LBB0_9
+; CHECK-NEXT:  # %bb.8: # %entry
+; CHECK-NEXT:    xststdcqp 0, 2, 4
+; CHECK-NEXT:    bc 12, 2, .LBB0_10
+; CHECK-NEXT:  .LBB0_9: # %entry
+; CHECK-NEXT:    xxlor 34, 0, 0
+; CHECK-NEXT:  .LBB0_10: # %entry
+; CHECK-NEXT:    addis 3, 2, .LCPI0_1@toc@ha
+; CHECK-NEXT:    addi 3, 3, .LCPI0_1@toc@l
+; CHECK-NEXT:    lxv 35, 0(3)
+; CHECK-NEXT:    xscmpuqp 0, 4, 3
+; CHECK-NEXT:    beqlr 0
+; CHECK-NEXT:  # %bb.11: # %entry
+; CHECK-NEXT:    vmr 2, 4
+; CHECK-NEXT:    blr
+entry:
+  %m = call fp128 @llvm.minimum.f128(fp128 %a, fp128 %b)
+  ret fp128 %m
+}
+
+define fp128 @f128_maximum(fp128 %a, fp128 %b) {
+; CHECK-LABEL: f128_maximum:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xscmpuqp 0, 2, 3
+; CHECK-NEXT:    vmr 4, 2
+; CHECK-NEXT:    ble 0, .LBB1_3
+; CHECK-NEXT:  # %bb.1: # %entry
+; CHECK-NEXT:    bun 0, .LBB1_4
+; CHECK-NEXT:  .LBB1_2: # %entry
+; CHECK-NEXT:    xststdcqp 0, 3, 4
+; CHECK-NEXT:    bc 12, 2, .LBB1_5
+; CHECK-NEXT:    b .LBB1_6
+; CHECK-NEXT:  .LBB1_3: # %entry
+; CHECK-NEXT:    vmr 4, 3
+; CHECK-NEXT:    bnu 0, .LBB1_2
+; CHECK-NEXT:  .LBB1_4:
+; CHECK-NEXT:    addis 3, 2, .LCPI1_0@toc@ha
+; CHECK-NEXT:    addi 3, 3, .LCPI1_0@toc@l
+; CHECK-NEXT:    lxv 36, 0(3)
+; CHECK-NEXT:    xststdcqp 0, 3, 4
+; CHECK-NEXT:    bc 4, 2, .LBB1_6
+; CHECK-NEXT:  .LBB1_5: # %entry
+; CHECK-NEXT:    xststdcqp 0, 2, 8
+; CHECK-NEXT:    xxlor 0, 34, 34
+; CHECK-NEXT:    bc 12, 2, .LBB1_7
+; CHECK-NEXT:  .LBB1_6: # %entry
+; CHECK-NEXT:    xxlor 0, 36, 36
+; CHECK-NEXT:  .LBB1_7: # %entry
+; CHECK-NEXT:    xststdcqp 0, 3, 8
+; CHECK-NEXT:    bc 4, 2, .LBB1_9
+; CHECK-NEXT:  # %bb.8: # %entry
+; CHECK-NEXT:    xststdcqp 0, 2, 4
+; CHECK-NEXT:    bc 12, 2, .LBB1_10
+; CHECK-NEXT:  .LBB1_9: # %entry
+; CHECK-NEXT:    xxlor 35, 0, 0
+; CHECK-NEXT:  .LBB1_10: # %entry
+; CHECK-NEXT:    addis 3, 2, .LCPI1_1@toc@ha
+; CHECK-NEXT:    addi 3, 3, .LCPI1_1@toc@l
+; CHECK-NEXT:    lxv 34, 0(3)
+; CHECK-NEXT:    xscmpuqp 0, 4, 2
+; CHECK-NEXT:    beq 0, .LBB1_12
+; CHECK-NEXT:  # %bb.11: # %entry
+; CHECK-NEXT:    vmr 3, 4
+; CHECK-NEXT:  .LBB1_12: # %entry
+; CHECK-NEXT:    vmr 2, 3
+; CHECK-NEXT:    blr
+entry:
+  %m = call fp128 @llvm.maximum.f128(fp128 %a, fp128 %b)
+  ret fp128 %m
+}
+
+declare fp128 @llvm.minimum.f128(fp128, fp128)
+declare fp128 @llvm.maximum.f128(fp128, fp128)
diff --git a/llvm/test/CodeGen/PowerPC/fminimum-fmaximum.ll b/llvm/test/CodeGen/PowerPC/fminimum-fmaximum.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/fminimum-fmaximum.ll
@@ -0,0 +1,1803 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s --check-prefix=NOVSX
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s --check-prefix=VSX
+; RUN: llc -mtriple=powerpc64-ibm-aix -mcpu=pwr8 < %s | FileCheck %s --check-prefix=AIX
+
+define float @f32_minimum(float %a, float %b) {
+; NOVSX-LABEL: f32_minimum:
+; NOVSX:       # %bb.0: # %entry
+; NOVSX-NEXT:    fcmpu 0, 1, 2
+; NOVSX-NEXT:    fmr 0, 1
+; NOVSX-NEXT:    stfs 1, -4(1)
+; NOVSX-NEXT:    stfs 2, -8(1)
+; NOVSX-NEXT:    bc 12, 0, .LBB0_2
+; NOVSX-NEXT:  # %bb.1: # %entry
+; NOVSX-NEXT:    fmr 0, 2
+; NOVSX-NEXT:  .LBB0_2: # %entry
+; NOVSX-NEXT:    lwz 3, -4(1)
+; NOVSX-NEXT:    lwz 4, -8(1)
+; NOVSX-NEXT:    bc 4, 3, .LBB0_4
+; NOVSX-NEXT:  # %bb.3:
+; NOVSX-NEXT:    addis 5, 2, .LCPI0_0@toc@ha
+; NOVSX-NEXT:    lfs 0, .LCPI0_0@toc@l(5)
+; NOVSX-NEXT:  .LBB0_4: # %entry
+; NOVSX-NEXT:    xoris 5, 4, 32768
+; NOVSX-NEXT:    or 5, 3, 5
+; NOVSX-NEXT:    cmpwi 5, 0
+; NOVSX-NEXT:    bc 12, 2, .LBB0_6
+; NOVSX-NEXT:  # %bb.5: # %entry
+; NOVSX-NEXT:    fmr 2, 0
+; NOVSX-NEXT:  .LBB0_6: # %entry
+; NOVSX-NEXT:    xoris 3, 3, 32768
+; NOVSX-NEXT:    or 3, 3, 4
+; NOVSX-NEXT:    cmpwi 3, 0
+; NOVSX-NEXT:    bc 12, 2, .LBB0_8
+; NOVSX-NEXT:  # %bb.7: # %entry
+; NOVSX-NEXT:    fmr 1, 2
+; NOVSX-NEXT:  .LBB0_8: # %entry
+; NOVSX-NEXT:    addis 3, 2, .LCPI0_1@toc@ha
+; NOVSX-NEXT:    lfs 2, .LCPI0_1@toc@l(3)
+; NOVSX-NEXT:    fcmpu 0, 0, 2
+; NOVSX-NEXT:    bclr 12, 2, 0
+; NOVSX-NEXT:  # %bb.9: # %entry
+; NOVSX-NEXT:    fmr 1, 0
+; NOVSX-NEXT:    blr
+;
+; VSX-LABEL: f32_minimum:
+; VSX:       # %bb.0: # %entry
+; VSX-NEXT:    xscvdpspn 0, 1
+; VSX-NEXT:    fcmpu 0, 1, 2
+; VSX-NEXT:    xscvdpspn 3, 2
+; VSX-NEXT:    mffprwz 4, 0
+; VSX-NEXT:    mffprwz 3, 3
+; VSX-NEXT:    bc 12, 3, .LBB0_2
+; VSX-NEXT:  # %bb.1: # %entry
+; VSX-NEXT:    xsmindp 0, 1, 2
+; VSX-NEXT:    b .LBB0_3
+; VSX-NEXT:  .LBB0_2:
+; VSX-NEXT:    addis 5, 2, .LCPI0_0@toc@ha
+; VSX-NEXT:    lfs 0, .LCPI0_0@toc@l(5)
+; VSX-NEXT:  .LBB0_3: # %entry
+; VSX-NEXT:    xoris 5, 3, 32768
+; VSX-NEXT:    or 5, 4, 5
+; VSX-NEXT:    cmpwi 5, 0
+; VSX-NEXT:    bc 12, 2, .LBB0_5
+; VSX-NEXT:  # %bb.4: # %entry
+; VSX-NEXT:    fmr 2, 0
+; VSX-NEXT:  .LBB0_5: # %entry
+; VSX-NEXT:    xoris 4, 4, 32768
+; VSX-NEXT:    or 3, 4, 3
+; VSX-NEXT:    cmpwi 3, 0
+; VSX-NEXT:    bc 12, 2, .LBB0_7
+; VSX-NEXT:  # %bb.6: # %entry
+; VSX-NEXT:    fmr 1, 2
+; VSX-NEXT:  .LBB0_7: # %entry
+; VSX-NEXT:    xxlxor 2, 2, 2
+; VSX-NEXT:    fcmpu 0, 0, 2
+; VSX-NEXT:    bclr 12, 2, 0
+; VSX-NEXT:  # %bb.8: # %entry
+; VSX-NEXT:    fmr 1, 0
+; VSX-NEXT:    blr
+;
+; AIX-LABEL: f32_minimum:
+; AIX:       # %bb.0: # %entry
+; AIX-NEXT:    xscvdpspn 0, 1
+; AIX-NEXT:    fcmpu 0, 1, 2
+; AIX-NEXT:    xscvdpspn 3, 2
+; AIX-NEXT:    mffprwz 4, 0
+; AIX-NEXT:    mffprwz 3, 3
+; AIX-NEXT:    bc 12, 3, L..BB0_2
+; AIX-NEXT:  # %bb.1: # %entry
+; AIX-NEXT:    xsmindp 0, 1, 2
+; AIX-NEXT:    b L..BB0_3
+; AIX-NEXT:  L..BB0_2:
+; AIX-NEXT:    ld 5, L..C0(2) # %const.0
+; AIX-NEXT:    lfs 0, 0(5)
+; AIX-NEXT:  L..BB0_3: # %entry
+; AIX-NEXT:    xoris 5, 3, 32768
+; AIX-NEXT:    or 5, 4, 5
+; AIX-NEXT:    cmpwi 5, 0
+; AIX-NEXT:    bc 12, 2, L..BB0_5
+; AIX-NEXT:  # %bb.4: # %entry
+; AIX-NEXT:    fmr 2, 0
+; AIX-NEXT:  L..BB0_5: # %entry
+; AIX-NEXT:    xoris 4, 4, 32768
+; AIX-NEXT:    or 3, 4, 3
+; AIX-NEXT:    cmpwi 3, 0
+; AIX-NEXT:    bc 12, 2, L..BB0_7
+; AIX-NEXT:  # %bb.6: # %entry
+; AIX-NEXT:    fmr 1, 2
+; AIX-NEXT:  L..BB0_7: # %entry
+; AIX-NEXT:    xxlxor 2, 2, 2
+; AIX-NEXT:    fcmpu 0, 0, 2
+; AIX-NEXT:    bclr 12, 2, 0
+; AIX-NEXT:  # %bb.8: # %entry
+; AIX-NEXT:    fmr 1, 0
+; AIX-NEXT:    blr
+entry:
+  %m = call float @llvm.minimum.f32(float %a, float %b)
+  ret float %m
+}
+
+define float @f32_maximum(float %a, float %b) {
+; NOVSX-LABEL: f32_maximum:
+; NOVSX:       # %bb.0: # %entry
+; NOVSX-NEXT:    fcmpu 0, 1, 2
+; NOVSX-NEXT:    fmr 0, 1
+; NOVSX-NEXT:    stfs 1, -4(1)
+; NOVSX-NEXT:    stfs 2, -8(1)
+; NOVSX-NEXT:    bc 12, 1, .LBB1_2
+; NOVSX-NEXT:  # %bb.1: # %entry
+; NOVSX-NEXT:    fmr 0, 2
+; NOVSX-NEXT:  .LBB1_2: # %entry
+; NOVSX-NEXT:    lwz 3, -4(1)
+; NOVSX-NEXT:    lwz 4, -8(1)
+; NOVSX-NEXT:    bc 4, 3, .LBB1_4
+; NOVSX-NEXT:  # %bb.3:
+; NOVSX-NEXT:    addis 5, 2, .LCPI1_0@toc@ha
+; NOVSX-NEXT:    lfs 0, .LCPI1_0@toc@l(5)
+; NOVSX-NEXT:  .LBB1_4: # %entry
+; NOVSX-NEXT:    xoris 5, 4, 32768
+; NOVSX-NEXT:    or 5, 3, 5
+; NOVSX-NEXT:    cmpwi 5, 0
+; NOVSX-NEXT:    bc 12, 2, .LBB1_6
+; NOVSX-NEXT:  # %bb.5: # %entry
+; NOVSX-NEXT:    fmr 1, 0
+; NOVSX-NEXT:  .LBB1_6: # %entry
+; NOVSX-NEXT:    xoris 3, 3, 32768
+; NOVSX-NEXT:    or 3, 3, 4
+; NOVSX-NEXT:    cmpwi 3, 0
+; NOVSX-NEXT:    bc 12, 2, .LBB1_8
+; NOVSX-NEXT:  # %bb.7: # %entry
+; NOVSX-NEXT:    fmr 2, 1
+; NOVSX-NEXT:  .LBB1_8: # %entry
+; NOVSX-NEXT:    addis 3, 2, .LCPI1_1@toc@ha
+; NOVSX-NEXT:    lfs 1, .LCPI1_1@toc@l(3)
+; NOVSX-NEXT:    fcmpu 0, 0, 1
+; NOVSX-NEXT:    bc 12, 2, .LBB1_10
+; NOVSX-NEXT:  # %bb.9: # %entry
+; NOVSX-NEXT:    fmr 2, 0
+; NOVSX-NEXT:  .LBB1_10: # %entry
+; NOVSX-NEXT:    fmr 1, 2
+; NOVSX-NEXT:    blr
+;
+; VSX-LABEL: f32_maximum:
+; VSX:       # %bb.0: # %entry
+; VSX-NEXT:    xscvdpspn 0, 1
+; VSX-NEXT:    fcmpu 0, 1, 2
+; VSX-NEXT:    xscvdpspn 3, 2
+; VSX-NEXT:    mffprwz 4, 0
+; VSX-NEXT:    mffprwz 3, 3
+; VSX-NEXT:    bc 12, 3, .LBB1_2
+; VSX-NEXT:  # %bb.1: # %entry
+; VSX-NEXT:    xsmaxdp 0, 1, 2
+; VSX-NEXT:    b .LBB1_3
+; VSX-NEXT:  .LBB1_2:
+; VSX-NEXT:    addis 5, 2, .LCPI1_0@toc@ha
+; VSX-NEXT:    lfs 0, .LCPI1_0@toc@l(5)
+; VSX-NEXT:  .LBB1_3: # %entry
+; VSX-NEXT:    xoris 5, 3, 32768
+; VSX-NEXT:    or 5, 4, 5
+; VSX-NEXT:    cmpwi 5, 0
+; VSX-NEXT:    bc 12, 2, .LBB1_5
+; VSX-NEXT:  # %bb.4: # %entry
+; VSX-NEXT:    fmr 1, 0
+; VSX-NEXT:  .LBB1_5: # %entry
+; VSX-NEXT:    xoris 4, 4, 32768
+; VSX-NEXT:    or 3, 4, 3
+; VSX-NEXT:    cmpwi 3, 0
+; VSX-NEXT:    bc 12, 2, .LBB1_7
+; VSX-NEXT:  # %bb.6: # %entry
+; VSX-NEXT:    fmr 2, 1
+; VSX-NEXT:  .LBB1_7: # %entry
+; VSX-NEXT:    xxlxor 1, 1, 1
+; VSX-NEXT:    fcmpu 0, 0, 1
+; VSX-NEXT:    bc 12, 2, .LBB1_9
+; VSX-NEXT:  # %bb.8: # %entry
+; VSX-NEXT:    fmr 2, 0
+; VSX-NEXT:  .LBB1_9: # %entry
+; VSX-NEXT:    fmr 1, 2
+; VSX-NEXT:    blr
+;
+; AIX-LABEL: f32_maximum:
+; AIX:       # %bb.0: # %entry
+; AIX-NEXT:    xscvdpspn 0, 1
+; AIX-NEXT:    fcmpu 0, 1, 2
+; AIX-NEXT:    xscvdpspn 3, 2
+; AIX-NEXT:    mffprwz 4, 0
+; AIX-NEXT:    mffprwz 3, 3
+; AIX-NEXT:    bc 12, 3, L..BB1_2
+; AIX-NEXT:  # %bb.1: # %entry
+; AIX-NEXT:    xsmaxdp 0, 1, 2
+; AIX-NEXT:    b L..BB1_3
+; AIX-NEXT:  L..BB1_2:
+; AIX-NEXT:    ld 5, L..C1(2) # %const.0
+; AIX-NEXT:    lfs 0, 0(5)
+; AIX-NEXT:  L..BB1_3: # %entry
+; AIX-NEXT:    xoris 5, 3, 32768
+; AIX-NEXT:    or 5, 4, 5
+; AIX-NEXT:    cmpwi 5, 0
+; AIX-NEXT:    bc 12, 2, L..BB1_5
+; AIX-NEXT:  # %bb.4: # %entry
+; AIX-NEXT:    fmr 1, 0
+; AIX-NEXT:  L..BB1_5: # %entry
+; AIX-NEXT:    xoris 4, 4, 32768
+; AIX-NEXT:    or 3, 4, 3
+; AIX-NEXT:    cmpwi 3, 0
+; AIX-NEXT:    bc 12, 2, L..BB1_7
+; AIX-NEXT:  # %bb.6: # %entry
+; AIX-NEXT:    fmr 2, 1
+; AIX-NEXT:  L..BB1_7: # %entry
+; AIX-NEXT:    xxlxor 1, 1, 1
+; AIX-NEXT:    fcmpu 0, 0, 1
+; AIX-NEXT:    bc 12, 2, L..BB1_9
+; AIX-NEXT:  # %bb.8: # %entry
+; AIX-NEXT:    fmr 2, 0
+; AIX-NEXT:  L..BB1_9: # %entry
+; AIX-NEXT:    fmr 1, 2
+; AIX-NEXT:    blr
+entry:
+  %m = call float @llvm.maximum.f32(float %a, float %b)
+  ret float %m
+}
+
+define double @f64_minimum(double %a, double %b) {
+; NOVSX-LABEL: f64_minimum:
+; NOVSX:       # %bb.0: # %entry
+; NOVSX-NEXT:    fcmpu 0, 1, 2
+; NOVSX-NEXT:    fmr 0, 1
+; NOVSX-NEXT:    stfd 1, -8(1)
+; NOVSX-NEXT:    stfd 2, -16(1)
+; NOVSX-NEXT:    bc 12, 0, .LBB2_2
+; NOVSX-NEXT:  # %bb.1: # %entry
+; NOVSX-NEXT:    fmr 0, 2
+; NOVSX-NEXT:  .LBB2_2: # %entry
+; NOVSX-NEXT:    ld 3, -8(1)
+; NOVSX-NEXT:    ld 4, -16(1)
+; NOVSX-NEXT:    bc 4, 3, .LBB2_4
+; NOVSX-NEXT:  # %bb.3:
+; NOVSX-NEXT:    addis 5, 2, .LCPI2_0@toc@ha
+; NOVSX-NEXT:    lfs 0, .LCPI2_0@toc@l(5)
+; NOVSX-NEXT:  .LBB2_4: # %entry
+; NOVSX-NEXT:    li 5, 1
+; NOVSX-NEXT:    rldic 5, 5, 63, 0
+; NOVSX-NEXT:    xor 6, 4, 5
+; NOVSX-NEXT:    or. 6, 3, 6
+; NOVSX-NEXT:    bc 12, 2, .LBB2_6
+; NOVSX-NEXT:  # %bb.5: # %entry
+; NOVSX-NEXT:    fmr 2, 0
+; NOVSX-NEXT:  .LBB2_6: # %entry
+; NOVSX-NEXT:    xor 3, 3, 5
+; NOVSX-NEXT:    or. 3, 3, 4
+; NOVSX-NEXT:    bc 12, 2, .LBB2_8
+; NOVSX-NEXT:  # %bb.7: # %entry
+; NOVSX-NEXT:    fmr 1, 2
+; NOVSX-NEXT:  .LBB2_8: # %entry
+; NOVSX-NEXT:    addis 3, 2, .LCPI2_1@toc@ha
+; NOVSX-NEXT:    lfs 2, .LCPI2_1@toc@l(3)
+; NOVSX-NEXT:    fcmpu 0, 0, 2
+; NOVSX-NEXT:    bclr 12, 2, 0
+; NOVSX-NEXT:  # %bb.9: # %entry
+; NOVSX-NEXT:    fmr 1, 0
+; NOVSX-NEXT:    blr
+;
+; VSX-LABEL: f64_minimum:
+; VSX:       # %bb.0: # %entry
+; VSX-NEXT:    fcmpu 0, 1, 2
+; VSX-NEXT:    mffprd 4, 1
+; VSX-NEXT:    mffprd 3, 2
+; VSX-NEXT:    bc 12, 3, .LBB2_2
+; VSX-NEXT:  # %bb.1: # %entry
+; VSX-NEXT:    xsmindp 0, 1, 2
+; VSX-NEXT:    b .LBB2_3
+; VSX-NEXT:  .LBB2_2:
+; VSX-NEXT:    addis 5, 2, .LCPI2_0@toc@ha
+; VSX-NEXT:    lfs 0, .LCPI2_0@toc@l(5)
+; VSX-NEXT:  .LBB2_3: # %entry
+; VSX-NEXT:    li 5, 1
+; VSX-NEXT:    rldic 5, 5, 63, 0
+; VSX-NEXT:    xor 6, 3, 5
+; VSX-NEXT:    or. 6, 4, 6
+; VSX-NEXT:    bc 12, 2, .LBB2_5
+; VSX-NEXT:  # %bb.4: # %entry
+; VSX-NEXT:    fmr 2, 0
+; VSX-NEXT:  .LBB2_5: # %entry
+; VSX-NEXT:    xor 4, 4, 5
+; VSX-NEXT:    or. 3, 4, 3
+; VSX-NEXT:    bc 12, 2, .LBB2_7
+; VSX-NEXT:  # %bb.6: # %entry
+; VSX-NEXT:    fmr 1, 2
+; VSX-NEXT:  .LBB2_7: # %entry
+; VSX-NEXT:    xxlxor 2, 2, 2
+; VSX-NEXT:    fcmpu 0, 0, 2
+; VSX-NEXT:    bclr 12, 2, 0
+; VSX-NEXT:  # %bb.8: # %entry
+; VSX-NEXT:    fmr 1, 0
+; VSX-NEXT:    blr
+;
+; AIX-LABEL: f64_minimum:
+; AIX:       # %bb.0: # %entry
+; AIX-NEXT:    fcmpu 0, 1, 2
+; AIX-NEXT:    mffprd 4, 1
+; AIX-NEXT:    mffprd 3, 2
+; AIX-NEXT:    bc 12, 3, L..BB2_2
+; AIX-NEXT:  # %bb.1: # %entry
+; AIX-NEXT:    xsmindp 0, 1, 2
+; AIX-NEXT:    b L..BB2_3
+; AIX-NEXT:  L..BB2_2:
+; AIX-NEXT:    ld 5, L..C2(2) # %const.0
+; AIX-NEXT:    lfs 0, 0(5)
+; AIX-NEXT:  L..BB2_3: # %entry
+; AIX-NEXT:    li 5, 1
+; AIX-NEXT:    rldic 5, 5, 63, 0
+; AIX-NEXT:    xor 6, 3, 5
+; AIX-NEXT:    or. 6, 4, 6
+; AIX-NEXT:    bc 12, 2, L..BB2_5
+; AIX-NEXT:  # %bb.4: # %entry
+; AIX-NEXT:    fmr 2, 0
+; AIX-NEXT:  L..BB2_5: # %entry
+; AIX-NEXT:    xor 4, 4, 5
+; AIX-NEXT:    or. 3, 4, 3
+; AIX-NEXT:    bc 12, 2, L..BB2_7
+; AIX-NEXT:  # %bb.6: # %entry
+; AIX-NEXT:    fmr 1, 2
+; AIX-NEXT:  L..BB2_7: # %entry
+; AIX-NEXT:    xxlxor 2, 2, 2
+; AIX-NEXT:    fcmpu 0, 0, 2
+; AIX-NEXT:    bclr 12, 2, 0
+; AIX-NEXT:  # %bb.8: # %entry
+; AIX-NEXT:    fmr 1, 0
+; AIX-NEXT:    blr
+entry:
+  %m = call double @llvm.minimum.f64(double %a, double %b)
+  ret double %m
+}
+
+define double @f64_maximum(double %a, double %b) {
+; NOVSX-LABEL: f64_maximum:
+; NOVSX:       # %bb.0: # %entry
+; NOVSX-NEXT:    fcmpu 0, 1, 2
+; NOVSX-NEXT:    fmr 0, 1
+; NOVSX-NEXT:    stfd 1, -8(1)
+; NOVSX-NEXT:    stfd 2, -16(1)
+; NOVSX-NEXT:    bc 12, 1, .LBB3_2
+; NOVSX-NEXT:  # %bb.1: # %entry
+; NOVSX-NEXT:    fmr 0, 2
+; NOVSX-NEXT:  .LBB3_2: # %entry
+; NOVSX-NEXT:    ld 3, -8(1)
+; NOVSX-NEXT:    ld 4, -16(1)
+; NOVSX-NEXT:    bc 4, 3, .LBB3_4
+; NOVSX-NEXT:  # %bb.3:
+; NOVSX-NEXT:    addis 5, 2, .LCPI3_0@toc@ha
+; NOVSX-NEXT:    lfs 0, .LCPI3_0@toc@l(5)
+; NOVSX-NEXT:  .LBB3_4: # %entry
+; NOVSX-NEXT:    li 5, 1
+; NOVSX-NEXT:    rldic 5, 5, 63, 0
+; NOVSX-NEXT:    xor 6, 4, 5
+; NOVSX-NEXT:    or. 6, 3, 6
+; NOVSX-NEXT:    bc 12, 2, .LBB3_6
+; NOVSX-NEXT:  # %bb.5: # %entry
+; NOVSX-NEXT:    fmr 1, 0
+; NOVSX-NEXT:  .LBB3_6: # %entry
+; NOVSX-NEXT:    xor 3, 3, 5
+; NOVSX-NEXT:    or. 3, 3, 4
+; NOVSX-NEXT:    bc 12, 2, .LBB3_8
+; NOVSX-NEXT:  # %bb.7: # %entry
+; NOVSX-NEXT:    fmr 2, 1
+; NOVSX-NEXT:  .LBB3_8: # %entry
+; NOVSX-NEXT:    addis 3, 2, .LCPI3_1@toc@ha
+; NOVSX-NEXT:    lfs 1, .LCPI3_1@toc@l(3)
+; NOVSX-NEXT:    fcmpu 0, 0, 1
+; NOVSX-NEXT:    bc 12, 2, .LBB3_10
+; NOVSX-NEXT:  # %bb.9: # %entry
+; NOVSX-NEXT:    fmr 2, 0
+; NOVSX-NEXT:  .LBB3_10: # %entry
+; NOVSX-NEXT:    fmr 1, 2
+; NOVSX-NEXT:    blr
+;
+; VSX-LABEL: f64_maximum:
+; VSX:       # %bb.0: # %entry
+; VSX-NEXT:    fcmpu 0, 1, 2
+; VSX-NEXT:    mffprd 4, 1
+; VSX-NEXT:    mffprd 3, 2
+; VSX-NEXT:    bc 12, 3, .LBB3_2
+; VSX-NEXT:  # %bb.1: # %entry
+; VSX-NEXT:    xsmaxdp 0, 1, 2
+; VSX-NEXT:    b .LBB3_3
+; VSX-NEXT:  .LBB3_2:
+; VSX-NEXT:    addis 5, 2, .LCPI3_0@toc@ha
+; VSX-NEXT:    lfs 0, .LCPI3_0@toc@l(5)
+; VSX-NEXT:  .LBB3_3: # %entry
+; VSX-NEXT:    li 5, 1
+; VSX-NEXT:    rldic 5, 5, 63, 0
+; VSX-NEXT:    xor 6, 3, 5
+; VSX-NEXT:    or. 6, 4, 6
+; VSX-NEXT:    bc 12, 2, .LBB3_5
+; VSX-NEXT:  # %bb.4: # %entry
+; VSX-NEXT:    fmr 1, 0
+; VSX-NEXT:  .LBB3_5: # %entry
+; VSX-NEXT:    xor 4, 4, 5
+; VSX-NEXT:    or. 3, 4, 3
+; VSX-NEXT:    bc 12, 2, .LBB3_7
+; VSX-NEXT:  # %bb.6: # %entry
+; VSX-NEXT:    fmr 2, 1
+; VSX-NEXT:  .LBB3_7: # %entry
+; VSX-NEXT:    xxlxor 1, 1, 1
+; VSX-NEXT:    fcmpu 0, 0, 1
+; VSX-NEXT:    bc 12, 2, .LBB3_9
+; VSX-NEXT:  # %bb.8: # %entry
+; VSX-NEXT:    fmr 2, 0
+; VSX-NEXT:  .LBB3_9: # %entry
+; VSX-NEXT:    fmr 1, 2
+; VSX-NEXT:    blr
+;
+; AIX-LABEL: f64_maximum:
+; AIX:       # %bb.0: # %entry
+; AIX-NEXT:    fcmpu 0, 1, 2
+; AIX-NEXT:    mffprd 4, 1
+; AIX-NEXT:    mffprd 3, 2
+; AIX-NEXT:    bc 12, 3, L..BB3_2
+; AIX-NEXT:  # %bb.1: # %entry
+; AIX-NEXT:    xsmaxdp 0, 1, 2
+; AIX-NEXT:    b L..BB3_3
+; AIX-NEXT:  L..BB3_2:
+; AIX-NEXT:    ld 5, L..C3(2) # %const.0
+; AIX-NEXT:    lfs 0, 0(5)
+; AIX-NEXT:  L..BB3_3: # %entry
+; AIX-NEXT:    li 5, 1
+; AIX-NEXT:    rldic 5, 5, 63, 0
+; AIX-NEXT:    xor 6, 3, 5
+; AIX-NEXT:    or. 6, 4, 6
+; AIX-NEXT:    bc 12, 2, L..BB3_5
+; AIX-NEXT:  # %bb.4: # %entry
+; AIX-NEXT:    fmr 1, 0
+; AIX-NEXT:  L..BB3_5: # %entry
+; AIX-NEXT:    xor 4, 4, 5
+; AIX-NEXT:    or. 3, 4, 3
+; AIX-NEXT:    bc 12, 2, L..BB3_7
+; AIX-NEXT:  # %bb.6: # %entry
+; AIX-NEXT:    fmr 2, 1
+; AIX-NEXT:  L..BB3_7: # %entry
+; AIX-NEXT:    xxlxor 1, 1, 1
+; AIX-NEXT:    fcmpu 0, 0, 1
+; AIX-NEXT:    bc 12, 2, L..BB3_9
+; AIX-NEXT:  # %bb.8: # %entry
+; AIX-NEXT:    fmr 2, 0
+; AIX-NEXT:  L..BB3_9: # %entry
+; AIX-NEXT:    fmr 1, 2
+; AIX-NEXT:    blr
+entry:
+  %m = call double @llvm.maximum.f64(double %a, double %b)
+  ret double %m
+}
+
+define <4 x float> @v4f32_minimum(<4 x float> %a, <4 x float> %b) {
+; NOVSX-LABEL: v4f32_minimum:
+; NOVSX:       # %bb.0: # %entry
+; NOVSX-NEXT:    addi 3, 1, -32
+; NOVSX-NEXT:    stvx 3, 0, 3
+; NOVSX-NEXT:    addi 3, 1, -48
+; NOVSX-NEXT:    stvx 2, 0, 3
+; NOVSX-NEXT:    lfs 4, -20(1)
+; NOVSX-NEXT:    lfs 8, -36(1)
+; NOVSX-NEXT:    lfs 7, -24(1)
+; NOVSX-NEXT:    lfs 6, -40(1)
+; NOVSX-NEXT:    lfs 5, -28(1)
+; NOVSX-NEXT:    lfs 3, -44(1)
+; NOVSX-NEXT:    lfs 1, -32(1)
+; NOVSX-NEXT:    stfs 4, -80(1)
+; NOVSX-NEXT:    fcmpu 0, 8, 4
+; NOVSX-NEXT:    fmr 10, 8
+; NOVSX-NEXT:    lfs 0, -48(1)
+; NOVSX-NEXT:    stfs 8, -76(1)
+; NOVSX-NEXT:    stfs 7, -72(1)
+; NOVSX-NEXT:    stfs 6, -68(1)
+; NOVSX-NEXT:    stfs 5, -64(1)
+; NOVSX-NEXT:    stfs 3, -60(1)
+; NOVSX-NEXT:    stfs 1, -56(1)
+; NOVSX-NEXT:    stfs 0, -52(1)
+; NOVSX-NEXT:    bc 12, 0, .LBB4_2
+; NOVSX-NEXT:  # %bb.1: # %entry
+; NOVSX-NEXT:    fmr 10, 4
+; NOVSX-NEXT:  .LBB4_2: # %entry
+; NOVSX-NEXT:    addis 3, 2, .LCPI4_0@toc@ha
+; NOVSX-NEXT:    lfs 2, .LCPI4_0@toc@l(3)
+; NOVSX-NEXT:    fmr 9, 2
+; NOVSX-NEXT:    bc 12, 3, .LBB4_4
+; NOVSX-NEXT:  # %bb.3: # %entry
+; NOVSX-NEXT:    fmr 9, 10
+; NOVSX-NEXT:  .LBB4_4: # %entry
+; NOVSX-NEXT:    lwz 3, -80(1)
+; NOVSX-NEXT:    lwz 4, -76(1)
+; NOVSX-NEXT:    xoris 5, 3, 32768
+; NOVSX-NEXT:    or 5, 4, 5
+; NOVSX-NEXT:    cmpwi 5, 0
+; NOVSX-NEXT:    bc 12, 2, .LBB4_6
+; NOVSX-NEXT:  # %bb.5: # %entry
+; NOVSX-NEXT:    fmr 4, 9
+; NOVSX-NEXT:  .LBB4_6: # %entry
+; NOVSX-NEXT:    xoris 4, 4, 32768
+; NOVSX-NEXT:    or 3, 4, 3
+; NOVSX-NEXT:    cmpwi 3, 0
+; NOVSX-NEXT:    bc 12, 2, .LBB4_8
+; NOVSX-NEXT:  # %bb.7: # %entry
+; NOVSX-NEXT:    fmr 8, 4
+; NOVSX-NEXT:  .LBB4_8: # %entry
+; NOVSX-NEXT:    addis 3, 2, .LCPI4_1@toc@ha
+; NOVSX-NEXT:    lfs 4, .LCPI4_1@toc@l(3)
+; NOVSX-NEXT:    fcmpu 0, 9, 4
+; NOVSX-NEXT:    bc 12, 2, .LBB4_10
+; NOVSX-NEXT:  # %bb.9: # %entry
+; NOVSX-NEXT:    fmr 8, 9
+; NOVSX-NEXT:  .LBB4_10: # %entry
+; NOVSX-NEXT:    fcmpu 0, 6, 7
+; NOVSX-NEXT:    fmr 9, 6
+; NOVSX-NEXT:    stfs 8, -4(1)
+; NOVSX-NEXT:    bc 12, 0, .LBB4_12
+; NOVSX-NEXT:  # %bb.11: # %entry
+; NOVSX-NEXT:    fmr 9, 7
+; NOVSX-NEXT:  .LBB4_12: # %entry
+; NOVSX-NEXT:    fmr 8, 2
+; NOVSX-NEXT:    bc 12, 3, .LBB4_14
+; NOVSX-NEXT:  # %bb.13: # %entry
+; NOVSX-NEXT:    fmr 8, 9
+; NOVSX-NEXT:  .LBB4_14: # %entry
+; NOVSX-NEXT:    lwz 3, -72(1)
+; NOVSX-NEXT:    lwz 4, -68(1)
+; NOVSX-NEXT:    xoris 5, 3, 32768
+; NOVSX-NEXT:    or 5, 4, 5
+; NOVSX-NEXT:    cmpwi 5, 0
+; NOVSX-NEXT:    bc 12, 2, .LBB4_16
+; NOVSX-NEXT:  # %bb.15: # %entry
+; NOVSX-NEXT:    fmr 7, 8
+; NOVSX-NEXT:  .LBB4_16: # %entry
+; NOVSX-NEXT:    xoris 4, 4, 32768
+; NOVSX-NEXT:    or 3, 4, 3
+; NOVSX-NEXT:    cmpwi 3, 0
+; NOVSX-NEXT:    bc 12, 2, .LBB4_18
+; NOVSX-NEXT:  # %bb.17: # %entry
+; NOVSX-NEXT:    fmr 6, 7
+; NOVSX-NEXT:  .LBB4_18: # %entry
+; NOVSX-NEXT:    fcmpu 0, 8, 4
+; NOVSX-NEXT:    bc 12, 2, .LBB4_20
+; NOVSX-NEXT:  # %bb.19: # %entry
+; NOVSX-NEXT:    fmr 6, 8
+; NOVSX-NEXT:  .LBB4_20: # %entry
+; NOVSX-NEXT:    fcmpu 0, 3, 5
+; NOVSX-NEXT:    fmr 7, 3
+; NOVSX-NEXT:    stfs 6, -8(1)
+; NOVSX-NEXT:    bc 12, 0, .LBB4_22
+; NOVSX-NEXT:  # %bb.21: # %entry
+; NOVSX-NEXT:    fmr 7, 5
+; NOVSX-NEXT:  .LBB4_22: # %entry
+; NOVSX-NEXT:    fmr 6, 2
+; NOVSX-NEXT:    bc 12, 3, .LBB4_24
+; NOVSX-NEXT:  # %bb.23: # %entry
+; NOVSX-NEXT:    fmr 6, 7
+; NOVSX-NEXT:  .LBB4_24: # %entry
+; NOVSX-NEXT:    lwz 3, -64(1)
+; NOVSX-NEXT:    lwz 4, -60(1)
+; NOVSX-NEXT:    xoris 5, 3, 32768
+; NOVSX-NEXT:    or 5, 4, 5
+; NOVSX-NEXT:    cmpwi 5, 0
+; NOVSX-NEXT:    bc 12, 2, .LBB4_26
+; NOVSX-NEXT:  # %bb.25: # %entry
+; NOVSX-NEXT:    fmr 5, 6
+; NOVSX-NEXT:  .LBB4_26: # %entry
+; NOVSX-NEXT:    xoris 4, 4, 32768
+; NOVSX-NEXT:    or 3, 4, 3
+; NOVSX-NEXT:    cmpwi 3, 0
+; NOVSX-NEXT:    bc 12, 2, .LBB4_28
+; NOVSX-NEXT:  # %bb.27: # %entry
+; NOVSX-NEXT:    fmr 3, 5
+; NOVSX-NEXT:  .LBB4_28: # %entry
+; NOVSX-NEXT:    fcmpu 0, 6, 4
+; NOVSX-NEXT:    bc 12, 2, .LBB4_30
+; NOVSX-NEXT:  # %bb.29: # %entry
+; NOVSX-NEXT:    fmr 3, 6
+; NOVSX-NEXT:  .LBB4_30: # %entry
+; NOVSX-NEXT:    fcmpu 0, 0, 1
+; NOVSX-NEXT:    stfs 3, -12(1)
+; NOVSX-NEXT:    fmr 3, 0
+; NOVSX-NEXT:    bc 12, 0, .LBB4_32
+; NOVSX-NEXT:  # %bb.31: # %entry
+; NOVSX-NEXT:    fmr 3, 1
+; NOVSX-NEXT:  .LBB4_32: # %entry
+; NOVSX-NEXT:    bc 12, 3, .LBB4_34
+; NOVSX-NEXT:  # %bb.33: # %entry
+; NOVSX-NEXT:    fmr 2, 3
+; NOVSX-NEXT:  .LBB4_34: # %entry
+; NOVSX-NEXT:    lwz 3, -56(1)
+; NOVSX-NEXT:    lwz 4, -52(1)
+; NOVSX-NEXT:    xoris 5, 3, 32768
+; NOVSX-NEXT:    or 5, 4, 5
+; NOVSX-NEXT:    cmpwi 5, 0
+; NOVSX-NEXT:    bc 12, 2, .LBB4_36
+; NOVSX-NEXT:  # %bb.35: # %entry
+; NOVSX-NEXT:    fmr 1, 2
+; NOVSX-NEXT:  .LBB4_36: # %entry
+; NOVSX-NEXT:    xoris 4, 4, 32768
+; NOVSX-NEXT:    or 3, 4, 3
+; NOVSX-NEXT:    cmpwi 3, 0
+; NOVSX-NEXT:    bc 12, 2, .LBB4_38
+; NOVSX-NEXT:  # %bb.37: # %entry
+; NOVSX-NEXT:    fmr 0, 1
+; NOVSX-NEXT:  .LBB4_38: # %entry
+; NOVSX-NEXT:    fcmpu 0, 2, 4
+; NOVSX-NEXT:    bc 12, 2, .LBB4_40
+; NOVSX-NEXT:  # %bb.39: # %entry
+; NOVSX-NEXT:    fmr 0, 2
+; NOVSX-NEXT:  .LBB4_40: # %entry
+; NOVSX-NEXT:    stfs 0, -16(1)
+; NOVSX-NEXT:    addi 3, 1, -16
+; NOVSX-NEXT:    lvx 2, 0, 3
+; NOVSX-NEXT:    blr
+;
+; VSX-LABEL: v4f32_minimum:
+; VSX:       # %bb.0: # %entry
+; VSX-NEXT:    xxsldwi 0, 35, 35, 3
+; VSX-NEXT:    xxsldwi 1, 34, 34, 3
+; VSX-NEXT:    addis 3, 2, .LCPI4_0@toc@ha
+; VSX-NEXT:    xscvspdpn 2, 0
+; VSX-NEXT:    lfs 0, .LCPI4_0@toc@l(3)
+; VSX-NEXT:    xscvspdpn 1, 1
+; VSX-NEXT:    fmr 3, 0
+; VSX-NEXT:    fcmpu 0, 1, 2
+; VSX-NEXT:    bc 12, 3, .LBB4_2
+; VSX-NEXT:  # %bb.1: # %entry
+; VSX-NEXT:    xsmindp 3, 1, 2
+; VSX-NEXT:  .LBB4_2: # %entry
+; VSX-NEXT:    xscvdpspn 4, 2
+; VSX-NEXT:    xscvdpspn 5, 1
+; VSX-NEXT:    mffprwz 3, 4
+; VSX-NEXT:    mffprwz 4, 5
+; VSX-NEXT:    xoris 5, 3, 32768
+; VSX-NEXT:    or 5, 4, 5
+; VSX-NEXT:    cmpwi 5, 0
+; VSX-NEXT:    bc 12, 2, .LBB4_4
+; VSX-NEXT:  # %bb.3: # %entry
+; VSX-NEXT:    fmr 2, 3
+; VSX-NEXT:  .LBB4_4: # %entry
+; VSX-NEXT:    xoris 4, 4, 32768
+; VSX-NEXT:    or 3, 4, 3
+; VSX-NEXT:    cmpwi 3, 0
+; VSX-NEXT:    bc 12, 2, .LBB4_6
+; VSX-NEXT:  # %bb.5: # %entry
+; VSX-NEXT:    fmr 1, 2
+; VSX-NEXT:  .LBB4_6: # %entry
+; VSX-NEXT:    xxlxor 2, 2, 2
+; VSX-NEXT:    fcmpu 0, 3, 2
+; VSX-NEXT:    bc 12, 2, .LBB4_8
+; VSX-NEXT:  # %bb.7: # %entry
+; VSX-NEXT:    fmr 1, 3
+; VSX-NEXT:  .LBB4_8: # %entry
+; VSX-NEXT:    xxsldwi 3, 35, 35, 1
+; VSX-NEXT:    xxsldwi 4, 34, 34, 1
+; VSX-NEXT:    xscvspdpn 5, 3
+; VSX-NEXT:    xscvspdpn 3, 4
+; VSX-NEXT:    fmr 4, 0
+; VSX-NEXT:    fcmpu 0, 3, 5
+; VSX-NEXT:    bc 12, 3, .LBB4_10
+; VSX-NEXT:  # %bb.9: # %entry
+; VSX-NEXT:    xsmindp 4, 3, 5
+; VSX-NEXT:  .LBB4_10: # %entry
+; VSX-NEXT:    xscvdpspn 6, 5
+; VSX-NEXT:    xscvdpspn 7, 3
+; VSX-NEXT:    mffprwz 3, 6
+; VSX-NEXT:    mffprwz 4, 7
+; VSX-NEXT:    xoris 5, 3, 32768
+; VSX-NEXT:    or 5, 4, 5
+; VSX-NEXT:    cmpwi 5, 0
+; VSX-NEXT:    bc 12, 2, .LBB4_12
+; VSX-NEXT:  # %bb.11: # %entry
+; VSX-NEXT:    fmr 5, 4
+; VSX-NEXT:  .LBB4_12: # %entry
+; VSX-NEXT:    xoris 4, 4, 32768
+; VSX-NEXT:    or 3, 4, 3
+; VSX-NEXT:    cmpwi 3, 0
+; VSX-NEXT:    bc 12, 2, .LBB4_14
+; VSX-NEXT:  # %bb.13: # %entry
+; VSX-NEXT:    fmr 3, 5
+; VSX-NEXT:  .LBB4_14: # %entry
+; VSX-NEXT:    fcmpu 0, 4, 2
+; VSX-NEXT:    bc 12, 2, .LBB4_16
+; VSX-NEXT:  # %bb.15: # %entry
+; VSX-NEXT:    fmr 3, 4
+; VSX-NEXT:  .LBB4_16: # %entry
+; VSX-NEXT:    xscvspdpn 6, 35
+; VSX-NEXT:    fmr 5, 0
+; VSX-NEXT:    xscvspdpn 4, 34
+; VSX-NEXT:    fcmpu 0, 4, 6
+; VSX-NEXT:    bc 12, 3, .LBB4_18
+; VSX-NEXT:  # %bb.17: # %entry
+; VSX-NEXT:    xsmindp 5, 4, 6
+; VSX-NEXT:  .LBB4_18: # %entry
+; VSX-NEXT:    xscvdpspn 7, 6
+; VSX-NEXT:    xscvdpspn 8, 4
+; VSX-NEXT:    mffprwz 3, 7
+; VSX-NEXT:    mffprwz 4, 8
+; VSX-NEXT:    xoris 5, 3, 32768
+; VSX-NEXT:    or 5, 4, 5
+; VSX-NEXT:    cmpwi 5, 0
+; VSX-NEXT:    bc 12, 2, .LBB4_20
+; VSX-NEXT:  # %bb.19: # %entry
+; VSX-NEXT:    fmr 6, 5
+; VSX-NEXT:  .LBB4_20: # %entry
+; VSX-NEXT:    xoris 4, 4, 32768
+; VSX-NEXT:    or 3, 4, 3
+; VSX-NEXT:    cmpwi 3, 0
+; VSX-NEXT:    bc 12, 2, .LBB4_22
+; VSX-NEXT:  # %bb.21: # %entry
+; VSX-NEXT:    fmr 4, 6
+; VSX-NEXT:  .LBB4_22: # %entry
+; VSX-NEXT:    fcmpu 0, 5, 2
+; VSX-NEXT:    bc 12, 2, .LBB4_24
+; VSX-NEXT:  # %bb.23: # %entry
+; VSX-NEXT:    fmr 4, 5
+; VSX-NEXT:  .LBB4_24: # %entry
+; VSX-NEXT:    xxswapd 5, 35
+; VSX-NEXT:    xxswapd 7, 34
+; VSX-NEXT:    xscvspdpn 6, 5
+; VSX-NEXT:    xscvspdpn 5, 7
+; VSX-NEXT:    fcmpu 0, 5, 6
+; VSX-NEXT:    bc 12, 3, .LBB4_26
+; VSX-NEXT:  # %bb.25: # %entry
+; VSX-NEXT:    xsmindp 0, 5, 6
+; VSX-NEXT:  .LBB4_26: # %entry
+; VSX-NEXT:    xscvdpspn 7, 6
+; VSX-NEXT:    xscvdpspn 8, 5
+; VSX-NEXT:    mffprwz 3, 7
+; VSX-NEXT:    mffprwz 4, 8
+; VSX-NEXT:    xoris 5, 3, 32768
+; VSX-NEXT:    or 5, 4, 5
+; VSX-NEXT:    cmpwi 5, 0
+; VSX-NEXT:    bc 12, 2, .LBB4_28
+; VSX-NEXT:  # %bb.27: # %entry
+; VSX-NEXT:    fmr 6, 0
+; VSX-NEXT:  .LBB4_28: # %entry
+; VSX-NEXT:    xoris 4, 4, 32768
+; VSX-NEXT:    xxmrghd 1, 3, 1
+; VSX-NEXT:    or 3, 4, 3
+; VSX-NEXT:    cmpwi 3, 0
+; VSX-NEXT:    bc 12, 2, .LBB4_30
+; VSX-NEXT:  # %bb.29: # %entry
+; VSX-NEXT:    fmr 5, 6
+; VSX-NEXT:  .LBB4_30: # %entry
+; VSX-NEXT:    fcmpu 0, 0, 2
+; VSX-NEXT:    xvcvdpsp 34, 1
+; VSX-NEXT:    bc 12, 2, .LBB4_32
+; VSX-NEXT:  # %bb.31: # %entry
+; VSX-NEXT:    fmr 5, 0
+; VSX-NEXT:  .LBB4_32: # %entry
+; VSX-NEXT:    xxmrghd 0, 4, 5
+; VSX-NEXT:    xvcvdpsp 35, 0
+; VSX-NEXT:    vmrgew 2, 3, 2
+; VSX-NEXT:    blr
+;
+; AIX-LABEL: v4f32_minimum:
+; AIX:       # %bb.0: # %entry
+; AIX-NEXT:    xxsldwi 0, 35, 35, 3
+; AIX-NEXT:    xxsldwi 1, 34, 34, 3
+; AIX-NEXT:    ld 3, L..C4(2) # %const.0
+; AIX-NEXT:    xscvspdpn 2, 0
+; AIX-NEXT:    lfs 0, 0(3)
+; AIX-NEXT:    xscvspdpn 1, 1
+; AIX-NEXT:    fmr 3, 0
+; AIX-NEXT:    fcmpu 0, 1, 2
+; AIX-NEXT:    bc 12, 3, L..BB4_2
+; AIX-NEXT:  # %bb.1: # %entry
+; AIX-NEXT:    xsmindp 3, 1, 2
+; AIX-NEXT:  L..BB4_2: # %entry
+; AIX-NEXT:    xscvdpspn 4, 2
+; AIX-NEXT:    xscvdpspn 5, 1
+; AIX-NEXT:    mffprwz 3, 4
+; AIX-NEXT:    mffprwz 4, 5
+; AIX-NEXT:    xoris 5, 3, 32768
+; AIX-NEXT:    or 5, 4, 5
+; AIX-NEXT:    cmpwi 5, 0
+; AIX-NEXT:    bc 12, 2, L..BB4_4
+; AIX-NEXT:  # %bb.3: # %entry
+; AIX-NEXT:    fmr 2, 3
+; AIX-NEXT:  L..BB4_4: # %entry
+; AIX-NEXT:    xoris 4, 4, 32768
+; AIX-NEXT:    or 3, 4, 3
+; AIX-NEXT:    cmpwi 3, 0
+; AIX-NEXT:    bc 12, 2, L..BB4_6
+; AIX-NEXT:  # %bb.5: # %entry
+; AIX-NEXT:    fmr 1, 2
+; AIX-NEXT:  L..BB4_6: # %entry
+; AIX-NEXT:    xxlxor 2, 2, 2
+; AIX-NEXT:    fcmpu 0, 3, 2
+; AIX-NEXT:    bc 12, 2, L..BB4_8
+; AIX-NEXT:  # %bb.7: # %entry
+; AIX-NEXT:    fmr 1, 3
+; AIX-NEXT:  L..BB4_8: # %entry
+; AIX-NEXT:    xxsldwi 3, 35, 35, 1
+; AIX-NEXT:    xxsldwi 4, 34, 34, 1
+; AIX-NEXT:    xscvspdpn 5, 3
+; AIX-NEXT:    xscvspdpn 3, 4
+; AIX-NEXT:    fmr 4, 0
+; AIX-NEXT:    fcmpu 0, 3, 5
+; AIX-NEXT:    bc 12, 3, L..BB4_10
+; AIX-NEXT:  # %bb.9: # %entry
+; AIX-NEXT:    xsmindp 4, 3, 5
+; AIX-NEXT:  L..BB4_10: # %entry
+; AIX-NEXT:    xscvdpspn 6, 5
+; AIX-NEXT:    xscvdpspn 7, 3
+; AIX-NEXT:    mffprwz 3, 6
+; AIX-NEXT:    mffprwz 4, 7
+; AIX-NEXT:    xoris 5, 3, 32768
+; AIX-NEXT:    or 5, 4, 5
+; AIX-NEXT:    cmpwi 5, 0
+; AIX-NEXT:    bc 12, 2, L..BB4_12
+; AIX-NEXT:  # %bb.11: # %entry
+; AIX-NEXT:    fmr 5, 4
+; AIX-NEXT:  L..BB4_12: # %entry
+; AIX-NEXT:    xoris 4, 4, 32768
+; AIX-NEXT:    or 3, 4, 3
+; AIX-NEXT:    cmpwi 3, 0
+; AIX-NEXT:    bc 12, 2, L..BB4_14
+; AIX-NEXT:  # %bb.13: # %entry
+; AIX-NEXT:    fmr 3, 5
+; AIX-NEXT:  L..BB4_14: # %entry
+; AIX-NEXT:    fcmpu 0, 4, 2
+; AIX-NEXT:    bc 12, 2, L..BB4_16
+; AIX-NEXT:  # %bb.15: # %entry
+; AIX-NEXT:    fmr 3, 4
+; AIX-NEXT:  L..BB4_16: # %entry
+; AIX-NEXT:    xscvspdpn 6, 35
+; AIX-NEXT:    fmr 5, 0
+; AIX-NEXT:    xscvspdpn 4, 34
+; AIX-NEXT:    fcmpu 0, 4, 6
+; AIX-NEXT:    bc 12, 3, L..BB4_18
+; AIX-NEXT:  # %bb.17: # %entry
+; AIX-NEXT:    xsmindp 5, 4, 6
+; AIX-NEXT:  L..BB4_18: # %entry
+; AIX-NEXT:    xscvdpspn 7, 6
+; AIX-NEXT:    xscvdpspn 8, 4
+; AIX-NEXT:    mffprwz 3, 7
+; AIX-NEXT:    mffprwz 4, 8
+; AIX-NEXT:    xoris 5, 3, 32768
+; AIX-NEXT:    or 5, 4, 5
+; AIX-NEXT:    cmpwi 5, 0
+; AIX-NEXT:    bc 12, 2, L..BB4_20
+; AIX-NEXT:  # %bb.19: # %entry
+; AIX-NEXT:    fmr 6, 5
+; AIX-NEXT:  L..BB4_20: # %entry
+; AIX-NEXT:    xoris 4, 4, 32768
+; AIX-NEXT:    or 3, 4, 3
+; AIX-NEXT:    cmpwi 3, 0
+; AIX-NEXT:    bc 12, 2, L..BB4_22
+; AIX-NEXT:  # %bb.21: # %entry
+; AIX-NEXT:    fmr 4, 6
+; AIX-NEXT:  L..BB4_22: # %entry
+; AIX-NEXT:    fcmpu 0, 5, 2
+; AIX-NEXT:    bc 12, 2, L..BB4_24
+; AIX-NEXT:  # %bb.23: # %entry
+; AIX-NEXT:    fmr 4, 5
+; AIX-NEXT:  L..BB4_24: # %entry
+; AIX-NEXT:    xxswapd 5, 35
+; AIX-NEXT:    xxswapd 7, 34
+; AIX-NEXT:    xscvspdpn 6, 5
+; AIX-NEXT:    xscvspdpn 5, 7
+; AIX-NEXT:    fcmpu 0, 5, 6
+; AIX-NEXT:    bc 12, 3, L..BB4_26
+; AIX-NEXT:  # %bb.25: # %entry
+; AIX-NEXT:    xsmindp 0, 5, 6
+; AIX-NEXT:  L..BB4_26: # %entry
+; AIX-NEXT:    xscvdpspn 7, 6
+; AIX-NEXT:    xscvdpspn 8, 5
+; AIX-NEXT:    mffprwz 3, 7
+; AIX-NEXT:    mffprwz 4, 8
+; AIX-NEXT:    xoris 5, 3, 32768
+; AIX-NEXT:    or 5, 4, 5
+; AIX-NEXT:    cmpwi 5, 0
+; AIX-NEXT:    bc 12, 2, L..BB4_28
+; AIX-NEXT:  # %bb.27: # %entry
+; AIX-NEXT:    fmr 6, 0
+; AIX-NEXT:  L..BB4_28: # %entry
+; AIX-NEXT:    xoris 4, 4, 32768
+; AIX-NEXT:    xxmrghd 1, 3, 1
+; AIX-NEXT:    or 3, 4, 3
+; AIX-NEXT:    cmpwi 3, 0
+; AIX-NEXT:    bc 12, 2, L..BB4_30
+; AIX-NEXT:  # %bb.29: # %entry
+; AIX-NEXT:    fmr 5, 6
+; AIX-NEXT:  L..BB4_30: # %entry
+; AIX-NEXT:    fcmpu 0, 0, 2
+; AIX-NEXT:    xvcvdpsp 34, 1
+; AIX-NEXT:    bc 12, 2, L..BB4_32
+; AIX-NEXT:  # %bb.31: # %entry
+; AIX-NEXT:    fmr 5, 0
+; AIX-NEXT:  L..BB4_32: # %entry
+; AIX-NEXT:    xxmrghd 0, 4, 5
+; AIX-NEXT:    xvcvdpsp 35, 0
+; AIX-NEXT:    vmrgew 2, 3, 2
+; AIX-NEXT:    blr
+entry:
+  %m = call <4 x float> @llvm.minimum.v4f32(<4 x float> %a, <4 x float> %b)
+  ret <4 x float> %m
+}
+
+define <4 x float> @v4f32_maximum(<4 x float> %a, <4 x float> %b) {
+; NOVSX-LABEL: v4f32_maximum:
+; NOVSX:       # %bb.0: # %entry
+; NOVSX-NEXT:    addi 3, 1, -32
+; NOVSX-NEXT:    stvx 3, 0, 3
+; NOVSX-NEXT:    addi 3, 1, -48
+; NOVSX-NEXT:    stvx 2, 0, 3
+; NOVSX-NEXT:    lfs 8, -20(1)
+; NOVSX-NEXT:    lfs 4, -36(1)
+; NOVSX-NEXT:    lfs 6, -24(1)
+; NOVSX-NEXT:    lfs 7, -40(1)
+; NOVSX-NEXT:    lfs 3, -28(1)
+; NOVSX-NEXT:    lfs 5, -44(1)
+; NOVSX-NEXT:    lfs 0, -32(1)
+; NOVSX-NEXT:    stfs 8, -80(1)
+; NOVSX-NEXT:    fcmpu 0, 4, 8
+; NOVSX-NEXT:    fmr 10, 4
+; NOVSX-NEXT:    lfs 1, -48(1)
+; NOVSX-NEXT:    stfs 4, -76(1)
+; NOVSX-NEXT:    stfs 6, -72(1)
+; NOVSX-NEXT:    stfs 7, -68(1)
+; NOVSX-NEXT:    stfs 3, -64(1)
+; NOVSX-NEXT:    stfs 5, -60(1)
+; NOVSX-NEXT:    stfs 0, -56(1)
+; NOVSX-NEXT:    stfs 1, -52(1)
+; NOVSX-NEXT:    bc 12, 1, .LBB5_2
+; NOVSX-NEXT:  # %bb.1: # %entry
+; NOVSX-NEXT:    fmr 10, 8
+; NOVSX-NEXT:  .LBB5_2: # %entry
+; NOVSX-NEXT:    addis 3, 2, .LCPI5_0@toc@ha
+; NOVSX-NEXT:    lfs 2, .LCPI5_0@toc@l(3)
+; NOVSX-NEXT:    fmr 9, 2
+; NOVSX-NEXT:    bc 12, 3, .LBB5_4
+; NOVSX-NEXT:  # %bb.3: # %entry
+; NOVSX-NEXT:    fmr 9, 10
+; NOVSX-NEXT:  .LBB5_4: # %entry
+; NOVSX-NEXT:    lwz 3, -80(1)
+; NOVSX-NEXT:    lwz 4, -76(1)
+; NOVSX-NEXT:    xoris 5, 3, 32768
+; NOVSX-NEXT:    or 5, 4, 5
+; NOVSX-NEXT:    cmpwi 5, 0
+; NOVSX-NEXT:    bc 12, 2, .LBB5_6
+; NOVSX-NEXT:  # %bb.5: # %entry
+; NOVSX-NEXT:    fmr 4, 9
+; NOVSX-NEXT:  .LBB5_6: # %entry
+; NOVSX-NEXT:    xoris 4, 4, 32768
+; NOVSX-NEXT:    or 3, 4, 3
+; NOVSX-NEXT:    cmpwi 3, 0
+; NOVSX-NEXT:    bc 12, 2, .LBB5_8
+; NOVSX-NEXT:  # %bb.7: # %entry
+; NOVSX-NEXT:    fmr 8, 4
+; NOVSX-NEXT:  .LBB5_8: # %entry
+; NOVSX-NEXT:    addis 3, 2, .LCPI5_1@toc@ha
+; NOVSX-NEXT:    lfs 4, .LCPI5_1@toc@l(3)
+; NOVSX-NEXT:    fcmpu 0, 9, 4
+; NOVSX-NEXT:    bc 12, 2, .LBB5_10
+; NOVSX-NEXT:  # %bb.9: # %entry
+; NOVSX-NEXT:    fmr 8, 9
+; NOVSX-NEXT:  .LBB5_10: # %entry
+; NOVSX-NEXT:    fcmpu 0, 7, 6
+; NOVSX-NEXT:    fmr 9, 7
+; NOVSX-NEXT:    stfs 8, -4(1)
+; NOVSX-NEXT:    bc 12, 1, .LBB5_12
+; NOVSX-NEXT:  # %bb.11: # %entry
+; NOVSX-NEXT:    fmr 9, 6
+; NOVSX-NEXT:  .LBB5_12: # %entry
+; NOVSX-NEXT:    fmr 8, 2
+; NOVSX-NEXT:    bc 12, 3, .LBB5_14
+; NOVSX-NEXT:  # %bb.13: # %entry
+; NOVSX-NEXT:    fmr 8, 9
+; NOVSX-NEXT:  .LBB5_14: # %entry
+; NOVSX-NEXT:    lwz 3, -72(1)
+; NOVSX-NEXT:    lwz 4, -68(1)
+; NOVSX-NEXT:    xoris 5, 3, 32768
+; NOVSX-NEXT:    or 5, 4, 5
+; NOVSX-NEXT:    cmpwi 5, 0
+; NOVSX-NEXT:    bc 12, 2, .LBB5_16
+; NOVSX-NEXT:  # %bb.15: # %entry
+; NOVSX-NEXT:    fmr 7, 8
+; NOVSX-NEXT:  .LBB5_16: # %entry
+; NOVSX-NEXT:    xoris 4, 4, 32768
+; NOVSX-NEXT:    or 3, 4, 3
+; NOVSX-NEXT:    cmpwi 3, 0
+; NOVSX-NEXT:    bc 12, 2, .LBB5_18
+; NOVSX-NEXT:  # %bb.17: # %entry
+; NOVSX-NEXT:    fmr 6, 7
+; NOVSX-NEXT:  .LBB5_18: # %entry
+; NOVSX-NEXT:    fcmpu 0, 8, 4
+; NOVSX-NEXT:    bc 12, 2, .LBB5_20
+; NOVSX-NEXT:  # %bb.19: # %entry
+; NOVSX-NEXT:    fmr 6, 8
+; NOVSX-NEXT:  .LBB5_20: # %entry
+; NOVSX-NEXT:    fcmpu 0, 5, 3
+; NOVSX-NEXT:    fmr 7, 5
+; NOVSX-NEXT:    stfs 6, -8(1)
+; NOVSX-NEXT:    bc 12, 1, .LBB5_22
+; NOVSX-NEXT:  # %bb.21: # %entry
+; NOVSX-NEXT:    fmr 7, 3
+; NOVSX-NEXT:  .LBB5_22: # %entry
+; NOVSX-NEXT:    fmr 6, 2
+; NOVSX-NEXT:    bc 12, 3, .LBB5_24
+; NOVSX-NEXT:  # %bb.23: # %entry
+; NOVSX-NEXT:    fmr 6, 7
+; NOVSX-NEXT:  .LBB5_24: # %entry
+; NOVSX-NEXT:    lwz 3, -64(1)
+; NOVSX-NEXT:    lwz 4, -60(1)
+; NOVSX-NEXT:    xoris 5, 3, 32768
+; NOVSX-NEXT:    or 5, 4, 5
+; NOVSX-NEXT:    cmpwi 5, 0
+; NOVSX-NEXT:    bc 12, 2, .LBB5_26
+; NOVSX-NEXT:  # %bb.25: # %entry
+; NOVSX-NEXT:    fmr 5, 6
+; NOVSX-NEXT:  .LBB5_26: # %entry
+; NOVSX-NEXT:    xoris 4, 4, 32768
+; NOVSX-NEXT:    or 3, 4, 3
+; NOVSX-NEXT:    cmpwi 3, 0
+; NOVSX-NEXT:    bc 12, 2, .LBB5_28
+; NOVSX-NEXT:  # %bb.27: # %entry
+; NOVSX-NEXT:    fmr 3, 5
+; NOVSX-NEXT:  .LBB5_28: # %entry
+; NOVSX-NEXT:    fcmpu 0, 6, 4
+; NOVSX-NEXT:    bc 12, 2, .LBB5_30
+; NOVSX-NEXT:  # %bb.29: # %entry
+; NOVSX-NEXT:    fmr 3, 6
+; NOVSX-NEXT:  .LBB5_30: # %entry
+; NOVSX-NEXT:    fcmpu 0, 1, 0
+; NOVSX-NEXT:    stfs 3, -12(1)
+; NOVSX-NEXT:    fmr 3, 1
+; NOVSX-NEXT:    bc 12, 1, .LBB5_32
+; NOVSX-NEXT:  # %bb.31: # %entry
+; NOVSX-NEXT:    fmr 3, 0
+; NOVSX-NEXT:  .LBB5_32: # %entry
+; NOVSX-NEXT:    bc 12, 3, .LBB5_34
+; NOVSX-NEXT:  # %bb.33: # %entry
+; NOVSX-NEXT:    fmr 2, 3
+; NOVSX-NEXT:  .LBB5_34: # %entry
+; NOVSX-NEXT:    lwz 3, -56(1)
+; NOVSX-NEXT:    lwz 4, -52(1)
+; NOVSX-NEXT:    xoris 5, 3, 32768
+; NOVSX-NEXT:    or 5, 4, 5
+; NOVSX-NEXT:    cmpwi 5, 0
+; NOVSX-NEXT:    bc 12, 2, .LBB5_36
+; NOVSX-NEXT:  # %bb.35: # %entry
+; NOVSX-NEXT:    fmr 1, 2
+; NOVSX-NEXT:  .LBB5_36: # %entry
+; NOVSX-NEXT:    xoris 4, 4, 32768
+; NOVSX-NEXT:    or 3, 4, 3
+; NOVSX-NEXT:    cmpwi 3, 0
+; NOVSX-NEXT:    bc 12, 2, .LBB5_38
+; NOVSX-NEXT:  # %bb.37: # %entry
+; NOVSX-NEXT:    fmr 0, 1
+; NOVSX-NEXT:  .LBB5_38: # %entry
+; NOVSX-NEXT:    fcmpu 0, 2, 4
+; NOVSX-NEXT:    bc 12, 2, .LBB5_40
+; NOVSX-NEXT:  # %bb.39: # %entry
+; NOVSX-NEXT:    fmr 0, 2
+; NOVSX-NEXT:  .LBB5_40: # %entry
+; NOVSX-NEXT:    stfs 0, -16(1)
+; NOVSX-NEXT:    addi 3, 1, -16
+; NOVSX-NEXT:    lvx 2, 0, 3
+; NOVSX-NEXT:    blr
+;
+; VSX-LABEL: v4f32_maximum:
+; VSX:       # %bb.0: # %entry
+; VSX-NEXT:    xxsldwi 0, 35, 35, 3
+; VSX-NEXT:    xxsldwi 2, 34, 34, 3
+; VSX-NEXT:    addis 3, 2, .LCPI5_0@toc@ha
+; VSX-NEXT:    xscvspdpn 1, 0
+; VSX-NEXT:    lfs 0, .LCPI5_0@toc@l(3)
+; VSX-NEXT:    xscvspdpn 2, 2
+; VSX-NEXT:    fmr 3, 0
+; VSX-NEXT:    fcmpu 0, 2, 1
+; VSX-NEXT:    bc 12, 3, .LBB5_2
+; VSX-NEXT:  # %bb.1: # %entry
+; VSX-NEXT:    xsmaxdp 3, 2, 1
+; VSX-NEXT:  .LBB5_2: # %entry
+; VSX-NEXT:    xscvdpspn 4, 1
+; VSX-NEXT:    xscvdpspn 5, 2
+; VSX-NEXT:    mffprwz 3, 4
+; VSX-NEXT:    mffprwz 4, 5
+; VSX-NEXT:    xoris 5, 3, 32768
+; VSX-NEXT:    or 5, 4, 5
+; VSX-NEXT:    cmpwi 5, 0
+; VSX-NEXT:    bc 12, 2, .LBB5_4
+; VSX-NEXT:  # %bb.3: # %entry
+; VSX-NEXT:    fmr 2, 3
+; VSX-NEXT:  .LBB5_4: # %entry
+; VSX-NEXT:    xoris 4, 4, 32768
+; VSX-NEXT:    or 3, 4, 3
+; VSX-NEXT:    cmpwi 3, 0
+; VSX-NEXT:    bc 12, 2, .LBB5_6
+; VSX-NEXT:  # %bb.5: # %entry
+; VSX-NEXT:    fmr 1, 2
+; VSX-NEXT:  .LBB5_6: # %entry
+; VSX-NEXT:    xxlxor 2, 2, 2
+; VSX-NEXT:    fcmpu 0, 3, 2
+; VSX-NEXT:    bc 12, 2, .LBB5_8
+; VSX-NEXT:  # %bb.7: # %entry
+; VSX-NEXT:    fmr 1, 3
+; VSX-NEXT:  .LBB5_8: # %entry
+; VSX-NEXT:    xxsldwi 3, 35, 35, 1
+; VSX-NEXT:    xxsldwi 4, 34, 34, 1
+; VSX-NEXT:    xscvspdpn 3, 3
+; VSX-NEXT:    xscvspdpn 5, 4
+; VSX-NEXT:    fmr 4, 0
+; VSX-NEXT:    fcmpu 0, 5, 3
+; VSX-NEXT:    bc 12, 3, .LBB5_10
+; VSX-NEXT:  # %bb.9: # %entry
+; VSX-NEXT:    xsmaxdp 4, 5, 3
+; VSX-NEXT:  .LBB5_10: # %entry
+; VSX-NEXT:    xscvdpspn 6, 3
+; VSX-NEXT:    xscvdpspn 7, 5
+; VSX-NEXT:    mffprwz 3, 6
+; VSX-NEXT:    mffprwz 4, 7
+; VSX-NEXT:    xoris 5, 3, 32768
+; VSX-NEXT:    or 5, 4, 5
+; VSX-NEXT:    cmpwi 5, 0
+; VSX-NEXT:    bc 12, 2, .LBB5_12
+; VSX-NEXT:  # %bb.11: # %entry
+; VSX-NEXT:    fmr 5, 4
+; VSX-NEXT:  .LBB5_12: # %entry
+; VSX-NEXT:    xoris 4, 4, 32768
+; VSX-NEXT:    or 3, 4, 3
+; VSX-NEXT:    cmpwi 3, 0
+; VSX-NEXT:    bc 12, 2, .LBB5_14
+; VSX-NEXT:  # %bb.13: # %entry
+; VSX-NEXT:    fmr 3, 5
+; VSX-NEXT:  .LBB5_14: # %entry
+; VSX-NEXT:    fcmpu 0, 4, 2
+; VSX-NEXT:    bc 12, 2, .LBB5_16
+; VSX-NEXT:  # %bb.15: # %entry
+; VSX-NEXT:    fmr 3, 4
+; VSX-NEXT:  .LBB5_16: # %entry
+; VSX-NEXT:    xscvspdpn 4, 35
+; VSX-NEXT:    fmr 5, 0
+; VSX-NEXT:    xscvspdpn 6, 34
+; VSX-NEXT:    fcmpu 0, 6, 4
+; VSX-NEXT:    bc 12, 3, .LBB5_18
+; VSX-NEXT:  # %bb.17: # %entry
+; VSX-NEXT:    xsmaxdp 5, 6, 4
+; VSX-NEXT:  .LBB5_18: # %entry
+; VSX-NEXT:    xscvdpspn 7, 4
+; VSX-NEXT:    xscvdpspn 8, 6
+; VSX-NEXT:    mffprwz 3, 7
+; VSX-NEXT:    mffprwz 4, 8
+; VSX-NEXT:    xoris 5, 3, 32768
+; VSX-NEXT:    or 5, 4, 5
+; VSX-NEXT:    cmpwi 5, 0
+; VSX-NEXT:    bc 12, 2, .LBB5_20
+; VSX-NEXT:  # %bb.19: # %entry
+; VSX-NEXT:    fmr 6, 5
+; VSX-NEXT:  .LBB5_20: # %entry
+; VSX-NEXT:    xoris 4, 4, 32768
+; VSX-NEXT:    or 3, 4, 3
+; VSX-NEXT:    cmpwi 3, 0
+; VSX-NEXT:    bc 12, 2, .LBB5_22
+; VSX-NEXT:  # %bb.21: # %entry
+; VSX-NEXT:    fmr 4, 6
+; VSX-NEXT:  .LBB5_22: # %entry
+; VSX-NEXT:    fcmpu 0, 5, 2
+; VSX-NEXT:    bc 12, 2, .LBB5_24
+; VSX-NEXT:  # %bb.23: # %entry
+; VSX-NEXT:    fmr 4, 5
+; VSX-NEXT:  .LBB5_24: # %entry
+; VSX-NEXT:    xxswapd 5, 35
+; VSX-NEXT:    xxswapd 6, 34
+; VSX-NEXT:    xscvspdpn 5, 5
+; VSX-NEXT:    xscvspdpn 6, 6
+; VSX-NEXT:    fcmpu 0, 6, 5
+; VSX-NEXT:    bc 12, 3, .LBB5_26
+; VSX-NEXT:  # %bb.25: # %entry
+; VSX-NEXT:    xsmaxdp 0, 6, 5
+; VSX-NEXT:  .LBB5_26: # %entry
+; VSX-NEXT:    xscvdpspn 7, 5
+; VSX-NEXT:    xscvdpspn 8, 6
+; VSX-NEXT:    mffprwz 3, 7
+; VSX-NEXT:    mffprwz 4, 8
+; VSX-NEXT:    xoris 5, 3, 32768
+; VSX-NEXT:    or 5, 4, 5
+; VSX-NEXT:    cmpwi 5, 0
+; VSX-NEXT:    bc 12, 2, .LBB5_28
+; VSX-NEXT:  # %bb.27: # %entry
+; VSX-NEXT:    fmr 6, 0
+; VSX-NEXT:  .LBB5_28: # %entry
+; VSX-NEXT:    xoris 4, 4, 32768
+; VSX-NEXT:    xxmrghd 1, 3, 1
+; VSX-NEXT:    or 3, 4, 3
+; VSX-NEXT:    cmpwi 3, 0
+; VSX-NEXT:    bc 12, 2, .LBB5_30
+; VSX-NEXT:  # %bb.29: # %entry
+; VSX-NEXT:    fmr 5, 6
+; VSX-NEXT:  .LBB5_30: # %entry
+; VSX-NEXT:    fcmpu 0, 0, 2
+; VSX-NEXT:    xvcvdpsp 34, 1
+; VSX-NEXT:    bc 12, 2, .LBB5_32
+; VSX-NEXT:  # %bb.31: # %entry
+; VSX-NEXT:    fmr 5, 0
+; VSX-NEXT:  .LBB5_32: # %entry
+; VSX-NEXT:    xxmrghd 0, 4, 5
+; VSX-NEXT:    xvcvdpsp 35, 0
+; VSX-NEXT:    vmrgew 2, 3, 2
+; VSX-NEXT:    blr
+;
+; AIX-LABEL: v4f32_maximum:
+; AIX:       # %bb.0: # %entry
+; AIX-NEXT:    xxsldwi 0, 35, 35, 3
+; AIX-NEXT:    xxsldwi 2, 34, 34, 3
+; AIX-NEXT:    ld 3, L..C5(2) # %const.0
+; AIX-NEXT:    xscvspdpn 1, 0
+; AIX-NEXT:    lfs 0, 0(3)
+; AIX-NEXT:    xscvspdpn 2, 2
+; AIX-NEXT:    fmr 3, 0
+; AIX-NEXT:    fcmpu 0, 2, 1
+; AIX-NEXT:    bc 12, 3, L..BB5_2
+; AIX-NEXT:  # %bb.1: # %entry
+; AIX-NEXT:    xsmaxdp 3, 2, 1
+; AIX-NEXT:  L..BB5_2: # %entry
+; AIX-NEXT:    xscvdpspn 4, 1
+; AIX-NEXT:    xscvdpspn 5, 2
+; AIX-NEXT:    mffprwz 3, 4
+; AIX-NEXT:    mffprwz 4, 5
+; AIX-NEXT:    xoris 5, 3, 32768
+; AIX-NEXT:    or 5, 4, 5
+; AIX-NEXT:    cmpwi 5, 0
+; AIX-NEXT:    bc 12, 2, L..BB5_4
+; AIX-NEXT:  # %bb.3: # %entry
+; AIX-NEXT:    fmr 2, 3
+; AIX-NEXT:  L..BB5_4: # %entry
+; AIX-NEXT:    xoris 4, 4, 32768
+; AIX-NEXT:    or 3, 4, 3
+; AIX-NEXT:    cmpwi 3, 0
+; AIX-NEXT:    bc 12, 2, L..BB5_6
+; AIX-NEXT:  # %bb.5: # %entry
+; AIX-NEXT:    fmr 1, 2
+; AIX-NEXT:  L..BB5_6: # %entry
+; AIX-NEXT:    xxlxor 2, 2, 2
+; AIX-NEXT:    fcmpu 0, 3, 2
+; AIX-NEXT:    bc 12, 2, L..BB5_8
+; AIX-NEXT:  # %bb.7: # %entry
+; AIX-NEXT:    fmr 1, 3
+; AIX-NEXT:  L..BB5_8: # %entry
+; AIX-NEXT:    xxsldwi 3, 35, 35, 1
+; AIX-NEXT:    xxsldwi 4, 34, 34, 1
+; AIX-NEXT:    xscvspdpn 3, 3
+; AIX-NEXT:    xscvspdpn 5, 4
+; AIX-NEXT:    fmr 4, 0
+; AIX-NEXT:    fcmpu 0, 5, 3
+; AIX-NEXT:    bc 12, 3, L..BB5_10
+; AIX-NEXT:  # %bb.9: # %entry
+; AIX-NEXT:    xsmaxdp 4, 5, 3
+; AIX-NEXT:  L..BB5_10: # %entry
+; AIX-NEXT:    xscvdpspn 6, 3
+; AIX-NEXT:    xscvdpspn 7, 5
+; AIX-NEXT:    mffprwz 3, 6
+; AIX-NEXT:    mffprwz 4, 7
+; AIX-NEXT:    xoris 5, 3, 32768
+; AIX-NEXT:    or 5, 4, 5
+; AIX-NEXT:    cmpwi 5, 0
+; AIX-NEXT:    bc 12, 2, L..BB5_12
+; AIX-NEXT:  # %bb.11: # %entry
+; AIX-NEXT:    fmr 5, 4
+; AIX-NEXT:  L..BB5_12: # %entry
+; AIX-NEXT:    xoris 4, 4, 32768
+; AIX-NEXT:    or 3, 4, 3
+; AIX-NEXT:    cmpwi 3, 0
+; AIX-NEXT:    bc 12, 2, L..BB5_14
+; AIX-NEXT:  # %bb.13: # %entry
+; AIX-NEXT:    fmr 3, 5
+; AIX-NEXT:  L..BB5_14: # %entry
+; AIX-NEXT:    fcmpu 0, 4, 2
+; AIX-NEXT:    bc 12, 2, L..BB5_16
+; AIX-NEXT:  # %bb.15: # %entry
+; AIX-NEXT:    fmr 3, 4
+; AIX-NEXT:  L..BB5_16: # %entry
+; AIX-NEXT:    xscvspdpn 4, 35
+; AIX-NEXT:    fmr 5, 0
+; AIX-NEXT:    xscvspdpn 6, 34
+; AIX-NEXT:    fcmpu 0, 6, 4
+; AIX-NEXT:    bc 12, 3, L..BB5_18
+; AIX-NEXT:  # %bb.17: # %entry
+; AIX-NEXT:    xsmaxdp 5, 6, 4
+; AIX-NEXT:  L..BB5_18: # %entry
+; AIX-NEXT:    xscvdpspn 7, 4
+; AIX-NEXT:    xscvdpspn 8, 6
+; AIX-NEXT:    mffprwz 3, 7
+; AIX-NEXT:    mffprwz 4, 8
+; AIX-NEXT:    xoris 5, 3, 32768
+; AIX-NEXT:    or 5, 4, 5
+; AIX-NEXT:    cmpwi 5, 0
+; AIX-NEXT:    bc 12, 2, L..BB5_20
+; AIX-NEXT:  # %bb.19: # %entry
+; AIX-NEXT:    fmr 6, 5
+; AIX-NEXT:  L..BB5_20: # %entry
+; AIX-NEXT:    xoris 4, 4, 32768
+; AIX-NEXT:    or 3, 4, 3
+; AIX-NEXT:    cmpwi 3, 0
+; AIX-NEXT:    bc 12, 2, L..BB5_22
+; AIX-NEXT:  # %bb.21: # %entry
+; AIX-NEXT:    fmr 4, 6
+; AIX-NEXT:  L..BB5_22: # %entry
+; AIX-NEXT:    fcmpu 0, 5, 2
+; AIX-NEXT:    bc 12, 2, L..BB5_24
+; AIX-NEXT:  # %bb.23: # %entry
+; AIX-NEXT:    fmr 4, 5
+; AIX-NEXT:  L..BB5_24: # %entry
+; AIX-NEXT:    xxswapd 5, 35
+; AIX-NEXT:    xxswapd 6, 34
+; AIX-NEXT:    xscvspdpn 5, 5
+; AIX-NEXT:    xscvspdpn 6, 6
+; AIX-NEXT:    fcmpu 0, 6, 5
+; AIX-NEXT:    bc 12, 3, L..BB5_26
+; AIX-NEXT:  # %bb.25: # %entry
+; AIX-NEXT:    xsmaxdp 0, 6, 5
+; AIX-NEXT:  L..BB5_26: # %entry
+; AIX-NEXT:    xscvdpspn 7, 5
+; AIX-NEXT:    xscvdpspn 8, 6
+; AIX-NEXT:    mffprwz 3, 7
+; AIX-NEXT:    mffprwz 4, 8
+; AIX-NEXT:    xoris 5, 3, 32768
+; AIX-NEXT:    or 5, 4, 5
+; AIX-NEXT:    cmpwi 5, 0
+; AIX-NEXT:    bc 12, 2, L..BB5_28
+; AIX-NEXT:  # %bb.27: # %entry
+; AIX-NEXT:    fmr 6, 0
+; AIX-NEXT:  L..BB5_28: # %entry
+; AIX-NEXT:    xoris 4, 4, 32768
+; AIX-NEXT:    xxmrghd 1, 3, 1
+; AIX-NEXT:    or 3, 4, 3
+; AIX-NEXT:    cmpwi 3, 0
+; AIX-NEXT:    bc 12, 2, L..BB5_30
+; AIX-NEXT:  # %bb.29: # %entry
+; AIX-NEXT:    fmr 5, 6
+; AIX-NEXT:  L..BB5_30: # %entry
+; AIX-NEXT:    fcmpu 0, 0, 2
+; AIX-NEXT:    xvcvdpsp 34, 1
+; AIX-NEXT:    bc 12, 2, L..BB5_32
+; AIX-NEXT:  # %bb.31: # %entry
+; AIX-NEXT:    fmr 5, 0
+; AIX-NEXT:  L..BB5_32: # %entry
+; AIX-NEXT:    xxmrghd 0, 4, 5
+; AIX-NEXT:    xvcvdpsp 35, 0
+; AIX-NEXT:    vmrgew 2, 3, 2
+; AIX-NEXT:    blr
+entry:
+  %m = call <4 x float> @llvm.maximum.v4f32(<4 x float> %a, <4 x float> %b)
+  ret <4 x float> %m
+}
+
+define <2 x double> @v2f64_minimum(<2 x double> %a, <2 x double> %b) {
+; NOVSX-LABEL: v2f64_minimum:
+; NOVSX:       # %bb.0: # %entry
+; NOVSX-NEXT:    fcmpu 0, 1, 3
+; NOVSX-NEXT:    fmr 6, 1
+; NOVSX-NEXT:    stfd 2, -8(1)
+; NOVSX-NEXT:    stfd 4, -16(1)
+; NOVSX-NEXT:    stfd 1, -24(1)
+; NOVSX-NEXT:    stfd 3, -32(1)
+; NOVSX-NEXT:    bc 12, 0, .LBB6_2
+; NOVSX-NEXT:  # %bb.1: # %entry
+; NOVSX-NEXT:    fmr 6, 3
+; NOVSX-NEXT:  .LBB6_2: # %entry
+; NOVSX-NEXT:    addis 3, 2, .LCPI6_0@toc@ha
+; NOVSX-NEXT:    ld 5, -24(1)
+; NOVSX-NEXT:    ld 4, -32(1)
+; NOVSX-NEXT:    lfs 0, .LCPI6_0@toc@l(3)
+; NOVSX-NEXT:    fmr 5, 0
+; NOVSX-NEXT:    bc 12, 3, .LBB6_4
+; NOVSX-NEXT:  # %bb.3: # %entry
+; NOVSX-NEXT:    fmr 5, 6
+; NOVSX-NEXT:  .LBB6_4: # %entry
+; NOVSX-NEXT:    li 3, 1
+; NOVSX-NEXT:    rldic 3, 3, 63, 0
+; NOVSX-NEXT:    xor 6, 4, 3
+; NOVSX-NEXT:    or. 6, 5, 6
+; NOVSX-NEXT:    bc 12, 2, .LBB6_6
+; NOVSX-NEXT:  # %bb.5: # %entry
+; NOVSX-NEXT:    fmr 3, 5
+; NOVSX-NEXT:  .LBB6_6: # %entry
+; NOVSX-NEXT:    xor 5, 5, 3
+; NOVSX-NEXT:    or. 4, 5, 4
+; NOVSX-NEXT:    bc 12, 2, .LBB6_8
+; NOVSX-NEXT:  # %bb.7: # %entry
+; NOVSX-NEXT:    fmr 1, 3
+; NOVSX-NEXT:  .LBB6_8: # %entry
+; NOVSX-NEXT:    addis 4, 2, .LCPI6_1@toc@ha
+; NOVSX-NEXT:    lfs 3, .LCPI6_1@toc@l(4)
+; NOVSX-NEXT:    fcmpu 0, 5, 3
+; NOVSX-NEXT:    bc 12, 2, .LBB6_10
+; NOVSX-NEXT:  # %bb.9: # %entry
+; NOVSX-NEXT:    fmr 1, 5
+; NOVSX-NEXT:  .LBB6_10: # %entry
+; NOVSX-NEXT:    fcmpu 0, 2, 4
+; NOVSX-NEXT:    fmr 5, 2
+; NOVSX-NEXT:    bc 12, 0, .LBB6_12
+; NOVSX-NEXT:  # %bb.11: # %entry
+; NOVSX-NEXT:    fmr 5, 4
+; NOVSX-NEXT:  .LBB6_12: # %entry
+; NOVSX-NEXT:    ld 4, -8(1)
+; NOVSX-NEXT:    ld 5, -16(1)
+; NOVSX-NEXT:    bc 12, 3, .LBB6_14
+; NOVSX-NEXT:  # %bb.13: # %entry
+; NOVSX-NEXT:    fmr 0, 5
+; NOVSX-NEXT:  .LBB6_14: # %entry
+; NOVSX-NEXT:    xor 6, 5, 3
+; NOVSX-NEXT:    or. 6, 4, 6
+; NOVSX-NEXT:    bc 12, 2, .LBB6_16
+; NOVSX-NEXT:  # %bb.15: # %entry
+; NOVSX-NEXT:    fmr 4, 0
+; NOVSX-NEXT:  .LBB6_16: # %entry
+; NOVSX-NEXT:    xor 3, 4, 3
+; NOVSX-NEXT:    or. 3, 3, 5
+; NOVSX-NEXT:    bc 12, 2, .LBB6_18
+; NOVSX-NEXT:  # %bb.17: # %entry
+; NOVSX-NEXT:    fmr 2, 4
+; NOVSX-NEXT:  .LBB6_18: # %entry
+; NOVSX-NEXT:    fcmpu 0, 0, 3
+; NOVSX-NEXT:    bclr 12, 2, 0
+; NOVSX-NEXT:  # %bb.19: # %entry
+; NOVSX-NEXT:    fmr 2, 0
+; NOVSX-NEXT:    blr
+;
+; VSX-LABEL: v2f64_minimum:
+; VSX:       # %bb.0: # %entry
+; VSX-NEXT:    xxlor 2, 35, 35
+; VSX-NEXT:    addis 3, 2, .LCPI6_0@toc@ha
+; VSX-NEXT:    xxlor 0, 34, 34
+; VSX-NEXT:    lfs 1, .LCPI6_0@toc@l(3)
+; VSX-NEXT:    fcmpu 0, 0, 2
+; VSX-NEXT:    fmr 3, 1
+; VSX-NEXT:    bc 12, 3, .LBB6_2
+; VSX-NEXT:  # %bb.1: # %entry
+; VSX-NEXT:    xsmindp 3, 0, 2
+; VSX-NEXT:  .LBB6_2: # %entry
+; VSX-NEXT:    mffprd 4, 2
+; VSX-NEXT:    li 3, 1
+; VSX-NEXT:    rldic 3, 3, 63, 0
+; VSX-NEXT:    mffprd 5, 0
+; VSX-NEXT:    xor 6, 4, 3
+; VSX-NEXT:    or. 6, 5, 6
+; VSX-NEXT:    bc 12, 2, .LBB6_4
+; VSX-NEXT:  # %bb.3: # %entry
+; VSX-NEXT:    fmr 2, 3
+; VSX-NEXT:  .LBB6_4: # %entry
+; VSX-NEXT:    xor 5, 5, 3
+; VSX-NEXT:    or. 4, 5, 4
+; VSX-NEXT:    bc 12, 2, .LBB6_6
+; VSX-NEXT:  # %bb.5: # %entry
+; VSX-NEXT:    fmr 0, 2
+; VSX-NEXT:  .LBB6_6: # %entry
+; VSX-NEXT:    xxlxor 2, 2, 2
+; VSX-NEXT:    fcmpu 0, 3, 2
+; VSX-NEXT:    bc 12, 2, .LBB6_8
+; VSX-NEXT:  # %bb.7: # %entry
+; VSX-NEXT:    fmr 0, 3
+; VSX-NEXT:  .LBB6_8: # %entry
+; VSX-NEXT:    xxswapd 4, 35
+; VSX-NEXT:    xxswapd 3, 34
+; VSX-NEXT:    fcmpu 0, 3, 4
+; VSX-NEXT:    bc 12, 3, .LBB6_10
+; VSX-NEXT:  # %bb.9: # %entry
+; VSX-NEXT:    xsmindp 1, 3, 4
+; VSX-NEXT:  .LBB6_10: # %entry
+; VSX-NEXT:    mffprd 4, 4
+; VSX-NEXT:    mffprd 5, 3
+; VSX-NEXT:    xor 6, 4, 3
+; VSX-NEXT:    or. 6, 5, 6
+; VSX-NEXT:    bc 12, 2, .LBB6_12
+; VSX-NEXT:  # %bb.11: # %entry
+; VSX-NEXT:    fmr 4, 1
+; VSX-NEXT:  .LBB6_12: # %entry
+; VSX-NEXT:    xor 3, 5, 3
+; VSX-NEXT:    or. 3, 3, 4
+; VSX-NEXT:    bc 4, 2, .LBB6_15
+; VSX-NEXT:  # %bb.13: # %entry
+; VSX-NEXT:    fcmpu 0, 1, 2
+; VSX-NEXT:    bc 4, 2, .LBB6_16
+; VSX-NEXT:  .LBB6_14: # %entry
+; VSX-NEXT:    xxmrghd 34, 0, 3
+; VSX-NEXT:    blr
+; VSX-NEXT:  .LBB6_15: # %entry
+; VSX-NEXT:    fmr 3, 4
+; VSX-NEXT:    fcmpu 0, 1, 2
+; VSX-NEXT:    bc 12, 2, .LBB6_14
+; VSX-NEXT:  .LBB6_16: # %entry
+; VSX-NEXT:    fmr 3, 1
+; VSX-NEXT:    xxmrghd 34, 0, 3
+; VSX-NEXT:    blr
+;
+; AIX-LABEL: v2f64_minimum:
+; AIX:       # %bb.0: # %entry
+; AIX-NEXT:    ld 3, L..C6(2) # %const.0
+; AIX-NEXT:    xxlor 2, 35, 35
+; AIX-NEXT:    xxlor 0, 34, 34
+; AIX-NEXT:    fcmpu 0, 0, 2
+; AIX-NEXT:    lfs 1, 0(3)
+; AIX-NEXT:    fmr 3, 1
+; AIX-NEXT:    bc 12, 3, L..BB6_2
+; AIX-NEXT:  # %bb.1: # %entry
+; AIX-NEXT:    xsmindp 3, 0, 2
+; AIX-NEXT:  L..BB6_2: # %entry
+; AIX-NEXT:    mffprd 4, 2
+; AIX-NEXT:    li 3, 1
+; AIX-NEXT:    rldic 3, 3, 63, 0
+; AIX-NEXT:    mffprd 5, 0
+; AIX-NEXT:    xor 6, 4, 3
+; AIX-NEXT:    or. 6, 5, 6
+; AIX-NEXT:    bc 12, 2, L..BB6_4
+; AIX-NEXT:  # %bb.3: # %entry
+; AIX-NEXT:    fmr 2, 3
+; AIX-NEXT:  L..BB6_4: # %entry
+; AIX-NEXT:    xor 5, 5, 3
+; AIX-NEXT:    or. 4, 5, 4
+; AIX-NEXT:    bc 12, 2, L..BB6_6
+; AIX-NEXT:  # %bb.5: # %entry
+; AIX-NEXT:    fmr 0, 2
+; AIX-NEXT:  L..BB6_6: # %entry
+; AIX-NEXT:    xxlxor 2, 2, 2
+; AIX-NEXT:    fcmpu 0, 3, 2
+; AIX-NEXT:    bc 12, 2, L..BB6_8
+; AIX-NEXT:  # %bb.7: # %entry
+; AIX-NEXT:    fmr 0, 3
+; AIX-NEXT:  L..BB6_8: # %entry
+; AIX-NEXT:    xxswapd 4, 35
+; AIX-NEXT:    xxswapd 3, 34
+; AIX-NEXT:    fcmpu 0, 3, 4
+; AIX-NEXT:    bc 12, 3, L..BB6_10
+; AIX-NEXT:  # %bb.9: # %entry
+; AIX-NEXT:    xsmindp 1, 3, 4
+; AIX-NEXT:  L..BB6_10: # %entry
+; AIX-NEXT:    mffprd 4, 4
+; AIX-NEXT:    mffprd 5, 3
+; AIX-NEXT:    xor 6, 4, 3
+; AIX-NEXT:    or. 6, 5, 6
+; AIX-NEXT:    bc 12, 2, L..BB6_12
+; AIX-NEXT:  # %bb.11: # %entry
+; AIX-NEXT:    fmr 4, 1
+; AIX-NEXT:  L..BB6_12: # %entry
+; AIX-NEXT:    xor 3, 5, 3
+; AIX-NEXT:    or. 3, 3, 4
+; AIX-NEXT:    bc 4, 2, L..BB6_15
+; AIX-NEXT:  # %bb.13: # %entry
+; AIX-NEXT:    fcmpu 0, 1, 2
+; AIX-NEXT:    bc 4, 2, L..BB6_16
+; AIX-NEXT:  L..BB6_14: # %entry
+; AIX-NEXT:    xxmrghd 34, 0, 3
+; AIX-NEXT:    blr
+; AIX-NEXT:  L..BB6_15: # %entry
+; AIX-NEXT:    fmr 3, 4
+; AIX-NEXT:    fcmpu 0, 1, 2
+; AIX-NEXT:    bc 12, 2, L..BB6_14
+; AIX-NEXT:  L..BB6_16: # %entry
+; AIX-NEXT:    fmr 3, 1
+; AIX-NEXT:    xxmrghd 34, 0, 3
+; AIX-NEXT:    blr
+entry:
+  %m = call <2 x double> @llvm.minimum.v2f64(<2 x double> %a, <2 x double> %b)
+  ret <2 x double> %m
+}
+
+define <2 x double> @v2f64_maximum(<2 x double> %a, <2 x double> %b) {
+; NOVSX-LABEL: v2f64_maximum:
+; NOVSX:       # %bb.0: # %entry
+; NOVSX-NEXT:    fcmpu 0, 1, 3
+; NOVSX-NEXT:    fmr 6, 1
+; NOVSX-NEXT:    stfd 2, -8(1)
+; NOVSX-NEXT:    stfd 4, -16(1)
+; NOVSX-NEXT:    stfd 1, -24(1)
+; NOVSX-NEXT:    stfd 3, -32(1)
+; NOVSX-NEXT:    bc 12, 1, .LBB7_2
+; NOVSX-NEXT:  # %bb.1: # %entry
+; NOVSX-NEXT:    fmr 6, 3
+; NOVSX-NEXT:  .LBB7_2: # %entry
+; NOVSX-NEXT:    addis 3, 2, .LCPI7_0@toc@ha
+; NOVSX-NEXT:    ld 5, -24(1)
+; NOVSX-NEXT:    ld 4, -32(1)
+; NOVSX-NEXT:    lfs 0, .LCPI7_0@toc@l(3)
+; NOVSX-NEXT:    fmr 5, 0
+; NOVSX-NEXT:    bc 12, 3, .LBB7_4
+; NOVSX-NEXT:  # %bb.3: # %entry
+; NOVSX-NEXT:    fmr 5, 6
+; NOVSX-NEXT:  .LBB7_4: # %entry
+; NOVSX-NEXT:    li 3, 1
+; NOVSX-NEXT:    rldic 3, 3, 63, 0
+; NOVSX-NEXT:    xor 6, 4, 3
+; NOVSX-NEXT:    or. 6, 5, 6
+; NOVSX-NEXT:    bc 12, 2, .LBB7_6
+; NOVSX-NEXT:  # %bb.5: # %entry
+; NOVSX-NEXT:    fmr 1, 5
+; NOVSX-NEXT:  .LBB7_6: # %entry
+; NOVSX-NEXT:    xor 5, 5, 3
+; NOVSX-NEXT:    or. 4, 5, 4
+; NOVSX-NEXT:    bc 12, 2, .LBB7_8
+; NOVSX-NEXT:  # %bb.7: # %entry
+; NOVSX-NEXT:    fmr 3, 1
+; NOVSX-NEXT:  .LBB7_8: # %entry
+; NOVSX-NEXT:    addis 4, 2, .LCPI7_1@toc@ha
+; NOVSX-NEXT:    lfs 1, .LCPI7_1@toc@l(4)
+; NOVSX-NEXT:    fcmpu 0, 5, 1
+; NOVSX-NEXT:    bc 12, 2, .LBB7_10
+; NOVSX-NEXT:  # %bb.9: # %entry
+; NOVSX-NEXT:    fmr 3, 5
+; NOVSX-NEXT:  .LBB7_10: # %entry
+; NOVSX-NEXT:    fcmpu 0, 2, 4
+; NOVSX-NEXT:    fmr 5, 2
+; NOVSX-NEXT:    bc 12, 1, .LBB7_12
+; NOVSX-NEXT:  # %bb.11: # %entry
+; NOVSX-NEXT:    fmr 5, 4
+; NOVSX-NEXT:  .LBB7_12: # %entry
+; NOVSX-NEXT:    ld 4, -8(1)
+; NOVSX-NEXT:    ld 5, -16(1)
+; NOVSX-NEXT:    bc 12, 3, .LBB7_14
+; NOVSX-NEXT:  # %bb.13: # %entry
+; NOVSX-NEXT:    fmr 0, 5
+; NOVSX-NEXT:  .LBB7_14: # %entry
+; NOVSX-NEXT:    xor 6, 5, 3
+; NOVSX-NEXT:    or. 6, 4, 6
+; NOVSX-NEXT:    bc 12, 2, .LBB7_16
+; NOVSX-NEXT:  # %bb.15: # %entry
+; NOVSX-NEXT:    fmr 2, 0
+; NOVSX-NEXT:  .LBB7_16: # %entry
+; NOVSX-NEXT:    xor 3, 4, 3
+; NOVSX-NEXT:    or. 3, 3, 5
+; NOVSX-NEXT:    bc 12, 2, .LBB7_18
+; NOVSX-NEXT:  # %bb.17: # %entry
+; NOVSX-NEXT:    fmr 4, 2
+; NOVSX-NEXT:  .LBB7_18: # %entry
+; NOVSX-NEXT:    fcmpu 0, 0, 1
+; NOVSX-NEXT:    bc 12, 2, .LBB7_20
+; NOVSX-NEXT:  # %bb.19: # %entry
+; NOVSX-NEXT:    fmr 4, 0
+; NOVSX-NEXT:  .LBB7_20: # %entry
+; NOVSX-NEXT:    fmr 1, 3
+; NOVSX-NEXT:    fmr 2, 4
+; NOVSX-NEXT:    blr
+;
+; VSX-LABEL: v2f64_maximum:
+; VSX:       # %bb.0: # %entry
+; VSX-NEXT:    xxlor 0, 35, 35
+; VSX-NEXT:    addis 3, 2, .LCPI7_0@toc@ha
+; VSX-NEXT:    xxlor 2, 34, 34
+; VSX-NEXT:    lfs 1, .LCPI7_0@toc@l(3)
+; VSX-NEXT:    fcmpu 0, 2, 0
+; VSX-NEXT:    fmr 3, 1
+; VSX-NEXT:    bc 12, 3, .LBB7_2
+; VSX-NEXT:  # %bb.1: # %entry
+; VSX-NEXT:    xsmaxdp 3, 2, 0
+; VSX-NEXT:  .LBB7_2: # %entry
+; VSX-NEXT:    mffprd 4, 0
+; VSX-NEXT:    li 3, 1
+; VSX-NEXT:    rldic 3, 3, 63, 0
+; VSX-NEXT:    mffprd 5, 2
+; VSX-NEXT:    xor 6, 4, 3
+; VSX-NEXT:    or. 6, 5, 6
+; VSX-NEXT:    bc 12, 2, .LBB7_4
+; VSX-NEXT:  # %bb.3: # %entry
+; VSX-NEXT:    fmr 2, 3
+; VSX-NEXT:  .LBB7_4: # %entry
+; VSX-NEXT:    xor 5, 5, 3
+; VSX-NEXT:    or. 4, 5, 4
+; VSX-NEXT:    bc 12, 2, .LBB7_6
+; VSX-NEXT:  # %bb.5: # %entry
+; VSX-NEXT:    fmr 0, 2
+; VSX-NEXT:  .LBB7_6: # %entry
+; VSX-NEXT:    xxlxor 2, 2, 2
+; VSX-NEXT:    fcmpu 0, 3, 2
+; VSX-NEXT:    bc 12, 2, .LBB7_8
+; VSX-NEXT:  # %bb.7: # %entry
+; VSX-NEXT:    fmr 0, 3
+; VSX-NEXT:  .LBB7_8: # %entry
+; VSX-NEXT:    xxswapd 3, 35
+; VSX-NEXT:    xxswapd 4, 34
+; VSX-NEXT:    fcmpu 0, 4, 3
+; VSX-NEXT:    bc 12, 3, .LBB7_10
+; VSX-NEXT:  # %bb.9: # %entry
+; VSX-NEXT:    xsmaxdp 1, 4, 3
+; VSX-NEXT:  .LBB7_10: # %entry
+; VSX-NEXT:    mffprd 4, 3
+; VSX-NEXT:    mffprd 5, 4
+; VSX-NEXT:    xor 6, 4, 3
+; VSX-NEXT:    or. 6, 5, 6
+; VSX-NEXT:    bc 12, 2, .LBB7_12
+; VSX-NEXT:  # %bb.11: # %entry
+; VSX-NEXT:    fmr 4, 1
+; VSX-NEXT:  .LBB7_12: # %entry
+; VSX-NEXT:    xor 3, 5, 3
+; VSX-NEXT:    or. 3, 3, 4
+; VSX-NEXT:    bc 4, 2, .LBB7_15
+; VSX-NEXT:  # %bb.13: # %entry
+; VSX-NEXT:    fcmpu 0, 1, 2
+; VSX-NEXT:    bc 4, 2, .LBB7_16
+; VSX-NEXT:  .LBB7_14: # %entry
+; VSX-NEXT:    xxmrghd 34, 0, 3
+; VSX-NEXT:    blr
+; VSX-NEXT:  .LBB7_15: # %entry
+; VSX-NEXT:    fmr 3, 4
+; VSX-NEXT:    fcmpu 0, 1, 2
+; VSX-NEXT:    bc 12, 2, .LBB7_14
+; VSX-NEXT:  .LBB7_16: # %entry
+; VSX-NEXT:    fmr 3, 1
+; VSX-NEXT:    xxmrghd 34, 0, 3
+; VSX-NEXT:    blr
+;
+; AIX-LABEL: v2f64_maximum:
+; AIX:       # %bb.0: # %entry
+; AIX-NEXT:    ld 3, L..C7(2) # %const.0
+; AIX-NEXT:    xxlor 0, 35, 35
+; AIX-NEXT:    xxlor 2, 34, 34
+; AIX-NEXT:    fcmpu 0, 2, 0
+; AIX-NEXT:    lfs 1, 0(3)
+; AIX-NEXT:    fmr 3, 1
+; AIX-NEXT:    bc 12, 3, L..BB7_2
+; AIX-NEXT:  # %bb.1: # %entry
+; AIX-NEXT:    xsmaxdp 3, 2, 0
+; AIX-NEXT:  L..BB7_2: # %entry
+; AIX-NEXT:    mffprd 4, 0
+; AIX-NEXT:    li 3, 1
+; AIX-NEXT:    rldic 3, 3, 63, 0
+; AIX-NEXT:    mffprd 5, 2
+; AIX-NEXT:    xor 6, 4, 3
+; AIX-NEXT:    or. 6, 5, 6
+; AIX-NEXT:    bc 12, 2, L..BB7_4
+; AIX-NEXT:  # %bb.3: # %entry
+; AIX-NEXT:    fmr 2, 3
+; AIX-NEXT:  L..BB7_4: # %entry
+; AIX-NEXT:    xor 5, 5, 3
+; AIX-NEXT:    or. 4, 5, 4
+; AIX-NEXT:    bc 12, 2, L..BB7_6
+; AIX-NEXT:  # %bb.5: # %entry
+; AIX-NEXT:    fmr 0, 2
+; AIX-NEXT:  L..BB7_6: # %entry
+; AIX-NEXT:    xxlxor 2, 2, 2
+; AIX-NEXT:    fcmpu 0, 3, 2
+; AIX-NEXT:    bc 12, 2, L..BB7_8
+; AIX-NEXT:  # %bb.7: # %entry
+; AIX-NEXT:    fmr 0, 3
+; AIX-NEXT:  L..BB7_8: # %entry
+; AIX-NEXT:    xxswapd 3, 35
+; AIX-NEXT:    xxswapd 4, 34
+; AIX-NEXT:    fcmpu 0, 4, 3
+; AIX-NEXT:    bc 12, 3, L..BB7_10
+; AIX-NEXT:  # %bb.9: # %entry
+; AIX-NEXT:    xsmaxdp 1, 4, 3
+; AIX-NEXT:  L..BB7_10: # %entry
+; AIX-NEXT:    mffprd 4, 3
+; AIX-NEXT:    mffprd 5, 4
+; AIX-NEXT:    xor 6, 4, 3
+; AIX-NEXT:    or. 6, 5, 6
+; AIX-NEXT:    bc 12, 2, L..BB7_12
+; AIX-NEXT:  # %bb.11: # %entry
+; AIX-NEXT:    fmr 4, 1
+; AIX-NEXT:  L..BB7_12: # %entry
+; AIX-NEXT:    xor 3, 5, 3
+; AIX-NEXT:    or. 3, 3, 4
+; AIX-NEXT:    bc 4, 2, L..BB7_15
+; AIX-NEXT:  # %bb.13: # %entry
+; AIX-NEXT:    fcmpu 0, 1, 2
+; AIX-NEXT:    bc 4, 2, L..BB7_16
+; AIX-NEXT:  L..BB7_14: # %entry
+; AIX-NEXT:    xxmrghd 34, 0, 3
+; AIX-NEXT:    blr
+; AIX-NEXT:  L..BB7_15: # %entry
+; AIX-NEXT:    fmr 3, 4
+; AIX-NEXT:    fcmpu 0, 1, 2
+; AIX-NEXT:    bc 12, 2, L..BB7_14
+; AIX-NEXT:  L..BB7_16: # %entry
+; AIX-NEXT:    fmr 3, 1
+; AIX-NEXT:    xxmrghd 34, 0, 3
+; AIX-NEXT:    blr
+entry:
+  %m = call <2 x double> @llvm.maximum.v2f64(<2 x double> %a, <2 x double> %b)
+  ret <2 x double> %m
+}
+
+declare float @llvm.maximum.f32(float, float)
+declare double @llvm.maximum.f64(double, double)
+declare <4 x float> @llvm.maximum.v4f32(<4 x float>, <4 x float>)
+declare <2 x double> @llvm.maximum.v2f64(<2 x double>, <2 x double>)
+
+declare float @llvm.minimum.f32(float, float)
+declare double @llvm.minimum.f64(double, double)
+declare <4 x float> @llvm.minimum.v4f32(<4 x float>, <4 x float>)
+declare <2 x double> @llvm.minimum.v2f64(<2 x double>, <2 x double>)