diff --git a/llvm/include/llvm/CodeGen/LiveRegUnits.h b/llvm/include/llvm/CodeGen/LiveRegUnits.h --- a/llvm/include/llvm/CodeGen/LiveRegUnits.h +++ b/llvm/include/llvm/CodeGen/LiveRegUnits.h @@ -93,7 +93,7 @@ void addRegMasked(MCPhysReg Reg, LaneBitmask Mask) { for (MCRegUnitMaskIterator Unit(Reg, TRI); Unit.isValid(); ++Unit) { LaneBitmask UnitMask = (*Unit).second; - if (UnitMask.none() || (UnitMask & Mask).any()) + if ((UnitMask & Mask).any()) Units.set((*Unit).first); } } diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp --- a/llvm/lib/CodeGen/MachineSink.cpp +++ b/llvm/lib/CodeGen/MachineSink.cpp @@ -1704,10 +1704,9 @@ for (auto U : UsedOpsInCopy) { Register SrcReg = MI->getOperand(U).getReg(); LaneBitmask Mask; - for (MCRegUnitMaskIterator S(SrcReg, TRI); S.isValid(); ++S) { + for (MCRegUnitMaskIterator S(SrcReg, TRI); S.isValid(); ++S) Mask |= (*S).second; - } - SuccBB->addLiveIn(SrcReg, Mask.any() ? Mask : LaneBitmask::getAll()); + SuccBB->addLiveIn(SrcReg, Mask); } SuccBB->sortUniqueLiveIns(); } diff --git a/llvm/lib/CodeGen/RDFRegisters.cpp b/llvm/lib/CodeGen/RDFRegisters.cpp --- a/llvm/lib/CodeGen/RDFRegisters.cpp +++ b/llvm/lib/CodeGen/RDFRegisters.cpp @@ -61,14 +61,7 @@ std::pair P = *I; UnitInfo &UI = UnitInfos[P.first]; UI.Reg = F; - if (P.second.any()) { - UI.Mask = P.second; - } else { - if (const TargetRegisterClass *RC = RegInfos[F].RegClass) - UI.Mask = RC->LaneMask; - else - UI.Mask = LaneBitmask::getAll(); - } + UI.Mask = P.second; } } } @@ -141,7 +134,7 @@ return Units; // Empty for (MCRegUnitMaskIterator UM(RR.idx(), &TRI); UM.isValid(); ++UM) { auto [U, M] = *UM; - if (M.none() || (M & RR.Mask).any()) + if ((M & RR.Mask).any()) Units.insert(U); } return Units; @@ -200,13 +193,6 @@ auto [AReg, AMask] = *AI; auto [BReg, BMask] = *BI; - // Lane masks are "none" for units that don't correspond to subregs - // e.g. a single unit in a leaf register, or aliased unit. - if (AMask.none()) - AMask = LaneBitmask::getAll(); - if (BMask.none()) - BMask = LaneBitmask::getAll(); - // If both iterators point to a unit contained in both A and B, then // compare the units. if ((AMask & A.Mask).any() && (BMask & B.Mask).any()) { @@ -245,13 +231,6 @@ auto [AReg, AMask] = *AI; auto [BReg, BMask] = *BI; - // Lane masks are "none" for units that don't correspond to subregs - // e.g. a single unit in a leaf register, or aliased unit. - if (AMask.none()) - AMask = LaneBitmask::getAll(); - if (BMask.none()) - BMask = LaneBitmask::getAll(); - // If both iterators point to a unit contained in both A and B, then // compare the units. if ((AMask & A.Mask).any() && (BMask & B.Mask).any()) { @@ -303,7 +282,7 @@ for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) { std::pair P = *U; - if (P.second.none() || (P.second & RR.Mask).any()) + if ((P.second & RR.Mask).any()) if (Units.test(P.first)) return true; } @@ -318,7 +297,7 @@ for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) { std::pair P = *U; - if (P.second.none() || (P.second & RR.Mask).any()) + if ((P.second & RR.Mask).any()) if (!Units.test(P.first)) return false; } @@ -333,7 +312,7 @@ for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) { std::pair P = *U; - if (P.second.none() || (P.second & RR.Mask).any()) + if ((P.second & RR.Mask).any()) Units.set(P.first); } return *this; @@ -407,7 +386,7 @@ for (MCRegUnitMaskIterator I(F, &PRI.getTRI()); I.isValid(); ++I) { std::pair P = *I; if (Units.test(P.first)) - M |= P.second.none() ? LaneBitmask::getAll() : P.second; + M |= P.second; } return RegisterRef(F, M); } diff --git a/llvm/utils/TableGen/CodeGenRegisters.cpp b/llvm/utils/TableGen/CodeGenRegisters.cpp --- a/llvm/utils/TableGen/CodeGenRegisters.cpp +++ b/llvm/utils/TableGen/CodeGenRegisters.cpp @@ -2123,8 +2123,8 @@ for (auto &Register : Registers) { // Create an initial lane mask for all register units. const auto &RegUnits = Register.getRegUnits(); - CodeGenRegister::RegUnitLaneMaskList - RegUnitLaneMasks(RegUnits.count(), LaneBitmask::getNone()); + CodeGenRegister::RegUnitLaneMaskList RegUnitLaneMasks( + RegUnits.count(), LaneBitmask::getAll()); // Iterate through SubRegisters. typedef CodeGenRegister::SubRegMap SubRegMap; const SubRegMap &SubRegs = Register.getSubRegs(); @@ -2143,7 +2143,7 @@ unsigned u = 0; for (unsigned RU : RegUnits) { if (SUI == RU) { - RegUnitLaneMasks[u] |= LaneMask; + RegUnitLaneMasks[u] &= LaneMask; assert(!Found); Found = true; } diff --git a/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/llvm/utils/TableGen/RegisterInfoEmitter.cpp --- a/llvm/utils/TableGen/RegisterInfoEmitter.cpp +++ b/llvm/utils/TableGen/RegisterInfoEmitter.cpp @@ -931,12 +931,6 @@ MaskVec &LaneMaskVec = RegUnitLaneMasks[i]; assert(LaneMaskVec.empty()); llvm::append_range(LaneMaskVec, RUMasks); - // Terminator mask should not be used inside of the list. -#ifndef NDEBUG - for (LaneBitmask M : LaneMaskVec) { - assert(!M.all() && "terminator mask should not be part of the list"); - } -#endif LaneMaskSeqs.add(LaneMaskVec); } @@ -956,6 +950,8 @@ // Emit the shared table of regunit lane mask sequences. OS << "extern const LaneBitmask " << TargetName << "LaneMaskLists[] = {\n"; + // TODO: Omit the terminator since it is never used. The length of this list + // is known implicitly from the corresponding reg unit list. LaneMaskSeqs.emit(OS, printMask, "LaneBitmask::getAll()"); OS << "};\n\n";