diff --git a/llvm/lib/ExecutionEngine/JITLink/aarch32.cpp b/llvm/lib/ExecutionEngine/JITLink/aarch32.cpp --- a/llvm/lib/ExecutionEngine/JITLink/aarch32.cpp +++ b/llvm/lib/ExecutionEngine/JITLink/aarch32.cpp @@ -175,7 +175,7 @@ template void writeRegister(WritableThumbRelocation &R, HalfWords Reg) { static constexpr HalfWords Mask = FixupInfo::RegMask; - assert((Mask.Hi & Reg.Hi) == Reg.Hi && (Mask.Hi & Reg.Hi) == Reg.Hi && + assert((Mask.Hi & Reg.Hi) == Reg.Hi && (Mask.Lo & Reg.Lo) == Reg.Lo && "Value bits exceed bit range of given mask"); R.Hi = (R.Hi & ~Mask.Hi) | Reg.Hi; R.Lo = (R.Lo & ~Mask.Lo) | Reg.Lo; @@ -184,7 +184,7 @@ template void writeImmediate(WritableThumbRelocation &R, HalfWords Imm) { static constexpr HalfWords Mask = FixupInfo::ImmMask; - assert((Mask.Hi & Imm.Hi) == Imm.Hi && (Mask.Hi & Imm.Hi) == Imm.Hi && + assert((Mask.Hi & Imm.Hi) == Imm.Hi && (Mask.Lo & Imm.Lo) == Imm.Lo && "Value bits exceed bit range of given mask"); R.Hi = (R.Hi & ~Mask.Hi) | Imm.Hi; R.Lo = (R.Lo & ~Mask.Lo) | Imm.Lo; @@ -242,7 +242,7 @@ case Thumb_Jump24: if (!checkOpcode(R)) return makeUnexpectedOpcodeError(G, R, Kind); - if (R.Lo & FixupInfo::LoBitConditional) + if (~R.Lo & FixupInfo::LoBitConditional) return make_error("Relocation expects an unconditional " "B.W branch instruction: " + StringRef(G.getEdgeKindName(Kind))); @@ -352,7 +352,7 @@ case Thumb_Jump24: { if (!checkOpcode(R)) return makeUnexpectedOpcodeError(G, R, Kind); - if (R.Lo & FixupInfo::LoBitConditional) + if (~R.Lo & FixupInfo::LoBitConditional) return make_error("Relocation expects an unconditional " "B.W branch instruction: " + StringRef(G.getEdgeKindName(Kind))); @@ -471,6 +471,7 @@ switch (K) { KIND_NAME_CASE(Data_Delta32) + KIND_NAME_CASE(Data_Pointer32) KIND_NAME_CASE(Arm_Call) KIND_NAME_CASE(Thumb_Call) KIND_NAME_CASE(Thumb_Jump24)