diff --git a/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h b/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h --- a/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h @@ -343,6 +343,13 @@ /// - RegNum - The register to add GIR_AddRegister, + /// Marks the implicit def of a register as dead. + /// - InsnID - Instruction ID to modify + /// - OpIdx - The implicit def operand index + /// + /// OpIdx starts at 0 for the first implicit def. + GIR_SetImplicitDefDead, + /// Add a temporary register to the specified instruction /// - InsnID - Instruction ID to modify /// - TempRegID - The temporary register ID to add diff --git a/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h b/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h --- a/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h @@ -978,7 +978,17 @@ << "], " << RegNum << ", " << RegFlags << ")\n"); break; } - + case GIR_SetImplicitDefDead: { + int64_t InsnID = MatchTable[CurrentIdx++]; + int64_t OpIdx = MatchTable[CurrentIdx++]; + DEBUG_WITH_TYPE(TgtExecutor::getName(), + dbgs() << CurrentIdx << ": GIR_SetImplicitDefDead(OutMIs[" + << InsnID << "], OpIdx=" << OpIdx << ")\n"); + MachineInstr *MI = OutMIs[InsnID]; + assert(MI && "Modifying undefined instruction"); + MI->getOperand(MI->getNumExplicitOperands() + OpIdx).setIsDead(); + break; + } case GIR_AddTempRegister: case GIR_AddTempSubRegister: { int64_t InsnID = MatchTable[CurrentIdx++]; diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-swap-compare-operands.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-swap-compare-operands.mir --- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-swap-compare-operands.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-swap-compare-operands.mir @@ -28,6 +28,7 @@ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sle), %cmp_rhs(s64), %cmp_lhs ; LOWER-NEXT: $w0 = COPY %cmp(s32) ; LOWER-NEXT: RET_ReallyLR implicit $w0 + ; ; SELECT-LABEL: name: swap_sextinreg_lhs ; SELECT: liveins: $x0, $x1 ; SELECT-NEXT: {{ $}} @@ -67,6 +68,7 @@ ; LOWER-NEXT: %cmp2:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %add ; LOWER-NEXT: $w0 = COPY %cmp2(s32) ; LOWER-NEXT: RET_ReallyLR implicit $w0 + ; ; SELECT-LABEL: name: dont_swap_more_than_one_use ; SELECT: liveins: $x0, $x1 ; SELECT-NEXT: {{ $}} @@ -108,6 +110,7 @@ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %cmp_rhs ; LOWER-NEXT: $w0 = COPY %cmp(s32) ; LOWER-NEXT: RET_ReallyLR implicit $w0 + ; ; SELECT-LABEL: name: dont_swap_legal_arith_immed_on_rhs ; SELECT: liveins: $x0, $x1 ; SELECT-NEXT: {{ $}} @@ -144,6 +147,7 @@ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sle), %cmp_rhs(s64), %cmp_lhs ; LOWER-NEXT: $w0 = COPY %cmp(s32) ; LOWER-NEXT: RET_ReallyLR implicit $w0 + ; ; SELECT-LABEL: name: swap_non_arith_immed_on_rhs ; SELECT: liveins: $x0, $x1 ; SELECT-NEXT: {{ $}} @@ -181,6 +185,7 @@ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sle), %cmp_rhs(s64), %cmp_lhs ; LOWER-NEXT: $w0 = COPY %cmp(s32) ; LOWER-NEXT: RET_ReallyLR implicit $w0 + ; ; SELECT-LABEL: name: swap_and_lhs_0xFF ; SELECT: liveins: $x0, $x1 ; SELECT-NEXT: {{ $}} @@ -220,6 +225,7 @@ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sle), %cmp_rhs(s64), %cmp_lhs ; LOWER-NEXT: $w0 = COPY %cmp(s32) ; LOWER-NEXT: RET_ReallyLR implicit $w0 + ; ; SELECT-LABEL: name: swap_and_lhs_0xFFFF ; SELECT: liveins: $x0, $x1 ; SELECT-NEXT: {{ $}} @@ -259,6 +265,7 @@ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sle), %cmp_rhs(s64), %cmp_lhs ; LOWER-NEXT: $w0 = COPY %cmp(s32) ; LOWER-NEXT: RET_ReallyLR implicit $w0 + ; ; SELECT-LABEL: name: swap_and_lhs_0xFFFFFFFF ; SELECT: liveins: $x0, $x1 ; SELECT-NEXT: {{ $}} @@ -301,6 +308,7 @@ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %cmp_rhs ; LOWER-NEXT: $w0 = COPY %cmp(s32) ; LOWER-NEXT: RET_ReallyLR implicit $w0 + ; ; SELECT-LABEL: name: dont_swap_and_lhs_wrong_mask ; SELECT: liveins: $x0, $x1 ; SELECT-NEXT: {{ $}} @@ -340,6 +348,7 @@ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sgt), %cmp_rhs(s64), %cmp_lhs ; LOWER-NEXT: $w0 = COPY %cmp(s32) ; LOWER-NEXT: RET_ReallyLR implicit $w0 + ; ; SELECT-LABEL: name: swap_shl_lhs ; SELECT: liveins: $x0, $x1 ; SELECT-NEXT: {{ $}} @@ -378,6 +387,7 @@ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sgt), %cmp_rhs(s64), %cmp_lhs ; LOWER-NEXT: $w0 = COPY %cmp(s32) ; LOWER-NEXT: RET_ReallyLR implicit $w0 + ; ; SELECT-LABEL: name: swap_ashr_lhs ; SELECT: liveins: $x0, $x1 ; SELECT-NEXT: {{ $}} @@ -416,6 +426,7 @@ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sgt), %cmp_rhs(s64), %cmp_lhs ; LOWER-NEXT: $w0 = COPY %cmp(s32) ; LOWER-NEXT: RET_ReallyLR implicit $w0 + ; ; SELECT-LABEL: name: swap_lshr_lhs ; SELECT: liveins: $x0, $x1 ; SELECT-NEXT: {{ $}} @@ -456,6 +467,7 @@ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(slt), %cmp_lhs(s64), %cmp_rhs ; LOWER-NEXT: $w0 = COPY %cmp(s32) ; LOWER-NEXT: RET_ReallyLR implicit $w0 + ; ; SELECT-LABEL: name: dont_swap_shift_s64_cst_too_large ; SELECT: liveins: $x0, $x1 ; SELECT-NEXT: {{ $}} @@ -500,6 +512,7 @@ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(slt), %cmp_lhs(s32), %cmp_rhs ; LOWER-NEXT: $w0 = COPY %cmp(s32) ; LOWER-NEXT: RET_ReallyLR implicit $w0 + ; ; SELECT-LABEL: name: dont_swap_shift_s32_cst_too_large ; SELECT: liveins: $w0, $w1 ; SELECT-NEXT: {{ $}} @@ -544,6 +557,7 @@ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(ne), %cmp_lhs(s64), %cmp_rhs ; LOWER-NEXT: $w0 = COPY %cmp(s32) ; LOWER-NEXT: RET_ReallyLR implicit $w0 + ; ; SELECT-LABEL: name: dont_swap_cmn_lhs_no_folding_opportunities ; SELECT: liveins: $x0, $x1 ; SELECT-NEXT: {{ $}} @@ -588,6 +602,7 @@ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(ne), %cmp_rhs(s64), %cmp_lhs ; LOWER-NEXT: $w0 = COPY %cmp(s32) ; LOWER-NEXT: RET_ReallyLR implicit $w0 + ; ; SELECT-LABEL: name: swap_cmn_lhs ; SELECT: liveins: $x0, $x1 ; SELECT-NEXT: {{ $}} @@ -640,6 +655,7 @@ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(eq), %cmp_lhs(s64), %cmp_rhs ; LOWER-NEXT: $w0 = COPY %cmp(s32) ; LOWER-NEXT: RET_ReallyLR implicit $w0 + ; ; SELECT-LABEL: name: dont_swap_cmn_lhs_when_rhs_more_profitable ; SELECT: liveins: $x0, $x1 ; SELECT-NEXT: {{ $}} @@ -648,7 +664,7 @@ ; SELECT-NEXT: %shl:gpr64 = UBFMXri %reg0, 1, 0 ; SELECT-NEXT: %reg1:gpr64 = COPY $x1 ; SELECT-NEXT: %sext_in_reg:gpr64 = SBFMXri %reg1, 0, 0 - ; SELECT-NEXT: %cmp_rhs:gpr64 = SUBSXrs %zero, %sext_in_reg, 131, implicit-def $nzcv + ; SELECT-NEXT: %cmp_rhs:gpr64 = SUBSXrs %zero, %sext_in_reg, 131, implicit-def dead $nzcv ; SELECT-NEXT: [[ADDSXrr:%[0-9]+]]:gpr64 = ADDSXrr %shl, %cmp_rhs, implicit-def $nzcv ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv ; SELECT-NEXT: $w0 = COPY %cmp @@ -694,6 +710,7 @@ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(slt), %cmp_lhs(s64), %cmp_rhs ; LOWER-NEXT: $w0 = COPY %cmp(s32) ; LOWER-NEXT: RET_ReallyLR implicit $w0 + ; ; SELECT-LABEL: name: dont_swap_rhs_with_supported_extend ; SELECT: liveins: $x0, $x1 ; SELECT-NEXT: {{ $}} @@ -746,6 +763,7 @@ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(slt), %cmp_rhs(s64), %cmp_lhs ; LOWER-NEXT: $w0 = COPY %cmp(s32) ; LOWER-NEXT: RET_ReallyLR implicit $w0 + ; ; SELECT-LABEL: name: swap_rhs_with_supported_extend ; SELECT: liveins: $x0, $x1 ; SELECT-NEXT: {{ $}} diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-arith-extended-reg.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-arith-extended-reg.mir --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-arith-extended-reg.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-arith-extended-reg.mir @@ -13,11 +13,12 @@ liveins: $w1, $x2 ; CHECK-LABEL: name: add_sext_s32_to_s64 ; CHECK: liveins: $w1, $x2 - ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1 - ; CHECK: %add_lhs:gpr64sp = COPY $x2 - ; CHECK: %res:gpr64sp = ADDXrx %add_lhs, [[COPY]], 48 - ; CHECK: $x3 = COPY %res - ; CHECK: RET_ReallyLR implicit $x3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1 + ; CHECK-NEXT: %add_lhs:gpr64sp = COPY $x2 + ; CHECK-NEXT: %res:gpr64sp = ADDXrx %add_lhs, [[COPY]], 48 + ; CHECK-NEXT: $x3 = COPY %res + ; CHECK-NEXT: RET_ReallyLR implicit $x3 %1:gpr(s32) = COPY $w1 %ext:gpr(s64) = G_SEXT %1(s32) %add_lhs:gpr(s64) = COPY $x2 @@ -37,13 +38,14 @@ liveins: $x1, $x2 ; CHECK-LABEL: name: add_and_s32_to_s64 ; CHECK: liveins: $x1, $x2 - ; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY $x1 - ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[COPY]].sub_32 - ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]] - ; CHECK: %add_lhs:gpr64sp = COPY $x2 - ; CHECK: %res:gpr64sp = ADDXrx %add_lhs, [[COPY2]], 16 - ; CHECK: $x3 = COPY %res - ; CHECK: RET_ReallyLR implicit $x3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64all = COPY $x1 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[COPY]].sub_32 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]] + ; CHECK-NEXT: %add_lhs:gpr64sp = COPY $x2 + ; CHECK-NEXT: %res:gpr64sp = ADDXrx %add_lhs, [[COPY2]], 16 + ; CHECK-NEXT: $x3 = COPY %res + ; CHECK-NEXT: RET_ReallyLR implicit $x3 %1:gpr(s64) = COPY $x1 %mask:gpr(s64) = G_CONSTANT i64 4294967295 ; 0xffff %ext:gpr(s64) = G_AND %1(s64), %mask @@ -64,11 +66,12 @@ liveins: $w1, $w2, $x2 ; CHECK-LABEL: name: add_sext_s16_to_s32 ; CHECK: liveins: $w1, $w2, $x2 - ; CHECK: %wide_1:gpr32 = COPY $w1 - ; CHECK: %add_lhs:gpr32sp = COPY $w2 - ; CHECK: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 40 - ; CHECK: $w3 = COPY %res - ; CHECK: RET_ReallyLR implicit $w3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1 + ; CHECK-NEXT: %add_lhs:gpr32sp = COPY $w2 + ; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 40 + ; CHECK-NEXT: $w3 = COPY %res + ; CHECK-NEXT: RET_ReallyLR implicit $w3 %wide_1:gpr(s32) = COPY $w1 %1:gpr(s16) = G_TRUNC %wide_1 %ext:gpr(s32) = G_SEXT %1(s16) @@ -89,11 +92,12 @@ liveins: $w1, $w2, $x2 ; CHECK-LABEL: name: add_zext_s16_to_s32 ; CHECK: liveins: $w1, $w2, $x2 - ; CHECK: %wide_1:gpr32 = COPY $w1 - ; CHECK: %add_lhs:gpr32sp = COPY $w2 - ; CHECK: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 8 - ; CHECK: $w3 = COPY %res - ; CHECK: RET_ReallyLR implicit $w3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1 + ; CHECK-NEXT: %add_lhs:gpr32sp = COPY $w2 + ; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 8 + ; CHECK-NEXT: $w3 = COPY %res + ; CHECK-NEXT: RET_ReallyLR implicit $w3 %wide_1:gpr(s32) = COPY $w1 %1:gpr(s16) = G_TRUNC %wide_1 %ext:gpr(s32) = G_ZEXT %1(s16) @@ -114,11 +118,12 @@ liveins: $w1, $w2, $x2 ; CHECK-LABEL: name: add_anyext_s16_to_s32 ; CHECK: liveins: $w1, $w2, $x2 - ; CHECK: %wide_1:gpr32 = COPY $w1 - ; CHECK: %add_lhs:gpr32sp = COPY $w2 - ; CHECK: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 8 - ; CHECK: $w3 = COPY %res - ; CHECK: RET_ReallyLR implicit $w3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1 + ; CHECK-NEXT: %add_lhs:gpr32sp = COPY $w2 + ; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 8 + ; CHECK-NEXT: $w3 = COPY %res + ; CHECK-NEXT: RET_ReallyLR implicit $w3 %wide_1:gpr(s32) = COPY $w1 %1:gpr(s16) = G_TRUNC %wide_1 %ext:gpr(s32) = G_ANYEXT %1(s16) @@ -139,11 +144,12 @@ liveins: $w1, $w2, $x2 ; CHECK-LABEL: name: add_and_s16_to_s32_uxtb ; CHECK: liveins: $w1, $w2, $x2 - ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1 - ; CHECK: %add_lhs:gpr32sp = COPY $w2 - ; CHECK: %res:gpr32sp = ADDWrx %add_lhs, [[COPY]], 0 - ; CHECK: $w3 = COPY %res - ; CHECK: RET_ReallyLR implicit $w3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1 + ; CHECK-NEXT: %add_lhs:gpr32sp = COPY $w2 + ; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, [[COPY]], 0 + ; CHECK-NEXT: $w3 = COPY %res + ; CHECK-NEXT: RET_ReallyLR implicit $w3 %1:gpr(s32) = COPY $w1 %mask:gpr(s32) = G_CONSTANT i32 255 ; 0xff %ext:gpr(s32) = G_AND %1(s32), %mask @@ -164,11 +170,12 @@ liveins: $w1, $w2, $x2 ; CHECK-LABEL: name: add_and_s16_to_s32_uxth ; CHECK: liveins: $w1, $w2, $x2 - ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1 - ; CHECK: %add_lhs:gpr32sp = COPY $w2 - ; CHECK: %res:gpr32sp = ADDWrx %add_lhs, [[COPY]], 8 - ; CHECK: $w3 = COPY %res - ; CHECK: RET_ReallyLR implicit $w3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1 + ; CHECK-NEXT: %add_lhs:gpr32sp = COPY $w2 + ; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, [[COPY]], 8 + ; CHECK-NEXT: $w3 = COPY %res + ; CHECK-NEXT: RET_ReallyLR implicit $w3 %1:gpr(s32) = COPY $w1 %mask:gpr(s32) = G_CONSTANT i32 65535 ; 0xffff %ext:gpr(s32) = G_AND %1(s32), %mask @@ -189,11 +196,12 @@ liveins: $w1, $w2, $x2 ; CHECK-LABEL: name: add_sext_s8_to_s32 ; CHECK: liveins: $w1, $w2, $x2 - ; CHECK: %wide_1:gpr32 = COPY $w1 - ; CHECK: %add_lhs:gpr32sp = COPY $w2 - ; CHECK: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 32 - ; CHECK: $w3 = COPY %res - ; CHECK: RET_ReallyLR implicit $w3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1 + ; CHECK-NEXT: %add_lhs:gpr32sp = COPY $w2 + ; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 32 + ; CHECK-NEXT: $w3 = COPY %res + ; CHECK-NEXT: RET_ReallyLR implicit $w3 %wide_1:gpr(s32) = COPY $w1 %1:gpr(s8) = G_TRUNC %wide_1 %ext:gpr(s32) = G_SEXT %1(s8) @@ -214,11 +222,12 @@ liveins: $w1, $w2, $x2 ; CHECK-LABEL: name: add_zext_s8_to_s32 ; CHECK: liveins: $w1, $w2, $x2 - ; CHECK: %wide_1:gpr32 = COPY $w1 - ; CHECK: %add_lhs:gpr32sp = COPY $w2 - ; CHECK: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 0 - ; CHECK: $w3 = COPY %res - ; CHECK: RET_ReallyLR implicit $w3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1 + ; CHECK-NEXT: %add_lhs:gpr32sp = COPY $w2 + ; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 0 + ; CHECK-NEXT: $w3 = COPY %res + ; CHECK-NEXT: RET_ReallyLR implicit $w3 %wide_1:gpr(s32) = COPY $w1 %1:gpr(s8) = G_TRUNC %wide_1 %ext:gpr(s32) = G_ZEXT %1(s8) @@ -239,11 +248,12 @@ liveins: $w1, $w2, $x2 ; CHECK-LABEL: name: add_anyext_s8_to_s32 ; CHECK: liveins: $w1, $w2, $x2 - ; CHECK: %wide_1:gpr32 = COPY $w1 - ; CHECK: %add_lhs:gpr32sp = COPY $w2 - ; CHECK: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 0 - ; CHECK: $w3 = COPY %res - ; CHECK: RET_ReallyLR implicit $w3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1 + ; CHECK-NEXT: %add_lhs:gpr32sp = COPY $w2 + ; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 0 + ; CHECK-NEXT: $w3 = COPY %res + ; CHECK-NEXT: RET_ReallyLR implicit $w3 %wide_1:gpr(s32) = COPY $w1 %1:gpr(s8) = G_TRUNC %wide_1 %ext:gpr(s32) = G_ANYEXT %1(s8) @@ -264,11 +274,12 @@ liveins: $w1, $w2, $x2 ; CHECK-LABEL: name: add_sext_with_shl ; CHECK: liveins: $w1, $w2, $x2 - ; CHECK: %wide_1:gpr32 = COPY $w1 - ; CHECK: %add_lhs:gpr32sp = COPY $w2 - ; CHECK: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 43 - ; CHECK: $w3 = COPY %res - ; CHECK: RET_ReallyLR implicit $w3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1 + ; CHECK-NEXT: %add_lhs:gpr32sp = COPY $w2 + ; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 43 + ; CHECK-NEXT: $w3 = COPY %res + ; CHECK-NEXT: RET_ReallyLR implicit $w3 %wide_1:gpr(s32) = COPY $w1 %1:gpr(s16) = G_TRUNC %wide_1 %ext:gpr(s32) = G_SEXT %1(s16) @@ -291,11 +302,12 @@ liveins: $w1, $w2, $x2 ; CHECK-LABEL: name: add_and_with_shl ; CHECK: liveins: $w1, $w2, $x2 - ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1 - ; CHECK: %add_lhs:gpr32sp = COPY $w2 - ; CHECK: %res:gpr32sp = ADDWrx %add_lhs, [[COPY]], 3 - ; CHECK: $w3 = COPY %res - ; CHECK: RET_ReallyLR implicit $w3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1 + ; CHECK-NEXT: %add_lhs:gpr32sp = COPY $w2 + ; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, [[COPY]], 3 + ; CHECK-NEXT: $w3 = COPY %res + ; CHECK-NEXT: RET_ReallyLR implicit $w3 %1:gpr(s32) = COPY $w1 %mask:gpr(s32) = G_CONSTANT i32 255 ; 0xff %ext:gpr(s32) = G_AND %1(s32), %mask @@ -319,13 +331,14 @@ liveins: $w1, $w2, $x2 ; CHECK-LABEL: name: dont_fold_invalid_mask ; CHECK: liveins: $w1, $w2, $x2 - ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1 - ; CHECK: %mask:gpr32 = MOVi32imm 42 - ; CHECK: %ext:gpr32 = ANDWrr [[COPY]], %mask - ; CHECK: %add_lhs:gpr32 = COPY $w2 - ; CHECK: %res:gpr32 = ADDWrr %add_lhs, %ext - ; CHECK: $w3 = COPY %res - ; CHECK: RET_ReallyLR implicit $w3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1 + ; CHECK-NEXT: %mask:gpr32 = MOVi32imm 42 + ; CHECK-NEXT: %ext:gpr32 = ANDWrr [[COPY]], %mask + ; CHECK-NEXT: %add_lhs:gpr32 = COPY $w2 + ; CHECK-NEXT: %res:gpr32 = ADDWrr %add_lhs, %ext + ; CHECK-NEXT: $w3 = COPY %res + ; CHECK-NEXT: RET_ReallyLR implicit $w3 %1:gpr(s32) = COPY $w1 %mask:gpr(s32) = G_CONSTANT i32 42 %ext:gpr(s32) = G_AND %1(s32), %mask @@ -346,12 +359,13 @@ liveins: $w1, $w2, $x2 ; CHECK-LABEL: name: dont_fold_invalid_shl ; CHECK: liveins: $w1, $w2, $x2 - ; CHECK: %wide_1:gpr32 = COPY $w1 - ; CHECK: %ext:gpr32 = SBFMWri %wide_1, 0, 15 - ; CHECK: %add_lhs:gpr32 = COPY $w2 - ; CHECK: %res:gpr32 = ADDWrs %add_lhs, %ext, 5 - ; CHECK: $w3 = COPY %res - ; CHECK: RET_ReallyLR implicit $w3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1 + ; CHECK-NEXT: %ext:gpr32 = SBFMWri %wide_1, 0, 15 + ; CHECK-NEXT: %add_lhs:gpr32 = COPY $w2 + ; CHECK-NEXT: %res:gpr32 = ADDWrs %add_lhs, %ext, 5 + ; CHECK-NEXT: $w3 = COPY %res + ; CHECK-NEXT: RET_ReallyLR implicit $w3 %wide_1:gpr(s32) = COPY $w1 %1:gpr(s16) = G_TRUNC %wide_1 %ext:gpr(s32) = G_SEXT %1(s16) @@ -374,11 +388,12 @@ liveins: $w1, $x2 ; CHECK-LABEL: name: sub_sext_s32_to_s64 ; CHECK: liveins: $w1, $x2 - ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1 - ; CHECK: %sub_lhs:gpr64sp = COPY $x2 - ; CHECK: %res:gpr64 = SUBSXrx %sub_lhs, [[COPY]], 48, implicit-def $nzcv - ; CHECK: $x3 = COPY %res - ; CHECK: RET_ReallyLR implicit $x3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1 + ; CHECK-NEXT: %sub_lhs:gpr64sp = COPY $x2 + ; CHECK-NEXT: %res:gpr64 = SUBSXrx %sub_lhs, [[COPY]], 48, implicit-def dead $nzcv + ; CHECK-NEXT: $x3 = COPY %res + ; CHECK-NEXT: RET_ReallyLR implicit $x3 %1:gpr(s32) = COPY $w1 %ext:gpr(s64) = G_SEXT %1(s32) %sub_lhs:gpr(s64) = COPY $x2 @@ -398,11 +413,12 @@ liveins: $w1, $w2, $x2 ; CHECK-LABEL: name: sub_sext_s16_to_s32 ; CHECK: liveins: $w1, $w2, $x2 - ; CHECK: %wide_1:gpr32 = COPY $w1 - ; CHECK: %sub_lhs:gpr32sp = COPY $w2 - ; CHECK: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 40, implicit-def $nzcv - ; CHECK: $w3 = COPY %res - ; CHECK: RET_ReallyLR implicit $w3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1 + ; CHECK-NEXT: %sub_lhs:gpr32sp = COPY $w2 + ; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 40, implicit-def dead $nzcv + ; CHECK-NEXT: $w3 = COPY %res + ; CHECK-NEXT: RET_ReallyLR implicit $w3 %wide_1:gpr(s32) = COPY $w1 %1:gpr(s16) = G_TRUNC %wide_1 %ext:gpr(s32) = G_SEXT %1(s16) @@ -423,11 +439,12 @@ liveins: $w1, $w2, $x2 ; CHECK-LABEL: name: sub_zext_s16_to_s32 ; CHECK: liveins: $w1, $w2, $x2 - ; CHECK: %wide_1:gpr32 = COPY $w1 - ; CHECK: %sub_lhs:gpr32sp = COPY $w2 - ; CHECK: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 8, implicit-def $nzcv - ; CHECK: $w3 = COPY %res - ; CHECK: RET_ReallyLR implicit $w3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1 + ; CHECK-NEXT: %sub_lhs:gpr32sp = COPY $w2 + ; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 8, implicit-def dead $nzcv + ; CHECK-NEXT: $w3 = COPY %res + ; CHECK-NEXT: RET_ReallyLR implicit $w3 %wide_1:gpr(s32) = COPY $w1 %1:gpr(s16) = G_TRUNC %wide_1 %ext:gpr(s32) = G_ZEXT %1(s16) @@ -448,11 +465,12 @@ liveins: $w1, $w2, $x2 ; CHECK-LABEL: name: sub_anyext_s16_to_s32 ; CHECK: liveins: $w1, $w2, $x2 - ; CHECK: %wide_1:gpr32 = COPY $w1 - ; CHECK: %sub_lhs:gpr32sp = COPY $w2 - ; CHECK: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 8, implicit-def $nzcv - ; CHECK: $w3 = COPY %res - ; CHECK: RET_ReallyLR implicit $w3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1 + ; CHECK-NEXT: %sub_lhs:gpr32sp = COPY $w2 + ; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 8, implicit-def dead $nzcv + ; CHECK-NEXT: $w3 = COPY %res + ; CHECK-NEXT: RET_ReallyLR implicit $w3 %wide_1:gpr(s32) = COPY $w1 %1:gpr(s16) = G_TRUNC %wide_1 %ext:gpr(s32) = G_ANYEXT %1(s16) @@ -473,11 +491,12 @@ liveins: $w1, $w2, $x2 ; CHECK-LABEL: name: sub_and_s16_to_s32_uxtb ; CHECK: liveins: $w1, $w2, $x2 - ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1 - ; CHECK: %sub_lhs:gpr32sp = COPY $w2 - ; CHECK: %res:gpr32 = SUBSWrx %sub_lhs, [[COPY]], 0, implicit-def $nzcv - ; CHECK: $w3 = COPY %res - ; CHECK: RET_ReallyLR implicit $w3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1 + ; CHECK-NEXT: %sub_lhs:gpr32sp = COPY $w2 + ; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, [[COPY]], 0, implicit-def dead $nzcv + ; CHECK-NEXT: $w3 = COPY %res + ; CHECK-NEXT: RET_ReallyLR implicit $w3 %1:gpr(s32) = COPY $w1 %mask:gpr(s32) = G_CONSTANT i32 255 ; 0xff %ext:gpr(s32) = G_AND %1(s32), %mask @@ -498,11 +517,12 @@ liveins: $w1, $w2, $x2 ; CHECK-LABEL: name: sub_and_s16_to_s32_uxth ; CHECK: liveins: $w1, $w2, $x2 - ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1 - ; CHECK: %sub_lhs:gpr32sp = COPY $w2 - ; CHECK: %res:gpr32 = SUBSWrx %sub_lhs, [[COPY]], 8, implicit-def $nzcv - ; CHECK: $w3 = COPY %res - ; CHECK: RET_ReallyLR implicit $w3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1 + ; CHECK-NEXT: %sub_lhs:gpr32sp = COPY $w2 + ; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, [[COPY]], 8, implicit-def dead $nzcv + ; CHECK-NEXT: $w3 = COPY %res + ; CHECK-NEXT: RET_ReallyLR implicit $w3 %1:gpr(s32) = COPY $w1 %mask:gpr(s32) = G_CONSTANT i32 65535 ; 0xffff %ext:gpr(s32) = G_AND %1(s32), %mask @@ -540,11 +560,12 @@ liveins: $w1, $w2, $x2 ; CHECK-LABEL: name: sub_zext_s8_to_s32 ; CHECK: liveins: $w1, $w2, $x2 - ; CHECK: %wide_1:gpr32 = COPY $w1 - ; CHECK: %sub_lhs:gpr32sp = COPY $w2 - ; CHECK: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 0, implicit-def $nzcv - ; CHECK: $w3 = COPY %res - ; CHECK: RET_ReallyLR implicit $w3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1 + ; CHECK-NEXT: %sub_lhs:gpr32sp = COPY $w2 + ; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 0, implicit-def dead $nzcv + ; CHECK-NEXT: $w3 = COPY %res + ; CHECK-NEXT: RET_ReallyLR implicit $w3 %wide_1:gpr(s32) = COPY $w1 %1:gpr(s8) = G_TRUNC %wide_1 %ext:gpr(s32) = G_ZEXT %1(s8) @@ -565,11 +586,12 @@ liveins: $w1, $w2, $x2 ; CHECK-LABEL: name: sub_anyext_s8_to_s32 ; CHECK: liveins: $w1, $w2, $x2 - ; CHECK: %wide_1:gpr32 = COPY $w1 - ; CHECK: %sub_lhs:gpr32sp = COPY $w2 - ; CHECK: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 0, implicit-def $nzcv - ; CHECK: $w3 = COPY %res - ; CHECK: RET_ReallyLR implicit $w3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1 + ; CHECK-NEXT: %sub_lhs:gpr32sp = COPY $w2 + ; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 0, implicit-def dead $nzcv + ; CHECK-NEXT: $w3 = COPY %res + ; CHECK-NEXT: RET_ReallyLR implicit $w3 %wide_1:gpr(s32) = COPY $w1 %1:gpr(s8) = G_TRUNC %wide_1 %ext:gpr(s32) = G_ANYEXT %1(s8) @@ -591,11 +613,12 @@ liveins: $w1, $w2, $x2 ; CHECK-LABEL: name: sub_sext_with_shl ; CHECK: liveins: $w1, $w2, $x2 - ; CHECK: %wide_1:gpr32 = COPY $w1 - ; CHECK: %sub_lhs:gpr32sp = COPY $w2 - ; CHECK: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 43, implicit-def $nzcv - ; CHECK: $w3 = COPY %res - ; CHECK: RET_ReallyLR implicit $w3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1 + ; CHECK-NEXT: %sub_lhs:gpr32sp = COPY $w2 + ; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 43, implicit-def dead $nzcv + ; CHECK-NEXT: $w3 = COPY %res + ; CHECK-NEXT: RET_ReallyLR implicit $w3 %wide_1:gpr(s32) = COPY $w1 %1:gpr(s16) = G_TRUNC %wide_1 %ext:gpr(s32) = G_SEXT %1(s16) @@ -618,11 +641,12 @@ liveins: $w1, $w2, $x2 ; CHECK-LABEL: name: sub_and_with_shl ; CHECK: liveins: $w1, $w2, $x2 - ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1 - ; CHECK: %sub_lhs:gpr32sp = COPY $w2 - ; CHECK: %res:gpr32 = SUBSWrx %sub_lhs, [[COPY]], 3, implicit-def $nzcv - ; CHECK: $w3 = COPY %res - ; CHECK: RET_ReallyLR implicit $w3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1 + ; CHECK-NEXT: %sub_lhs:gpr32sp = COPY $w2 + ; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, [[COPY]], 3, implicit-def dead $nzcv + ; CHECK-NEXT: $w3 = COPY %res + ; CHECK-NEXT: RET_ReallyLR implicit $w3 %1:gpr(s32) = COPY $w1 %mask:gpr(s32) = G_CONSTANT i32 255 ; 0xff %ext:gpr(s32) = G_AND %1(s32), %mask @@ -649,14 +673,15 @@ ; CHECK-LABEL: name: store_16b_zext ; CHECK: liveins: $x0, $x1, $x2 - ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 - ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 - ; CHECK: [[COPY2:%[0-9]+]]:gpr64all = COPY $x2 - ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_32 - ; CHECK: %zext:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 15 - ; CHECK: [[COPY3:%[0-9]+]]:gpr64 = COPY [[COPY2]] - ; CHECK: STRXroX [[COPY3]], [[COPY]], %zext, 0, 1 :: (store (p0)) - ; CHECK: RET_ReallyLR + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY $x2 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_32 + ; CHECK-NEXT: %zext:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 15 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY [[COPY2]] + ; CHECK-NEXT: STRXroX [[COPY3]], [[COPY]], %zext, 0, 1 :: (store (p0)) + ; CHECK-NEXT: RET_ReallyLR %0:gpr(p0) = COPY $x0 %1:gpr(s32) = COPY $w1 %2:gpr(p0) = COPY $x2 @@ -684,14 +709,15 @@ ; CHECK-LABEL: name: store_8b_zext ; CHECK: liveins: $x0, $x1, $x2 - ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 - ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 - ; CHECK: [[COPY2:%[0-9]+]]:gpr64all = COPY $x2 - ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_32 - ; CHECK: %zext:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 7 - ; CHECK: [[COPY3:%[0-9]+]]:gpr64 = COPY [[COPY2]] - ; CHECK: STRXroX [[COPY3]], [[COPY]], %zext, 0, 1 :: (store (p0)) - ; CHECK: RET_ReallyLR + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY $x2 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_32 + ; CHECK-NEXT: %zext:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 7 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY [[COPY2]] + ; CHECK-NEXT: STRXroX [[COPY3]], [[COPY]], %zext, 0, 1 :: (store (p0)) + ; CHECK-NEXT: RET_ReallyLR %0:gpr(p0) = COPY $x0 %1:gpr(s32) = COPY $w1 %2:gpr(p0) = COPY $x2 @@ -719,14 +745,15 @@ ; CHECK-LABEL: name: store_16b_sext ; CHECK: liveins: $x0, $x1, $x2 - ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 - ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 - ; CHECK: [[COPY2:%[0-9]+]]:gpr64all = COPY $x2 - ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_32 - ; CHECK: %zext:gpr64 = SBFMXri [[SUBREG_TO_REG]], 0, 15 - ; CHECK: [[COPY3:%[0-9]+]]:gpr64 = COPY [[COPY2]] - ; CHECK: STRXroX [[COPY3]], [[COPY]], %zext, 0, 1 :: (store (p0)) - ; CHECK: RET_ReallyLR + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY $x2 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_32 + ; CHECK-NEXT: %zext:gpr64 = SBFMXri [[SUBREG_TO_REG]], 0, 15 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY [[COPY2]] + ; CHECK-NEXT: STRXroX [[COPY3]], [[COPY]], %zext, 0, 1 :: (store (p0)) + ; CHECK-NEXT: RET_ReallyLR %0:gpr(p0) = COPY $x0 %1:gpr(s32) = COPY $w1 %2:gpr(p0) = COPY $x2 @@ -754,14 +781,15 @@ ; CHECK-LABEL: name: store_8b_sext ; CHECK: liveins: $x0, $x1, $x2 - ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 - ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 - ; CHECK: [[COPY2:%[0-9]+]]:gpr64all = COPY $x2 - ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_32 - ; CHECK: %zext:gpr64 = SBFMXri [[SUBREG_TO_REG]], 0, 7 - ; CHECK: [[COPY3:%[0-9]+]]:gpr64 = COPY [[COPY2]] - ; CHECK: STRXroX [[COPY3]], [[COPY]], %zext, 0, 1 :: (store (p0)) - ; CHECK: RET_ReallyLR + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY $x2 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_32 + ; CHECK-NEXT: %zext:gpr64 = SBFMXri [[SUBREG_TO_REG]], 0, 7 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY [[COPY2]] + ; CHECK-NEXT: STRXroX [[COPY3]], [[COPY]], %zext, 0, 1 :: (store (p0)) + ; CHECK-NEXT: RET_ReallyLR %0:gpr(p0) = COPY $x0 %1:gpr(s32) = COPY $w1 %2:gpr(p0) = COPY $x2 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-arith-shifted-reg.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-arith-shifted-reg.mir --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-arith-shifted-reg.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-arith-shifted-reg.mir @@ -11,10 +11,11 @@ liveins: $x0 ; CHECK-LABEL: name: add_shl_s64_rhs ; CHECK: liveins: $x0 - ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 - ; CHECK: [[ADDXrs:%[0-9]+]]:gpr64 = ADDXrs [[COPY]], [[COPY]], 8 - ; CHECK: $x0 = COPY [[ADDXrs]] - ; CHECK: RET_ReallyLR implicit $x0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 + ; CHECK-NEXT: [[ADDXrs:%[0-9]+]]:gpr64 = ADDXrs [[COPY]], [[COPY]], 8 + ; CHECK-NEXT: $x0 = COPY [[ADDXrs]] + ; CHECK-NEXT: RET_ReallyLR implicit $x0 %0:gpr(s64) = COPY $x0 %1:gpr(s64) = G_CONSTANT i64 8 %2:gpr(s64) = G_SHL %0, %1:gpr(s64) @@ -33,11 +34,12 @@ liveins: $x0, $x1 ; CHECK-LABEL: name: add_shl_s64_lhs ; CHECK: liveins: $x0, $x1 - ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 - ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 - ; CHECK: [[ADDXrs:%[0-9]+]]:gpr64 = ADDXrs [[COPY1]], [[COPY]], 8 - ; CHECK: $x0 = COPY [[ADDXrs]] - ; CHECK: RET_ReallyLR implicit $x0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 + ; CHECK-NEXT: [[ADDXrs:%[0-9]+]]:gpr64 = ADDXrs [[COPY1]], [[COPY]], 8 + ; CHECK-NEXT: $x0 = COPY [[ADDXrs]] + ; CHECK-NEXT: RET_ReallyLR implicit $x0 %0:gpr(s64) = COPY $x0 %4:gpr(s64) = COPY $x1 %1:gpr(s64) = G_CONSTANT i64 8 @@ -57,10 +59,11 @@ liveins: $x0 ; CHECK-LABEL: name: sub_shl_s64_rhs ; CHECK: liveins: $x0 - ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 - ; CHECK: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs [[COPY]], [[COPY]], 8, implicit-def $nzcv - ; CHECK: $x0 = COPY [[SUBSXrs]] - ; CHECK: RET_ReallyLR implicit $x0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 + ; CHECK-NEXT: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs [[COPY]], [[COPY]], 8, implicit-def dead $nzcv + ; CHECK-NEXT: $x0 = COPY [[SUBSXrs]] + ; CHECK-NEXT: RET_ReallyLR implicit $x0 %0:gpr(s64) = COPY $x0 %1:gpr(s64) = G_CONSTANT i64 8 %2:gpr(s64) = G_SHL %0, %1:gpr(s64) @@ -94,11 +97,12 @@ liveins: $x0, $x1 ; CHECK-LABEL: name: add_lshr_s64_lhs ; CHECK: liveins: $x0, $x1 - ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 - ; CHECK: %param2:gpr64 = COPY $x1 - ; CHECK: [[ADDXrs:%[0-9]+]]:gpr64 = ADDXrs %param2, [[COPY]], 72 - ; CHECK: $x0 = COPY [[ADDXrs]] - ; CHECK: RET_ReallyLR implicit $x0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 + ; CHECK-NEXT: %param2:gpr64 = COPY $x1 + ; CHECK-NEXT: [[ADDXrs:%[0-9]+]]:gpr64 = ADDXrs %param2, [[COPY]], 72 + ; CHECK-NEXT: $x0 = COPY [[ADDXrs]] + ; CHECK-NEXT: RET_ReallyLR implicit $x0 %0:gpr(s64) = COPY $x0 %param2:gpr(s64) = COPY $x1 %1:gpr(s64) = G_CONSTANT i64 8 @@ -118,10 +122,11 @@ liveins: $x0 ; CHECK-LABEL: name: sub_lshr_s64_rhs ; CHECK: liveins: $x0 - ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 - ; CHECK: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs [[COPY]], [[COPY]], 72, implicit-def $nzcv - ; CHECK: $x0 = COPY [[SUBSXrs]] - ; CHECK: RET_ReallyLR implicit $x0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 + ; CHECK-NEXT: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs [[COPY]], [[COPY]], 72, implicit-def dead $nzcv + ; CHECK-NEXT: $x0 = COPY [[SUBSXrs]] + ; CHECK-NEXT: RET_ReallyLR implicit $x0 %0:gpr(s64) = COPY $x0 %1:gpr(s64) = G_CONSTANT i64 8 %2:gpr(s64) = G_LSHR %0, %1:gpr(s64) @@ -140,10 +145,11 @@ liveins: $x0 ; CHECK-LABEL: name: add_ashr_s64_rhs ; CHECK: liveins: $x0 - ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 - ; CHECK: [[ADDXrs:%[0-9]+]]:gpr64 = ADDXrs [[COPY]], [[COPY]], 136 - ; CHECK: $x0 = COPY [[ADDXrs]] - ; CHECK: RET_ReallyLR implicit $x0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 + ; CHECK-NEXT: [[ADDXrs:%[0-9]+]]:gpr64 = ADDXrs [[COPY]], [[COPY]], 136 + ; CHECK-NEXT: $x0 = COPY [[ADDXrs]] + ; CHECK-NEXT: RET_ReallyLR implicit $x0 %0:gpr(s64) = COPY $x0 %1:gpr(s64) = G_CONSTANT i64 8 %2:gpr(s64) = G_ASHR %0, %1:gpr(s64) @@ -162,11 +168,12 @@ liveins: $x0, $x1 ; CHECK-LABEL: name: add_ashr_s64_lhs ; CHECK: liveins: $x0, $x1 - ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 - ; CHECK: %param2:gpr64 = COPY $x1 - ; CHECK: [[ADDXrs:%[0-9]+]]:gpr64 = ADDXrs %param2, [[COPY]], 136 - ; CHECK: $x0 = COPY [[ADDXrs]] - ; CHECK: RET_ReallyLR implicit $x0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 + ; CHECK-NEXT: %param2:gpr64 = COPY $x1 + ; CHECK-NEXT: [[ADDXrs:%[0-9]+]]:gpr64 = ADDXrs %param2, [[COPY]], 136 + ; CHECK-NEXT: $x0 = COPY [[ADDXrs]] + ; CHECK-NEXT: RET_ReallyLR implicit $x0 %0:gpr(s64) = COPY $x0 %param2:gpr(s64) = COPY $x1 %1:gpr(s64) = G_CONSTANT i64 8 @@ -186,10 +193,11 @@ liveins: $x0 ; CHECK-LABEL: name: sub_ashr_s64_rhs ; CHECK: liveins: $x0 - ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 - ; CHECK: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs [[COPY]], [[COPY]], 136, implicit-def $nzcv - ; CHECK: $x0 = COPY [[SUBSXrs]] - ; CHECK: RET_ReallyLR implicit $x0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 + ; CHECK-NEXT: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs [[COPY]], [[COPY]], 136, implicit-def dead $nzcv + ; CHECK-NEXT: $x0 = COPY [[SUBSXrs]] + ; CHECK-NEXT: RET_ReallyLR implicit $x0 %0:gpr(s64) = COPY $x0 %1:gpr(s64) = G_CONSTANT i64 8 %2:gpr(s64) = G_ASHR %0, %1:gpr(s64) @@ -223,11 +231,12 @@ liveins: $w0, $w1 ; CHECK-LABEL: name: add_shl_s32_lhs ; CHECK: liveins: $w0, $w1 - ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 - ; CHECK: %param2:gpr32 = COPY $w1 - ; CHECK: [[ADDWrs:%[0-9]+]]:gpr32 = ADDWrs %param2, [[COPY]], 8 - ; CHECK: $w0 = COPY [[ADDWrs]] - ; CHECK: RET_ReallyLR implicit $w0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 + ; CHECK-NEXT: %param2:gpr32 = COPY $w1 + ; CHECK-NEXT: [[ADDWrs:%[0-9]+]]:gpr32 = ADDWrs %param2, [[COPY]], 8 + ; CHECK-NEXT: $w0 = COPY [[ADDWrs]] + ; CHECK-NEXT: RET_ReallyLR implicit $w0 %0:gpr(s32) = COPY $w0 %param2:gpr(s32) = COPY $w1 %1:gpr(s32) = G_CONSTANT i32 8 @@ -247,10 +256,11 @@ liveins: $w0 ; CHECK-LABEL: name: sub_shl_s32_rhs ; CHECK: liveins: $w0 - ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 - ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs [[COPY]], [[COPY]], 8, implicit-def $nzcv - ; CHECK: $w0 = COPY [[SUBSWrs]] - ; CHECK: RET_ReallyLR implicit $w0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 + ; CHECK-NEXT: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs [[COPY]], [[COPY]], 8, implicit-def dead $nzcv + ; CHECK-NEXT: $w0 = COPY [[SUBSWrs]] + ; CHECK-NEXT: RET_ReallyLR implicit $w0 %0:gpr(s32) = COPY $w0 %1:gpr(s32) = G_CONSTANT i32 8 %2:gpr(s32) = G_SHL %0, %1:gpr(s32) @@ -269,10 +279,11 @@ liveins: $w0 ; CHECK-LABEL: name: add_lshr_s32_rhs ; CHECK: liveins: $w0 - ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 - ; CHECK: [[ADDWrs:%[0-9]+]]:gpr32 = ADDWrs [[COPY]], [[COPY]], 72 - ; CHECK: $w0 = COPY [[ADDWrs]] - ; CHECK: RET_ReallyLR implicit $w0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 + ; CHECK-NEXT: [[ADDWrs:%[0-9]+]]:gpr32 = ADDWrs [[COPY]], [[COPY]], 72 + ; CHECK-NEXT: $w0 = COPY [[ADDWrs]] + ; CHECK-NEXT: RET_ReallyLR implicit $w0 %0:gpr(s32) = COPY $w0 %1:gpr(s32) = G_CONSTANT i32 8 %2:gpr(s32) = G_LSHR %0, %1:gpr(s32) @@ -291,11 +302,12 @@ liveins: $w0, $w1 ; CHECK-LABEL: name: add_lshr_s32_lhs ; CHECK: liveins: $w0, $w1 - ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 - ; CHECK: %param2:gpr32 = COPY $w1 - ; CHECK: [[ADDWrs:%[0-9]+]]:gpr32 = ADDWrs %param2, [[COPY]], 72 - ; CHECK: $w0 = COPY [[ADDWrs]] - ; CHECK: RET_ReallyLR implicit $w0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 + ; CHECK-NEXT: %param2:gpr32 = COPY $w1 + ; CHECK-NEXT: [[ADDWrs:%[0-9]+]]:gpr32 = ADDWrs %param2, [[COPY]], 72 + ; CHECK-NEXT: $w0 = COPY [[ADDWrs]] + ; CHECK-NEXT: RET_ReallyLR implicit $w0 %0:gpr(s32) = COPY $w0 %param2:gpr(s32) = COPY $w1 %1:gpr(s32) = G_CONSTANT i32 8 @@ -315,10 +327,11 @@ liveins: $w0 ; CHECK-LABEL: name: sub_lshr_s32_rhs ; CHECK: liveins: $w0 - ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 - ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs [[COPY]], [[COPY]], 72, implicit-def $nzcv - ; CHECK: $w0 = COPY [[SUBSWrs]] - ; CHECK: RET_ReallyLR implicit $w0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 + ; CHECK-NEXT: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs [[COPY]], [[COPY]], 72, implicit-def dead $nzcv + ; CHECK-NEXT: $w0 = COPY [[SUBSWrs]] + ; CHECK-NEXT: RET_ReallyLR implicit $w0 %0:gpr(s32) = COPY $w0 %1:gpr(s32) = G_CONSTANT i32 8 %2:gpr(s32) = G_LSHR %0, %1:gpr(s32) @@ -337,10 +350,11 @@ liveins: $w0 ; CHECK-LABEL: name: add_ashr_s32_rhs ; CHECK: liveins: $w0 - ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 - ; CHECK: [[ADDWrs:%[0-9]+]]:gpr32 = ADDWrs [[COPY]], [[COPY]], 136 - ; CHECK: $w0 = COPY [[ADDWrs]] - ; CHECK: RET_ReallyLR implicit $w0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 + ; CHECK-NEXT: [[ADDWrs:%[0-9]+]]:gpr32 = ADDWrs [[COPY]], [[COPY]], 136 + ; CHECK-NEXT: $w0 = COPY [[ADDWrs]] + ; CHECK-NEXT: RET_ReallyLR implicit $w0 %0:gpr(s32) = COPY $w0 %1:gpr(s32) = G_CONSTANT i32 8 %2:gpr(s32) = G_ASHR %0, %1:gpr(s32) @@ -359,11 +373,12 @@ liveins: $w0, $w1 ; CHECK-LABEL: name: add_ashr_s32_lhs ; CHECK: liveins: $w0, $w1 - ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 - ; CHECK: %param2:gpr32 = COPY $w1 - ; CHECK: [[ADDWrs:%[0-9]+]]:gpr32 = ADDWrs %param2, [[COPY]], 136 - ; CHECK: $w0 = COPY [[ADDWrs]] - ; CHECK: RET_ReallyLR implicit $w0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 + ; CHECK-NEXT: %param2:gpr32 = COPY $w1 + ; CHECK-NEXT: [[ADDWrs:%[0-9]+]]:gpr32 = ADDWrs %param2, [[COPY]], 136 + ; CHECK-NEXT: $w0 = COPY [[ADDWrs]] + ; CHECK-NEXT: RET_ReallyLR implicit $w0 %0:gpr(s32) = COPY $w0 %param2:gpr(s32) = COPY $w1 %1:gpr(s32) = G_CONSTANT i32 8 @@ -383,10 +398,11 @@ liveins: $w0 ; CHECK-LABEL: name: sub_ashr_s32_rhs ; CHECK: liveins: $w0 - ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 - ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs [[COPY]], [[COPY]], 136, implicit-def $nzcv - ; CHECK: $w0 = COPY [[SUBSWrs]] - ; CHECK: RET_ReallyLR implicit $w0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 + ; CHECK-NEXT: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs [[COPY]], [[COPY]], 136, implicit-def dead $nzcv + ; CHECK-NEXT: $w0 = COPY [[SUBSWrs]] + ; CHECK-NEXT: RET_ReallyLR implicit $w0 %0:gpr(s32) = COPY $w0 %1:gpr(s32) = G_CONSTANT i32 8 %2:gpr(s32) = G_ASHR %0, %1:gpr(s32) diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-binop.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-binop.mir --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-binop.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-binop.mir @@ -17,10 +17,12 @@ liveins: $w0, $w1 ; CHECK-LABEL: name: add_s32_gpr - ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 - ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 - ; CHECK: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY1]] - ; CHECK: $w0 = COPY [[ADDWrr]] + ; CHECK: liveins: $w0, $w1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 + ; CHECK-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY1]] + ; CHECK-NEXT: $w0 = COPY [[ADDWrr]] %0(s32) = COPY $w0 %1(s32) = COPY $w1 %2(s32) = G_ADD %0, %1 @@ -43,10 +45,12 @@ liveins: $x0, $x1 ; CHECK-LABEL: name: add_s64_gpr - ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 - ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 - ; CHECK: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[COPY1]] - ; CHECK: $x0 = COPY [[ADDXrr]] + ; CHECK: liveins: $x0, $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 + ; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x0 = COPY [[ADDXrr]] %0(s64) = COPY $x0 %1(s64) = COPY $x1 %2(s64) = G_ADD %0, %1 @@ -68,9 +72,11 @@ liveins: $w0, $w1 ; CHECK-LABEL: name: add_imm_s32_gpr - ; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0 - ; CHECK: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY]], 1, 0 - ; CHECK: $w0 = COPY [[ADDWri]] + ; CHECK: liveins: $w0, $w1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0 + ; CHECK-NEXT: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY]], 1, 0 + ; CHECK-NEXT: $w0 = COPY [[ADDWri]] %0(s32) = COPY $w0 %1(s32) = G_CONSTANT i32 1 %2(s32) = G_ADD %0, %1 @@ -92,9 +98,11 @@ liveins: $x0, $w1 ; CHECK-LABEL: name: add_imm_s64_gpr - ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 - ; CHECK: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri [[COPY]], 1, 0 - ; CHECK: $x0 = COPY [[ADDXri]] + ; CHECK: liveins: $x0, $w1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 + ; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri [[COPY]], 1, 0 + ; CHECK-NEXT: $x0 = COPY [[ADDXri]] %0(s64) = COPY $x0 %1(s64) = G_CONSTANT i64 1 %2(s64) = G_ADD %0, %1 @@ -116,9 +124,11 @@ liveins: $w1, $w2 ; We should be able to turn the ADD into a SUB. ; CHECK-LABEL: name: add_neg_s32_gpr - ; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w1 - ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 0, implicit-def $nzcv - ; CHECK: $w2 = COPY [[SUBSWri]] + ; CHECK: liveins: $w1, $w2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32sp = COPY $w1 + ; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 0, implicit-def dead $nzcv + ; CHECK-NEXT: $w2 = COPY [[SUBSWri]] %0(s32) = COPY $w1 %1(s32) = G_CONSTANT i32 -1 %2(s32) = G_ADD %0, %1 @@ -140,9 +150,11 @@ liveins: $x0, $x1 ; We should be able to turn the ADD into a SUB. ; CHECK-LABEL: name: add_neg_s64_gpr - ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 - ; CHECK: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[COPY]], 1, 0, implicit-def $nzcv - ; CHECK: $x0 = COPY [[SUBSXri]] + ; CHECK: liveins: $x0, $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 + ; CHECK-NEXT: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[COPY]], 1, 0, implicit-def dead $nzcv + ; CHECK-NEXT: $x0 = COPY [[SUBSXri]] %0(s64) = COPY $x0 %1(s64) = G_CONSTANT i64 -1 %2(s64) = G_ADD %0, %1 @@ -164,10 +176,12 @@ liveins: $x0, $x1 ; We can't select this if the value is out of range. ; CHECK-LABEL: name: add_neg_invalid_immed_s32 - ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 - ; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm -5000 - ; CHECK: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[MOVi64imm]] - ; CHECK: $x0 = COPY [[ADDXrr]] + ; CHECK: liveins: $x0, $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 + ; CHECK-NEXT: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm -5000 + ; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[MOVi64imm]] + ; CHECK-NEXT: $x0 = COPY [[ADDXrr]] %0(s64) = COPY $x0 %1(s64) = G_CONSTANT i64 -5000 %2(s64) = G_ADD %0, %1 @@ -189,10 +203,12 @@ liveins: $x0, $x1 ; We can't select this if the value is out of range. ; CHECK-LABEL: name: add_neg_invalid_immed_s64 - ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 - ; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm -5000 - ; CHECK: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[MOVi64imm]] - ; CHECK: $x0 = COPY [[ADDXrr]] + ; CHECK: liveins: $x0, $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 + ; CHECK-NEXT: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm -5000 + ; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[MOVi64imm]] + ; CHECK-NEXT: $x0 = COPY [[ADDXrr]] %0(s64) = COPY $x0 %1(s64) = G_CONSTANT i64 -5000 %2(s64) = G_ADD %0, %1 @@ -215,9 +231,11 @@ ; We shouldn't get a SUB here, because "cmp wN, $0" and "cmp wN, #0" have ; opposite effects on the C flag. ; CHECK-LABEL: name: add_imm_0_s32 - ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 - ; CHECK: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri [[COPY]], 0, 0 - ; CHECK: $x0 = COPY [[ADDXri]] + ; CHECK: liveins: $x0, $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 + ; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri [[COPY]], 0, 0 + ; CHECK-NEXT: $x0 = COPY [[ADDXri]] %0(s64) = COPY $x0 %1(s64) = G_CONSTANT i64 0 %2(s64) = G_ADD %0, %1 @@ -240,9 +258,11 @@ ; We shouldn't get a SUB here, because "cmp xN, $0" and "cmp xN, #0" have ; opposite effects on the C flag. ; CHECK-LABEL: name: add_imm_0_s64 - ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 - ; CHECK: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri [[COPY]], 0, 0 - ; CHECK: $x0 = COPY [[ADDXri]] + ; CHECK: liveins: $x0, $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 + ; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri [[COPY]], 0, 0 + ; CHECK-NEXT: $x0 = COPY [[ADDXri]] %0(s64) = COPY $x0 %1(s64) = G_CONSTANT i64 0 %2(s64) = G_ADD %0, %1 @@ -262,12 +282,15 @@ body: | ; CHECK-LABEL: name: add_imm_s32_gpr_bb ; CHECK: bb.0: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0 - ; CHECK: B %bb.1 - ; CHECK: bb.1: - ; CHECK: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY]], 1, 0 - ; CHECK: $w0 = COPY [[ADDWri]] + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $w0, $w1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0 + ; CHECK-NEXT: B %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY]], 1, 0 + ; CHECK-NEXT: $w0 = COPY [[ADDWri]] bb.0: liveins: $w0, $w1 successors: %bb.1 @@ -297,10 +320,12 @@ liveins: $w0, $w1 ; CHECK-LABEL: name: sub_s32_gpr - ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 - ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 - ; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY]], [[COPY1]], implicit-def dead $nzcv - ; CHECK: $w0 = COPY [[SUBSWrr]] + ; CHECK: liveins: $w0, $w1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 + ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY]], [[COPY1]], implicit-def dead $nzcv + ; CHECK-NEXT: $w0 = COPY [[SUBSWrr]] %0(s32) = COPY $w0 %1(s32) = COPY $w1 %2(s32) = G_SUB %0, %1 @@ -323,10 +348,12 @@ liveins: $x0, $x1 ; CHECK-LABEL: name: sub_s64_gpr - ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 - ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 - ; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[COPY1]], implicit-def dead $nzcv - ; CHECK: $x0 = COPY [[SUBSXrr]] + ; CHECK: liveins: $x0, $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 + ; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[COPY1]], implicit-def dead $nzcv + ; CHECK-NEXT: $x0 = COPY [[SUBSXrr]] %0(s64) = COPY $x0 %1(s64) = COPY $x1 %2(s64) = G_SUB %0, %1 @@ -349,10 +376,12 @@ liveins: $w0, $w1 ; CHECK-LABEL: name: or_s32_gpr - ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 - ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 - ; CHECK: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[COPY]], [[COPY1]] - ; CHECK: $w0 = COPY [[ORRWrr]] + ; CHECK: liveins: $w0, $w1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 + ; CHECK-NEXT: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[COPY]], [[COPY1]] + ; CHECK-NEXT: $w0 = COPY [[ORRWrr]] %0(s32) = COPY $w0 %1(s32) = COPY $w1 %2(s32) = G_OR %0, %1 @@ -375,10 +404,12 @@ liveins: $x0, $x1 ; CHECK-LABEL: name: or_s64_gpr - ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 - ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 - ; CHECK: [[ORRXrr:%[0-9]+]]:gpr64 = ORRXrr [[COPY]], [[COPY1]] - ; CHECK: $x0 = COPY [[ORRXrr]] + ; CHECK: liveins: $x0, $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 + ; CHECK-NEXT: [[ORRXrr:%[0-9]+]]:gpr64 = ORRXrr [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x0 = COPY [[ORRXrr]] %0(s64) = COPY $x0 %1(s64) = COPY $x1 %2(s64) = G_OR %0, %1 @@ -403,10 +434,12 @@ liveins: $d0, $d1 ; CHECK-LABEL: name: or_v2s32_fpr - ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 - ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 - ; CHECK: [[ORRv8i8_:%[0-9]+]]:fpr64 = ORRv8i8 [[COPY]], [[COPY1]] - ; CHECK: $d0 = COPY [[ORRv8i8_]] + ; CHECK: liveins: $d0, $d1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK-NEXT: [[ORRv8i8_:%[0-9]+]]:fpr64 = ORRv8i8 [[COPY]], [[COPY1]] + ; CHECK-NEXT: $d0 = COPY [[ORRv8i8_]] %0(<2 x s32>) = COPY $d0 %1(<2 x s32>) = COPY $d1 %2(<2 x s32>) = G_OR %0, %1 @@ -429,10 +462,12 @@ liveins: $w0, $w1 ; CHECK-LABEL: name: and_s32_gpr - ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 - ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 - ; CHECK: [[ANDWrr:%[0-9]+]]:gpr32 = ANDWrr [[COPY]], [[COPY1]] - ; CHECK: $w0 = COPY [[ANDWrr]] + ; CHECK: liveins: $w0, $w1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 + ; CHECK-NEXT: [[ANDWrr:%[0-9]+]]:gpr32 = ANDWrr [[COPY]], [[COPY1]] + ; CHECK-NEXT: $w0 = COPY [[ANDWrr]] %0(s32) = COPY $w0 %1(s32) = COPY $w1 %2(s32) = G_AND %0, %1 @@ -455,10 +490,12 @@ liveins: $x0, $x1 ; CHECK-LABEL: name: and_s64_gpr - ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 - ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 - ; CHECK: [[ANDXrr:%[0-9]+]]:gpr64 = ANDXrr [[COPY]], [[COPY1]] - ; CHECK: $x0 = COPY [[ANDXrr]] + ; CHECK: liveins: $x0, $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 + ; CHECK-NEXT: [[ANDXrr:%[0-9]+]]:gpr64 = ANDXrr [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x0 = COPY [[ANDXrr]] %0(s64) = COPY $x0 %1(s64) = COPY $x1 %2(s64) = G_AND %0, %1 @@ -481,10 +518,12 @@ liveins: $w0, $w1 ; CHECK-LABEL: name: shl_s32_gpr - ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 - ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 - ; CHECK: [[LSLVWr:%[0-9]+]]:gpr32 = LSLVWr [[COPY]], [[COPY1]] - ; CHECK: $w0 = COPY [[LSLVWr]] + ; CHECK: liveins: $w0, $w1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 + ; CHECK-NEXT: [[LSLVWr:%[0-9]+]]:gpr32 = LSLVWr [[COPY]], [[COPY1]] + ; CHECK-NEXT: $w0 = COPY [[LSLVWr]] %0(s32) = COPY $w0 %1(s32) = COPY $w1 %2(s32) = G_SHL %0, %1 @@ -506,11 +545,13 @@ liveins: $w0, $x1 ; CHECK-LABEL: name: shl_s32_64_gpr - ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 - ; CHECK: [[COPY1:%[0-9]+]]:gpr64all = COPY $x1 - ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]].sub_32 - ; CHECK: [[LSLVWr:%[0-9]+]]:gpr32 = LSLVWr [[COPY]], [[COPY2]] - ; CHECK: $w0 = COPY [[LSLVWr]] + ; CHECK: liveins: $w0, $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64all = COPY $x1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]].sub_32 + ; CHECK-NEXT: [[LSLVWr:%[0-9]+]]:gpr32 = LSLVWr [[COPY]], [[COPY2]] + ; CHECK-NEXT: $w0 = COPY [[LSLVWr]] %0(s32) = COPY $w0 %1(s64) = COPY $x1 %2(s32) = G_SHL %0, %1 @@ -533,10 +574,12 @@ liveins: $x0, $x1 ; CHECK-LABEL: name: shl_s64_gpr - ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 - ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 - ; CHECK: [[LSLVXr:%[0-9]+]]:gpr64 = LSLVXr [[COPY]], [[COPY1]] - ; CHECK: $x0 = COPY [[LSLVXr]] + ; CHECK: liveins: $x0, $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 + ; CHECK-NEXT: [[LSLVXr:%[0-9]+]]:gpr64 = LSLVXr [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x0 = COPY [[LSLVXr]] %0(s64) = COPY $x0 %1(s64) = COPY $x1 %2(s64) = G_SHL %0, %1 @@ -559,10 +602,12 @@ liveins: $w0, $w1 ; CHECK-LABEL: name: lshr_s32_gpr - ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 - ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 - ; CHECK: [[LSRVWr:%[0-9]+]]:gpr32 = LSRVWr [[COPY]], [[COPY1]] - ; CHECK: $w0 = COPY [[LSRVWr]] + ; CHECK: liveins: $w0, $w1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 + ; CHECK-NEXT: [[LSRVWr:%[0-9]+]]:gpr32 = LSRVWr [[COPY]], [[COPY1]] + ; CHECK-NEXT: $w0 = COPY [[LSRVWr]] %0(s32) = COPY $w0 %1(s32) = COPY $w1 %2(s32) = G_LSHR %0, %1 @@ -585,10 +630,12 @@ liveins: $x0, $x1 ; CHECK-LABEL: name: lshr_s64_gpr - ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 - ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 - ; CHECK: [[LSRVXr:%[0-9]+]]:gpr64 = LSRVXr [[COPY]], [[COPY1]] - ; CHECK: $x0 = COPY [[LSRVXr]] + ; CHECK: liveins: $x0, $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 + ; CHECK-NEXT: [[LSRVXr:%[0-9]+]]:gpr64 = LSRVXr [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x0 = COPY [[LSRVXr]] %0(s64) = COPY $x0 %1(s64) = COPY $x1 %2(s64) = G_LSHR %0, %1 @@ -611,10 +658,12 @@ liveins: $w0, $w1 ; CHECK-LABEL: name: ashr_s32_gpr - ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 - ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 - ; CHECK: [[ASRVWr:%[0-9]+]]:gpr32 = ASRVWr [[COPY]], [[COPY1]] - ; CHECK: $w0 = COPY [[ASRVWr]] + ; CHECK: liveins: $w0, $w1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 + ; CHECK-NEXT: [[ASRVWr:%[0-9]+]]:gpr32 = ASRVWr [[COPY]], [[COPY1]] + ; CHECK-NEXT: $w0 = COPY [[ASRVWr]] %0(s32) = COPY $w0 %1(s32) = COPY $w1 %2(s32) = G_ASHR %0, %1 @@ -637,10 +686,12 @@ liveins: $x0, $x1 ; CHECK-LABEL: name: ashr_s64_gpr - ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 - ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 - ; CHECK: [[ASRVXr:%[0-9]+]]:gpr64 = ASRVXr [[COPY]], [[COPY1]] - ; CHECK: $x0 = COPY [[ASRVXr]] + ; CHECK: liveins: $x0, $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 + ; CHECK-NEXT: [[ASRVXr:%[0-9]+]]:gpr64 = ASRVXr [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x0 = COPY [[ASRVXr]] %0(s64) = COPY $x0 %1(s64) = COPY $x1 %2(s64) = G_ASHR %0, %1 @@ -664,10 +715,12 @@ liveins: $w0, $w1 ; CHECK-LABEL: name: mul_s32_gpr - ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 - ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 - ; CHECK: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY]], [[COPY1]], $wzr - ; CHECK: $w0 = COPY [[MADDWrrr]] + ; CHECK: liveins: $w0, $w1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 + ; CHECK-NEXT: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY]], [[COPY1]], $wzr + ; CHECK-NEXT: $w0 = COPY [[MADDWrrr]] %0(s32) = COPY $w0 %1(s32) = COPY $w1 %2(s32) = G_MUL %0, %1 @@ -690,10 +743,12 @@ liveins: $x0, $x1 ; CHECK-LABEL: name: mul_s64_gpr - ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 - ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 - ; CHECK: [[MADDXrrr:%[0-9]+]]:gpr64 = MADDXrrr [[COPY]], [[COPY1]], $xzr - ; CHECK: $x0 = COPY [[MADDXrrr]] + ; CHECK: liveins: $x0, $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 + ; CHECK-NEXT: [[MADDXrrr:%[0-9]+]]:gpr64 = MADDXrrr [[COPY]], [[COPY1]], $xzr + ; CHECK-NEXT: $x0 = COPY [[MADDXrrr]] %0(s64) = COPY $x0 %1(s64) = COPY $x1 %2(s64) = G_MUL %0, %1 @@ -712,12 +767,14 @@ liveins: $x0, $x1 ; CHECK-LABEL: name: mulh_s64_gpr - ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 - ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 - ; CHECK: [[SMULHrr:%[0-9]+]]:gpr64 = SMULHrr [[COPY]], [[COPY1]] - ; CHECK: [[UMULHrr:%[0-9]+]]:gpr64 = UMULHrr [[COPY]], [[COPY1]] - ; CHECK: $x0 = COPY [[SMULHrr]] - ; CHECK: $x0 = COPY [[UMULHrr]] + ; CHECK: liveins: $x0, $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 + ; CHECK-NEXT: [[SMULHrr:%[0-9]+]]:gpr64 = SMULHrr [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[UMULHrr:%[0-9]+]]:gpr64 = UMULHrr [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x0 = COPY [[SMULHrr]] + ; CHECK-NEXT: $x0 = COPY [[UMULHrr]] %0:gpr(s64) = COPY $x0 %1:gpr(s64) = COPY $x1 %2:gpr(s64) = G_SMULH %0, %1 @@ -742,10 +799,12 @@ liveins: $w0, $w1 ; CHECK-LABEL: name: sdiv_s32_gpr - ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 - ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 - ; CHECK: [[SDIVWr:%[0-9]+]]:gpr32 = SDIVWr [[COPY]], [[COPY1]] - ; CHECK: $w0 = COPY [[SDIVWr]] + ; CHECK: liveins: $w0, $w1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 + ; CHECK-NEXT: [[SDIVWr:%[0-9]+]]:gpr32 = SDIVWr [[COPY]], [[COPY1]] + ; CHECK-NEXT: $w0 = COPY [[SDIVWr]] %0(s32) = COPY $w0 %1(s32) = COPY $w1 %2(s32) = G_SDIV %0, %1 @@ -768,10 +827,12 @@ liveins: $x0, $x1 ; CHECK-LABEL: name: sdiv_s64_gpr - ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 - ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 - ; CHECK: [[SDIVXr:%[0-9]+]]:gpr64 = SDIVXr [[COPY]], [[COPY1]] - ; CHECK: $x0 = COPY [[SDIVXr]] + ; CHECK: liveins: $x0, $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 + ; CHECK-NEXT: [[SDIVXr:%[0-9]+]]:gpr64 = SDIVXr [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x0 = COPY [[SDIVXr]] %0(s64) = COPY $x0 %1(s64) = COPY $x1 %2(s64) = G_SDIV %0, %1 @@ -794,10 +855,12 @@ liveins: $w0, $w1 ; CHECK-LABEL: name: udiv_s32_gpr - ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 - ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 - ; CHECK: [[UDIVWr:%[0-9]+]]:gpr32 = UDIVWr [[COPY]], [[COPY1]] - ; CHECK: $w0 = COPY [[UDIVWr]] + ; CHECK: liveins: $w0, $w1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 + ; CHECK-NEXT: [[UDIVWr:%[0-9]+]]:gpr32 = UDIVWr [[COPY]], [[COPY1]] + ; CHECK-NEXT: $w0 = COPY [[UDIVWr]] %0(s32) = COPY $w0 %1(s32) = COPY $w1 %2(s32) = G_UDIV %0, %1 @@ -820,10 +883,12 @@ liveins: $x0, $x1 ; CHECK-LABEL: name: udiv_s64_gpr - ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 - ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 - ; CHECK: [[UDIVXr:%[0-9]+]]:gpr64 = UDIVXr [[COPY]], [[COPY1]] - ; CHECK: $x0 = COPY [[UDIVXr]] + ; CHECK: liveins: $x0, $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 + ; CHECK-NEXT: [[UDIVXr:%[0-9]+]]:gpr64 = UDIVXr [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x0 = COPY [[UDIVXr]] %0(s64) = COPY $x0 %1(s64) = COPY $x1 %2(s64) = G_UDIV %0, %1 @@ -846,10 +911,12 @@ liveins: $s0, $s1 ; CHECK-LABEL: name: fadd_s32_fpr - ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0 - ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1 - ; CHECK: [[FADDSrr:%[0-9]+]]:fpr32 = nofpexcept FADDSrr [[COPY]], [[COPY1]] - ; CHECK: $s0 = COPY [[FADDSrr]] + ; CHECK: liveins: $s0, $s1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1 + ; CHECK-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = nofpexcept FADDSrr [[COPY]], [[COPY1]], implicit $fpcr + ; CHECK-NEXT: $s0 = COPY [[FADDSrr]] %0(s32) = COPY $s0 %1(s32) = COPY $s1 %2(s32) = G_FADD %0, %1 @@ -871,10 +938,12 @@ liveins: $d0, $d1 ; CHECK-LABEL: name: fadd_s64_fpr - ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 - ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 - ; CHECK: [[FADDDrr:%[0-9]+]]:fpr64 = nofpexcept FADDDrr [[COPY]], [[COPY1]] - ; CHECK: $d0 = COPY [[FADDDrr]] + ; CHECK: liveins: $d0, $d1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK-NEXT: [[FADDDrr:%[0-9]+]]:fpr64 = nofpexcept FADDDrr [[COPY]], [[COPY1]], implicit $fpcr + ; CHECK-NEXT: $d0 = COPY [[FADDDrr]] %0(s64) = COPY $d0 %1(s64) = COPY $d1 %2(s64) = G_FADD %0, %1 @@ -896,10 +965,12 @@ liveins: $s0, $s1 ; CHECK-LABEL: name: fsub_s32_fpr - ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0 - ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1 - ; CHECK: [[FSUBSrr:%[0-9]+]]:fpr32 = nofpexcept FSUBSrr [[COPY]], [[COPY1]] - ; CHECK: $s0 = COPY [[FSUBSrr]] + ; CHECK: liveins: $s0, $s1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1 + ; CHECK-NEXT: [[FSUBSrr:%[0-9]+]]:fpr32 = nofpexcept FSUBSrr [[COPY]], [[COPY1]], implicit $fpcr + ; CHECK-NEXT: $s0 = COPY [[FSUBSrr]] %0(s32) = COPY $s0 %1(s32) = COPY $s1 %2(s32) = G_FSUB %0, %1 @@ -921,10 +992,12 @@ liveins: $d0, $d1 ; CHECK-LABEL: name: fsub_s64_fpr - ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 - ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 - ; CHECK: [[FSUBDrr:%[0-9]+]]:fpr64 = nofpexcept FSUBDrr [[COPY]], [[COPY1]] - ; CHECK: $d0 = COPY [[FSUBDrr]] + ; CHECK: liveins: $d0, $d1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK-NEXT: [[FSUBDrr:%[0-9]+]]:fpr64 = nofpexcept FSUBDrr [[COPY]], [[COPY1]], implicit $fpcr + ; CHECK-NEXT: $d0 = COPY [[FSUBDrr]] %0(s64) = COPY $d0 %1(s64) = COPY $d1 %2(s64) = G_FSUB %0, %1 @@ -946,10 +1019,12 @@ liveins: $s0, $s1 ; CHECK-LABEL: name: fmul_s32_fpr - ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0 - ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1 - ; CHECK: [[FMULSrr:%[0-9]+]]:fpr32 = nofpexcept FMULSrr [[COPY]], [[COPY1]] - ; CHECK: $s0 = COPY [[FMULSrr]] + ; CHECK: liveins: $s0, $s1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1 + ; CHECK-NEXT: [[FMULSrr:%[0-9]+]]:fpr32 = nofpexcept FMULSrr [[COPY]], [[COPY1]], implicit $fpcr + ; CHECK-NEXT: $s0 = COPY [[FMULSrr]] %0(s32) = COPY $s0 %1(s32) = COPY $s1 %2(s32) = G_FMUL %0, %1 @@ -971,10 +1046,12 @@ liveins: $d0, $d1 ; CHECK-LABEL: name: fmul_s64_fpr - ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 - ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 - ; CHECK: [[FMULDrr:%[0-9]+]]:fpr64 = nofpexcept FMULDrr [[COPY]], [[COPY1]] - ; CHECK: $d0 = COPY [[FMULDrr]] + ; CHECK: liveins: $d0, $d1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK-NEXT: [[FMULDrr:%[0-9]+]]:fpr64 = nofpexcept FMULDrr [[COPY]], [[COPY1]], implicit $fpcr + ; CHECK-NEXT: $d0 = COPY [[FMULDrr]] %0(s64) = COPY $d0 %1(s64) = COPY $d1 %2(s64) = G_FMUL %0, %1 @@ -996,10 +1073,12 @@ liveins: $s0, $s1 ; CHECK-LABEL: name: fdiv_s32_fpr - ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0 - ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1 - ; CHECK: [[FDIVSrr:%[0-9]+]]:fpr32 = nofpexcept FDIVSrr [[COPY]], [[COPY1]] - ; CHECK: $s0 = COPY [[FDIVSrr]] + ; CHECK: liveins: $s0, $s1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1 + ; CHECK-NEXT: [[FDIVSrr:%[0-9]+]]:fpr32 = nofpexcept FDIVSrr [[COPY]], [[COPY1]], implicit $fpcr + ; CHECK-NEXT: $s0 = COPY [[FDIVSrr]] %0(s32) = COPY $s0 %1(s32) = COPY $s1 %2(s32) = G_FDIV %0, %1 @@ -1021,10 +1100,12 @@ liveins: $d0, $d1 ; CHECK-LABEL: name: fdiv_s64_fpr - ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 - ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 - ; CHECK: [[FDIVDrr:%[0-9]+]]:fpr64 = nofpexcept FDIVDrr [[COPY]], [[COPY1]] - ; CHECK: $d0 = COPY [[FDIVDrr]] + ; CHECK: liveins: $d0, $d1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK-NEXT: [[FDIVDrr:%[0-9]+]]:fpr64 = nofpexcept FDIVDrr [[COPY]], [[COPY1]], implicit $fpcr + ; CHECK-NEXT: $d0 = COPY [[FDIVDrr]] %0(s64) = COPY $d0 %1(s64) = COPY $d1 %2(s64) = G_FDIV %0, %1 @@ -1047,11 +1128,12 @@ ; CHECK-LABEL: name: add_v8i16 ; CHECK: liveins: $q0, $q1 - ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 - ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 - ; CHECK: [[ADDv8i16_:%[0-9]+]]:fpr128 = ADDv8i16 [[COPY]], [[COPY1]] - ; CHECK: $q0 = COPY [[ADDv8i16_]] - ; CHECK: RET_ReallyLR implicit $q0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 + ; CHECK-NEXT: [[ADDv8i16_:%[0-9]+]]:fpr128 = ADDv8i16 [[COPY]], [[COPY1]] + ; CHECK-NEXT: $q0 = COPY [[ADDv8i16_]] + ; CHECK-NEXT: RET_ReallyLR implicit $q0 %0:fpr(<8 x s16>) = COPY $q0 %1:fpr(<8 x s16>) = COPY $q1 %2:fpr(<8 x s16>) = G_ADD %0, %1 @@ -1076,11 +1158,12 @@ ; CHECK-LABEL: name: add_v16i8 ; CHECK: liveins: $q0, $q1 - ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 - ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 - ; CHECK: [[ADDv16i8_:%[0-9]+]]:fpr128 = ADDv16i8 [[COPY]], [[COPY1]] - ; CHECK: $q0 = COPY [[ADDv16i8_]] - ; CHECK: RET_ReallyLR implicit $q0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 + ; CHECK-NEXT: [[ADDv16i8_:%[0-9]+]]:fpr128 = ADDv16i8 [[COPY]], [[COPY1]] + ; CHECK-NEXT: $q0 = COPY [[ADDv16i8_]] + ; CHECK-NEXT: RET_ReallyLR implicit $q0 %0:fpr(<16 x s8>) = COPY $q0 %1:fpr(<16 x s8>) = COPY $q1 %2:fpr(<16 x s8>) = G_ADD %0, %1 @@ -1099,11 +1182,12 @@ ; CHECK-LABEL: name: add_v4i16 ; CHECK: liveins: $d0, $d1 - ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 - ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 - ; CHECK: [[ADDv4i16_:%[0-9]+]]:fpr64 = ADDv4i16 [[COPY]], [[COPY1]] - ; CHECK: $d0 = COPY [[ADDv4i16_]] - ; CHECK: RET_ReallyLR implicit $d0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK-NEXT: [[ADDv4i16_:%[0-9]+]]:fpr64 = ADDv4i16 [[COPY]], [[COPY1]] + ; CHECK-NEXT: $d0 = COPY [[ADDv4i16_]] + ; CHECK-NEXT: RET_ReallyLR implicit $d0 %0:fpr(<4 x s16>) = COPY $d0 %1:fpr(<4 x s16>) = COPY $d1 %2:fpr(<4 x s16>) = G_ADD %0, %1 @@ -1121,11 +1205,12 @@ ; CHECK-LABEL: name: or_v4i16 ; CHECK: liveins: $d0, $d1 - ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 - ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 - ; CHECK: [[ORRv8i8_:%[0-9]+]]:fpr64 = ORRv8i8 [[COPY]], [[COPY1]] - ; CHECK: $d0 = COPY [[ORRv8i8_]] - ; CHECK: RET_ReallyLR implicit $d0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK-NEXT: [[ORRv8i8_:%[0-9]+]]:fpr64 = ORRv8i8 [[COPY]], [[COPY1]] + ; CHECK-NEXT: $d0 = COPY [[ORRv8i8_]] + ; CHECK-NEXT: RET_ReallyLR implicit $d0 %0:fpr(<4 x s16>) = COPY $d0 %1:fpr(<4 x s16>) = COPY $d1 %2:fpr(<4 x s16>) = G_OR %0, %1 @@ -1143,11 +1228,12 @@ ; CHECK-LABEL: name: xor_v4i16 ; CHECK: liveins: $d0, $d1 - ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 - ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 - ; CHECK: [[EORv8i8_:%[0-9]+]]:fpr64 = EORv8i8 [[COPY]], [[COPY1]] - ; CHECK: $d0 = COPY [[EORv8i8_]] - ; CHECK: RET_ReallyLR implicit $d0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK-NEXT: [[EORv8i8_:%[0-9]+]]:fpr64 = EORv8i8 [[COPY]], [[COPY1]] + ; CHECK-NEXT: $d0 = COPY [[EORv8i8_]] + ; CHECK-NEXT: RET_ReallyLR implicit $d0 %0:fpr(<4 x s16>) = COPY $d0 %1:fpr(<4 x s16>) = COPY $d1 %2:fpr(<4 x s16>) = G_XOR %0, %1 @@ -1165,11 +1251,12 @@ ; CHECK-LABEL: name: mul_v4i16 ; CHECK: liveins: $d0, $d1 - ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 - ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 - ; CHECK: [[MULv4i16_:%[0-9]+]]:fpr64 = MULv4i16 [[COPY]], [[COPY1]] - ; CHECK: $d0 = COPY [[MULv4i16_]] - ; CHECK: RET_ReallyLR implicit $d0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK-NEXT: [[MULv4i16_:%[0-9]+]]:fpr64 = MULv4i16 [[COPY]], [[COPY1]] + ; CHECK-NEXT: $d0 = COPY [[MULv4i16_]] + ; CHECK-NEXT: RET_ReallyLR implicit $d0 %0:fpr(<4 x s16>) = COPY $d0 %1:fpr(<4 x s16>) = COPY $d1 %2:fpr(<4 x s16>) = G_MUL %0, %1 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir @@ -59,7 +59,7 @@ ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32common = COPY $w0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $wzr - ; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 4, 0, implicit-def $nzcv + ; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 4, 0, implicit-def dead $nzcv ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, [[SUBSWri]], 0 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64common = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32 ; CHECK-NEXT: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[SUBREG_TO_REG]], 71, 0, implicit-def $nzcv diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-ptr-add.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-ptr-add.mir --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-ptr-add.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-ptr-add.mir @@ -8,10 +8,12 @@ bb.0: liveins: $x0 ; CHECK-LABEL: name: ptr_add - ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 - ; CHECK: [[COPY1:%[0-9]+]]:gpr64common = COPY [[COPY]] - ; CHECK: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri [[COPY1]], 42, 0 - ; CHECK: $x0 = COPY [[ADDXri]] + ; CHECK: liveins: $x0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64common = COPY [[COPY]] + ; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri [[COPY1]], 42, 0 + ; CHECK-NEXT: $x0 = COPY [[ADDXri]] %0:gpr(p0) = COPY $x0 %1:gpr(s64) = G_CONSTANT i64 42 %2:gpr(p0) = G_PTR_ADD %0, %1(s64) @@ -26,10 +28,12 @@ bb.0: liveins: $x0, $x1 ; CHECK-LABEL: name: ptr_add_no_constant - ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 - ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 - ; CHECK: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[COPY1]] - ; CHECK: $x0 = COPY [[ADDXrr]] + ; CHECK: liveins: $x0, $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 + ; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x0 = COPY [[ADDXrr]] %0:gpr(p0) = COPY $x0 %1:gpr(s64) = COPY $x1 %2:gpr(p0) = G_PTR_ADD %0, %1(s64) @@ -44,11 +48,13 @@ bb.0: liveins: $x0, $x1 ; CHECK-LABEL: name: ptr_add_bad_imm - ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 - ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 10000 - ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 - ; CHECK: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[SUBREG_TO_REG]] - ; CHECK: $x0 = COPY [[ADDXrr]] + ; CHECK: liveins: $x0, $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 + ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 10000 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[SUBREG_TO_REG]] + ; CHECK-NEXT: $x0 = COPY [[ADDXrr]] %0:gpr(p0) = COPY $x0 %1:gpr(s64) = G_CONSTANT i64 10000 %2:gpr(p0) = G_PTR_ADD %0, %1(s64) @@ -63,10 +69,12 @@ bb.0: liveins: $q0, $q1 ; CHECK-LABEL: name: ptr_add_vec - ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 - ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 - ; CHECK: [[ADDv2i64_:%[0-9]+]]:fpr128 = ADDv2i64 [[COPY]], [[COPY1]] - ; CHECK: $q0 = COPY [[ADDv2i64_]] + ; CHECK: liveins: $q0, $q1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 + ; CHECK-NEXT: [[ADDv2i64_:%[0-9]+]]:fpr128 = ADDv2i64 [[COPY]], [[COPY1]] + ; CHECK-NEXT: $q0 = COPY [[ADDv2i64_]] %0:fpr(<2 x p0>) = COPY $q0 %1:fpr(<2 x s64>) = COPY $q1 %3:fpr(<2 x p0>) = G_PTR_ADD %0, %1(<2 x s64>) @@ -80,10 +88,12 @@ bb.0: liveins: $x0 ; CHECK-LABEL: name: ptr_add_neg_imm - ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 - ; CHECK: [[COPY1:%[0-9]+]]:gpr64common = COPY [[COPY]] - ; CHECK: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[COPY1]], 10, 0, implicit-def $nzcv - ; CHECK: $x0 = COPY [[SUBSXri]] + ; CHECK: liveins: $x0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64common = COPY [[COPY]] + ; CHECK-NEXT: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[COPY1]], 10, 0, implicit-def dead $nzcv + ; CHECK-NEXT: $x0 = COPY [[SUBSXri]] %0:gpr(p0) = COPY $x0 %1:gpr(s64) = G_CONSTANT i64 -10 %2:gpr(p0) = G_PTR_ADD %0, %1(s64) @@ -97,11 +107,13 @@ bb.0: liveins: $x0 ; CHECK-LABEL: name: ptr_add_arith_extended - ; CHECK: %reg0:gpr32 = COPY $w0 - ; CHECK: %ptr:gpr64 = COPY $x1 - ; CHECK: [[COPY:%[0-9]+]]:gpr64common = COPY %ptr - ; CHECK: %ptr_add:gpr64sp = ADDXrx [[COPY]], %reg0, 18 - ; CHECK: $x0 = COPY %ptr_add + ; CHECK: liveins: $x0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %reg0:gpr32 = COPY $w0 + ; CHECK-NEXT: %ptr:gpr64 = COPY $x1 + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY %ptr + ; CHECK-NEXT: %ptr_add:gpr64sp = ADDXrx [[COPY]], %reg0, 18 + ; CHECK-NEXT: $x0 = COPY %ptr_add %reg0:gpr(s32) = COPY $w0 %ptr:gpr(p0) = COPY $x1 %ext:gpr(s64) = G_ZEXT %reg0(s32) @@ -118,10 +130,12 @@ bb.0: liveins: $x0, $x1 ; CHECK-LABEL: name: ptr_add_negated_reg - ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 - ; CHECK: %src:gpr64 = COPY $x1 - ; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], %src, implicit-def dead $nzcv - ; CHECK: $x0 = COPY [[SUBSXrr]] + ; CHECK: liveins: $x0, $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 + ; CHECK-NEXT: %src:gpr64 = COPY $x1 + ; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], %src, implicit-def dead $nzcv + ; CHECK-NEXT: $x0 = COPY [[SUBSXrr]] %0:gpr(p0) = COPY $x0 %src:gpr(s64) = COPY $x1 %1:gpr(s64) = G_CONSTANT i64 0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/sext-inreg-ldrow-16b.mir b/llvm/test/CodeGen/AArch64/GlobalISel/sext-inreg-ldrow-16b.mir --- a/llvm/test/CodeGen/AArch64/GlobalISel/sext-inreg-ldrow-16b.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/sext-inreg-ldrow-16b.mir @@ -59,19 +59,20 @@ ; CHECK-LABEL: name: check_sext_not_lost ; CHECK: liveins: $x0 - ; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY $x0 - ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY [[COPY]] - ; CHECK: STRXui [[COPY1]], %stack.0.ptr.addr, 0 :: (store (p0) into %ir.ptr.addr) - ; CHECK: [[LDRXui:%[0-9]+]]:gpr64common = LDRXui %stack.0.ptr.addr, 0 :: (dereferenceable load (p0) from %ir.ptr.addr) - ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) @x - ; CHECK: [[LDRWui:%[0-9]+]]:gpr32common = LDRWui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) @x :: (dereferenceable load (s32) from @x) - ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = nsw SUBSWri [[LDRWui]], 8, 12, implicit-def $nzcv - ; CHECK: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF - ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[SUBSWri]], %subreg.sub_32 - ; CHECK: [[SBFMXri:%[0-9]+]]:gpr64 = SBFMXri [[INSERT_SUBREG]], 0, 15 - ; CHECK: [[LDRWroX:%[0-9]+]]:gpr32 = LDRWroX [[LDRXui]], [[SBFMXri]], 0, 1 :: (load (s32) from %ir.arrayidx) - ; CHECK: $w0 = COPY [[LDRWroX]] - ; CHECK: RET_ReallyLR implicit $w0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64all = COPY $x0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY [[COPY]] + ; CHECK-NEXT: STRXui [[COPY1]], %stack.0.ptr.addr, 0 :: (store (p0) into %ir.ptr.addr) + ; CHECK-NEXT: [[LDRXui:%[0-9]+]]:gpr64common = LDRXui %stack.0.ptr.addr, 0 :: (dereferenceable load (p0) from %ir.ptr.addr) + ; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) @x + ; CHECK-NEXT: [[LDRWui:%[0-9]+]]:gpr32common = LDRWui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) @x :: (dereferenceable load (s32) from @x) + ; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = nsw SUBSWri [[LDRWui]], 8, 12, implicit-def dead $nzcv + ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF + ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[SUBSWri]], %subreg.sub_32 + ; CHECK-NEXT: [[SBFMXri:%[0-9]+]]:gpr64 = SBFMXri [[INSERT_SUBREG]], 0, 15 + ; CHECK-NEXT: [[LDRWroX:%[0-9]+]]:gpr32 = LDRWroX [[LDRXui]], [[SBFMXri]], 0, 1 :: (load (s32) from %ir.arrayidx) + ; CHECK-NEXT: $w0 = COPY [[LDRWroX]] + ; CHECK-NEXT: RET_ReallyLR implicit $w0 %0:gpr(p0) = COPY $x0 %1:gpr(p0) = G_FRAME_INDEX %stack.0.ptr.addr G_STORE %0(p0), %1(p0) :: (store (p0) into %ir.ptr.addr) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-abs.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-abs.mir --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-abs.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-abs.mir @@ -18,13 +18,14 @@ ; GFX6: liveins: $sgpr0 ; GFX6-NEXT: {{ $}} ; GFX6-NEXT: %src0:sreg_32 = COPY $sgpr0 - ; GFX6-NEXT: %smax:sreg_32 = S_ABS_I32 %src0, implicit-def $scc + ; GFX6-NEXT: %smax:sreg_32 = S_ABS_I32 %src0, implicit-def dead $scc ; GFX6-NEXT: S_ENDPGM 0, implicit %smax + ; ; GFX9-LABEL: name: smax_neg_abs_pattern_s32_ss ; GFX9: liveins: $sgpr0 ; GFX9-NEXT: {{ $}} ; GFX9-NEXT: %src0:sreg_32 = COPY $sgpr0 - ; GFX9-NEXT: %smax:sreg_32 = S_ABS_I32 %src0, implicit-def $scc + ; GFX9-NEXT: %smax:sreg_32 = S_ABS_I32 %src0, implicit-def dead $scc ; GFX9-NEXT: S_ENDPGM 0, implicit %smax %src0:sgpr(s32) = COPY $sgpr0 %zero:sgpr(s32) = G_CONSTANT i32 0 @@ -47,13 +48,14 @@ ; GFX6: liveins: $sgpr0 ; GFX6-NEXT: {{ $}} ; GFX6-NEXT: %src0:sreg_32 = COPY $sgpr0 - ; GFX6-NEXT: %smax:sreg_32 = S_ABS_I32 %src0, implicit-def $scc + ; GFX6-NEXT: %smax:sreg_32 = S_ABS_I32 %src0, implicit-def dead $scc ; GFX6-NEXT: S_ENDPGM 0, implicit %smax + ; ; GFX9-LABEL: name: smax_neg_abs_pattern_s32_ss_commute ; GFX9: liveins: $sgpr0 ; GFX9-NEXT: {{ $}} ; GFX9-NEXT: %src0:sreg_32 = COPY $sgpr0 - ; GFX9-NEXT: %smax:sreg_32 = S_ABS_I32 %src0, implicit-def $scc + ; GFX9-NEXT: %smax:sreg_32 = S_ABS_I32 %src0, implicit-def dead $scc ; GFX9-NEXT: S_ENDPGM 0, implicit %smax %src0:sgpr(s32) = COPY $sgpr0 %zero:sgpr(s32) = G_CONSTANT i32 0 @@ -80,6 +82,7 @@ ; GFX6-NEXT: %ineg:vgpr_32, dead %4:sreg_64 = V_SUB_CO_U32_e64 %zero, %src0, 0, implicit $exec ; GFX6-NEXT: %smax:vgpr_32 = V_MAX_I32_e64 %src0, %ineg, implicit $exec ; GFX6-NEXT: S_ENDPGM 0, implicit %smax + ; ; GFX9-LABEL: name: smax_neg_abs_pattern_s32_vv ; GFX9: liveins: $vgpr0 ; GFX9-NEXT: {{ $}} diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir @@ -71,14 +71,14 @@ ; GFX6: liveins: $sgpr0 ; GFX6-NEXT: {{ $}} ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 - ; GFX6-NEXT: [[S_SUB_I32_:%[0-9]+]]:sreg_32 = S_SUB_I32 [[COPY]], 64, implicit-def $scc + ; GFX6-NEXT: [[S_SUB_I32_:%[0-9]+]]:sreg_32 = S_SUB_I32 [[COPY]], 64, implicit-def dead $scc ; GFX6-NEXT: S_ENDPGM 0, implicit [[S_SUB_I32_]] ; ; GFX9-LABEL: name: add_neg_inline_const_64_to_sub_s32_s ; GFX9: liveins: $sgpr0 ; GFX9-NEXT: {{ $}} ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 - ; GFX9-NEXT: [[S_SUB_I32_:%[0-9]+]]:sreg_32 = S_SUB_I32 [[COPY]], 64, implicit-def $scc + ; GFX9-NEXT: [[S_SUB_I32_:%[0-9]+]]:sreg_32 = S_SUB_I32 [[COPY]], 64, implicit-def dead $scc ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_SUB_I32_]] %0:sgpr(s32) = COPY $sgpr0 %1:sgpr(s32) = G_CONSTANT i32 -64 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir @@ -137,7 +137,7 @@ ; GCN-NEXT: {{ $}} ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535 - ; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_MOV_B32_]], [[COPY]], implicit-def $scc + ; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_MOV_B32_]], [[COPY]], implicit-def dead $scc ; GCN-NEXT: $sgpr0 = COPY [[S_AND_B32_]] %0:sgpr(s32) = COPY $sgpr0 %1:sgpr(s1) = G_TRUNC %0 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector-trunc.v2s16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector-trunc.v2s16.mir --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector-trunc.v2s16.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector-trunc.v2s16.mir @@ -575,9 +575,9 @@ ; GFX9PLUS: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 123 ; GFX9PLUS-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 65535 - ; GFX9PLUS-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_MOV_B32_1]], [[DEF]], implicit-def $scc + ; GFX9PLUS-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_MOV_B32_1]], [[DEF]], implicit-def dead $scc ; GFX9PLUS-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 65535 - ; GFX9PLUS-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_MOV_B32_2]], [[S_MOV_B32_]], implicit-def $scc + ; GFX9PLUS-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_MOV_B32_2]], [[S_MOV_B32_]], implicit-def dead $scc ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_AND_B32_]], [[S_AND_B32_1]] ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] %0:sgpr(s16) = G_IMPLICIT_DEF diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir @@ -19,7 +19,7 @@ ; SI-NEXT: {{ $}} ; SI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647 - ; SI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc + ; SI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc ; SI-NEXT: $sgpr0 = COPY [[S_AND_B32_]] ; ; VI-LABEL: name: fabs_s32_ss @@ -27,7 +27,7 @@ ; VI-NEXT: {{ $}} ; VI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647 - ; VI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc + ; VI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc ; VI-NEXT: $sgpr0 = COPY [[S_AND_B32_]] ; ; GFX9-LABEL: name: fabs_s32_ss @@ -35,7 +35,7 @@ ; GFX9-NEXT: {{ $}} ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647 - ; GFX9-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc + ; GFX9-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc ; GFX9-NEXT: $sgpr0 = COPY [[S_AND_B32_]] ; ; GFX10-LABEL: name: fabs_s32_ss @@ -43,7 +43,7 @@ ; GFX10-NEXT: {{ $}} ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647 - ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc + ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc ; GFX10-NEXT: $sgpr0 = COPY [[S_AND_B32_]] %0:sgpr(s32) = COPY $sgpr0 %1:sgpr(s32) = G_FABS %0 @@ -150,7 +150,7 @@ ; SI-NEXT: {{ $}} ; SI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147450879 - ; SI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc + ; SI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc ; SI-NEXT: $sgpr0 = COPY [[S_AND_B32_]] ; ; VI-LABEL: name: fabs_v2s16_ss @@ -158,7 +158,7 @@ ; VI-NEXT: {{ $}} ; VI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147450879 - ; VI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc + ; VI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc ; VI-NEXT: $sgpr0 = COPY [[S_AND_B32_]] ; ; GFX9-LABEL: name: fabs_v2s16_ss @@ -166,7 +166,7 @@ ; GFX9-NEXT: {{ $}} ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147450879 - ; GFX9-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc + ; GFX9-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc ; GFX9-NEXT: $sgpr0 = COPY [[S_AND_B32_]] ; ; GFX10-LABEL: name: fabs_v2s16_ss @@ -174,7 +174,7 @@ ; GFX10-NEXT: {{ $}} ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147450879 - ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc + ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc ; GFX10-NEXT: $sgpr0 = COPY [[S_AND_B32_]] %0:sgpr(<2 x s16>) = COPY $sgpr0 %1:sgpr(<2 x s16>) = G_FABS %0 @@ -195,7 +195,7 @@ ; SI-NEXT: {{ $}} ; SI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32767 - ; SI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc + ; SI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc ; SI-NEXT: $sgpr0 = COPY [[S_AND_B32_]] ; ; VI-LABEL: name: fabs_s16_ss @@ -203,7 +203,7 @@ ; VI-NEXT: {{ $}} ; VI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32767 - ; VI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc + ; VI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc ; VI-NEXT: $sgpr0 = COPY [[S_AND_B32_]] ; ; GFX9-LABEL: name: fabs_s16_ss @@ -211,7 +211,7 @@ ; GFX9-NEXT: {{ $}} ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32767 - ; GFX9-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc + ; GFX9-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc ; GFX9-NEXT: $sgpr0 = COPY [[S_AND_B32_]] ; ; GFX10-LABEL: name: fabs_s16_ss @@ -219,7 +219,7 @@ ; GFX10-NEXT: {{ $}} ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32767 - ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc + ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc ; GFX10-NEXT: $sgpr0 = COPY [[S_AND_B32_]] %0:sgpr(s32) = COPY $sgpr0 %1:sgpr(s16) = G_TRUNC %0 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir @@ -19,7 +19,7 @@ ; SI-NEXT: {{ $}} ; SI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648 - ; SI-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc + ; SI-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc ; SI-NEXT: $sgpr0 = COPY [[S_XOR_B32_]] ; ; VI-LABEL: name: fneg_s32_ss @@ -27,7 +27,7 @@ ; VI-NEXT: {{ $}} ; VI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648 - ; VI-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc + ; VI-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc ; VI-NEXT: $sgpr0 = COPY [[S_XOR_B32_]] ; ; GFX9-LABEL: name: fneg_s32_ss @@ -35,7 +35,7 @@ ; GFX9-NEXT: {{ $}} ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648 - ; GFX9-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc + ; GFX9-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc ; GFX9-NEXT: $sgpr0 = COPY [[S_XOR_B32_]] ; ; GFX10-LABEL: name: fneg_s32_ss @@ -43,7 +43,7 @@ ; GFX10-NEXT: {{ $}} ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648 - ; GFX10-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc + ; GFX10-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc ; GFX10-NEXT: $sgpr0 = COPY [[S_XOR_B32_]] %0:sgpr(s32) = COPY $sgpr0 %1:sgpr(s32) = G_FNEG %0 @@ -150,7 +150,7 @@ ; SI-NEXT: {{ $}} ; SI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768 - ; SI-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc + ; SI-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc ; SI-NEXT: $sgpr0 = COPY [[S_XOR_B32_]] ; ; VI-LABEL: name: fneg_s16_ss @@ -158,7 +158,7 @@ ; VI-NEXT: {{ $}} ; VI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768 - ; VI-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc + ; VI-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc ; VI-NEXT: $sgpr0 = COPY [[S_XOR_B32_]] ; ; GFX9-LABEL: name: fneg_s16_ss @@ -166,7 +166,7 @@ ; GFX9-NEXT: {{ $}} ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768 - ; GFX9-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc + ; GFX9-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc ; GFX9-NEXT: $sgpr0 = COPY [[S_XOR_B32_]] ; ; GFX10-LABEL: name: fneg_s16_ss @@ -174,7 +174,7 @@ ; GFX10-NEXT: {{ $}} ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768 - ; GFX10-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc + ; GFX10-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc ; GFX10-NEXT: $sgpr0 = COPY [[S_XOR_B32_]] %0:sgpr(s32) = COPY $sgpr0 %1:sgpr(s16) = G_TRUNC %0 @@ -296,7 +296,7 @@ ; SI-NEXT: {{ $}} ; SI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147516416 - ; SI-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc + ; SI-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc ; SI-NEXT: $sgpr0 = COPY [[S_XOR_B32_]] ; ; VI-LABEL: name: fneg_v2s16_ss @@ -304,7 +304,7 @@ ; VI-NEXT: {{ $}} ; VI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147516416 - ; VI-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc + ; VI-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc ; VI-NEXT: $sgpr0 = COPY [[S_XOR_B32_]] ; ; GFX9-LABEL: name: fneg_v2s16_ss @@ -312,7 +312,7 @@ ; GFX9-NEXT: {{ $}} ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147516416 - ; GFX9-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc + ; GFX9-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc ; GFX9-NEXT: $sgpr0 = COPY [[S_XOR_B32_]] ; ; GFX10-LABEL: name: fneg_v2s16_ss @@ -320,7 +320,7 @@ ; GFX10-NEXT: {{ $}} ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147516416 - ; GFX10-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc + ; GFX10-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc ; GFX10-NEXT: $sgpr0 = COPY [[S_XOR_B32_]] %0:sgpr(<2 x s16>) = COPY $sgpr0 %1:sgpr(<2 x s16>) = G_FNEG %0 @@ -583,7 +583,7 @@ ; SI-NEXT: {{ $}} ; SI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648 - ; SI-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc + ; SI-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc ; SI-NEXT: S_ENDPGM 0, implicit [[S_OR_B32_]] ; ; VI-LABEL: name: fneg_fabs_s32_ss @@ -591,7 +591,7 @@ ; VI-NEXT: {{ $}} ; VI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648 - ; VI-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc + ; VI-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc ; VI-NEXT: S_ENDPGM 0, implicit [[S_OR_B32_]] ; ; GFX9-LABEL: name: fneg_fabs_s32_ss @@ -599,7 +599,7 @@ ; GFX9-NEXT: {{ $}} ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648 - ; GFX9-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc + ; GFX9-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_OR_B32_]] ; ; GFX10-LABEL: name: fneg_fabs_s32_ss @@ -607,7 +607,7 @@ ; GFX10-NEXT: {{ $}} ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648 - ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc + ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc ; GFX10-NEXT: S_ENDPGM 0, implicit [[S_OR_B32_]] %0:sgpr(s32) = COPY $sgpr0 %1:sgpr(s32) = G_FABS %0 @@ -725,7 +725,7 @@ ; SI-NEXT: {{ $}} ; SI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768 - ; SI-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc + ; SI-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc ; SI-NEXT: $sgpr0 = COPY [[S_OR_B32_]] ; ; VI-LABEL: name: fneg_fabs_s16_ss @@ -733,7 +733,7 @@ ; VI-NEXT: {{ $}} ; VI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768 - ; VI-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc + ; VI-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc ; VI-NEXT: $sgpr0 = COPY [[S_OR_B32_]] ; ; GFX9-LABEL: name: fneg_fabs_s16_ss @@ -741,7 +741,7 @@ ; GFX9-NEXT: {{ $}} ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768 - ; GFX9-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc + ; GFX9-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc ; GFX9-NEXT: $sgpr0 = COPY [[S_OR_B32_]] ; ; GFX10-LABEL: name: fneg_fabs_s16_ss @@ -749,7 +749,7 @@ ; GFX10-NEXT: {{ $}} ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768 - ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc + ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc ; GFX10-NEXT: $sgpr0 = COPY [[S_OR_B32_]] %0:sgpr(s32) = COPY $sgpr0 %1:sgpr(s16) = G_TRUNC %0 @@ -882,7 +882,7 @@ ; SI-NEXT: {{ $}} ; SI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147516416 - ; SI-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc + ; SI-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc ; SI-NEXT: $sgpr0 = COPY [[S_OR_B32_]] ; ; VI-LABEL: name: fneg_fabs_v2s16_ss @@ -890,7 +890,7 @@ ; VI-NEXT: {{ $}} ; VI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147516416 - ; VI-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc + ; VI-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc ; VI-NEXT: $sgpr0 = COPY [[S_OR_B32_]] ; ; GFX9-LABEL: name: fneg_fabs_v2s16_ss @@ -898,7 +898,7 @@ ; GFX9-NEXT: {{ $}} ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147516416 - ; GFX9-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc + ; GFX9-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc ; GFX9-NEXT: $sgpr0 = COPY [[S_OR_B32_]] ; ; GFX10-LABEL: name: fneg_fabs_v2s16_ss @@ -906,7 +906,7 @@ ; GFX10-NEXT: {{ $}} ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147516416 - ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc + ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc ; GFX10-NEXT: $sgpr0 = COPY [[S_OR_B32_]] %0:sgpr(<2 x s16>) = COPY $sgpr0 %1:sgpr(<2 x s16>) = G_FABS %0 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-select.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-select.mir --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-select.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-select.mir @@ -548,7 +548,7 @@ ; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 ; GCN-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648 - ; GCN-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc + ; GCN-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY2]], [[S_MOV_B32_]], implicit-def dead $scc ; GCN-NEXT: S_CMP_EQ_U32 [[COPY]], [[COPY1]], implicit-def $scc ; GCN-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $scc ; GCN-NEXT: $scc = COPY [[COPY4]] @@ -582,7 +582,7 @@ ; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 ; GCN-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648 - ; GCN-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY3]], [[S_MOV_B32_]], implicit-def $scc + ; GCN-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY3]], [[S_MOV_B32_]], implicit-def dead $scc ; GCN-NEXT: S_CMP_EQ_U32 [[COPY]], [[COPY1]], implicit-def $scc ; GCN-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $scc ; GCN-NEXT: $scc = COPY [[COPY4]] diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir @@ -16,7 +16,7 @@ ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GCN-NEXT: [[S_BFE_I32_:%[0-9]+]]:sreg_32 = S_BFE_I32 [[COPY]], 65536, implicit-def $scc ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535 - ; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_MOV_B32_]], [[S_BFE_I32_]], implicit-def $scc + ; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_MOV_B32_]], [[S_BFE_I32_]], implicit-def dead $scc ; GCN-NEXT: $sgpr0 = COPY [[S_AND_B32_]] %0:sgpr(s32) = COPY $sgpr0 %1:sgpr(s1) = G_TRUNC %0 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir @@ -82,7 +82,7 @@ ; GCN-NEXT: {{ $}} ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535 - ; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_MOV_B32_]], [[COPY]], implicit-def $scc + ; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_MOV_B32_]], [[COPY]], implicit-def dead $scc ; GCN-NEXT: $sgpr0 = COPY [[S_AND_B32_]] %0:sgpr(s32) = COPY $sgpr0 %1:sgpr(s16) = G_TRUNC %0 diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-ashr-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/select-ashr-scalar.mir --- a/llvm/test/CodeGen/X86/GlobalISel/select-ashr-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-ashr-scalar.mir @@ -69,13 +69,14 @@ ; ALL-LABEL: name: test_ashr_i64 ; ALL: liveins: $rdi, $rsi - ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi - ; ALL: [[COPY1:%[0-9]+]]:gr64_with_sub_8bit = COPY $rsi - ; ALL: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit - ; ALL: $cl = COPY [[COPY2]] - ; ALL: [[SAR64rCL:%[0-9]+]]:gr64 = SAR64rCL [[COPY]], implicit-def $eflags, implicit $cl - ; ALL: $rax = COPY [[SAR64rCL]] - ; ALL: RET 0, implicit $rax + ; ALL-NEXT: {{ $}} + ; ALL-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi + ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr64_with_sub_8bit = COPY $rsi + ; ALL-NEXT: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit + ; ALL-NEXT: $cl = COPY [[COPY2]] + ; ALL-NEXT: [[SAR64rCL:%[0-9]+]]:gr64 = SAR64rCL [[COPY]], implicit-def dead $eflags, implicit $cl + ; ALL-NEXT: $rax = COPY [[SAR64rCL]] + ; ALL-NEXT: RET 0, implicit $rax %0(s64) = COPY $rdi %1(s64) = COPY $rsi %2(s8) = G_TRUNC %1 @@ -104,10 +105,11 @@ ; ALL-LABEL: name: test_ashr_i64_imm ; ALL: liveins: $rdi - ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi - ; ALL: [[SAR64ri:%[0-9]+]]:gr64 = SAR64ri [[COPY]], 5, implicit-def $eflags - ; ALL: $rax = COPY [[SAR64ri]] - ; ALL: RET 0, implicit $rax + ; ALL-NEXT: {{ $}} + ; ALL-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi + ; ALL-NEXT: [[SAR64ri:%[0-9]+]]:gr64 = SAR64ri [[COPY]], 5, implicit-def dead $eflags + ; ALL-NEXT: $rax = COPY [[SAR64ri]] + ; ALL-NEXT: RET 0, implicit $rax %0(s64) = COPY $rdi %1(s8) = G_CONSTANT i8 5 %2(s64) = G_ASHR %0, %1 @@ -136,13 +138,14 @@ ; ALL-LABEL: name: test_ashr_i32 ; ALL: liveins: $edi, $esi - ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY $esi - ; ALL: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit - ; ALL: $cl = COPY [[COPY2]] - ; ALL: [[SAR32rCL:%[0-9]+]]:gr32 = SAR32rCL [[COPY]], implicit-def $eflags, implicit $cl - ; ALL: $eax = COPY [[SAR32rCL]] - ; ALL: RET 0, implicit $eax + ; ALL-NEXT: {{ $}} + ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi + ; ALL-NEXT: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit + ; ALL-NEXT: $cl = COPY [[COPY2]] + ; ALL-NEXT: [[SAR32rCL:%[0-9]+]]:gr32 = SAR32rCL [[COPY]], implicit-def dead $eflags, implicit $cl + ; ALL-NEXT: $eax = COPY [[SAR32rCL]] + ; ALL-NEXT: RET 0, implicit $eax %0(s32) = COPY $edi %1(s32) = COPY $esi %2(s8) = G_TRUNC %1 @@ -171,10 +174,11 @@ ; ALL-LABEL: name: test_ashr_i32_imm ; ALL: liveins: $edi - ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; ALL: [[SAR32ri:%[0-9]+]]:gr32 = SAR32ri [[COPY]], 5, implicit-def $eflags - ; ALL: $eax = COPY [[SAR32ri]] - ; ALL: RET 0, implicit $eax + ; ALL-NEXT: {{ $}} + ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; ALL-NEXT: [[SAR32ri:%[0-9]+]]:gr32 = SAR32ri [[COPY]], 5, implicit-def dead $eflags + ; ALL-NEXT: $eax = COPY [[SAR32ri]] + ; ALL-NEXT: RET 0, implicit $eax %0(s32) = COPY $edi %1(s8) = G_CONSTANT i8 5 %2(s32) = G_ASHR %0, %1 @@ -204,14 +208,15 @@ ; ALL-LABEL: name: test_ashr_i16 ; ALL: liveins: $edi, $esi - ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY $esi - ; ALL: [[COPY2:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit - ; ALL: [[COPY3:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit - ; ALL: $cl = COPY [[COPY3]] - ; ALL: [[SAR16rCL:%[0-9]+]]:gr16 = SAR16rCL [[COPY2]], implicit-def $eflags, implicit $cl - ; ALL: $ax = COPY [[SAR16rCL]] - ; ALL: RET 0, implicit $ax + ; ALL-NEXT: {{ $}} + ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi + ; ALL-NEXT: [[COPY2:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit + ; ALL-NEXT: [[COPY3:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit + ; ALL-NEXT: $cl = COPY [[COPY3]] + ; ALL-NEXT: [[SAR16rCL:%[0-9]+]]:gr16 = SAR16rCL [[COPY2]], implicit-def dead $eflags, implicit $cl + ; ALL-NEXT: $ax = COPY [[SAR16rCL]] + ; ALL-NEXT: RET 0, implicit $ax %0(s32) = COPY $edi %1(s32) = COPY $esi %2(s16) = G_TRUNC %0(s32) @@ -242,11 +247,12 @@ ; ALL-LABEL: name: test_ashr_i16_imm ; ALL: liveins: $edi - ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; ALL: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit - ; ALL: [[SAR16ri:%[0-9]+]]:gr16 = SAR16ri [[COPY1]], 5, implicit-def $eflags - ; ALL: $ax = COPY [[SAR16ri]] - ; ALL: RET 0, implicit $ax + ; ALL-NEXT: {{ $}} + ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit + ; ALL-NEXT: [[SAR16ri:%[0-9]+]]:gr16 = SAR16ri [[COPY1]], 5, implicit-def dead $eflags + ; ALL-NEXT: $ax = COPY [[SAR16ri]] + ; ALL-NEXT: RET 0, implicit $ax %0(s32) = COPY $edi %2(s8) = G_CONSTANT i8 5 %1(s16) = G_TRUNC %0(s32) @@ -277,14 +283,15 @@ ; ALL-LABEL: name: test_ashr_i8 ; ALL: liveins: $edi, $esi - ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY $esi - ; ALL: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit - ; ALL: [[COPY3:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit - ; ALL: $cl = COPY [[COPY3]] - ; ALL: [[SAR8rCL:%[0-9]+]]:gr8 = SAR8rCL [[COPY2]], implicit-def $eflags, implicit $cl - ; ALL: $al = COPY [[SAR8rCL]] - ; ALL: RET 0, implicit $al + ; ALL-NEXT: {{ $}} + ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi + ; ALL-NEXT: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit + ; ALL-NEXT: [[COPY3:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit + ; ALL-NEXT: $cl = COPY [[COPY3]] + ; ALL-NEXT: [[SAR8rCL:%[0-9]+]]:gr8 = SAR8rCL [[COPY2]], implicit-def dead $eflags, implicit $cl + ; ALL-NEXT: $al = COPY [[SAR8rCL]] + ; ALL-NEXT: RET 0, implicit $al %0(s32) = COPY $edi %1(s32) = COPY $esi %2(s8) = G_TRUNC %0(s32) @@ -315,11 +322,12 @@ ; ALL-LABEL: name: test_ashr_i8_imm ; ALL: liveins: $edi - ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; ALL: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit - ; ALL: [[SAR8ri:%[0-9]+]]:gr8 = SAR8ri [[COPY1]], 5, implicit-def $eflags - ; ALL: $al = COPY [[SAR8ri]] - ; ALL: RET 0, implicit $al + ; ALL-NEXT: {{ $}} + ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit + ; ALL-NEXT: [[SAR8ri:%[0-9]+]]:gr8 = SAR8ri [[COPY1]], 5, implicit-def dead $eflags + ; ALL-NEXT: $al = COPY [[SAR8ri]] + ; ALL-NEXT: RET 0, implicit $al %0(s32) = COPY $edi %2(s8) = G_CONSTANT i8 5 %1(s8) = G_TRUNC %0(s32) diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-blsi.mir b/llvm/test/CodeGen/X86/GlobalISel/select-blsi.mir --- a/llvm/test/CodeGen/X86/GlobalISel/select-blsi.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-blsi.mir @@ -27,7 +27,7 @@ ; CHECK: liveins: $edi ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; CHECK-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags + ; CHECK-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags ; CHECK-NEXT: [[SUB32rr:%[0-9]+]]:gr32 = SUB32rr [[MOV32r0_]], [[COPY]], implicit-def dead $eflags ; CHECK-NEXT: [[AND32rr:%[0-9]+]]:gr32 = AND32rr [[SUB32rr]], [[COPY]], implicit-def dead $eflags ; CHECK-NEXT: $edi = COPY [[AND32rr]] @@ -57,8 +57,8 @@ ; CHECK: liveins: $edi ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; CHECK-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags - ; CHECK-NEXT: [[SUB32ri:%[0-9]+]]:gr32 = SUB32ri [[MOV32r0_]], 0, implicit-def $eflags + ; CHECK-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags + ; CHECK-NEXT: [[SUB32ri:%[0-9]+]]:gr32 = SUB32ri [[MOV32r0_]], 0, implicit-def dead $eflags ; CHECK-NEXT: [[AND32rr:%[0-9]+]]:gr32 = AND32rr [[SUB32ri]], [[COPY]], implicit-def dead $eflags ; CHECK-NEXT: $edi = COPY [[AND32rr]] %0(s32) = COPY $edi diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-blsr.mir b/llvm/test/CodeGen/X86/GlobalISel/select-blsr.mir --- a/llvm/test/CodeGen/X86/GlobalISel/select-blsr.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-blsr.mir @@ -24,7 +24,7 @@ ; CHECK: liveins: $edi ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; CHECK-NEXT: [[DEC32r:%[0-9]+]]:gr32 = DEC32r [[COPY]], implicit-def $eflags + ; CHECK-NEXT: [[DEC32r:%[0-9]+]]:gr32 = DEC32r [[COPY]], implicit-def dead $eflags ; CHECK-NEXT: [[AND32rr:%[0-9]+]]:gr32 = AND32rr [[DEC32r]], [[COPY]], implicit-def dead $eflags ; CHECK-NEXT: $edi = COPY [[AND32rr]] %0(s32) = COPY $edi @@ -54,7 +54,7 @@ ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi ; CHECK-NEXT: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri -1 - ; CHECK-NEXT: [[DEC32r:%[0-9]+]]:gr32 = DEC32r [[MOV32ri]], implicit-def $eflags + ; CHECK-NEXT: [[DEC32r:%[0-9]+]]:gr32 = DEC32r [[MOV32ri]], implicit-def dead $eflags ; CHECK-NEXT: [[AND32rr:%[0-9]+]]:gr32 = AND32rr [[DEC32r]], [[COPY]], implicit-def dead $eflags ; CHECK-NEXT: $edi = COPY [[AND32rr]] %0(s32) = COPY $edi diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-brcond.mir b/llvm/test/CodeGen/X86/GlobalISel/select-brcond.mir --- a/llvm/test/CodeGen/X86/GlobalISel/select-brcond.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-brcond.mir @@ -29,7 +29,7 @@ - { id: 3, class: gpr, preferred-register: '' } # X64: %0:gr32 = COPY $edi # X32: %0:gr32_abcd = COPY $edi -# CHECK-NEXT: %2:gr32 = MOV32r0 implicit-def $eflags +# CHECK-NEXT: %2:gr32 = MOV32r0 implicit-def dead $eflags # CHECK-NEXT: %3:gr32 = MOV32ri 1 # CHECK-NEXT: %1:gr8 = COPY %0.sub_8bit # CHECK-NEXT: TEST8ri %1, 1, implicit-def $eflags diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-cmp.mir b/llvm/test/CodeGen/X86/GlobalISel/select-cmp.mir --- a/llvm/test/CodeGen/X86/GlobalISel/select-cmp.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-cmp.mir @@ -99,14 +99,16 @@ liveins: $edi, $esi ; CHECK-LABEL: name: test_icmp_eq_i8 - ; CHECK: [[COPY:%[0-9]+]]:gr8 = COPY $dil - ; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY $sil - ; CHECK: CMP8rr [[COPY]], [[COPY1]], implicit-def $eflags - ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags - ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] - ; CHECK: [[AND32ri_:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def $eflags - ; CHECK: $eax = COPY [[AND32ri_]] - ; CHECK: RET 0, implicit $eax + ; CHECK: liveins: $edi, $esi + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr8 = COPY $dil + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY $sil + ; CHECK-NEXT: CMP8rr [[COPY]], [[COPY1]], implicit-def $eflags + ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags + ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] + ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags + ; CHECK-NEXT: $eax = COPY [[AND32ri]] + ; CHECK-NEXT: RET 0, implicit $eax %0(s8) = COPY $dil %1(s8) = COPY $sil %4(s8) = G_ICMP intpred(eq), %0(s8), %1 @@ -135,14 +137,16 @@ liveins: $edi, $esi ; CHECK-LABEL: name: test_icmp_eq_i16 - ; CHECK: [[COPY:%[0-9]+]]:gr16 = COPY $di - ; CHECK: [[COPY1:%[0-9]+]]:gr16 = COPY $si - ; CHECK: CMP16rr [[COPY]], [[COPY1]], implicit-def $eflags - ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags - ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] - ; CHECK: [[AND32ri_:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def $eflags - ; CHECK: $eax = COPY [[AND32ri_]] - ; CHECK: RET 0, implicit $eax + ; CHECK: liveins: $edi, $esi + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr16 = COPY $di + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY $si + ; CHECK-NEXT: CMP16rr [[COPY]], [[COPY1]], implicit-def $eflags + ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags + ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] + ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags + ; CHECK-NEXT: $eax = COPY [[AND32ri]] + ; CHECK-NEXT: RET 0, implicit $eax %0(s16) = COPY $di %1(s16) = COPY $si %4(s8) = G_ICMP intpred(eq), %0(s16), %1 @@ -171,14 +175,16 @@ liveins: $rdi, $rsi ; CHECK-LABEL: name: test_icmp_eq_i64 - ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi - ; CHECK: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi - ; CHECK: CMP64rr [[COPY]], [[COPY1]], implicit-def $eflags - ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags - ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] - ; CHECK: [[AND32ri_:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def $eflags - ; CHECK: $eax = COPY [[AND32ri_]] - ; CHECK: RET 0, implicit $eax + ; CHECK: liveins: $rdi, $rsi + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi + ; CHECK-NEXT: CMP64rr [[COPY]], [[COPY1]], implicit-def $eflags + ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags + ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] + ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags + ; CHECK-NEXT: $eax = COPY [[AND32ri]] + ; CHECK-NEXT: RET 0, implicit $eax %0(s64) = COPY $rdi %1(s64) = COPY $rsi %4(s8) = G_ICMP intpred(eq), %0(s64), %1 @@ -207,14 +213,16 @@ liveins: $edi, $esi ; CHECK-LABEL: name: test_icmp_eq_i32 - ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi - ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags - ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags - ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] - ; CHECK: [[AND32ri_:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def $eflags - ; CHECK: $eax = COPY [[AND32ri_]] - ; CHECK: RET 0, implicit $eax + ; CHECK: liveins: $edi, $esi + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi + ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags + ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags + ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] + ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags + ; CHECK-NEXT: $eax = COPY [[AND32ri]] + ; CHECK-NEXT: RET 0, implicit $eax %0(s32) = COPY $edi %1(s32) = COPY $esi %4(s8) = G_ICMP intpred(eq), %0(s32), %1 @@ -243,14 +251,16 @@ liveins: $edi, $esi ; CHECK-LABEL: name: test_icmp_ne_i32 - ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi - ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags - ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 5, implicit $eflags - ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] - ; CHECK: [[AND32ri_:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def $eflags - ; CHECK: $eax = COPY [[AND32ri_]] - ; CHECK: RET 0, implicit $eax + ; CHECK: liveins: $edi, $esi + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi + ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags + ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 5, implicit $eflags + ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] + ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags + ; CHECK-NEXT: $eax = COPY [[AND32ri]] + ; CHECK-NEXT: RET 0, implicit $eax %0(s32) = COPY $edi %1(s32) = COPY $esi %4(s8) = G_ICMP intpred(ne), %0(s32), %1 @@ -279,14 +289,16 @@ liveins: $edi, $esi ; CHECK-LABEL: name: test_icmp_ugt_i32 - ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi - ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags - ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags - ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] - ; CHECK: [[AND32ri_:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def $eflags - ; CHECK: $eax = COPY [[AND32ri_]] - ; CHECK: RET 0, implicit $eax + ; CHECK: liveins: $edi, $esi + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi + ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags + ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags + ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] + ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags + ; CHECK-NEXT: $eax = COPY [[AND32ri]] + ; CHECK-NEXT: RET 0, implicit $eax %0(s32) = COPY $edi %1(s32) = COPY $esi %4(s8) = G_ICMP intpred(ugt), %0(s32), %1 @@ -315,14 +327,16 @@ liveins: $edi, $esi ; CHECK-LABEL: name: test_icmp_uge_i32 - ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi - ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags - ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 3, implicit $eflags - ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] - ; CHECK: [[AND32ri_:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def $eflags - ; CHECK: $eax = COPY [[AND32ri_]] - ; CHECK: RET 0, implicit $eax + ; CHECK: liveins: $edi, $esi + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi + ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags + ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 3, implicit $eflags + ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] + ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags + ; CHECK-NEXT: $eax = COPY [[AND32ri]] + ; CHECK-NEXT: RET 0, implicit $eax %0(s32) = COPY $edi %1(s32) = COPY $esi %4(s8) = G_ICMP intpred(uge), %0(s32), %1 @@ -351,14 +365,16 @@ liveins: $edi, $esi ; CHECK-LABEL: name: test_icmp_ult_i32 - ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi - ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags - ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags - ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] - ; CHECK: [[AND32ri_:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def $eflags - ; CHECK: $eax = COPY [[AND32ri_]] - ; CHECK: RET 0, implicit $eax + ; CHECK: liveins: $edi, $esi + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi + ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags + ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags + ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] + ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags + ; CHECK-NEXT: $eax = COPY [[AND32ri]] + ; CHECK-NEXT: RET 0, implicit $eax %0(s32) = COPY $edi %1(s32) = COPY $esi %4(s8) = G_ICMP intpred(ult), %0(s32), %1 @@ -387,14 +403,16 @@ liveins: $edi, $esi ; CHECK-LABEL: name: test_icmp_ule_i32 - ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi - ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags - ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 6, implicit $eflags - ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] - ; CHECK: [[AND32ri_:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def $eflags - ; CHECK: $eax = COPY [[AND32ri_]] - ; CHECK: RET 0, implicit $eax + ; CHECK: liveins: $edi, $esi + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi + ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags + ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 6, implicit $eflags + ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] + ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags + ; CHECK-NEXT: $eax = COPY [[AND32ri]] + ; CHECK-NEXT: RET 0, implicit $eax %0(s32) = COPY $edi %1(s32) = COPY $esi %4(s8) = G_ICMP intpred(ule), %0(s32), %1 @@ -423,14 +441,16 @@ liveins: $edi, $esi ; CHECK-LABEL: name: test_icmp_sgt_i32 - ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi - ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags - ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags - ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] - ; CHECK: [[AND32ri_:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def $eflags - ; CHECK: $eax = COPY [[AND32ri_]] - ; CHECK: RET 0, implicit $eax + ; CHECK: liveins: $edi, $esi + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi + ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags + ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags + ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] + ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags + ; CHECK-NEXT: $eax = COPY [[AND32ri]] + ; CHECK-NEXT: RET 0, implicit $eax %0(s32) = COPY $edi %1(s32) = COPY $esi %4(s8) = G_ICMP intpred(sgt), %0(s32), %1 @@ -459,14 +479,16 @@ liveins: $edi, $esi ; CHECK-LABEL: name: test_icmp_sge_i32 - ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi - ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags - ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 13, implicit $eflags - ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] - ; CHECK: [[AND32ri_:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def $eflags - ; CHECK: $eax = COPY [[AND32ri_]] - ; CHECK: RET 0, implicit $eax + ; CHECK: liveins: $edi, $esi + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi + ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags + ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 13, implicit $eflags + ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] + ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags + ; CHECK-NEXT: $eax = COPY [[AND32ri]] + ; CHECK-NEXT: RET 0, implicit $eax %0(s32) = COPY $edi %1(s32) = COPY $esi %4(s8) = G_ICMP intpred(sge), %0(s32), %1 @@ -495,14 +517,16 @@ liveins: $edi, $esi ; CHECK-LABEL: name: test_icmp_slt_i32 - ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi - ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags - ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 12, implicit $eflags - ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] - ; CHECK: [[AND32ri_:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def $eflags - ; CHECK: $eax = COPY [[AND32ri_]] - ; CHECK: RET 0, implicit $eax + ; CHECK: liveins: $edi, $esi + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi + ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags + ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 12, implicit $eflags + ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] + ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags + ; CHECK-NEXT: $eax = COPY [[AND32ri]] + ; CHECK-NEXT: RET 0, implicit $eax %0(s32) = COPY $edi %1(s32) = COPY $esi %4(s8) = G_ICMP intpred(slt), %0(s32), %1 @@ -531,14 +555,16 @@ liveins: $edi, $esi ; CHECK-LABEL: name: test_icmp_sle_i32 - ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi - ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags - ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 14, implicit $eflags - ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] - ; CHECK: [[AND32ri_:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def $eflags - ; CHECK: $eax = COPY [[AND32ri_]] - ; CHECK: RET 0, implicit $eax + ; CHECK: liveins: $edi, $esi + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi + ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags + ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 14, implicit $eflags + ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] + ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags + ; CHECK-NEXT: $eax = COPY [[AND32ri]] + ; CHECK-NEXT: RET 0, implicit $eax %0(s32) = COPY $edi %1(s32) = COPY $esi %4(s8) = G_ICMP intpred(sle), %0(s32), %1 diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-constant.mir b/llvm/test/CodeGen/X86/GlobalISel/select-constant.mir --- a/llvm/test/CodeGen/X86/GlobalISel/select-constant.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-constant.mir @@ -47,8 +47,8 @@ bb.1 (%ir-block.0): ; CHECK-LABEL: name: const_i8 ; CHECK: [[MOV8ri:%[0-9]+]]:gr8 = MOV8ri 2 - ; CHECK: $al = COPY [[MOV8ri]] - ; CHECK: RET 0, implicit $al + ; CHECK-NEXT: $al = COPY [[MOV8ri]] + ; CHECK-NEXT: RET 0, implicit $al %0(s8) = G_CONSTANT i8 2 $al = COPY %0(s8) RET 0, implicit $al @@ -65,8 +65,8 @@ bb.1 (%ir-block.0): ; CHECK-LABEL: name: const_i16 ; CHECK: [[MOV16ri:%[0-9]+]]:gr16 = MOV16ri 3 - ; CHECK: $ax = COPY [[MOV16ri]] - ; CHECK: RET 0, implicit $ax + ; CHECK-NEXT: $ax = COPY [[MOV16ri]] + ; CHECK-NEXT: RET 0, implicit $ax %0(s16) = G_CONSTANT i16 3 $ax = COPY %0(s16) RET 0, implicit $ax @@ -83,8 +83,8 @@ bb.1 (%ir-block.0): ; CHECK-LABEL: name: const_i32 ; CHECK: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 4 - ; CHECK: $eax = COPY [[MOV32ri]] - ; CHECK: RET 0, implicit $eax + ; CHECK-NEXT: $eax = COPY [[MOV32ri]] + ; CHECK-NEXT: RET 0, implicit $eax %0(s32) = G_CONSTANT i32 4 $eax = COPY %0(s32) RET 0, implicit $eax @@ -99,9 +99,9 @@ body: | bb.1 (%ir-block.0): ; CHECK-LABEL: name: const_i32_0 - ; CHECK: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags - ; CHECK: $eax = COPY [[MOV32r0_]] - ; CHECK: RET 0, implicit $eax + ; CHECK: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags + ; CHECK-NEXT: $eax = COPY [[MOV32r0_]] + ; CHECK-NEXT: RET 0, implicit $eax %0(s32) = G_CONSTANT i32 0 $eax = COPY %0(s32) RET 0, implicit $eax @@ -118,8 +118,8 @@ bb.1 (%ir-block.0): ; CHECK-LABEL: name: const_i64 ; CHECK: [[MOV64ri:%[0-9]+]]:gr64 = MOV64ri 68719476720 - ; CHECK: $rax = COPY [[MOV64ri]] - ; CHECK: RET 0, implicit $rax + ; CHECK-NEXT: $rax = COPY [[MOV64ri]] + ; CHECK-NEXT: RET 0, implicit $rax %0(s64) = G_CONSTANT i64 68719476720 $rax = COPY %0(s64) RET 0, implicit $rax @@ -137,8 +137,8 @@ bb.1 (%ir-block.0): ; CHECK-LABEL: name: const_i64_u32 ; CHECK: [[MOV32ri64_:%[0-9]+]]:gr64 = MOV32ri64 1879048192 - ; CHECK: $rax = COPY [[MOV32ri64_]] - ; CHECK: RET 0, implicit $rax + ; CHECK-NEXT: $rax = COPY [[MOV32ri64_]] + ; CHECK-NEXT: RET 0, implicit $rax %0(s64) = G_CONSTANT i64 1879048192 $rax = COPY %0(s64) RET 0, implicit $rax @@ -155,8 +155,8 @@ bb.1 (%ir-block.0): ; CHECK-LABEL: name: const_i64_i32 ; CHECK: [[MOV64ri32_:%[0-9]+]]:gr64 = MOV64ri32 -1 - ; CHECK: $rax = COPY [[MOV64ri32_]] - ; CHECK: RET 0, implicit $rax + ; CHECK-NEXT: $rax = COPY [[MOV64ri32_]] + ; CHECK-NEXT: RET 0, implicit $rax %0(s64) = G_CONSTANT i64 -1 $rax = COPY %0(s64) RET 0, implicit $rax @@ -175,10 +175,12 @@ liveins: $rdi ; CHECK-LABEL: name: main - ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi - ; CHECK: [[MOV64ri32_:%[0-9]+]]:gr64 = MOV64ri32 0 - ; CHECK: MOV64mr [[COPY]], 1, $noreg, 0, $noreg, [[MOV64ri32_]] :: (store (p0) into %ir.data) - ; CHECK: RET 0 + ; CHECK: liveins: $rdi + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi + ; CHECK-NEXT: [[MOV64ri32_:%[0-9]+]]:gr64 = MOV64ri32 0 + ; CHECK-NEXT: MOV64mr [[COPY]], 1, $noreg, 0, $noreg, [[MOV64ri32_]] :: (store (p0) into %ir.data) + ; CHECK-NEXT: RET 0 %0(p0) = COPY $rdi %1(p0) = G_CONSTANT i64 0 G_STORE %1(p0), %0(p0) :: (store (p0) into %ir.data) diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-leaf-constant.mir b/llvm/test/CodeGen/X86/GlobalISel/select-leaf-constant.mir --- a/llvm/test/CodeGen/X86/GlobalISel/select-leaf-constant.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-leaf-constant.mir @@ -34,8 +34,8 @@ bb.1 (%ir-block.0): ; CHECK-LABEL: name: const_i32_1 ; CHECK: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 1 - ; CHECK: $eax = COPY [[MOV32ri]] - ; CHECK: RET 0, implicit $eax + ; CHECK-NEXT: $eax = COPY [[MOV32ri]] + ; CHECK-NEXT: RET 0, implicit $eax %0(s32) = G_CONSTANT i32 1 $eax = COPY %0(s32) RET 0, implicit $eax @@ -50,9 +50,9 @@ body: | bb.1 (%ir-block.0): ; CHECK-LABEL: name: const_i32_1_optsize - ; CHECK: [[MOV32r1_:%[0-9]+]]:gr32 = MOV32r1 implicit-def $eflags - ; CHECK: $eax = COPY [[MOV32r1_]] - ; CHECK: RET 0, implicit $eax + ; CHECK: [[MOV32r1_:%[0-9]+]]:gr32 = MOV32r1 implicit-def dead $eflags + ; CHECK-NEXT: $eax = COPY [[MOV32r1_]] + ; CHECK-NEXT: RET 0, implicit $eax %0(s32) = G_CONSTANT i32 1 $eax = COPY %0(s32) RET 0, implicit $eax @@ -68,8 +68,8 @@ bb.1 (%ir-block.0): ; CHECK-LABEL: name: const_i32_1b ; CHECK: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 1 - ; CHECK: $eax = COPY [[MOV32ri]] - ; CHECK: RET 0, implicit $eax + ; CHECK-NEXT: $eax = COPY [[MOV32ri]] + ; CHECK-NEXT: RET 0, implicit $eax %0(s32) = G_CONSTANT i32 1 $eax = COPY %0(s32) RET 0, implicit $eax @@ -84,9 +84,9 @@ body: | bb.1 (%ir-block.0): ; CHECK-LABEL: name: const_i32_1_optsizeb - ; CHECK: [[MOV32r1_:%[0-9]+]]:gr32 = MOV32r1 implicit-def $eflags - ; CHECK: $eax = COPY [[MOV32r1_]] - ; CHECK: RET 0, implicit $eax + ; CHECK: [[MOV32r1_:%[0-9]+]]:gr32 = MOV32r1 implicit-def dead $eflags + ; CHECK-NEXT: $eax = COPY [[MOV32r1_]] + ; CHECK-NEXT: RET 0, implicit $eax %0(s32) = G_CONSTANT i32 1 $eax = COPY %0(s32) RET 0, implicit $eax diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-lshr-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/select-lshr-scalar.mir --- a/llvm/test/CodeGen/X86/GlobalISel/select-lshr-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-lshr-scalar.mir @@ -70,13 +70,14 @@ ; ALL-LABEL: name: test_lshr_i64 ; ALL: liveins: $rdi, $rsi - ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi - ; ALL: [[COPY1:%[0-9]+]]:gr64_with_sub_8bit = COPY $rsi - ; ALL: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit - ; ALL: $cl = COPY [[COPY2]] - ; ALL: [[SHR64rCL:%[0-9]+]]:gr64 = SHR64rCL [[COPY]], implicit-def $eflags, implicit $cl - ; ALL: $rax = COPY [[SHR64rCL]] - ; ALL: RET 0, implicit $rax + ; ALL-NEXT: {{ $}} + ; ALL-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi + ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr64_with_sub_8bit = COPY $rsi + ; ALL-NEXT: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit + ; ALL-NEXT: $cl = COPY [[COPY2]] + ; ALL-NEXT: [[SHR64rCL:%[0-9]+]]:gr64 = SHR64rCL [[COPY]], implicit-def dead $eflags, implicit $cl + ; ALL-NEXT: $rax = COPY [[SHR64rCL]] + ; ALL-NEXT: RET 0, implicit $rax %0(s64) = COPY $rdi %1(s64) = COPY $rsi %2(s8) = G_TRUNC %1 @@ -105,10 +106,11 @@ ; ALL-LABEL: name: test_lshr_i64_imm ; ALL: liveins: $rdi - ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi - ; ALL: [[SHR64ri:%[0-9]+]]:gr64 = SHR64ri [[COPY]], 5, implicit-def $eflags - ; ALL: $rax = COPY [[SHR64ri]] - ; ALL: RET 0, implicit $rax + ; ALL-NEXT: {{ $}} + ; ALL-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi + ; ALL-NEXT: [[SHR64ri:%[0-9]+]]:gr64 = SHR64ri [[COPY]], 5, implicit-def dead $eflags + ; ALL-NEXT: $rax = COPY [[SHR64ri]] + ; ALL-NEXT: RET 0, implicit $rax %0(s64) = COPY $rdi %1(s8) = G_CONSTANT i8 5 %2(s64) = G_LSHR %0, %1 @@ -137,13 +139,14 @@ ; ALL-LABEL: name: test_lshr_i32 ; ALL: liveins: $edi, $esi - ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY $esi - ; ALL: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit - ; ALL: $cl = COPY [[COPY2]] - ; ALL: [[SHR32rCL:%[0-9]+]]:gr32 = SHR32rCL [[COPY]], implicit-def $eflags, implicit $cl - ; ALL: $eax = COPY [[SHR32rCL]] - ; ALL: RET 0, implicit $eax + ; ALL-NEXT: {{ $}} + ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi + ; ALL-NEXT: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit + ; ALL-NEXT: $cl = COPY [[COPY2]] + ; ALL-NEXT: [[SHR32rCL:%[0-9]+]]:gr32 = SHR32rCL [[COPY]], implicit-def dead $eflags, implicit $cl + ; ALL-NEXT: $eax = COPY [[SHR32rCL]] + ; ALL-NEXT: RET 0, implicit $eax %0(s32) = COPY $edi %1(s32) = COPY $esi %2(s8) = G_TRUNC %1 @@ -172,10 +175,11 @@ ; ALL-LABEL: name: test_lshr_i32_imm ; ALL: liveins: $edi - ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; ALL: [[SHR32ri:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 5, implicit-def $eflags - ; ALL: $eax = COPY [[SHR32ri]] - ; ALL: RET 0, implicit $eax + ; ALL-NEXT: {{ $}} + ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; ALL-NEXT: [[SHR32ri:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 5, implicit-def dead $eflags + ; ALL-NEXT: $eax = COPY [[SHR32ri]] + ; ALL-NEXT: RET 0, implicit $eax %0(s32) = COPY $edi %1(s8) = G_CONSTANT i8 5 %2(s32) = G_LSHR %0, %1 @@ -205,14 +209,15 @@ ; ALL-LABEL: name: test_lshr_i16 ; ALL: liveins: $edi, $esi - ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY $esi - ; ALL: [[COPY2:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit - ; ALL: [[COPY3:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit - ; ALL: $cl = COPY [[COPY3]] - ; ALL: [[SHR16rCL:%[0-9]+]]:gr16 = SHR16rCL [[COPY2]], implicit-def $eflags, implicit $cl - ; ALL: $ax = COPY [[SHR16rCL]] - ; ALL: RET 0, implicit $ax + ; ALL-NEXT: {{ $}} + ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi + ; ALL-NEXT: [[COPY2:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit + ; ALL-NEXT: [[COPY3:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit + ; ALL-NEXT: $cl = COPY [[COPY3]] + ; ALL-NEXT: [[SHR16rCL:%[0-9]+]]:gr16 = SHR16rCL [[COPY2]], implicit-def dead $eflags, implicit $cl + ; ALL-NEXT: $ax = COPY [[SHR16rCL]] + ; ALL-NEXT: RET 0, implicit $ax %0(s32) = COPY $edi %1(s32) = COPY $esi %2(s16) = G_TRUNC %0(s32) @@ -243,11 +248,12 @@ ; ALL-LABEL: name: test_lshr_i16_imm ; ALL: liveins: $edi - ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; ALL: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit - ; ALL: [[SHR16ri:%[0-9]+]]:gr16 = SHR16ri [[COPY1]], 5, implicit-def $eflags - ; ALL: $ax = COPY [[SHR16ri]] - ; ALL: RET 0, implicit $ax + ; ALL-NEXT: {{ $}} + ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit + ; ALL-NEXT: [[SHR16ri:%[0-9]+]]:gr16 = SHR16ri [[COPY1]], 5, implicit-def dead $eflags + ; ALL-NEXT: $ax = COPY [[SHR16ri]] + ; ALL-NEXT: RET 0, implicit $ax %0(s32) = COPY $edi %2(s8) = G_CONSTANT i8 5 %1(s16) = G_TRUNC %0(s32) @@ -278,14 +284,15 @@ ; ALL-LABEL: name: test_lshr_i8 ; ALL: liveins: $edi, $esi - ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY $esi - ; ALL: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit - ; ALL: [[COPY3:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit - ; ALL: $cl = COPY [[COPY3]] - ; ALL: [[SHR8rCL:%[0-9]+]]:gr8 = SHR8rCL [[COPY2]], implicit-def $eflags, implicit $cl - ; ALL: $al = COPY [[SHR8rCL]] - ; ALL: RET 0, implicit $al + ; ALL-NEXT: {{ $}} + ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi + ; ALL-NEXT: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit + ; ALL-NEXT: [[COPY3:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit + ; ALL-NEXT: $cl = COPY [[COPY3]] + ; ALL-NEXT: [[SHR8rCL:%[0-9]+]]:gr8 = SHR8rCL [[COPY2]], implicit-def dead $eflags, implicit $cl + ; ALL-NEXT: $al = COPY [[SHR8rCL]] + ; ALL-NEXT: RET 0, implicit $al %0(s32) = COPY $edi %1(s32) = COPY $esi %2(s8) = G_TRUNC %0(s32) @@ -316,11 +323,12 @@ ; ALL-LABEL: name: test_lshr_i8_imm ; ALL: liveins: $edi - ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; ALL: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit - ; ALL: [[SHR8ri:%[0-9]+]]:gr8 = SHR8ri [[COPY1]], 5, implicit-def $eflags - ; ALL: $al = COPY [[SHR8ri]] - ; ALL: RET 0, implicit $al + ; ALL-NEXT: {{ $}} + ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit + ; ALL-NEXT: [[SHR8ri:%[0-9]+]]:gr8 = SHR8ri [[COPY1]], 5, implicit-def dead $eflags + ; ALL-NEXT: $al = COPY [[SHR8ri]] + ; ALL-NEXT: RET 0, implicit $al %0(s32) = COPY $edi %2(s8) = G_CONSTANT i8 5 %1(s8) = G_TRUNC %0(s32) diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-phi.mir b/llvm/test/CodeGen/X86/GlobalISel/select-phi.mir --- a/llvm/test/CodeGen/X86/GlobalISel/select-phi.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-phi.mir @@ -126,7 +126,7 @@ ; ALL-NEXT: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit ; ALL-NEXT: [[COPY3:%[0-9]+]]:gr32 = COPY $edx ; ALL-NEXT: [[COPY4:%[0-9]+]]:gr8 = COPY [[COPY3]].sub_8bit - ; ALL-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags + ; ALL-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags ; ALL-NEXT: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags ; ALL-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags ; ALL-NEXT: TEST8ri [[SETCCr]], 1, implicit-def $eflags @@ -190,7 +190,7 @@ ; ALL-NEXT: [[COPY2:%[0-9]+]]:gr16 = COPY [[COPY1]].sub_16bit ; ALL-NEXT: [[COPY3:%[0-9]+]]:gr32 = COPY $edx ; ALL-NEXT: [[COPY4:%[0-9]+]]:gr16 = COPY [[COPY3]].sub_16bit - ; ALL-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags + ; ALL-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags ; ALL-NEXT: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags ; ALL-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags ; ALL-NEXT: TEST8ri [[SETCCr]], 1, implicit-def $eflags @@ -251,7 +251,7 @@ ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi ; ALL-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY $edx - ; ALL-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags + ; ALL-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags ; ALL-NEXT: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags ; ALL-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags ; ALL-NEXT: TEST8ri [[SETCCr]], 1, implicit-def $eflags @@ -322,7 +322,7 @@ ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi ; ALL-NEXT: [[COPY2:%[0-9]+]]:gr64 = COPY $rdx - ; ALL-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags + ; ALL-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags ; ALL-NEXT: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags ; ALL-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags ; ALL-NEXT: TEST8ri [[SETCCr]], 1, implicit-def $eflags @@ -401,7 +401,7 @@ ; ALL-NEXT: [[COPY2:%[0-9]+]]:fr32 = COPY [[COPY1]] ; ALL-NEXT: [[COPY3:%[0-9]+]]:vr128 = COPY $xmm1 ; ALL-NEXT: [[COPY4:%[0-9]+]]:fr32 = COPY [[COPY3]] - ; ALL-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags + ; ALL-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags ; ALL-NEXT: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags ; ALL-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags ; ALL-NEXT: TEST8ri [[SETCCr]], 1, implicit-def $eflags @@ -467,7 +467,7 @@ ; ALL-NEXT: [[COPY2:%[0-9]+]]:fr64 = COPY [[COPY1]] ; ALL-NEXT: [[COPY3:%[0-9]+]]:vr128 = COPY $xmm1 ; ALL-NEXT: [[COPY4:%[0-9]+]]:fr64 = COPY [[COPY3]] - ; ALL-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags + ; ALL-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags ; ALL-NEXT: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags ; ALL-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags ; ALL-NEXT: TEST8ri [[SETCCr]], 1, implicit-def $eflags diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-shl-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/select-shl-scalar.mir --- a/llvm/test/CodeGen/X86/GlobalISel/select-shl-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-shl-scalar.mir @@ -92,13 +92,14 @@ ; ALL-LABEL: name: test_shl_i64 ; ALL: liveins: $rdi, $rsi - ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi - ; ALL: [[COPY1:%[0-9]+]]:gr64_with_sub_8bit = COPY $rsi - ; ALL: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit - ; ALL: $cl = COPY [[COPY2]] - ; ALL: [[SHL64rCL:%[0-9]+]]:gr64 = SHL64rCL [[COPY]], implicit-def $eflags, implicit $cl - ; ALL: $rax = COPY [[SHL64rCL]] - ; ALL: RET 0, implicit $rax + ; ALL-NEXT: {{ $}} + ; ALL-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi + ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr64_with_sub_8bit = COPY $rsi + ; ALL-NEXT: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit + ; ALL-NEXT: $cl = COPY [[COPY2]] + ; ALL-NEXT: [[SHL64rCL:%[0-9]+]]:gr64 = SHL64rCL [[COPY]], implicit-def dead $eflags, implicit $cl + ; ALL-NEXT: $rax = COPY [[SHL64rCL]] + ; ALL-NEXT: RET 0, implicit $rax %0(s64) = COPY $rdi %1(s64) = COPY $rsi %2(s8) = G_TRUNC %1 @@ -127,10 +128,11 @@ ; ALL-LABEL: name: test_shl_i64_imm ; ALL: liveins: $rdi - ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi - ; ALL: [[SHL64ri:%[0-9]+]]:gr64 = SHL64ri [[COPY]], 5, implicit-def $eflags - ; ALL: $rax = COPY [[SHL64ri]] - ; ALL: RET 0, implicit $rax + ; ALL-NEXT: {{ $}} + ; ALL-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi + ; ALL-NEXT: [[SHL64ri:%[0-9]+]]:gr64 = SHL64ri [[COPY]], 5, implicit-def dead $eflags + ; ALL-NEXT: $rax = COPY [[SHL64ri]] + ; ALL-NEXT: RET 0, implicit $rax %0(s64) = COPY $rdi %1(s8) = G_CONSTANT i8 5 %2(s64) = G_SHL %0, %1 @@ -158,10 +160,11 @@ ; ALL-LABEL: name: test_shl_i64_imm1 ; ALL: liveins: $rdi - ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi - ; ALL: [[ADD64rr:%[0-9]+]]:gr64 = ADD64rr [[COPY]], [[COPY]], implicit-def $eflags - ; ALL: $rax = COPY [[ADD64rr]] - ; ALL: RET 0, implicit $rax + ; ALL-NEXT: {{ $}} + ; ALL-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi + ; ALL-NEXT: [[ADD64rr:%[0-9]+]]:gr64 = ADD64rr [[COPY]], [[COPY]], implicit-def dead $eflags + ; ALL-NEXT: $rax = COPY [[ADD64rr]] + ; ALL-NEXT: RET 0, implicit $rax %0(s64) = COPY $rdi %1(s8) = G_CONSTANT i8 1 %2(s64) = G_SHL %0, %1 @@ -190,13 +193,14 @@ ; ALL-LABEL: name: test_shl_i32 ; ALL: liveins: $edi, $esi - ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY $esi - ; ALL: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit - ; ALL: $cl = COPY [[COPY2]] - ; ALL: [[SHL32rCL:%[0-9]+]]:gr32 = SHL32rCL [[COPY]], implicit-def $eflags, implicit $cl - ; ALL: $eax = COPY [[SHL32rCL]] - ; ALL: RET 0, implicit $eax + ; ALL-NEXT: {{ $}} + ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi + ; ALL-NEXT: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit + ; ALL-NEXT: $cl = COPY [[COPY2]] + ; ALL-NEXT: [[SHL32rCL:%[0-9]+]]:gr32 = SHL32rCL [[COPY]], implicit-def dead $eflags, implicit $cl + ; ALL-NEXT: $eax = COPY [[SHL32rCL]] + ; ALL-NEXT: RET 0, implicit $eax %0(s32) = COPY $edi %1(s32) = COPY $esi %2(s8) = G_TRUNC %1 @@ -225,10 +229,11 @@ ; ALL-LABEL: name: test_shl_i32_imm ; ALL: liveins: $edi - ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; ALL: [[SHL32ri:%[0-9]+]]:gr32 = SHL32ri [[COPY]], 5, implicit-def $eflags - ; ALL: $eax = COPY [[SHL32ri]] - ; ALL: RET 0, implicit $eax + ; ALL-NEXT: {{ $}} + ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; ALL-NEXT: [[SHL32ri:%[0-9]+]]:gr32 = SHL32ri [[COPY]], 5, implicit-def dead $eflags + ; ALL-NEXT: $eax = COPY [[SHL32ri]] + ; ALL-NEXT: RET 0, implicit $eax %0(s32) = COPY $edi %1(s8) = G_CONSTANT i8 5 %2(s32) = G_SHL %0, %1 @@ -256,10 +261,11 @@ ; ALL-LABEL: name: test_shl_i32_imm1 ; ALL: liveins: $edi - ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; ALL: [[ADD32rr:%[0-9]+]]:gr32 = ADD32rr [[COPY]], [[COPY]], implicit-def $eflags - ; ALL: $eax = COPY [[ADD32rr]] - ; ALL: RET 0, implicit $eax + ; ALL-NEXT: {{ $}} + ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; ALL-NEXT: [[ADD32rr:%[0-9]+]]:gr32 = ADD32rr [[COPY]], [[COPY]], implicit-def dead $eflags + ; ALL-NEXT: $eax = COPY [[ADD32rr]] + ; ALL-NEXT: RET 0, implicit $eax %0(s32) = COPY $edi %1(s8) = G_CONSTANT i8 1 %2(s32) = G_SHL %0, %1 @@ -289,14 +295,15 @@ ; ALL-LABEL: name: test_shl_i16 ; ALL: liveins: $edi, $esi - ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY $esi - ; ALL: [[COPY2:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit - ; ALL: [[COPY3:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit - ; ALL: $cl = COPY [[COPY3]] - ; ALL: [[SHL16rCL:%[0-9]+]]:gr16 = SHL16rCL [[COPY2]], implicit-def $eflags, implicit $cl - ; ALL: $ax = COPY [[SHL16rCL]] - ; ALL: RET 0, implicit $ax + ; ALL-NEXT: {{ $}} + ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi + ; ALL-NEXT: [[COPY2:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit + ; ALL-NEXT: [[COPY3:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit + ; ALL-NEXT: $cl = COPY [[COPY3]] + ; ALL-NEXT: [[SHL16rCL:%[0-9]+]]:gr16 = SHL16rCL [[COPY2]], implicit-def dead $eflags, implicit $cl + ; ALL-NEXT: $ax = COPY [[SHL16rCL]] + ; ALL-NEXT: RET 0, implicit $ax %0(s32) = COPY $edi %1(s32) = COPY $esi %2(s16) = G_TRUNC %0(s32) @@ -327,11 +334,12 @@ ; ALL-LABEL: name: test_shl_i16_imm ; ALL: liveins: $edi - ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; ALL: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit - ; ALL: [[SHL16ri:%[0-9]+]]:gr16 = SHL16ri [[COPY1]], 5, implicit-def $eflags - ; ALL: $ax = COPY [[SHL16ri]] - ; ALL: RET 0, implicit $ax + ; ALL-NEXT: {{ $}} + ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit + ; ALL-NEXT: [[SHL16ri:%[0-9]+]]:gr16 = SHL16ri [[COPY1]], 5, implicit-def dead $eflags + ; ALL-NEXT: $ax = COPY [[SHL16ri]] + ; ALL-NEXT: RET 0, implicit $ax %0(s32) = COPY $edi %2(s8) = G_CONSTANT i8 5 %1(s16) = G_TRUNC %0(s32) @@ -361,11 +369,12 @@ ; ALL-LABEL: name: test_shl_i16_imm1 ; ALL: liveins: $edi - ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; ALL: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit - ; ALL: [[ADD16rr:%[0-9]+]]:gr16 = ADD16rr [[COPY1]], [[COPY1]], implicit-def $eflags - ; ALL: $ax = COPY [[ADD16rr]] - ; ALL: RET 0, implicit $ax + ; ALL-NEXT: {{ $}} + ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit + ; ALL-NEXT: [[ADD16rr:%[0-9]+]]:gr16 = ADD16rr [[COPY1]], [[COPY1]], implicit-def dead $eflags + ; ALL-NEXT: $ax = COPY [[ADD16rr]] + ; ALL-NEXT: RET 0, implicit $ax %0(s32) = COPY $edi %2(s8) = G_CONSTANT i8 1 %1(s16) = G_TRUNC %0(s32) @@ -396,14 +405,15 @@ ; ALL-LABEL: name: test_shl_i8 ; ALL: liveins: $edi, $esi - ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY $esi - ; ALL: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit - ; ALL: [[COPY3:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit - ; ALL: $cl = COPY [[COPY3]] - ; ALL: [[SHL8rCL:%[0-9]+]]:gr8 = SHL8rCL [[COPY2]], implicit-def $eflags, implicit $cl - ; ALL: $al = COPY [[SHL8rCL]] - ; ALL: RET 0, implicit $al + ; ALL-NEXT: {{ $}} + ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi + ; ALL-NEXT: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit + ; ALL-NEXT: [[COPY3:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit + ; ALL-NEXT: $cl = COPY [[COPY3]] + ; ALL-NEXT: [[SHL8rCL:%[0-9]+]]:gr8 = SHL8rCL [[COPY2]], implicit-def dead $eflags, implicit $cl + ; ALL-NEXT: $al = COPY [[SHL8rCL]] + ; ALL-NEXT: RET 0, implicit $al %0(s32) = COPY $edi %1(s32) = COPY $esi %2(s8) = G_TRUNC %0(s32) @@ -434,11 +444,12 @@ ; ALL-LABEL: name: test_shl_i8_imm ; ALL: liveins: $edi - ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; ALL: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit - ; ALL: [[SHL8ri:%[0-9]+]]:gr8 = SHL8ri [[COPY1]], 5, implicit-def $eflags - ; ALL: $al = COPY [[SHL8ri]] - ; ALL: RET 0, implicit $al + ; ALL-NEXT: {{ $}} + ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit + ; ALL-NEXT: [[SHL8ri:%[0-9]+]]:gr8 = SHL8ri [[COPY1]], 5, implicit-def dead $eflags + ; ALL-NEXT: $al = COPY [[SHL8ri]] + ; ALL-NEXT: RET 0, implicit $al %0(s32) = COPY $edi %2(s8) = G_CONSTANT i8 5 %1(s8) = G_TRUNC %0(s32) @@ -468,11 +479,12 @@ ; ALL-LABEL: name: test_shl_i8_imm1 ; ALL: liveins: $edi - ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; ALL: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit - ; ALL: [[ADD8rr:%[0-9]+]]:gr8 = ADD8rr [[COPY1]], [[COPY1]], implicit-def $eflags - ; ALL: $al = COPY [[ADD8rr]] - ; ALL: RET 0, implicit $al + ; ALL-NEXT: {{ $}} + ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit + ; ALL-NEXT: [[ADD8rr:%[0-9]+]]:gr8 = ADD8rr [[COPY1]], [[COPY1]], implicit-def dead $eflags + ; ALL-NEXT: $al = COPY [[ADD8rr]] + ; ALL-NEXT: RET 0, implicit $al %0(s32) = COPY $edi %2(s8) = G_CONSTANT i8 1 %1(s8) = G_TRUNC %0(s32) diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-zext.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-zext.mir --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-zext.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-zext.mir @@ -72,11 +72,12 @@ ; CHECK-LABEL: name: zext_i1_to_i8 ; CHECK: liveins: $edi - ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit - ; CHECK: [[AND8ri:%[0-9]+]]:gr8 = AND8ri [[COPY1]], 1, implicit-def $eflags - ; CHECK: $al = COPY [[AND8ri]] - ; CHECK: RET 0, implicit $al + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit + ; CHECK-NEXT: [[AND8ri:%[0-9]+]]:gr8 = AND8ri [[COPY1]], 1, implicit-def dead $eflags + ; CHECK-NEXT: $al = COPY [[AND8ri]] + ; CHECK-NEXT: RET 0, implicit $al %1:gpr(s32) = COPY $edi %3:gpr(s8) = G_CONSTANT i8 1 %4:gpr(s8) = G_TRUNC %1(s32) @@ -103,11 +104,12 @@ ; CHECK-LABEL: name: zext_i1_to_i16 ; CHECK: liveins: $edi - ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; CHECK: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit - ; CHECK: [[AND16ri_:%[0-9]+]]:gr16 = AND16ri [[COPY1]], 1, implicit-def $eflags - ; CHECK: $ax = COPY [[AND16ri_]] - ; CHECK: RET 0, implicit $ax + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit + ; CHECK-NEXT: [[AND16ri:%[0-9]+]]:gr16 = AND16ri [[COPY1]], 1, implicit-def dead $eflags + ; CHECK-NEXT: $ax = COPY [[AND16ri]] + ; CHECK-NEXT: RET 0, implicit $ax %1:gpr(s32) = COPY $edi %3:gpr(s16) = G_CONSTANT i16 1 %4:gpr(s16) = G_TRUNC %1(s32) @@ -134,10 +136,11 @@ ; CHECK-LABEL: name: zext_i1_to_i32 ; CHECK: liveins: $edi - ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; CHECK: [[AND32ri_:%[0-9]+]]:gr32 = AND32ri [[COPY]], 1, implicit-def $eflags - ; CHECK: $eax = COPY [[AND32ri_]] - ; CHECK: RET 0, implicit $eax + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[COPY]], 1, implicit-def dead $eflags + ; CHECK-NEXT: $eax = COPY [[AND32ri]] + ; CHECK-NEXT: RET 0, implicit $eax %1:gpr(s32) = COPY $edi %3:gpr(s32) = G_CONSTANT i32 1 %4:gpr(s32) = COPY %1(s32) @@ -164,12 +167,13 @@ ; CHECK-LABEL: name: zext_i1_to_i64 ; CHECK: liveins: $edi - ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; CHECK: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF - ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32bit - ; CHECK: [[AND64ri32_:%[0-9]+]]:gr64 = AND64ri32 [[INSERT_SUBREG]], 1, implicit-def $eflags - ; CHECK: $rax = COPY [[AND64ri32_]] - ; CHECK: RET 0, implicit $rax + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; CHECK-NEXT: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF + ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32bit + ; CHECK-NEXT: [[AND64ri32_:%[0-9]+]]:gr64 = AND64ri32 [[INSERT_SUBREG]], 1, implicit-def dead $eflags + ; CHECK-NEXT: $rax = COPY [[AND64ri32_]] + ; CHECK-NEXT: RET 0, implicit $rax %1:gpr(s32) = COPY $edi %3:gpr(s64) = G_CONSTANT i64 1 %4:gpr(s64) = G_ANYEXT %1(s32) @@ -196,13 +200,14 @@ ; CHECK-LABEL: name: zext_i8_to_i16 ; CHECK: liveins: $edi - ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; CHECK: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit - ; CHECK: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit - ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY2]] - ; CHECK: [[COPY3:%[0-9]+]]:gr16 = COPY [[MOVZX32rr8_]].sub_16bit - ; CHECK: $ax = COPY [[COPY3]] - ; CHECK: RET 0, implicit $ax + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit + ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY2]] + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gr16 = COPY [[MOVZX32rr8_]].sub_16bit + ; CHECK-NEXT: $ax = COPY [[COPY3]] + ; CHECK-NEXT: RET 0, implicit $ax %1:gpr(s32) = COPY $edi %3:gpr(s16) = G_CONSTANT i16 255 %4:gpr(s16) = G_TRUNC %1(s32) @@ -229,11 +234,12 @@ ; CHECK-LABEL: name: zext_i8_to_i32 ; CHECK: liveins: $edi - ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit - ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY1]] - ; CHECK: $eax = COPY [[MOVZX32rr8_]] - ; CHECK: RET 0, implicit $eax + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit + ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY1]] + ; CHECK-NEXT: $eax = COPY [[MOVZX32rr8_]] + ; CHECK-NEXT: RET 0, implicit $eax %1:gpr(s32) = COPY $edi %3:gpr(s32) = G_CONSTANT i32 255 %4:gpr(s32) = COPY %1(s32) @@ -260,12 +266,13 @@ ; CHECK-LABEL: name: zext_i8_to_i64 ; CHECK: liveins: $edi - ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; CHECK: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF - ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32bit - ; CHECK: [[AND64ri32_:%[0-9]+]]:gr64 = AND64ri32 [[INSERT_SUBREG]], 255, implicit-def $eflags - ; CHECK: $rax = COPY [[AND64ri32_]] - ; CHECK: RET 0, implicit $rax + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; CHECK-NEXT: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF + ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32bit + ; CHECK-NEXT: [[AND64ri32_:%[0-9]+]]:gr64 = AND64ri32 [[INSERT_SUBREG]], 255, implicit-def dead $eflags + ; CHECK-NEXT: $rax = COPY [[AND64ri32_]] + ; CHECK-NEXT: RET 0, implicit $rax %1:gpr(s32) = COPY $edi %3:gpr(s64) = G_CONSTANT i64 255 %4:gpr(s64) = G_ANYEXT %1(s32) @@ -292,11 +299,12 @@ ; CHECK-LABEL: name: zext_i16_to_i32 ; CHECK: liveins: $edi - ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; CHECK: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit - ; CHECK: [[MOVZX32rr16_:%[0-9]+]]:gr32 = MOVZX32rr16 [[COPY1]] - ; CHECK: $eax = COPY [[MOVZX32rr16_]] - ; CHECK: RET 0, implicit $eax + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit + ; CHECK-NEXT: [[MOVZX32rr16_:%[0-9]+]]:gr32 = MOVZX32rr16 [[COPY1]] + ; CHECK-NEXT: $eax = COPY [[MOVZX32rr16_]] + ; CHECK-NEXT: RET 0, implicit $eax %1:gpr(s32) = COPY $edi %3:gpr(s32) = G_CONSTANT i32 65535 %4:gpr(s32) = COPY %1(s32) @@ -323,12 +331,13 @@ ; CHECK-LABEL: name: zext_i16_to_i64 ; CHECK: liveins: $edi - ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; CHECK: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF - ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32bit - ; CHECK: [[AND64ri32_:%[0-9]+]]:gr64 = AND64ri32 [[INSERT_SUBREG]], 65535, implicit-def $eflags - ; CHECK: $rax = COPY [[AND64ri32_]] - ; CHECK: RET 0, implicit $rax + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; CHECK-NEXT: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF + ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32bit + ; CHECK-NEXT: [[AND64ri32_:%[0-9]+]]:gr64 = AND64ri32 [[INSERT_SUBREG]], 65535, implicit-def dead $eflags + ; CHECK-NEXT: $rax = COPY [[AND64ri32_]] + ; CHECK-NEXT: RET 0, implicit $rax %1:gpr(s32) = COPY $edi %3:gpr(s64) = G_CONSTANT i64 65535 %4:gpr(s64) = G_ANYEXT %1(s32) @@ -352,11 +361,12 @@ ; CHECK-LABEL: name: zext_i32_to_i64 ; CHECK: liveins: $edi - ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; CHECK: [[MOV32rr:%[0-9]+]]:gr32 = MOV32rr [[COPY]] - ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[MOV32rr]], %subreg.sub_32bit - ; CHECK: $rax = COPY [[SUBREG_TO_REG]] - ; CHECK: RET 0, implicit $rax + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; CHECK-NEXT: [[MOV32rr:%[0-9]+]]:gr32 = MOV32rr [[COPY]] + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[MOV32rr]], %subreg.sub_32bit + ; CHECK-NEXT: $rax = COPY [[SUBREG_TO_REG]] + ; CHECK-NEXT: RET 0, implicit $rax %0:gpr(s32) = COPY $edi %1:gpr(s64) = G_ZEXT %0(s32) $rax = COPY %1(s64) diff --git a/llvm/test/CodeGen/X86/switch-bit-test-unreachable-default.ll b/llvm/test/CodeGen/X86/switch-bit-test-unreachable-default.ll --- a/llvm/test/CodeGen/X86/switch-bit-test-unreachable-default.ll +++ b/llvm/test/CodeGen/X86/switch-bit-test-unreachable-default.ll @@ -39,17 +39,17 @@ ; CHECK-GISEL: liveins: $edi ; CHECK-GISEL: %0:gr32 = COPY $edi ; CHECK-GISEL: %10:gr32 = MOV32ri 1 -; CHECK-GISEL: %11:gr32 = MOV32r0 implicit-def $eflags -; CHECK-GISEL: %2:gr32 = SUB32ri %0:gr32(tied-def 0), 0, implicit-def $eflags +; CHECK-GISEL: %11:gr32 = MOV32r0 implicit-def dead $eflags +; CHECK-GISEL: %2:gr32 = SUB32ri %0:gr32(tied-def 0), 0, implicit-def dead $eflags ; CHECK-GISEL: bb.5 (%ir-block.1): ; CHECK-GISEL: ; predecessors: %bb.1 ; CHECK-GISEL: successors: %bb.4(0x55555555), %bb.2(0x2aaaaaab); %bb.4(66.67%), %bb.2(33.33%) ; CHECK-GISEL: %3:gr32 = MOV32ri 1 ; CHECK-GISEL: %13:gr8 = COPY %2.sub_8bit:gr32 ; CHECK-GISEL: $cl = COPY %13:gr8 -; CHECK-GISEL: %4:gr32 = SHL32rCL %3:gr32(tied-def 0), implicit-def $eflags, implicit $cl -; CHECK-GISEL: %6:gr32 = AND32ri %4:gr32(tied-def 0), 13056, implicit-def $eflags -; CHECK-GISEL: %7:gr32 = MOV32r0 implicit-def $eflags +; CHECK-GISEL: %4:gr32 = SHL32rCL %3:gr32(tied-def 0), implicit-def dead $eflags, implicit $cl +; CHECK-GISEL: %6:gr32 = AND32ri %4:gr32(tied-def 0), 13056, implicit-def dead $eflags +; CHECK-GISEL: %7:gr32 = MOV32r0 implicit-def dead $eflags ; CHECK-GISEL: CMP32rr %6:gr32, %7:gr32, implicit-def $eflags ; CHECK-GISEL: %12:gr8 = SETCCr 5, implicit $eflags ; CHECK-GISEL: TEST8ri %12:gr8, 1, implicit-def $eflags diff --git a/llvm/test/tools/UpdateTestChecks/update_mir_test_checks/Inputs/x86-condbr.mir.expected b/llvm/test/tools/UpdateTestChecks/update_mir_test_checks/Inputs/x86-condbr.mir.expected --- a/llvm/test/tools/UpdateTestChecks/update_mir_test_checks/Inputs/x86-condbr.mir.expected +++ b/llvm/test/tools/UpdateTestChecks/update_mir_test_checks/Inputs/x86-condbr.mir.expected @@ -33,7 +33,7 @@ ; CHECK-NEXT: liveins: $edi ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; CHECK-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags + ; CHECK-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags ; CHECK-NEXT: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 1 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit ; CHECK-NEXT: TEST8ri [[COPY1]], 1, implicit-def $eflags diff --git a/llvm/utils/TableGen/GlobalISelMatchTable.cpp b/llvm/utils/TableGen/GlobalISelMatchTable.cpp --- a/llvm/utils/TableGen/GlobalISelMatchTable.cpp +++ b/llvm/utils/TableGen/GlobalISelMatchTable.cpp @@ -1966,6 +1966,19 @@ for (const auto &Renderer : OperandRenderers) Renderer->emitRenderOpcodes(Table, Rule); + for (auto [OpIdx, Def] : enumerate(I->ImplicitDefs)) { + auto Namespace = + Def->getValue("Namespace") ? Def->getValueAsString("Namespace") : ""; + if (DeadImplicitDefs.contains(Def)) { + Table + << MatchTable::Opcode("GIR_SetImplicitDefDead") + << MatchTable::Comment("InsnID") << MatchTable::IntValue(InsnID) + << MatchTable::Comment( + ("OpIdx for " + Namespace + "::" + Def->getName() + "").str()) + << MatchTable::IntValue(OpIdx) << MatchTable::LineBreak; + } + } + if (I->mayLoad || I->mayStore) { Table << MatchTable::Opcode("GIR_MergeMemOperands") << MatchTable::Comment("InsnID") << MatchTable::IntValue(InsnID)