diff --git a/llvm/include/llvm/CodeGen/MachineRegisterInfo.h b/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
--- a/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
+++ b/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
@@ -672,9 +672,9 @@
   /// conditions are met:
   /// 1. Generic virtual registers are created.
   /// 2. The machine function has not completely been through the
-  ///    instruction selection process.
+  ///    instruction selection process or selected using GlobalISel.
   /// None of this condition is possible without GlobalISel for now.
-  /// In other words, if GlobalISel is not used or if the query happens after
+  /// In other words, if GlobalISel is not used and if the query happens after
   /// the select pass, using getRegClass is safe.
   const TargetRegisterClass *getRegClassOrNull(Register Reg) const {
     const RegClassOrRegBank &Val = VRegInfo[Reg].first;
diff --git a/llvm/lib/Target/X86/X86FastPreTileConfig.cpp b/llvm/lib/Target/X86/X86FastPreTileConfig.cpp
--- a/llvm/lib/Target/X86/X86FastPreTileConfig.cpp
+++ b/llvm/lib/Target/X86/X86FastPreTileConfig.cpp
@@ -668,7 +668,8 @@
   bool HasVirtTileReg = false;
   for (unsigned I = 0, E = NumVirtRegs; I != E; ++I) {
     Register VirtReg = Register::index2VirtReg(I);
-    if (MRI->getRegClass(VirtReg)->getID() == X86::TILERegClassID) {
+    const TargetRegisterClass *RC = MRI->getRegClassOrNull(VirtReg);
+    if (RC && RC->getID() == X86::TILERegClassID) {
       HasVirtTileReg = true;
       break;
     }
diff --git a/llvm/test/CodeGen/X86/AMX/amx-fastpreconfig-gisel.ll b/llvm/test/CodeGen/X86/AMX/amx-fastpreconfig-gisel.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/X86/AMX/amx-fastpreconfig-gisel.ll
@@ -0,0 +1,14 @@
+; RUN: llc -mtriple=x86_64-- -stop-after fastpretileconfig -global-isel -O0 -o - %s | FileCheck %s
+
+; GlobalIsel doesn't use all virtual registers and there are may be holes
+; during consecutive iteration of them. Note that %3 is absent.
+; https://github.com/llvm/llvm-project/issues/64452
+define i64 @f(i64 %0, i64 %1) {
+entry:
+; CHECK:     liveins
+; CHECK-NOT: %3:
+; CHECK:     RET 0, implicit $rax
+  %2 = lshr i64 %0, %1
+  %3 = add i64 %2, 123456789
+  ret i64 %3
+}