diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp
--- a/llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp
@@ -207,6 +207,8 @@
   case AtomicRMWInst::UMin:
   case AtomicRMWInst::FAdd:
   case AtomicRMWInst::FSub:
+  case AtomicRMWInst::FMax:
+  case AtomicRMWInst::FMin:
     break;
   }
 
@@ -315,6 +317,12 @@
   case Intrinsic::amdgcn_global_atomic_fadd:
     Op = AtomicRMWInst::FAdd;
     break;
+  case Intrinsic::amdgcn_global_atomic_fmax:
+    Op = AtomicRMWInst::FMax;
+    break;
+  case Intrinsic::amdgcn_global_atomic_fmin:
+    Op = AtomicRMWInst::FMin;
+    break;
   }
 
   // Only 32-bit floating point atomic ops are supported.
@@ -325,7 +333,8 @@
   unsigned ValIdx = 0;
 
   // TODO: Operand order is not consistent for atomic fadd intrinsics
-  if (Op == AtomicRMWInst::FAdd) {
+  if (Op == AtomicRMWInst::FAdd || Op == AtomicRMWInst::FMax ||
+      Op == AtomicRMWInst::FMin) {
     ValIdx = 1;
   }
 
@@ -392,6 +401,10 @@
   case AtomicRMWInst::UMin:
     Pred = CmpInst::ICMP_ULT;
     break;
+  case AtomicRMWInst::FMax:
+    return B.CreateSelect(B.CreateFCmp(FCmpInst::FCMP_UGT, LHS, RHS), LHS, RHS);
+  case AtomicRMWInst::FMin:
+    return B.CreateSelect(B.CreateFCmp(FCmpInst::FCMP_ULT, LHS, RHS), LHS, RHS);
   }
   Value *Cond = B.CreateICmp(Pred, LHS, RHS);
   return B.CreateSelect(Cond, LHS, RHS);
@@ -712,6 +725,10 @@
     return APFloat::getZero(Semantics, false);
   case AtomicRMWInst::FSub:
     return APFloat::getZero(Semantics, true);
+  case AtomicRMWInst::FMin:
+    return APFloat::getInf(Semantics, false);
+  case AtomicRMWInst::FMax:
+    return APFloat::getInf(Semantics, true);
   }
 }
 
@@ -906,6 +923,8 @@
     case AtomicRMWInst::Min:
     case AtomicRMWInst::UMax:
     case AtomicRMWInst::UMin:
+    case AtomicRMWInst::FMin:
+    case AtomicRMWInst::FMax:
       // These operations with a uniform value are idempotent: doing the atomic
       // operation multiple times has the same effect as doing it once.
       NewV = V;
diff --git a/llvm/test/CodeGen/AMDGPU/global_atomics_iterative_scan_fp.ll b/llvm/test/CodeGen/AMDGPU/global_atomics_iterative_scan_fp.ll
--- a/llvm/test/CodeGen/AMDGPU/global_atomics_iterative_scan_fp.ll
+++ b/llvm/test/CodeGen/AMDGPU/global_atomics_iterative_scan_fp.ll
@@ -282,4 +282,280 @@
   ret void
 }
 
+define amdgpu_kernel void @global_atomic_fmin_uni_value(ptr addrspace(1) %ptr) #0 {
+; IR-ITERATIVE-LABEL: @global_atomic_fmin_uni_value(
+; IR-ITERATIVE-NEXT:    [[TMP1:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)
+; IR-ITERATIVE-NEXT:    [[TMP2:%.*]] = bitcast i64 [[TMP1]] to <2 x i32>
+; IR-ITERATIVE-NEXT:    [[TMP3:%.*]] = extractelement <2 x i32> [[TMP2]], i32 0
+; IR-ITERATIVE-NEXT:    [[TMP4:%.*]] = extractelement <2 x i32> [[TMP2]], i32 1
+; IR-ITERATIVE-NEXT:    [[TMP5:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP3]], i32 0)
+; IR-ITERATIVE-NEXT:    [[TMP6:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP4]], i32 [[TMP5]])
+; IR-ITERATIVE-NEXT:    [[TMP7:%.*]] = icmp eq i32 [[TMP6]], 0
+; IR-ITERATIVE-NEXT:    br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP10:%.*]]
+; IR-ITERATIVE:       8:
+; IR-ITERATIVE-NEXT:    [[TMP9:%.*]] = atomicrmw fmin ptr addrspace(1) [[PTR:%.*]], float 4.000000e+00 seq_cst, align 4
+; IR-ITERATIVE-NEXT:    br label [[TMP10]]
+; IR-ITERATIVE:       10:
+; IR-ITERATIVE-NEXT:    ret void
+;
+; IR-DPP-LABEL: @global_atomic_fmin_uni_value(
+; IR-DPP-NEXT:    [[TMP1:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)
+; IR-DPP-NEXT:    [[TMP2:%.*]] = bitcast i64 [[TMP1]] to <2 x i32>
+; IR-DPP-NEXT:    [[TMP3:%.*]] = extractelement <2 x i32> [[TMP2]], i32 0
+; IR-DPP-NEXT:    [[TMP4:%.*]] = extractelement <2 x i32> [[TMP2]], i32 1
+; IR-DPP-NEXT:    [[TMP5:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP3]], i32 0)
+; IR-DPP-NEXT:    [[TMP6:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP4]], i32 [[TMP5]])
+; IR-DPP-NEXT:    [[TMP7:%.*]] = icmp eq i32 [[TMP6]], 0
+; IR-DPP-NEXT:    br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP10:%.*]]
+; IR-DPP:       8:
+; IR-DPP-NEXT:    [[TMP9:%.*]] = atomicrmw fmin ptr addrspace(1) [[PTR:%.*]], float 4.000000e+00 seq_cst, align 4
+; IR-DPP-NEXT:    br label [[TMP10]]
+; IR-DPP:       10:
+; IR-DPP-NEXT:    ret void
+;
+  %result = atomicrmw fmin ptr addrspace(1) %ptr, float 4.0 seq_cst
+  ret void
+}
+
+define amdgpu_kernel void @global_atomic_fmin_div_value(ptr addrspace(1) %ptr) #0 {
+; IR-ITERATIVE-LABEL: @global_atomic_fmin_div_value(
+; IR-ITERATIVE-NEXT:    [[ID_X:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
+; IR-ITERATIVE-NEXT:    [[DIVVALUE:%.*]] = bitcast i32 [[ID_X]] to float
+; IR-ITERATIVE-NEXT:    [[TMP1:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)
+; IR-ITERATIVE-NEXT:    [[TMP2:%.*]] = bitcast i64 [[TMP1]] to <2 x i32>
+; IR-ITERATIVE-NEXT:    [[TMP3:%.*]] = extractelement <2 x i32> [[TMP2]], i32 0
+; IR-ITERATIVE-NEXT:    [[TMP4:%.*]] = extractelement <2 x i32> [[TMP2]], i32 1
+; IR-ITERATIVE-NEXT:    [[TMP5:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP3]], i32 0)
+; IR-ITERATIVE-NEXT:    [[TMP6:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP4]], i32 [[TMP5]])
+; IR-ITERATIVE-NEXT:    [[TMP7:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)
+; IR-ITERATIVE-NEXT:    br label [[COMPUTELOOP:%.*]]
+; IR-ITERATIVE:       8:
+; IR-ITERATIVE-NEXT:    [[TMP9:%.*]] = atomicrmw fmin ptr addrspace(1) [[PTR:%.*]], float [[TMP17:%.*]] seq_cst, align 4
+; IR-ITERATIVE-NEXT:    br label [[TMP10:%.*]]
+; IR-ITERATIVE:       10:
+; IR-ITERATIVE-NEXT:    ret void
+; IR-ITERATIVE:       ComputeLoop:
+; IR-ITERATIVE-NEXT:    [[ACCUMULATOR:%.*]] = phi float [ 0x7FF0000000000000, [[TMP0:%.*]] ], [ [[TMP17]], [[COMPUTELOOP]] ]
+; IR-ITERATIVE-NEXT:    [[ACTIVEBITS:%.*]] = phi i64 [ [[TMP7]], [[TMP0]] ], [ [[TMP20:%.*]], [[COMPUTELOOP]] ]
+; IR-ITERATIVE-NEXT:    [[TMP11:%.*]] = call i64 @llvm.cttz.i64(i64 [[ACTIVEBITS]], i1 true)
+; IR-ITERATIVE-NEXT:    [[TMP12:%.*]] = trunc i64 [[TMP11]] to i32
+; IR-ITERATIVE-NEXT:    [[TMP13:%.*]] = bitcast float [[DIVVALUE]] to i32
+; IR-ITERATIVE-NEXT:    [[TMP14:%.*]] = call i32 @llvm.amdgcn.readlane(i32 [[TMP13]], i32 [[TMP12]])
+; IR-ITERATIVE-NEXT:    [[TMP15:%.*]] = bitcast i32 [[TMP14]] to float
+; IR-ITERATIVE-NEXT:    [[TMP16:%.*]] = fcmp ult float [[ACCUMULATOR]], [[TMP15]]
+; IR-ITERATIVE-NEXT:    [[TMP17]] = select i1 [[TMP16]], float [[ACCUMULATOR]], float [[TMP15]]
+; IR-ITERATIVE-NEXT:    [[TMP18:%.*]] = shl i64 1, [[TMP11]]
+; IR-ITERATIVE-NEXT:    [[TMP19:%.*]] = xor i64 [[TMP18]], -1
+; IR-ITERATIVE-NEXT:    [[TMP20]] = and i64 [[ACTIVEBITS]], [[TMP19]]
+; IR-ITERATIVE-NEXT:    [[TMP21:%.*]] = icmp eq i64 [[TMP20]], 0
+; IR-ITERATIVE-NEXT:    br i1 [[TMP21]], label [[COMPUTEEND:%.*]], label [[COMPUTELOOP]]
+; IR-ITERATIVE:       ComputeEnd:
+; IR-ITERATIVE-NEXT:    [[TMP22:%.*]] = icmp eq i32 [[TMP6]], 0
+; IR-ITERATIVE-NEXT:    br i1 [[TMP22]], label [[TMP8:%.*]], label [[TMP10]]
+;
+; IR-DPP-LABEL: @global_atomic_fmin_div_value(
+; IR-DPP-NEXT:    [[ID_X:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
+; IR-DPP-NEXT:    [[DIVVALUE:%.*]] = bitcast i32 [[ID_X]] to float
+; IR-DPP-NEXT:    [[TMP1:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)
+; IR-DPP-NEXT:    [[TMP2:%.*]] = bitcast i64 [[TMP1]] to <2 x i32>
+; IR-DPP-NEXT:    [[TMP3:%.*]] = extractelement <2 x i32> [[TMP2]], i32 0
+; IR-DPP-NEXT:    [[TMP4:%.*]] = extractelement <2 x i32> [[TMP2]], i32 1
+; IR-DPP-NEXT:    [[TMP5:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP3]], i32 0)
+; IR-DPP-NEXT:    [[TMP6:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP4]], i32 [[TMP5]])
+; IR-DPP-NEXT:    [[TMP7:%.*]] = bitcast float [[DIVVALUE]] to i32
+; IR-DPP-NEXT:    [[TMP8:%.*]] = call i32 @llvm.amdgcn.set.inactive.i32(i32 [[TMP7]], i32 2139095040)
+; IR-DPP-NEXT:    [[TMP9:%.*]] = bitcast i32 [[TMP8]] to float
+; IR-DPP-NEXT:    [[TMP10:%.*]] = bitcast i32 [[TMP7]] to float
+; IR-DPP-NEXT:    [[TMP11:%.*]] = bitcast float [[TMP9]] to i32
+; IR-DPP-NEXT:    [[TMP12:%.*]] = call i32 @llvm.amdgcn.update.dpp.i32(i32 2139095040, i32 [[TMP11]], i32 273, i32 15, i32 15, i1 false)
+; IR-DPP-NEXT:    [[TMP13:%.*]] = bitcast i32 [[TMP12]] to float
+; IR-DPP-NEXT:    [[TMP14:%.*]] = bitcast i32 [[TMP11]] to float
+; IR-DPP-NEXT:    [[TMP15:%.*]] = fcmp ult float [[TMP14]], [[TMP13]]
+; IR-DPP-NEXT:    [[TMP16:%.*]] = select i1 [[TMP15]], float [[TMP14]], float [[TMP13]]
+; IR-DPP-NEXT:    [[TMP17:%.*]] = bitcast float [[TMP16]] to i32
+; IR-DPP-NEXT:    [[TMP18:%.*]] = call i32 @llvm.amdgcn.update.dpp.i32(i32 2139095040, i32 [[TMP17]], i32 274, i32 15, i32 15, i1 false)
+; IR-DPP-NEXT:    [[TMP19:%.*]] = bitcast i32 [[TMP18]] to float
+; IR-DPP-NEXT:    [[TMP20:%.*]] = bitcast i32 [[TMP17]] to float
+; IR-DPP-NEXT:    [[TMP21:%.*]] = fcmp ult float [[TMP20]], [[TMP19]]
+; IR-DPP-NEXT:    [[TMP22:%.*]] = select i1 [[TMP21]], float [[TMP20]], float [[TMP19]]
+; IR-DPP-NEXT:    [[TMP23:%.*]] = bitcast float [[TMP22]] to i32
+; IR-DPP-NEXT:    [[TMP24:%.*]] = call i32 @llvm.amdgcn.update.dpp.i32(i32 2139095040, i32 [[TMP23]], i32 276, i32 15, i32 15, i1 false)
+; IR-DPP-NEXT:    [[TMP25:%.*]] = bitcast i32 [[TMP24]] to float
+; IR-DPP-NEXT:    [[TMP26:%.*]] = bitcast i32 [[TMP23]] to float
+; IR-DPP-NEXT:    [[TMP27:%.*]] = fcmp ult float [[TMP26]], [[TMP25]]
+; IR-DPP-NEXT:    [[TMP28:%.*]] = select i1 [[TMP27]], float [[TMP26]], float [[TMP25]]
+; IR-DPP-NEXT:    [[TMP29:%.*]] = bitcast float [[TMP28]] to i32
+; IR-DPP-NEXT:    [[TMP30:%.*]] = call i32 @llvm.amdgcn.update.dpp.i32(i32 2139095040, i32 [[TMP29]], i32 280, i32 15, i32 15, i1 false)
+; IR-DPP-NEXT:    [[TMP31:%.*]] = bitcast i32 [[TMP30]] to float
+; IR-DPP-NEXT:    [[TMP32:%.*]] = bitcast i32 [[TMP29]] to float
+; IR-DPP-NEXT:    [[TMP33:%.*]] = fcmp ult float [[TMP32]], [[TMP31]]
+; IR-DPP-NEXT:    [[TMP34:%.*]] = select i1 [[TMP33]], float [[TMP32]], float [[TMP31]]
+; IR-DPP-NEXT:    [[TMP35:%.*]] = bitcast float [[TMP34]] to i32
+; IR-DPP-NEXT:    [[TMP36:%.*]] = call i32 @llvm.amdgcn.update.dpp.i32(i32 2139095040, i32 [[TMP35]], i32 322, i32 10, i32 15, i1 false)
+; IR-DPP-NEXT:    [[TMP37:%.*]] = bitcast i32 [[TMP36]] to float
+; IR-DPP-NEXT:    [[TMP38:%.*]] = bitcast i32 [[TMP35]] to float
+; IR-DPP-NEXT:    [[TMP39:%.*]] = fcmp ult float [[TMP38]], [[TMP37]]
+; IR-DPP-NEXT:    [[TMP40:%.*]] = select i1 [[TMP39]], float [[TMP38]], float [[TMP37]]
+; IR-DPP-NEXT:    [[TMP41:%.*]] = bitcast float [[TMP40]] to i32
+; IR-DPP-NEXT:    [[TMP42:%.*]] = call i32 @llvm.amdgcn.update.dpp.i32(i32 2139095040, i32 [[TMP41]], i32 323, i32 12, i32 15, i1 false)
+; IR-DPP-NEXT:    [[TMP43:%.*]] = bitcast i32 [[TMP42]] to float
+; IR-DPP-NEXT:    [[TMP44:%.*]] = bitcast i32 [[TMP41]] to float
+; IR-DPP-NEXT:    [[TMP45:%.*]] = fcmp ult float [[TMP44]], [[TMP43]]
+; IR-DPP-NEXT:    [[TMP46:%.*]] = select i1 [[TMP45]], float [[TMP44]], float [[TMP43]]
+; IR-DPP-NEXT:    [[TMP47:%.*]] = bitcast float [[TMP46]] to i32
+; IR-DPP-NEXT:    [[TMP48:%.*]] = call i32 @llvm.amdgcn.readlane(i32 [[TMP47]], i32 63)
+; IR-DPP-NEXT:    [[TMP49:%.*]] = bitcast i32 [[TMP48]] to float
+; IR-DPP-NEXT:    [[TMP50:%.*]] = call float @llvm.amdgcn.strict.wwm.f32(float [[TMP49]])
+; IR-DPP-NEXT:    [[TMP51:%.*]] = icmp eq i32 [[TMP6]], 0
+; IR-DPP-NEXT:    br i1 [[TMP51]], label [[TMP52:%.*]], label [[TMP54:%.*]]
+; IR-DPP:       52:
+; IR-DPP-NEXT:    [[TMP53:%.*]] = atomicrmw fmin ptr addrspace(1) [[PTR:%.*]], float [[TMP50]] seq_cst, align 4
+; IR-DPP-NEXT:    br label [[TMP54]]
+; IR-DPP:       54:
+; IR-DPP-NEXT:    ret void
+;
+  %id.x = call i32 @llvm.amdgcn.workitem.id.x()
+  %divValue = bitcast i32 %id.x to float
+  %result = atomicrmw fmin ptr addrspace(1) %ptr, float %divValue seq_cst
+  ret void
+}
+
+define amdgpu_kernel void @global_atomic_fmax_uni_value(ptr addrspace(1) %ptr) #0 {
+; IR-ITERATIVE-LABEL: @global_atomic_fmax_uni_value(
+; IR-ITERATIVE-NEXT:    [[TMP1:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)
+; IR-ITERATIVE-NEXT:    [[TMP2:%.*]] = bitcast i64 [[TMP1]] to <2 x i32>
+; IR-ITERATIVE-NEXT:    [[TMP3:%.*]] = extractelement <2 x i32> [[TMP2]], i32 0
+; IR-ITERATIVE-NEXT:    [[TMP4:%.*]] = extractelement <2 x i32> [[TMP2]], i32 1
+; IR-ITERATIVE-NEXT:    [[TMP5:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP3]], i32 0)
+; IR-ITERATIVE-NEXT:    [[TMP6:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP4]], i32 [[TMP5]])
+; IR-ITERATIVE-NEXT:    [[TMP7:%.*]] = icmp eq i32 [[TMP6]], 0
+; IR-ITERATIVE-NEXT:    br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP10:%.*]]
+; IR-ITERATIVE:       8:
+; IR-ITERATIVE-NEXT:    [[TMP9:%.*]] = atomicrmw fmax ptr addrspace(1) [[PTR:%.*]], float 4.000000e+00 seq_cst, align 4
+; IR-ITERATIVE-NEXT:    br label [[TMP10]]
+; IR-ITERATIVE:       10:
+; IR-ITERATIVE-NEXT:    ret void
+;
+; IR-DPP-LABEL: @global_atomic_fmax_uni_value(
+; IR-DPP-NEXT:    [[TMP1:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)
+; IR-DPP-NEXT:    [[TMP2:%.*]] = bitcast i64 [[TMP1]] to <2 x i32>
+; IR-DPP-NEXT:    [[TMP3:%.*]] = extractelement <2 x i32> [[TMP2]], i32 0
+; IR-DPP-NEXT:    [[TMP4:%.*]] = extractelement <2 x i32> [[TMP2]], i32 1
+; IR-DPP-NEXT:    [[TMP5:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP3]], i32 0)
+; IR-DPP-NEXT:    [[TMP6:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP4]], i32 [[TMP5]])
+; IR-DPP-NEXT:    [[TMP7:%.*]] = icmp eq i32 [[TMP6]], 0
+; IR-DPP-NEXT:    br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP10:%.*]]
+; IR-DPP:       8:
+; IR-DPP-NEXT:    [[TMP9:%.*]] = atomicrmw fmax ptr addrspace(1) [[PTR:%.*]], float 4.000000e+00 seq_cst, align 4
+; IR-DPP-NEXT:    br label [[TMP10]]
+; IR-DPP:       10:
+; IR-DPP-NEXT:    ret void
+;
+  %result = atomicrmw fmax ptr addrspace(1) %ptr, float 4.0 seq_cst
+  ret void
+}
+
+define amdgpu_kernel void @global_atomic_fmax_div_value(ptr addrspace(1) %ptr) #0 {
+; IR-ITERATIVE-LABEL: @global_atomic_fmax_div_value(
+; IR-ITERATIVE-NEXT:    [[ID_X:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
+; IR-ITERATIVE-NEXT:    [[DIVVALUE:%.*]] = bitcast i32 [[ID_X]] to float
+; IR-ITERATIVE-NEXT:    [[TMP1:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)
+; IR-ITERATIVE-NEXT:    [[TMP2:%.*]] = bitcast i64 [[TMP1]] to <2 x i32>
+; IR-ITERATIVE-NEXT:    [[TMP3:%.*]] = extractelement <2 x i32> [[TMP2]], i32 0
+; IR-ITERATIVE-NEXT:    [[TMP4:%.*]] = extractelement <2 x i32> [[TMP2]], i32 1
+; IR-ITERATIVE-NEXT:    [[TMP5:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP3]], i32 0)
+; IR-ITERATIVE-NEXT:    [[TMP6:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP4]], i32 [[TMP5]])
+; IR-ITERATIVE-NEXT:    [[TMP7:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)
+; IR-ITERATIVE-NEXT:    br label [[COMPUTELOOP:%.*]]
+; IR-ITERATIVE:       8:
+; IR-ITERATIVE-NEXT:    [[TMP9:%.*]] = atomicrmw fmax ptr addrspace(1) [[PTR:%.*]], float [[TMP17:%.*]] seq_cst, align 4
+; IR-ITERATIVE-NEXT:    br label [[TMP10:%.*]]
+; IR-ITERATIVE:       10:
+; IR-ITERATIVE-NEXT:    ret void
+; IR-ITERATIVE:       ComputeLoop:
+; IR-ITERATIVE-NEXT:    [[ACCUMULATOR:%.*]] = phi float [ 0xFFF0000000000000, [[TMP0:%.*]] ], [ [[TMP17]], [[COMPUTELOOP]] ]
+; IR-ITERATIVE-NEXT:    [[ACTIVEBITS:%.*]] = phi i64 [ [[TMP7]], [[TMP0]] ], [ [[TMP20:%.*]], [[COMPUTELOOP]] ]
+; IR-ITERATIVE-NEXT:    [[TMP11:%.*]] = call i64 @llvm.cttz.i64(i64 [[ACTIVEBITS]], i1 true)
+; IR-ITERATIVE-NEXT:    [[TMP12:%.*]] = trunc i64 [[TMP11]] to i32
+; IR-ITERATIVE-NEXT:    [[TMP13:%.*]] = bitcast float [[DIVVALUE]] to i32
+; IR-ITERATIVE-NEXT:    [[TMP14:%.*]] = call i32 @llvm.amdgcn.readlane(i32 [[TMP13]], i32 [[TMP12]])
+; IR-ITERATIVE-NEXT:    [[TMP15:%.*]] = bitcast i32 [[TMP14]] to float
+; IR-ITERATIVE-NEXT:    [[TMP16:%.*]] = fcmp ugt float [[ACCUMULATOR]], [[TMP15]]
+; IR-ITERATIVE-NEXT:    [[TMP17]] = select i1 [[TMP16]], float [[ACCUMULATOR]], float [[TMP15]]
+; IR-ITERATIVE-NEXT:    [[TMP18:%.*]] = shl i64 1, [[TMP11]]
+; IR-ITERATIVE-NEXT:    [[TMP19:%.*]] = xor i64 [[TMP18]], -1
+; IR-ITERATIVE-NEXT:    [[TMP20]] = and i64 [[ACTIVEBITS]], [[TMP19]]
+; IR-ITERATIVE-NEXT:    [[TMP21:%.*]] = icmp eq i64 [[TMP20]], 0
+; IR-ITERATIVE-NEXT:    br i1 [[TMP21]], label [[COMPUTEEND:%.*]], label [[COMPUTELOOP]]
+; IR-ITERATIVE:       ComputeEnd:
+; IR-ITERATIVE-NEXT:    [[TMP22:%.*]] = icmp eq i32 [[TMP6]], 0
+; IR-ITERATIVE-NEXT:    br i1 [[TMP22]], label [[TMP8:%.*]], label [[TMP10]]
+;
+; IR-DPP-LABEL: @global_atomic_fmax_div_value(
+; IR-DPP-NEXT:    [[ID_X:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
+; IR-DPP-NEXT:    [[DIVVALUE:%.*]] = bitcast i32 [[ID_X]] to float
+; IR-DPP-NEXT:    [[TMP1:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)
+; IR-DPP-NEXT:    [[TMP2:%.*]] = bitcast i64 [[TMP1]] to <2 x i32>
+; IR-DPP-NEXT:    [[TMP3:%.*]] = extractelement <2 x i32> [[TMP2]], i32 0
+; IR-DPP-NEXT:    [[TMP4:%.*]] = extractelement <2 x i32> [[TMP2]], i32 1
+; IR-DPP-NEXT:    [[TMP5:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP3]], i32 0)
+; IR-DPP-NEXT:    [[TMP6:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP4]], i32 [[TMP5]])
+; IR-DPP-NEXT:    [[TMP7:%.*]] = bitcast float [[DIVVALUE]] to i32
+; IR-DPP-NEXT:    [[TMP8:%.*]] = call i32 @llvm.amdgcn.set.inactive.i32(i32 [[TMP7]], i32 -8388608)
+; IR-DPP-NEXT:    [[TMP9:%.*]] = bitcast i32 [[TMP8]] to float
+; IR-DPP-NEXT:    [[TMP10:%.*]] = bitcast i32 [[TMP7]] to float
+; IR-DPP-NEXT:    [[TMP11:%.*]] = bitcast float [[TMP9]] to i32
+; IR-DPP-NEXT:    [[TMP12:%.*]] = call i32 @llvm.amdgcn.update.dpp.i32(i32 -8388608, i32 [[TMP11]], i32 273, i32 15, i32 15, i1 false)
+; IR-DPP-NEXT:    [[TMP13:%.*]] = bitcast i32 [[TMP12]] to float
+; IR-DPP-NEXT:    [[TMP14:%.*]] = bitcast i32 [[TMP11]] to float
+; IR-DPP-NEXT:    [[TMP15:%.*]] = fcmp ugt float [[TMP14]], [[TMP13]]
+; IR-DPP-NEXT:    [[TMP16:%.*]] = select i1 [[TMP15]], float [[TMP14]], float [[TMP13]]
+; IR-DPP-NEXT:    [[TMP17:%.*]] = bitcast float [[TMP16]] to i32
+; IR-DPP-NEXT:    [[TMP18:%.*]] = call i32 @llvm.amdgcn.update.dpp.i32(i32 -8388608, i32 [[TMP17]], i32 274, i32 15, i32 15, i1 false)
+; IR-DPP-NEXT:    [[TMP19:%.*]] = bitcast i32 [[TMP18]] to float
+; IR-DPP-NEXT:    [[TMP20:%.*]] = bitcast i32 [[TMP17]] to float
+; IR-DPP-NEXT:    [[TMP21:%.*]] = fcmp ugt float [[TMP20]], [[TMP19]]
+; IR-DPP-NEXT:    [[TMP22:%.*]] = select i1 [[TMP21]], float [[TMP20]], float [[TMP19]]
+; IR-DPP-NEXT:    [[TMP23:%.*]] = bitcast float [[TMP22]] to i32
+; IR-DPP-NEXT:    [[TMP24:%.*]] = call i32 @llvm.amdgcn.update.dpp.i32(i32 -8388608, i32 [[TMP23]], i32 276, i32 15, i32 15, i1 false)
+; IR-DPP-NEXT:    [[TMP25:%.*]] = bitcast i32 [[TMP24]] to float
+; IR-DPP-NEXT:    [[TMP26:%.*]] = bitcast i32 [[TMP23]] to float
+; IR-DPP-NEXT:    [[TMP27:%.*]] = fcmp ugt float [[TMP26]], [[TMP25]]
+; IR-DPP-NEXT:    [[TMP28:%.*]] = select i1 [[TMP27]], float [[TMP26]], float [[TMP25]]
+; IR-DPP-NEXT:    [[TMP29:%.*]] = bitcast float [[TMP28]] to i32
+; IR-DPP-NEXT:    [[TMP30:%.*]] = call i32 @llvm.amdgcn.update.dpp.i32(i32 -8388608, i32 [[TMP29]], i32 280, i32 15, i32 15, i1 false)
+; IR-DPP-NEXT:    [[TMP31:%.*]] = bitcast i32 [[TMP30]] to float
+; IR-DPP-NEXT:    [[TMP32:%.*]] = bitcast i32 [[TMP29]] to float
+; IR-DPP-NEXT:    [[TMP33:%.*]] = fcmp ugt float [[TMP32]], [[TMP31]]
+; IR-DPP-NEXT:    [[TMP34:%.*]] = select i1 [[TMP33]], float [[TMP32]], float [[TMP31]]
+; IR-DPP-NEXT:    [[TMP35:%.*]] = bitcast float [[TMP34]] to i32
+; IR-DPP-NEXT:    [[TMP36:%.*]] = call i32 @llvm.amdgcn.update.dpp.i32(i32 -8388608, i32 [[TMP35]], i32 322, i32 10, i32 15, i1 false)
+; IR-DPP-NEXT:    [[TMP37:%.*]] = bitcast i32 [[TMP36]] to float
+; IR-DPP-NEXT:    [[TMP38:%.*]] = bitcast i32 [[TMP35]] to float
+; IR-DPP-NEXT:    [[TMP39:%.*]] = fcmp ugt float [[TMP38]], [[TMP37]]
+; IR-DPP-NEXT:    [[TMP40:%.*]] = select i1 [[TMP39]], float [[TMP38]], float [[TMP37]]
+; IR-DPP-NEXT:    [[TMP41:%.*]] = bitcast float [[TMP40]] to i32
+; IR-DPP-NEXT:    [[TMP42:%.*]] = call i32 @llvm.amdgcn.update.dpp.i32(i32 -8388608, i32 [[TMP41]], i32 323, i32 12, i32 15, i1 false)
+; IR-DPP-NEXT:    [[TMP43:%.*]] = bitcast i32 [[TMP42]] to float
+; IR-DPP-NEXT:    [[TMP44:%.*]] = bitcast i32 [[TMP41]] to float
+; IR-DPP-NEXT:    [[TMP45:%.*]] = fcmp ugt float [[TMP44]], [[TMP43]]
+; IR-DPP-NEXT:    [[TMP46:%.*]] = select i1 [[TMP45]], float [[TMP44]], float [[TMP43]]
+; IR-DPP-NEXT:    [[TMP47:%.*]] = bitcast float [[TMP46]] to i32
+; IR-DPP-NEXT:    [[TMP48:%.*]] = call i32 @llvm.amdgcn.readlane(i32 [[TMP47]], i32 63)
+; IR-DPP-NEXT:    [[TMP49:%.*]] = bitcast i32 [[TMP48]] to float
+; IR-DPP-NEXT:    [[TMP50:%.*]] = call float @llvm.amdgcn.strict.wwm.f32(float [[TMP49]])
+; IR-DPP-NEXT:    [[TMP51:%.*]] = icmp eq i32 [[TMP6]], 0
+; IR-DPP-NEXT:    br i1 [[TMP51]], label [[TMP52:%.*]], label [[TMP54:%.*]]
+; IR-DPP:       52:
+; IR-DPP-NEXT:    [[TMP53:%.*]] = atomicrmw fmax ptr addrspace(1) [[PTR:%.*]], float [[TMP50]] seq_cst, align 4
+; IR-DPP-NEXT:    br label [[TMP54]]
+; IR-DPP:       54:
+; IR-DPP-NEXT:    ret void
+;
+  %id.x = call i32 @llvm.amdgcn.workitem.id.x()
+  %divValue = bitcast i32 %id.x to float
+  %result = atomicrmw fmax ptr addrspace(1) %ptr, float %divValue seq_cst
+  ret void
+}
+
 attributes #0 = {"target-cpu"="gfx906"}