Index: llvm/lib/Target/Sparc/SparcInstrInfo.td
===================================================================
--- llvm/lib/Target/Sparc/SparcInstrInfo.td
+++ llvm/lib/Target/Sparc/SparcInstrInfo.td
@@ -1769,6 +1769,15 @@
   def RDPR : F3_1<2, 0b101010,
                  (outs IntRegs:$rd), (ins PRRegs:$rs1),
                  "rdpr $rs1, $rd", []>;
+
+// Special case %fq as the register is also used in V8
+// (albeit with different instructions and encoding).
+// This allows us to reuse the register definition and
+// the "%fq" designation while giving it a different encoding.
+let Uses = [FQ], rs1 = 15, rs2 = 0 in
+  def RDFQ : F3_1<2, 0b101010,
+                 (outs IntRegs:$rd), (ins),
+                 "rdpr %fq, $rd", []>;
 }
 
 // Section A.62 - Write Privileged Register Instructions
Index: llvm/test/MC/Disassembler/Sparc/sparc-v9.txt
===================================================================
--- llvm/test/MC/Disassembler/Sparc/sparc-v9.txt
+++ llvm/test/MC/Disassembler/Sparc/sparc-v9.txt
@@ -149,3 +149,6 @@
 
 # CHECK: restored
 0x83,0x88,0x00,0x00
+
+# CHECK: rdpr %fq, %i5
+0xbb,0x53,0xc0,0x00
Index: llvm/test/MC/Sparc/sparcv9-instructions.s
===================================================================
--- llvm/test/MC/Sparc/sparcv9-instructions.s
+++ llvm/test/MC/Sparc/sparcv9-instructions.s
@@ -416,6 +416,10 @@
         ! V9: rdpr %wstate, %i5         ! encoding: [0xbb,0x53,0x80,0x00]
         rdpr %wstate,%i5
 
+        ! V8:      error: instruction requires a CPU feature not currently enabled
+        ! V8-NEXT: rdpr %fq,%i5
+        ! V9: rdpr %fq, %i5             ! encoding: [0xbb,0x53,0xc0,0x00]
+        rdpr %fq,%i5
         ! V8:      error: instruction requires a CPU feature not currently enabled
         ! V8-NEXT: rdpr %ver,%i5
         ! V9: rdpr %ver, %i5            ! encoding: [0xbb,0x57,0xc0,0x00]