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AVX512BW: Enable packed word shift for 512bit vector.
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Authored by igorb on Dec 22 2015, 5:13 AM.

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Summary

AVX512BW: Enable packed word shift for 512bit vector. Enable lowering scalar immidiate shift v64i8 .
Fix predicate for AVX1/2 shifts. Lowering variable shift v32i8 / v16i8 with AVX512BW and VLX will be implement in different patch.

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igorb updated this revision to Diff 43441.Dec 22 2015, 5:13 AM
igorb retitled this revision from to AVX512BW: Enable packed word shift for 512bit vector. .
igorb updated this object.
igorb added reviewers: delena, AsafBadouh.
igorb set the repository for this revision to rL LLVM.
igorb added a subscriber: llvm-commits.
delena added inline comments.Dec 22 2015, 5:29 AM
lib/Target/X86/X86ISelLowering.cpp
18301 ↗(On Diff #43446)

you can add a pattern to .td file for extending 256 and 128 to 512 and you'll not need the VLX checks

18366 ↗(On Diff #43446)

64i8 is legal on bwi only.

igorb updated this revision to Diff 43446.Dec 22 2015, 7:58 AM
igorb marked 2 inline comments as done.

Thanks for review.

delena added inline comments.Dec 22 2015, 12:04 PM
lib/Target/X86/X86ISelLowering.cpp
18301 ↗(On Diff #43446)

Now it should be hasAVX512() right?

delena accepted this revision.Dec 22 2015, 11:29 PM
delena edited edge metadata.

LGTM

This revision is now accepted and ready to land.Dec 22 2015, 11:29 PM
This revision was automatically updated to reflect the committed changes.