diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp --- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp @@ -876,6 +876,10 @@ switch (VT.SimpleTy) { default: llvm_unreachable("Unexpected size"); + case MVT::bf16: + assert(Subtarget->hasStdExtZfbfmin()); + Opc = RISCV::FMV_H_X; + break; case MVT::f16: Opc = Subtarget->hasStdExtZhinxOrZhinxmin() ? RISCV::COPY : RISCV::FMV_H_X; diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -1899,6 +1899,8 @@ IsLegalVT = Subtarget.hasStdExtFOrZfinx(); else if (VT == MVT::f64) IsLegalVT = Subtarget.hasStdExtDOrZdinx(); + else if (VT == MVT::bf16) + IsLegalVT = Subtarget.hasStdExtZfbfmin(); if (!IsLegalVT) return false; diff --git a/llvm/test/CodeGen/RISCV/bfloat-imm.ll b/llvm/test/CodeGen/RISCV/bfloat-imm.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/bfloat-imm.ll @@ -0,0 +1,31 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfbfmin -verify-machineinstrs \ +; RUN: -target-abi ilp32f < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfbfmin -verify-machineinstrs \ +; RUN: -target-abi lp64f < %s | FileCheck %s + +define bfloat @bfloat_imm() nounwind { +; CHECK-LABEL: bfloat_imm: +; CHECK: # %bb.0: +; CHECK-NEXT: lui a0, %hi(.LCPI0_0) +; CHECK-NEXT: flh fa0, %lo(.LCPI0_0)(a0) +; CHECK-NEXT: ret + ret bfloat 3.0 +} + +define bfloat @bfloat_zero() nounwind { +; CHECK-LABEL: bfloat_zero: +; CHECK: # %bb.0: +; CHECK-NEXT: fmv.h.x fa0, zero +; CHECK-NEXT: ret + ret bfloat 0.0 +} + +define bfloat @bfloat_negative_zero() nounwind { +; CHECK-LABEL: bfloat_negative_zero: +; CHECK: # %bb.0: +; CHECK-NEXT: lui a0, 1048568 +; CHECK-NEXT: fmv.h.x fa0, a0 +; CHECK-NEXT: ret + ret bfloat -0.0 +}