Index: llvm/lib/Analysis/InstructionSimplify.cpp
===================================================================
--- llvm/lib/Analysis/InstructionSimplify.cpp
+++ llvm/lib/Analysis/InstructionSimplify.cpp
@@ -2121,7 +2121,7 @@
   Value *Shift;
   if (match(Op1, m_Power2(PowerC)) &&
       match(Op0, m_Add(m_Value(Shift), m_AllOnes())) &&
-      isKnownToBeAPowerOfTwo(Shift, Q.DL, /*OrZero*/ true, 0, Q.AC, Q.CxtI,
+      isKnownToBeAPowerOfTwo(Shift, Q.DL, /*OrZero*/ false, 0, Q.AC, Q.CxtI,
                              Q.DT)) {
     KnownBits Known = computeKnownBits(Shift, Q.DL, 0, Q.AC, Q.CxtI, Q.DT);
     // Use getActiveBits() to make use of the additional power of two knowledge
Index: llvm/test/Transforms/InstCombine/rem-mul-shl.ll
===================================================================
--- llvm/test/Transforms/InstCombine/rem-mul-shl.ll
+++ llvm/test/Transforms/InstCombine/rem-mul-shl.ll
@@ -2,6 +2,7 @@
 ; RUN: opt < %s -passes=instcombine -S | FileCheck %s
 declare void @use8(i8)
 declare i64 @llvm.vscale.i64()
+declare i32 @llvm.vscale.i32()
 
 define i8 @srem_non_matching(i8 %X, i8 %Y) {
 ; CHECK-LABEL: @srem_non_matching(
@@ -913,3 +914,32 @@
   %rem = and i64 3072, %add
   ret i64 %rem
 }
+
+; Allow for INT_MIN, https://alive2.llvm.org/ce/z/yZ_I2a
+define i32 @and_add_shl_vscale_not_power2_negative() vscale_range(1,16) {
+; CHECK-LABEL: @and_add_shl_vscale_not_power2_negative(
+; CHECK-NEXT:    ret i32 0
+;
+  %vscale = call i32 @llvm.vscale.i32()
+  %shift = shl nuw nsw i32 %vscale, 6
+  %add = add i32 %shift, -1
+  %rem = and i32 -2147483648, %add
+  ret i32 %rem
+}
+
+; Negative test: the %sign may be 0, https://alive2.llvm.org/ce/z/WU_j4a
+define i32 @and_add_and (i32 %x) {
+; CHECK-LABEL: @and_add_and(
+; CHECK-NEXT:    [[X1:%.*]] = lshr i32 [[X:%.*]], 7
+; CHECK-NEXT:    [[SIGN:%.*]] = and i32 [[X1]], 1
+; CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[SIGN]], -1
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[ADD]], -2147483648
+; CHECK-NEXT:    ret i32 [[AND]]
+;
+  %x1 = lshr i32 %x, 7
+  %sign = and i32 %x1, 1  ; %sign = (%x >> 7) & 1
+  %add = add i32 %sign, -1
+  %and = and i32 %add, 2147483648
+  ret i32 %and
+}
+