diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -6071,6 +6071,10 @@
           ISD::OR, DL, VT, FalseV,
           DAG.getNode(RISCVISD::CZERO_EQZ, DL, VT, TrueV, CondV));
 
+    // Try some other optimizations before falling back to generic lowering.
+    if (SDValue V = combineSelectToBinOp(Op.getNode(), DAG, Subtarget))
+      return V;
+
     // (select c, t, f) -> (or (czero_eqz t, c), (czero_nez f, c))
     return DAG.getNode(ISD::OR, DL, VT,
                        DAG.getNode(RISCVISD::CZERO_EQZ, DL, VT, TrueV, CondV),
diff --git a/llvm/test/CodeGen/RISCV/select-binop-identity.ll b/llvm/test/CodeGen/RISCV/select-binop-identity.ll
--- a/llvm/test/CodeGen/RISCV/select-binop-identity.ll
+++ b/llvm/test/CodeGen/RISCV/select-binop-identity.ll
@@ -44,19 +44,15 @@
 ;
 ; VTCONDOPS64-LABEL: and_select_all_ones_i32:
 ; VTCONDOPS64:       # %bb.0:
-; VTCONDOPS64-NEXT:    li a3, -1
-; VTCONDOPS64-NEXT:    vt.maskcn a3, a3, a0
-; VTCONDOPS64-NEXT:    vt.maskc a0, a1, a0
-; VTCONDOPS64-NEXT:    or a0, a0, a3
+; VTCONDOPS64-NEXT:    addi a0, a0, -1
+; VTCONDOPS64-NEXT:    or a0, a0, a1
 ; VTCONDOPS64-NEXT:    and a0, a0, a2
 ; VTCONDOPS64-NEXT:    ret
 ;
 ; ZICOND-LABEL: and_select_all_ones_i32:
 ; ZICOND:       # %bb.0:
-; ZICOND-NEXT:    li a3, -1
-; ZICOND-NEXT:    czero.nez a3, a3, a0
-; ZICOND-NEXT:    czero.eqz a0, a1, a0
-; ZICOND-NEXT:    or a0, a0, a3
+; ZICOND-NEXT:    addi a0, a0, -1
+; ZICOND-NEXT:    or a0, a0, a1
 ; ZICOND-NEXT:    and a0, a0, a2
 ; ZICOND-NEXT:    ret
   %a = select i1 %c, i32 %x, i32 -1
@@ -92,30 +88,23 @@
 ;
 ; VTCONDOPS64-LABEL: and_select_all_ones_i64:
 ; VTCONDOPS64:       # %bb.0:
-; VTCONDOPS64-NEXT:    vt.maskcn a1, a1, a0
-; VTCONDOPS64-NEXT:    li a3, -1
-; VTCONDOPS64-NEXT:    vt.maskc a0, a3, a0
+; VTCONDOPS64-NEXT:    neg a0, a0
 ; VTCONDOPS64-NEXT:    or a0, a0, a1
 ; VTCONDOPS64-NEXT:    and a0, a2, a0
 ; VTCONDOPS64-NEXT:    ret
 ;
 ; ZICOND32-LABEL: and_select_all_ones_i64:
 ; ZICOND32:       # %bb.0:
-; ZICOND32-NEXT:    czero.nez a2, a2, a0
-; ZICOND32-NEXT:    li a5, -1
-; ZICOND32-NEXT:    czero.eqz a5, a5, a0
-; ZICOND32-NEXT:    or a2, a5, a2
-; ZICOND32-NEXT:    czero.nez a0, a1, a0
-; ZICOND32-NEXT:    or a0, a5, a0
+; ZICOND32-NEXT:    neg a0, a0
+; ZICOND32-NEXT:    or a2, a0, a2
+; ZICOND32-NEXT:    or a0, a0, a1
 ; ZICOND32-NEXT:    and a0, a3, a0
 ; ZICOND32-NEXT:    and a1, a4, a2
 ; ZICOND32-NEXT:    ret
 ;
 ; ZICOND64-LABEL: and_select_all_ones_i64:
 ; ZICOND64:       # %bb.0:
-; ZICOND64-NEXT:    czero.nez a1, a1, a0
-; ZICOND64-NEXT:    li a3, -1
-; ZICOND64-NEXT:    czero.eqz a0, a3, a0
+; ZICOND64-NEXT:    neg a0, a0
 ; ZICOND64-NEXT:    or a0, a0, a1
 ; ZICOND64-NEXT:    and a0, a2, a0
 ; ZICOND64-NEXT:    ret
diff --git a/llvm/test/CodeGen/RISCV/xaluo.ll b/llvm/test/CodeGen/RISCV/xaluo.ll
--- a/llvm/test/CodeGen/RISCV/xaluo.ll
+++ b/llvm/test/CodeGen/RISCV/xaluo.ll
@@ -5670,9 +5670,7 @@
 ; RV32ZICOND-NEXT:    sltu a0, a3, a0
 ; RV32ZICOND-NEXT:    add a4, a1, a0
 ; RV32ZICOND-NEXT:    sltu a1, a4, a1
-; RV32ZICOND-NEXT:    czero.eqz a1, a1, a0
-; RV32ZICOND-NEXT:    czero.nez a0, a0, a0
-; RV32ZICOND-NEXT:    or a0, a0, a1
+; RV32ZICOND-NEXT:    and a0, a0, a1
 ; RV32ZICOND-NEXT:    sw a3, 0(a2)
 ; RV32ZICOND-NEXT:    sw a4, 4(a2)
 ; RV32ZICOND-NEXT:    ret
@@ -5739,9 +5737,7 @@
 ; RV32ZICOND-NEXT:    sltu a0, a3, a0
 ; RV32ZICOND-NEXT:    add a4, a1, a0
 ; RV32ZICOND-NEXT:    sltu a1, a4, a1
-; RV32ZICOND-NEXT:    czero.eqz a1, a1, a0
-; RV32ZICOND-NEXT:    czero.nez a0, a0, a0
-; RV32ZICOND-NEXT:    or a0, a0, a1
+; RV32ZICOND-NEXT:    and a0, a0, a1
 ; RV32ZICOND-NEXT:    sw a3, 0(a2)
 ; RV32ZICOND-NEXT:    sw a4, 4(a2)
 ; RV32ZICOND-NEXT:    ret
@@ -5809,9 +5805,7 @@
 ; RV32ZICOND-NEXT:    sltu a0, a3, a0
 ; RV32ZICOND-NEXT:    add a4, a1, a0
 ; RV32ZICOND-NEXT:    sltu a1, a4, a1
-; RV32ZICOND-NEXT:    czero.eqz a1, a1, a0
-; RV32ZICOND-NEXT:    czero.nez a0, a0, a0
-; RV32ZICOND-NEXT:    or a0, a0, a1
+; RV32ZICOND-NEXT:    and a0, a0, a1
 ; RV32ZICOND-NEXT:    sw a3, 0(a2)
 ; RV32ZICOND-NEXT:    sw a4, 4(a2)
 ; RV32ZICOND-NEXT:    ret
@@ -5892,9 +5886,7 @@
 ; RV32ZICOND-NEXT:    sltu a3, a0, a1
 ; RV32ZICOND-NEXT:    add a1, a2, a3
 ; RV32ZICOND-NEXT:    sltu a2, a1, a2
-; RV32ZICOND-NEXT:    czero.eqz a2, a2, a3
-; RV32ZICOND-NEXT:    czero.nez a3, a3, a3
-; RV32ZICOND-NEXT:    or a2, a3, a2
+; RV32ZICOND-NEXT:    and a2, a3, a2
 ; RV32ZICOND-NEXT:    bnez a2, .LBB69_2
 ; RV32ZICOND-NEXT:  # %bb.1: # %IfOverflow
 ; RV32ZICOND-NEXT:    li a0, 0