diff --git a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp --- a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp +++ b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp @@ -6283,18 +6283,20 @@ } static bool ShouldUseSwitchConditionAsTableIndex( - ConstantInt &MinCaseVal, const ConstantInt &MaxCaseVal, + ConstantInt &BeginCaseVal, const ConstantInt &EndCaseVal, bool HasDefaultResults, const SmallDenseMap &ResultTypes, const DataLayout &DL, const TargetTransformInfo &TTI) { - if (MinCaseVal.isNullValue()) + if (BeginCaseVal.isNullValue()) return true; - if (MinCaseVal.isNegative() || - MaxCaseVal.getLimitedValue() == std::numeric_limits::max() || + if (BeginCaseVal.getValue().sge(EndCaseVal.getValue())) + return false; + if (BeginCaseVal.isNegative() || + EndCaseVal.getLimitedValue() == std::numeric_limits::max() || !HasDefaultResults) return false; return all_of(ResultTypes, [&](const auto &KV) { return SwitchLookupTable::WouldFitInRegister( - DL, MaxCaseVal.getLimitedValue() + 1 /* TableSize */, + DL, EndCaseVal.getLimitedValue() + 1 /* TableSize */, KV.second /* ResultType */); }); } @@ -6383,7 +6385,7 @@ /// If the switch is only used to initialize one or more phi nodes in a common /// successor block with different constant values, replace the switch with /// lookup tables. -static bool SwitchToLookupTable(SwitchInst *SI, IRBuilder<> &Builder, +static bool switchToLookupTable(SwitchInst *SI, IRBuilder<> &Builder, DomTreeUpdater *DTU, const DataLayout &DL, const TargetTransformInfo &TTI) { assert(SI->getNumCases() > 1 && "Degenerate switch?"); @@ -6411,9 +6413,6 @@ // Figure out the corresponding result for each case value and phi node in the // common destination, as well as the min and max case values. assert(!SI->cases().empty()); - SwitchInst::CaseIt CI = SI->case_begin(); - ConstantInt *MinCaseVal = CI->getCaseValue(); - ConstantInt *MaxCaseVal = CI->getCaseValue(); BasicBlock *CommonDest = nullptr; @@ -6424,17 +6423,60 @@ SmallDenseMap ResultTypes; SmallVector PHIs; - for (SwitchInst::CaseIt E = SI->case_end(); CI != E; ++CI) { - ConstantInt *CaseVal = CI->getCaseValue(); - if (CaseVal->getValue().slt(MinCaseVal->getValue())) - MinCaseVal = CaseVal; - if (CaseVal->getValue().sgt(MaxCaseVal->getValue())) - MaxCaseVal = CaseVal; + SmallVector CaseVals; + for (auto CI : SI->cases()) { + ConstantInt *CaseVal = CI.getCaseValue(); + CaseVals.push_back(CaseVal); + } + + // We want to find a range of indexes that will create the minimal table. + // We can treat all possible index values as a circle. For example, the i8 is + // [-128, -1] and [0, 127]. After that find the minimal range from this circle + // that can cover all exist values. First, create an incrementing sequence. + llvm::sort(CaseVals, [](const ConstantInt *A, const ConstantInt *B) { + return A->getValue().slt(B->getValue()); + }); + SmallVectorImpl::iterator CaseValIter = CaseVals.begin(); + // We start by using the begin and end as the minimal table. + ConstantInt *BeginCaseVal = *CaseValIter; + ConstantInt *EndCaseVal = *CaseVals.rbegin(); + bool RangeOverflow = false; + uint64_t MinTableSize = EndCaseVal->getValue() + .ssub_ov(BeginCaseVal->getValue(), RangeOverflow) + .getLimitedValue() + + 1; + // If there is no overflow, then this must be the minimal table. + if (RangeOverflow) { + auto MaxValue = APInt::getMaxValue(BeginCaseVal->getBitWidth()); + while (CaseValIter != CaseVals.end()) { + auto *CurrentCaseVal = *CaseValIter++; + if (CaseValIter == CaseVals.end()) { + break; + } + ConstantInt *NextCaseVal = *CaseValIter; + auto NextVal = NextCaseVal->getValue(); + auto CurVal = CurrentCaseVal->getValue(); + uint64_t RequireTableSize = + (MaxValue - (NextVal - CurVal) + 1).getLimitedValue() + 1; + // FIXME: When there is more than one minimal table, we can choose the + // best one. The current simple strategy may not be the best. + if (((RequireTableSize < MinTableSize) || + (RequireTableSize == MinTableSize && + NextCaseVal->getValue().isZero()))) { + BeginCaseVal = NextCaseVal; + EndCaseVal = CurrentCaseVal; + MinTableSize = RequireTableSize; + } + } + } + + for (const auto CI : SI->cases()) { + ConstantInt *CaseVal = CI.getCaseValue(); // Resulting value at phi nodes for this case value. using ResultsTy = SmallVector, 4>; ResultsTy Results; - if (!getCaseResults(SI, CaseVal, CI->getCaseSuccessor(), &CommonDest, + if (!getCaseResults(SI, CaseVal, CI.getCaseSuccessor(), &CommonDest, Results, DL, TTI)) return false; @@ -6469,13 +6511,12 @@ } bool UseSwitchConditionAsTableIndex = ShouldUseSwitchConditionAsTableIndex( - *MinCaseVal, *MaxCaseVal, HasDefaultResults, ResultTypes, DL, TTI); + *BeginCaseVal, *EndCaseVal, HasDefaultResults, ResultTypes, DL, TTI); uint64_t TableSize; if (UseSwitchConditionAsTableIndex) - TableSize = MaxCaseVal->getLimitedValue() + 1; + TableSize = EndCaseVal->getLimitedValue() + 1; else - TableSize = - (MaxCaseVal->getValue() - MinCaseVal->getValue()).getLimitedValue() + 1; + TableSize = MinTableSize; bool TableHasHoles = (NumResults < TableSize); bool NeedMask = (TableHasHoles && !HasDefaultResults); @@ -6494,7 +6535,7 @@ // Compute the maximum table size representable by the integer type we are // switching upon. - unsigned CaseSize = MinCaseVal->getType()->getPrimitiveSizeInBits(); + unsigned CaseSize = BeginCaseVal->getType()->getPrimitiveSizeInBits(); uint64_t MaxTableSize = CaseSize > 63 ? UINT64_MAX : 1ULL << CaseSize; assert(MaxTableSize >= TableSize && "It is impossible for a switch to have more entries than the max " @@ -6517,15 +6558,17 @@ Value *TableIndex; ConstantInt *TableIndexOffset; if (UseSwitchConditionAsTableIndex) { - TableIndexOffset = ConstantInt::get(MaxCaseVal->getType(), 0); + TableIndexOffset = ConstantInt::get(EndCaseVal->getType(), 0); TableIndex = SI->getCondition(); } else { - TableIndexOffset = MinCaseVal; + TableIndexOffset = BeginCaseVal; // If the default is unreachable, all case values are s>= MinCaseVal. Then // we can try to attach nsw. bool MayWrap = true; - if (!DefaultIsReachable) { - APInt Res = MaxCaseVal->getValue().ssub_ov(MinCaseVal->getValue(), MayWrap); + if (!DefaultIsReachable && + EndCaseVal->getValue().sge(BeginCaseVal->getValue())) { + APInt Res = + EndCaseVal->getValue().ssub_ov(BeginCaseVal->getValue(), MayWrap); (void)Res; } @@ -6544,7 +6587,7 @@ // PHI value for the default case in case we're using a bit mask. } else { Value *Cmp = Builder.CreateICmpULT( - TableIndex, ConstantInt::get(MinCaseVal->getType(), TableSize)); + TableIndex, ConstantInt::get(BeginCaseVal->getType(), TableSize)); RangeCheckBranch = Builder.CreateCondBr(Cmp, LookupBB, SI->getDefaultDest()); if (DTU) @@ -6788,7 +6831,7 @@ // CVP. Therefore, only apply this transformation during late stages of the // optimisation pipeline. if (Options.ConvertSwitchToLookupTable && - SwitchToLookupTable(SI, Builder, DTU, DL, TTI)) + switchToLookupTable(SI, Builder, DTU, DL, TTI)) return requestResimplify(); if (ReduceSwitchRange(SI, Builder, DL, TTI)) diff --git a/llvm/test/Transforms/SimplifyCFG/X86/CoveredLookupTable.ll b/llvm/test/Transforms/SimplifyCFG/X86/CoveredLookupTable.ll --- a/llvm/test/Transforms/SimplifyCFG/X86/CoveredLookupTable.ll +++ b/llvm/test/Transforms/SimplifyCFG/X86/CoveredLookupTable.ll @@ -9,12 +9,13 @@ define i3 @coveredswitch_test(i3 %input) { ; CHECK-LABEL: @coveredswitch_test( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = sub i3 [[INPUT:%.*]], -4 -; CHECK-NEXT: [[SWITCH_CAST:%.*]] = zext i3 [[SWITCH_TABLEIDX]] to i24 -; CHECK-NEXT: [[SWITCH_SHIFTAMT:%.*]] = mul nuw nsw i24 [[SWITCH_CAST]], 3 -; CHECK-NEXT: [[SWITCH_DOWNSHIFT:%.*]] = lshr i24 7507338, [[SWITCH_SHIFTAMT]] -; CHECK-NEXT: [[SWITCH_MASKED:%.*]] = trunc i24 [[SWITCH_DOWNSHIFT]] to i3 -; CHECK-NEXT: ret i3 [[SWITCH_MASKED]] +; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i3 [[INPUT:%.*]], -2 +; CHECK-NEXT: [[SWITCH_CAST:%.*]] = zext i3 [[INPUT]] to i18 +; CHECK-NEXT: [[SWITCH_SHIFTAMT:%.*]] = mul nuw nsw i18 [[SWITCH_CAST]], 3 +; CHECK-NEXT: [[SWITCH_DOWNSHIFT:%.*]] = lshr i18 42792, [[SWITCH_SHIFTAMT]] +; CHECK-NEXT: [[SWITCH_MASKED:%.*]] = trunc i18 [[SWITCH_DOWNSHIFT]] to i3 +; CHECK-NEXT: [[RESULT:%.*]] = select i1 [[TMP0]], i3 [[SWITCH_MASKED]], i3 -2 +; CHECK-NEXT: ret i3 [[RESULT]] ; entry: switch i3 %input, label %bb8 [ diff --git a/llvm/test/Transforms/SimplifyCFG/X86/switch-covered-bug.ll b/llvm/test/Transforms/SimplifyCFG/X86/switch-covered-bug.ll --- a/llvm/test/Transforms/SimplifyCFG/X86/switch-covered-bug.ll +++ b/llvm/test/Transforms/SimplifyCFG/X86/switch-covered-bug.ll @@ -9,11 +9,17 @@ define i64 @test(i3 %arg) { ; CHECK-LABEL: @test( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = sub i3 [[ARG:%.*]], -4 +; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = sub i3 [[ARG:%.*]], 1 +; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i3 [[SWITCH_TABLEIDX]], -2 +; CHECK-NEXT: br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[DEFAULT:%.*]] +; CHECK: switch.lookup: ; CHECK-NEXT: [[SWITCH_TABLEIDX_ZEXT:%.*]] = zext i3 [[SWITCH_TABLEIDX]] to i4 -; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [8 x i64], ptr @switch.table.test, i32 0, i4 [[SWITCH_TABLEIDX_ZEXT]] +; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [6 x i64], ptr @switch.table.test, i32 0, i4 [[SWITCH_TABLEIDX_ZEXT]] ; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i64, ptr [[SWITCH_GEP]], align 8 -; CHECK-NEXT: [[V3:%.*]] = add i64 [[SWITCH_LOAD]], 0 +; CHECK-NEXT: br label [[DEFAULT]] +; CHECK: Default: +; CHECK-NEXT: [[V1:%.*]] = phi i64 [ 8, [[ENTRY:%.*]] ], [ [[SWITCH_LOAD]], [[SWITCH_LOOKUP]] ] +; CHECK-NEXT: [[V3:%.*]] = add i64 [[V1]], 0 ; CHECK-NEXT: ret i64 [[V3]] ; entry: diff --git a/llvm/test/Transforms/SimplifyCFG/X86/switch-table-bug.ll b/llvm/test/Transforms/SimplifyCFG/X86/switch-table-bug.ll --- a/llvm/test/Transforms/SimplifyCFG/X86/switch-table-bug.ll +++ b/llvm/test/Transforms/SimplifyCFG/X86/switch-table-bug.ll @@ -9,11 +9,8 @@ define i64 @_TFO6reduce1E5toRawfS0_FT_Si(i2) { ; CHECK-LABEL: @_TFO6reduce1E5toRawfS0_FT_Si( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = sub i2 [[TMP0:%.*]], -2 -; CHECK-NEXT: [[SWITCH_TABLEIDX_ZEXT:%.*]] = zext i2 [[SWITCH_TABLEIDX]] to i3 -; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [4 x i64], ptr @switch.table._TFO6reduce1E5toRawfS0_FT_Si, i32 0, i3 [[SWITCH_TABLEIDX_ZEXT]] -; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i64, ptr [[SWITCH_GEP]], align 8 -; CHECK-NEXT: ret i64 [[SWITCH_LOAD]] +; CHECK-NEXT: [[SWITCH_IDX_CAST:%.*]] = zext i2 [[TMP0:%.*]] to i64 +; CHECK-NEXT: ret i64 [[SWITCH_IDX_CAST]] ; entry: switch i2 %0, label %1 [ diff --git a/llvm/test/Transforms/SimplifyCFG/X86/switch_to_lookup_table.ll b/llvm/test/Transforms/SimplifyCFG/X86/switch_to_lookup_table.ll --- a/llvm/test/Transforms/SimplifyCFG/X86/switch_to_lookup_table.ll +++ b/llvm/test/Transforms/SimplifyCFG/X86/switch_to_lookup_table.ll @@ -120,31 +120,15 @@ define i32 @f_i8_128(i8 %c) { ; CHECK-LABEL: @f_i8_128( ; CHECK-NEXT: entry: -; CHECK-NEXT: switch i8 [[C:%.*]], label [[SW_DEFAULT:%.*]] [ -; CHECK-NEXT: i8 122, label [[RETURN:%.*]] -; CHECK-NEXT: i8 123, label [[SW_BB1:%.*]] -; CHECK-NEXT: i8 124, label [[SW_BB2:%.*]] -; CHECK-NEXT: i8 125, label [[SW_BB3:%.*]] -; CHECK-NEXT: i8 126, label [[SW_BB4:%.*]] -; CHECK-NEXT: i8 127, label [[SW_BB5:%.*]] -; CHECK-NEXT: i8 -128, label [[SW_BB6:%.*]] -; CHECK-NEXT: ] -; CHECK: sw.bb1: -; CHECK-NEXT: br label [[RETURN]] -; CHECK: sw.bb2: -; CHECK-NEXT: br label [[RETURN]] -; CHECK: sw.bb3: -; CHECK-NEXT: br label [[RETURN]] -; CHECK: sw.bb4: -; CHECK-NEXT: br label [[RETURN]] -; CHECK: sw.bb5: -; CHECK-NEXT: br label [[RETURN]] -; CHECK: sw.bb6: -; CHECK-NEXT: br label [[RETURN]] -; CHECK: sw.default: +; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = sub i8 [[C:%.*]], 122 +; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i8 [[SWITCH_TABLEIDX]], 7 +; CHECK-NEXT: br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[RETURN:%.*]] +; CHECK: switch.lookup: +; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [7 x i32], ptr @switch.table.f_i8_128, i32 0, i8 [[SWITCH_TABLEIDX]] +; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i32, ptr [[SWITCH_GEP]], align 4 ; CHECK-NEXT: br label [[RETURN]] ; CHECK: return: -; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32 [ 15, [[SW_DEFAULT]] ], [ 1, [[SW_BB6]] ], [ 62, [[SW_BB5]] ], [ 27, [[SW_BB4]] ], [ -1, [[SW_BB3]] ], [ 0, [[SW_BB2]] ], [ 123, [[SW_BB1]] ], [ 55, [[ENTRY:%.*]] ] +; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32 [ [[SWITCH_LOAD]], [[SWITCH_LOOKUP]] ], [ 15, [[ENTRY:%.*]] ] ; CHECK-NEXT: ret i32 [[RETVAL_0]] ; entry: @@ -175,11 +159,17 @@ define i32 @f_min_max(i3 %c) { ; CHECK-LABEL: @f_min_max( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = sub i3 [[C:%.*]], -4 +; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = sub i3 [[C:%.*]], 3 +; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i3 [[SWITCH_TABLEIDX]], -2 +; CHECK-NEXT: br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[RETURN:%.*]] +; CHECK: switch.lookup: ; CHECK-NEXT: [[SWITCH_TABLEIDX_ZEXT:%.*]] = zext i3 [[SWITCH_TABLEIDX]] to i4 -; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [8 x i32], ptr @switch.table.f_min_max, i32 0, i4 [[SWITCH_TABLEIDX_ZEXT]] +; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [6 x i32], ptr @switch.table.f_min_max, i32 0, i4 [[SWITCH_TABLEIDX_ZEXT]] ; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i32, ptr [[SWITCH_GEP]], align 4 -; CHECK-NEXT: ret i32 [[SWITCH_LOAD]] +; CHECK-NEXT: br label [[RETURN]] +; CHECK: return: +; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32 [ [[SWITCH_LOAD]], [[SWITCH_LOOKUP]] ], [ 15, [[ENTRY:%.*]] ] +; CHECK-NEXT: ret i32 [[RETVAL_0]] ; entry: switch i3 %c, label %sw.default [ @@ -207,11 +197,17 @@ define i32 @f_min_max_2(i3 %c) { ; CHECK-LABEL: @f_min_max_2( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = sub i3 [[C:%.*]], -4 +; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = sub i3 [[C:%.*]], -1 +; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i3 [[SWITCH_TABLEIDX]], -2 +; CHECK-NEXT: br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[RETURN:%.*]] +; CHECK: switch.lookup: ; CHECK-NEXT: [[SWITCH_TABLEIDX_ZEXT:%.*]] = zext i3 [[SWITCH_TABLEIDX]] to i4 -; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [8 x i32], ptr @switch.table.f_min_max_2, i32 0, i4 [[SWITCH_TABLEIDX_ZEXT]] +; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [6 x i32], ptr @switch.table.f_min_max_2, i32 0, i4 [[SWITCH_TABLEIDX_ZEXT]] ; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i32, ptr [[SWITCH_GEP]], align 4 -; CHECK-NEXT: ret i32 [[SWITCH_LOAD]] +; CHECK-NEXT: br label [[RETURN]] +; CHECK: return: +; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32 [ [[SWITCH_LOAD]], [[SWITCH_LOOKUP]] ], [ 15, [[ENTRY:%.*]] ] +; CHECK-NEXT: ret i32 [[RETVAL_0]] ; entry: switch i3 %c, label %sw.default [ @@ -1657,14 +1653,11 @@ define i32 @covered_switch_with_bit_tests(i3) { ; CHECK-LABEL: @covered_switch_with_bit_tests( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = sub i3 [[TMP0:%.*]], -4 -; CHECK-NEXT: [[SWITCH_MASKINDEX:%.*]] = zext i3 [[SWITCH_TABLEIDX]] to i8 -; CHECK-NEXT: [[SWITCH_SHIFTED:%.*]] = lshr i8 -61, [[SWITCH_MASKINDEX]] -; CHECK-NEXT: [[SWITCH_LOBIT:%.*]] = trunc i8 [[SWITCH_SHIFTED]] to i1 -; CHECK-NEXT: br i1 [[SWITCH_LOBIT]], label [[SWITCH_LOOKUP:%.*]], label [[L6:%.*]] +; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = sub i3 [[TMP0:%.*]], 2 +; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i3 [[SWITCH_TABLEIDX]], -4 +; CHECK-NEXT: br i1 [[TMP1]], label [[SWITCH_LOOKUP:%.*]], label [[L6:%.*]] ; CHECK: switch.lookup: -; CHECK-NEXT: [[SWITCH_TABLEIDX_ZEXT:%.*]] = zext i3 [[SWITCH_TABLEIDX]] to i4 -; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [8 x i32], ptr @switch.table.covered_switch_with_bit_tests, i32 0, i4 [[SWITCH_TABLEIDX_ZEXT]] +; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [4 x i32], ptr @switch.table.covered_switch_with_bit_tests, i32 0, i3 [[SWITCH_TABLEIDX]] ; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i32, ptr [[SWITCH_GEP]], align 4 ; CHECK-NEXT: br label [[L6]] ; CHECK: l6: @@ -1815,11 +1808,10 @@ ; CHECK-LABEL: @signed_overflow1( ; CHECK-NEXT: start: ; CHECK-NEXT: [[TRUNC:%.*]] = trunc i8 [[N:%.*]] to i2 -; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = sub i2 [[TRUNC]], -2 -; CHECK-NEXT: [[SWITCH_TABLEIDX_ZEXT:%.*]] = zext i2 [[SWITCH_TABLEIDX]] to i3 -; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [4 x i32], ptr @switch.table.signed_overflow1, i32 0, i3 [[SWITCH_TABLEIDX_ZEXT]] -; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i32, ptr [[SWITCH_GEP]], align 4 -; CHECK-NEXT: ret i32 [[SWITCH_LOAD]] +; CHECK-NEXT: [[SWITCH_IDX_CAST:%.*]] = zext i2 [[TRUNC]] to i32 +; CHECK-NEXT: [[SWITCH_IDX_MULT:%.*]] = mul nsw i32 [[SWITCH_IDX_CAST]], 1111 +; CHECK-NEXT: [[SWITCH_OFFSET:%.*]] = add nsw i32 [[SWITCH_IDX_MULT]], 1111 +; CHECK-NEXT: ret i32 [[SWITCH_OFFSET]] ; start: %trunc = trunc i8 %n to i2 @@ -1851,20 +1843,11 @@ ; CHECK-LABEL: @signed_overflow2( ; CHECK-NEXT: start: ; CHECK-NEXT: [[TRUNC:%.*]] = trunc i8 [[N:%.*]] to i2 -; CHECK-NEXT: switch i2 [[TRUNC]], label [[BB1:%.*]] [ -; CHECK-NEXT: i2 1, label [[BB6:%.*]] -; CHECK-NEXT: i2 -2, label [[BB4:%.*]] -; CHECK-NEXT: i2 -1, label [[BB5:%.*]] -; CHECK-NEXT: ] -; CHECK: bb1: -; CHECK-NEXT: unreachable -; CHECK: bb4: -; CHECK-NEXT: br label [[BB6]] -; CHECK: bb5: -; CHECK-NEXT: br label [[BB6]] -; CHECK: bb6: -; CHECK-NEXT: [[DOTSROA_0_0:%.*]] = phi i32 [ 4444, [[BB5]] ], [ 3333, [[BB4]] ], [ 2222, [[START:%.*]] ] -; CHECK-NEXT: ret i32 [[DOTSROA_0_0]] +; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = sub i2 [[TRUNC]], 1 +; CHECK-NEXT: [[SWITCH_IDX_CAST:%.*]] = zext i2 [[SWITCH_TABLEIDX]] to i32 +; CHECK-NEXT: [[SWITCH_IDX_MULT:%.*]] = mul nsw i32 [[SWITCH_IDX_CAST]], 1111 +; CHECK-NEXT: [[SWITCH_OFFSET:%.*]] = add nsw i32 [[SWITCH_IDX_MULT]], 2222 +; CHECK-NEXT: ret i32 [[SWITCH_OFFSET]] ; start: %trunc = trunc i8 %n to i2 @@ -1895,11 +1878,10 @@ ; CHECK-LABEL: @signed_overflow_negative( ; CHECK-NEXT: start: ; CHECK-NEXT: [[TRUNC:%.*]] = trunc i8 [[N:%.*]] to i2 -; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = sub i2 [[TRUNC]], -2 -; CHECK-NEXT: [[SWITCH_IDX_CAST:%.*]] = zext i2 [[SWITCH_TABLEIDX]] to i32 -; CHECK-NEXT: [[SWITCH_IDX_MULT:%.*]] = mul nsw i32 [[SWITCH_IDX_CAST]], 1111 -; CHECK-NEXT: [[SWITCH_OFFSET:%.*]] = add nsw i32 [[SWITCH_IDX_MULT]], 1111 -; CHECK-NEXT: ret i32 [[SWITCH_OFFSET]] +; CHECK-NEXT: [[SWITCH_TABLEIDX_ZEXT:%.*]] = zext i2 [[TRUNC]] to i3 +; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [4 x i32], ptr @switch.table.signed_overflow_negative, i32 0, i3 [[SWITCH_TABLEIDX_ZEXT]] +; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i32, ptr [[SWITCH_GEP]], align 4 +; CHECK-NEXT: ret i32 [[SWITCH_LOAD]] ; start: %trunc = trunc i8 %n to i2