diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
--- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
@@ -270,17 +270,17 @@
 }
 
 // Instruction formats are listed in the order they appear in the RISC-V
-// instruction set manual (R, I, S, B, U, J) with sub-formats (e.g. RVInstR4,
-// RVInstRAtomic) sorted alphabetically.
+// instruction set manual (R, R4, I, S, B, U, J).
 
-class RVInstR<bits<7> funct7, bits<3> funct3, RISCVOpcode opcode, dag outs,
-              dag ins, string opcodestr, string argstr>
+// Common base class for R format instructions. Bits {31-25} should be set by
+// the subclasses.
+class RVInstRBase<bits<3> funct3, RISCVOpcode opcode, dag outs,
+                  dag ins, string opcodestr, string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
   bits<5> rs2;
   bits<5> rs1;
   bits<5> rd;
 
-  let Inst{31-25} = funct7;
   let Inst{24-20} = rs2;
   let Inst{19-15} = rs1;
   let Inst{14-12} = funct3;
@@ -288,34 +288,30 @@
   let Inst{6-0} = opcode.Value;
 }
 
-class RVInstR4<bits<2> funct2, bits<3> funct3, RISCVOpcode opcode, dag outs,
-               dag ins, string opcodestr, string argstr>
-    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR4> {
-  bits<5> rs3;
-  bits<5> rs2;
-  bits<5> rs1;
-  bits<5> rd;
+class RVInstR<bits<7> funct7, bits<3> funct3, RISCVOpcode opcode, dag outs,
+              dag ins, string opcodestr, string argstr>
+    : RVInstRBase<funct3, opcode, outs, ins, opcodestr, argstr> {
+  let Inst{31-25} = funct7;
+}
 
-  let Inst{31-27} = rs3;
-  let Inst{26-25} = funct2;
-  let Inst{24-20} = rs2;
-  let Inst{19-15} = rs1;
-  let Inst{14-12} = funct3;
-  let Inst{11-7} = rd;
-  let Inst{6-0} = opcode.Value;
+class RVInstRAtomic<bits<5> funct5, bit aq, bit rl, bits<3> funct3,
+                    RISCVOpcode opcode, dag outs, dag ins, string opcodestr,
+                    string argstr>
+    : RVInstRBase<funct3, opcode, outs, ins, opcodestr, argstr> {
+  let Inst{31-27} = funct5;
+  let Inst{26} = aq;
+  let Inst{25} = rl;
 }
 
-class RVInstR4Frm<bits<2> funct2, RISCVOpcode opcode, dag outs, dag ins,
-                  string opcodestr, string argstr>
-    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR4> {
-  bits<5> rs3;
+class RVInstRFrm<bits<7> funct7, RISCVOpcode opcode, dag outs, dag ins,
+                 string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
   bits<5> rs2;
   bits<5> rs1;
   bits<3> frm;
   bits<5> rd;
 
-  let Inst{31-27} = rs3;
-  let Inst{26-25} = funct2;
+  let Inst{31-25} = funct7;
   let Inst{24-20} = rs2;
   let Inst{19-15} = rs1;
   let Inst{14-12} = frm;
@@ -323,17 +319,16 @@
   let Inst{6-0} = opcode.Value;
 }
 
-class RVInstRAtomic<bits<5> funct5, bit aq, bit rl, bits<3> funct3,
-                    RISCVOpcode opcode, dag outs, dag ins, string opcodestr,
-                    string argstr>
-    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+class RVInstR4<bits<2> funct2, bits<3> funct3, RISCVOpcode opcode, dag outs,
+               dag ins, string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR4> {
+  bits<5> rs3;
   bits<5> rs2;
   bits<5> rs1;
   bits<5> rd;
 
-  let Inst{31-27} = funct5;
-  let Inst{26} = aq;
-  let Inst{25} = rl;
+  let Inst{31-27} = rs3;
+  let Inst{26-25} = funct2;
   let Inst{24-20} = rs2;
   let Inst{19-15} = rs1;
   let Inst{14-12} = funct3;
@@ -341,15 +336,17 @@
   let Inst{6-0} = opcode.Value;
 }
 
-class RVInstRFrm<bits<7> funct7, RISCVOpcode opcode, dag outs, dag ins,
-                 string opcodestr, string argstr>
-    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+class RVInstR4Frm<bits<2> funct2, RISCVOpcode opcode, dag outs, dag ins,
+                  string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR4> {
+  bits<5> rs3;
   bits<5> rs2;
   bits<5> rs1;
   bits<3> frm;
   bits<5> rd;
 
-  let Inst{31-25} = funct7;
+  let Inst{31-27} = rs3;
+  let Inst{26-25} = funct2;
   let Inst{24-20} = rs2;
   let Inst{19-15} = rs1;
   let Inst{14-12} = frm;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
@@ -78,20 +78,12 @@
 
 class CVInstMacMulN<bits<2> funct2, bits<3> funct3, dag outs, dag ins,
                     string opcodestr>
-    : RVInst<outs, ins, opcodestr, "$rd, $rs1, $rs2, $imm5",
-             [], InstFormatOther> {
+    : RVInstRBase<funct3, OPC_CUSTOM_2, outs, ins, opcodestr,
+                  "$rd, $rs1, $rs2, $imm5"> {
   bits<5> imm5;
-  bits<5> rs2;
-  bits<5> rs1;
-  bits<5> rd;
 
   let Inst{31-30} = funct2;
   let Inst{29-25} = imm5;
-  let Inst{24-20} = rs2;
-  let Inst{19-15} = rs1;
-  let Inst{14-12} = funct3;
-  let Inst{11-7} = rd;
-  let Inst{6-0} = OPC_CUSTOM_2.Value;
   let DecoderNamespace = "XCVmac";
 }
 
@@ -171,20 +163,13 @@
 
 let DecoderNamespace = "XCValu" in {
   class CVInstAluRRI<bits<2> funct2, bits<3> funct3, string opcodestr>
-      : RVInst<(outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
-                opcodestr, "$rd, $rs1, $rs2, $imm5", [], InstFormatOther> {
+      : RVInstRBase<funct3, OPC_CUSTOM_2, (outs GPR:$rd),
+                    (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5), opcodestr,
+                    "$rd, $rs1, $rs2, $imm5"> {
     bits<5> imm5;
-    bits<5> rs2;
-    bits<5> rs1;
-    bits<5> rd;
 
     let Inst{31-30} = funct2;
     let Inst{29-25} = imm5;
-    let Inst{24-20} = rs2;
-    let Inst{19-15} = rs1;
-    let Inst{14-12} = funct3;
-    let Inst{11-7} = rd;
-    let Inst{6-0} = OPC_CUSTOM_2.Value;
   }
 
   class CVInstAluRR<bits<7> funct7, bits<3> funct3, string opcodestr>
@@ -295,19 +280,10 @@
 class CVInstSIMDRR<bits<5> funct5, bit F, bit funct1, bits<3> funct3,
                    RISCVOpcode opcode, dag outs,
                    dag ins, string opcodestr, string argstr>
-    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
-  bits<5> rs2;
-  bits<5> rs1;
-  bits<5> rd;
-
+    : RVInstRBase<funct3, opcode, outs, ins, opcodestr, argstr> {
   let Inst{31-27} = funct5;
   let Inst{26} = F;
   let Inst{25} = funct1;
-  let Inst{24-20} = rs2;
-  let Inst{19-15} = rs1;
-  let Inst{14-12} = funct3;
-  let Inst{11-7} = rd;
-  let Inst{6-0} = opcode.Value;
   let DecoderNamespace = "CoreVSIMD";
 }
 
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
@@ -66,9 +66,9 @@
 let Predicates = [HasVendorXTHeadBa], DecoderNamespace = "THeadBa",
   hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 class THShiftALU_rri<bits<3> funct3, string opcodestr>
-    : RVInstR<0, funct3, OPC_CUSTOM_0, (outs GPR:$rd),
-              (ins GPR:$rs1, GPR:$rs2, uimm2:$uimm2),
-              opcodestr, "$rd, $rs1, $rs2, $uimm2"> {
+    : RVInstRBase<funct3, OPC_CUSTOM_0, (outs GPR:$rd),
+                  (ins GPR:$rs1, GPR:$rs2, uimm2:$uimm2),
+                  opcodestr, "$rd, $rs1, $rs2, $uimm2"> {
   bits<2> uimm2;
   let Inst{31-27} = 0;
   let Inst{26-25} = uimm2;
@@ -124,11 +124,12 @@
 let Predicates = [HasVendorXTHeadMemPair], DecoderNamespace = "THeadMemPair",
   hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
 class THLoadPair<bits<5> funct5, string opcodestr>
-  : RVInstR<!shl(funct5, 2), 0b100, OPC_CUSTOM_0,
-            (outs GPR:$rd, GPR:$rs2),
-            (ins GPR:$rs1, uimm2:$uimm2, uimm7:$const3or4),
-             opcodestr, "$rd, $rs2, (${rs1}), $uimm2, $const3or4"> {
+  : RVInstRBase<0b100, OPC_CUSTOM_0,
+                (outs GPR:$rd, GPR:$rs2),
+                (ins GPR:$rs1, uimm2:$uimm2, uimm7:$const3or4),
+                 opcodestr, "$rd, $rs2, (${rs1}), $uimm2, $const3or4"> {
   bits<2> uimm2;
+  let Inst{31-27} = funct5;
   let Inst{26-25} = uimm2;
   let DecoderMethod = "decodeXTHeadMemPair";
   let Constraints = "@earlyclobber $rd,@earlyclobber $rs2";
@@ -137,11 +138,11 @@
 let Predicates = [HasVendorXTHeadMemPair], DecoderNamespace = "THeadMemPair",
   hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
 class THStorePair<bits<5> funct5, string opcodestr>
-  : RVInstR<!shl(funct5, 2), 0b101, OPC_CUSTOM_0,
-            (outs),
-            (ins GPR:$rd, GPR:$rs2, GPR:$rs1, uimm2:$uimm2, uimm7:$const3or4),
-            opcodestr, "$rd, $rs2, (${rs1}), $uimm2, $const3or4"> {
+  : RVInstRBase<0b101, OPC_CUSTOM_0, (outs),
+              (ins GPR:$rd, GPR:$rs2, GPR:$rs1, uimm2:$uimm2, uimm7:$const3or4),
+              opcodestr, "$rd, $rs2, (${rs1}), $uimm2, $const3or4"> {
   bits<2> uimm2;
+  let Inst{31-27} = funct5;
   let Inst{26-25} = uimm2;
   let DecoderMethod = "decodeXTHeadMemPair";
 }
@@ -171,10 +172,11 @@
 
 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
 class THLoadIndexed<RegisterClass Ty, bits<5> funct5, string opcodestr>
-    : RVInstR<!shl(funct5, 2), !if(!eq(Ty, GPR), 0b100, 0b110), OPC_CUSTOM_0,
-              (outs Ty:$rd), (ins GPR:$rs1, GPR:$rs2, uimm2:$uimm2),
-              opcodestr, "$rd, $rs1, $rs2, $uimm2"> {
+    : RVInstRBase<!if(!eq(Ty, GPR), 0b100, 0b110), OPC_CUSTOM_0,
+                  (outs Ty:$rd), (ins GPR:$rs1, GPR:$rs2, uimm2:$uimm2),
+                  opcodestr, "$rd, $rs1, $rs2, $uimm2"> {
   bits<2> uimm2;
+  let Inst{31-27} = funct5;
   let Inst{26-25} = uimm2;
 }
 
@@ -193,10 +195,11 @@
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
 class THStoreIndexed<RegisterClass StTy, bits<5> funct5, string opcodestr>
-    : RVInstR<!shl(funct5, 2), !if(!eq(StTy, GPR), 0b101, 0b111), OPC_CUSTOM_0,
-              (outs), (ins StTy:$rd, GPR:$rs1, GPR:$rs2, uimm2:$uimm2),
-              opcodestr, "$rd, $rs1, $rs2, $uimm2"> {
+    : RVInstRBase<!if(!eq(StTy, GPR), 0b101, 0b111), OPC_CUSTOM_0,
+                  (outs), (ins StTy:$rd, GPR:$rs1, GPR:$rs2, uimm2:$uimm2),
+                  opcodestr, "$rd, $rs1, $rs2, $uimm2"> {
   bits<2> uimm2;
+  let Inst{31-27} = funct5;
   let Inst{26-25} = uimm2;
 }