diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
--- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
@@ -357,62 +357,51 @@
   let Inst{6-0} = opcode.Value;
 }
 
-class RVInstI<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
-              string opcodestr, string argstr>
+// Common base class for I format instructions. Bits {31-20} should be set by
+// the subclasses.
+class RVInstIBase<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
+                  string opcodestr, string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
-  bits<12> imm12;
   bits<5> rs1;
   bits<5> rd;
 
-  let Inst{31-20} = imm12;
   let Inst{19-15} = rs1;
   let Inst{14-12} = funct3;
   let Inst{11-7} = rd;
   let Inst{6-0} = opcode.Value;
 }
 
+class RVInstI<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
+              string opcodestr, string argstr>
+    : RVInstIBase<funct3, opcode, outs, ins, opcodestr, argstr> {
+  bits<12> imm12;
+
+  let Inst{31-20} = imm12;
+}
+
 class RVInstIShift<bits<5> imm11_7, bits<3> funct3, RISCVOpcode opcode,
                    dag outs, dag ins, string opcodestr, string argstr>
-    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
+    : RVInstIBase<funct3, opcode, outs, ins, opcodestr, argstr> {
   bits<6> shamt;
-  bits<5> rs1;
-  bits<5> rd;
 
   let Inst{31-27} = imm11_7;
   let Inst{26} = 0;
   let Inst{25-20} = shamt;
-  let Inst{19-15} = rs1;
-  let Inst{14-12} = funct3;
-  let Inst{11-7} = rd;
-  let Inst{6-0} = opcode.Value;
 }
 
 class RVInstIShiftW<bits<7> imm11_5, bits<3> funct3, RISCVOpcode opcode,
                     dag outs, dag ins, string opcodestr, string argstr>
-    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
+    : RVInstIBase<funct3, opcode, outs, ins, opcodestr, argstr> {
   bits<5> shamt;
-  bits<5> rs1;
-  bits<5> rd;
 
   let Inst{31-25} = imm11_5;
   let Inst{24-20} = shamt;
-  let Inst{19-15} = rs1;
-  let Inst{14-12} = funct3;
-  let Inst{11-7} = rd;
-  let Inst{6-0} = opcode.Value;
 }
 
 class RVInstIUnary<bits<12> imm12, bits<3> funct3, RISCVOpcode opcode,
                    dag outs, dag ins, string opcodestr, string argstr>
-    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
-  bits<5> rs1;
-  bits<5> rd;
-
+    : RVInstIBase<funct3, opcode, outs, ins, opcodestr, argstr> {
   let Inst{31-20} = imm12;
-  let Inst{19-15} = rs1;
-  let Inst{14-12} = funct3;
-  let Inst{11-7} = rd;
-  let Inst{6-0} = opcode.Value;
 }
 
 class RVInstS<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
@@ -13,10 +13,12 @@
 let DecoderNamespace = "XCVbitmanip" in {
   class CVInstBitManipRII<bits<2> funct2, bits<3> funct3, dag outs, dag ins,
                       string opcodestr, string argstr>
-      : RVInstI<funct3, OPC_CUSTOM_2, outs, ins, opcodestr, argstr> {
+      : RVInstIBase<funct3, OPC_CUSTOM_2, outs, ins, opcodestr, argstr> {
     bits<5> is3;
     bits<5> is2;
-    let imm12 = {funct2, is3, is2};
+    let Inst{31-30} = funct2;
+    let Inst{29-25} = is3;
+    let Inst{24-20} = is2;
   }
 
   class CVBitManipRII<bits<2> funct2, bits<3> funct3, string opcodestr,
@@ -194,18 +196,13 @@
               (ins GPR:$rd, GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2">;
 
   class CVInstAluRI<bits<7> funct7, bits<3> funct3, string opcodestr>
-      : RVInst<(outs GPR:$rd), (ins GPR:$rs1, uimm5:$imm5), opcodestr,
-                "$rd, $rs1, $imm5", [], InstFormatOther> {
+      : RVInstIBase<funct3, OPC_CUSTOM_1, (outs GPR:$rd),
+                    (ins GPR:$rs1, uimm5:$imm5), opcodestr,
+                    "$rd, $rs1, $imm5"> {
     bits<5> imm5;
-    bits<5> rs1;
-    bits<5> rd;
 
     let Inst{31-25} = funct7;
     let Inst{24-20} = imm5;
-    let Inst{19-15} = rs1;
-    let Inst{14-12} = funct3;
-    let Inst{11-7} = rd;
-    let Inst{6-0} = OPC_CUSTOM_1.Value;
   }
 
   class CVInstAluR<bits<7> funct7, bits<3> funct3, string opcodestr>
@@ -316,19 +313,13 @@
 
 class CVInstSIMDRI<bits<5> funct5, bit F, bits<3> funct3, RISCVOpcode opcode,
                    dag outs, dag ins, string opcodestr, string argstr>
-    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
+    : RVInstIBase<funct3, opcode, outs, ins, opcodestr, argstr> {
   bits<6> imm6;
-  bits<5> rs1;
-  bits<5> rd;
 
   let Inst{31-27} = funct5;
   let Inst{26} = F;
   let Inst{25} = imm6{0}; // funct1 unused
   let Inst{24-20} = imm6{5-1};
-  let Inst{19-15} = rs1;
-  let Inst{14-12} = funct3;
-  let Inst{11-7} = rd;
-  let Inst{6-0} = opcode.Value;
   let DecoderNamespace = "XCVsimd";
 }
 
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
@@ -87,9 +87,9 @@
                    opcodestr, "$rd, $rs1, $shamt">;
 
 class THBitfieldExtract_rii<bits<3> funct3, string opcodestr>
-    : RVInstI<funct3, OPC_CUSTOM_0, (outs GPR:$rd),
-              (ins GPR:$rs1, uimmlog2xlen:$msb, uimmlog2xlen:$lsb),
-              opcodestr, "$rd, $rs1, $msb, $lsb"> {
+    : RVInstIBase<funct3, OPC_CUSTOM_0, (outs GPR:$rd),
+                  (ins GPR:$rs1, uimmlog2xlen:$msb, uimmlog2xlen:$lsb),
+                  opcodestr, "$rd, $rs1, $msb, $lsb"> {
   bits<6> msb;
   bits<6> lsb;
   let Inst{31-26} = msb;
@@ -184,14 +184,14 @@
 }
 
 class THLoadUpdate<bits<5> funct5, string opcodestr>
-    : RVInstI<0b100, OPC_CUSTOM_0, (outs GPR:$rd, GPR:$rs1_wb),
-              (ins GPR:$rs1, simm5:$simm5, uimm2:$uimm2),
-              opcodestr, "$rd, (${rs1}), $simm5, $uimm2"> {
+    : RVInstIBase<0b100, OPC_CUSTOM_0, (outs GPR:$rd, GPR:$rs1_wb),
+                  (ins GPR:$rs1, simm5:$simm5, uimm2:$uimm2),
+                  opcodestr, "$rd, (${rs1}), $simm5, $uimm2"> {
   bits<5> simm5;
   bits<2> uimm2;
-  let imm12{11-7} = funct5;
-  let imm12{6-5} = uimm2;
-  let imm12{4-0} = simm5;
+  let Inst{31-27} = funct5;
+  let Inst{26-25} = uimm2;
+  let Inst{24-20} = simm5;
   let Constraints = "@earlyclobber $rd, $rs1_wb = $rs1";
 }
 }
@@ -206,14 +206,14 @@
 }
 
 class THStoreUpdate<bits<5> funct5, string opcodestr>
-    : RVInstI<0b101, OPC_CUSTOM_0, (outs GPR:$rs1_up),
-              (ins GPR:$rd, GPR:$rs1, simm5:$simm5, uimm2:$uimm2),
-              opcodestr, "$rd, (${rs1}), $simm5, $uimm2"> {
+    : RVInstIBase<0b101, OPC_CUSTOM_0, (outs GPR:$rs1_up),
+                  (ins GPR:$rd, GPR:$rs1, simm5:$simm5, uimm2:$uimm2),
+                  opcodestr, "$rd, (${rs1}), $simm5, $uimm2"> {
   bits<5> simm5;
   bits<2> uimm2;
-  let imm12{11-7} = funct5;
-  let imm12{6-5} = uimm2;
-  let imm12{4-0} = simm5;
+  let Inst{31-27} = funct5;
+  let Inst{26-25} = uimm2;
+  let Inst{24-20} = simm5;
   let Constraints = "$rs1_up = $rs1";
 }
 }
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZk.td
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZk.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZk.td
@@ -70,12 +70,12 @@
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 class RVKUnary_rnum<bits<7> funct7, bits<3> funct3, string opcodestr>
-    : RVInstI<funct3, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1, rnum:$rnum),
-              opcodestr, "$rd, $rs1, $rnum">{
+    : RVInstIBase<funct3, OPC_OP_IMM, (outs GPR:$rd),
+                  (ins GPR:$rs1, rnum:$rnum), opcodestr, "$rd, $rs1, $rnum"> {
   bits<4> rnum;
-  let imm12{11-5} = funct7;
-  let imm12{4} = 0b1;
-  let imm12{3-0} = rnum;
+  let Inst{31-25} = funct7;
+  let Inst{24} = 0b1;
+  let Inst{23-20} = rnum;
 }
 
 //===----------------------------------------------------------------------===//