diff --git a/llvm/lib/Target/BPF/BPFInstrInfo.cpp b/llvm/lib/Target/BPF/BPFInstrInfo.cpp --- a/llvm/lib/Target/BPF/BPFInstrInfo.cpp +++ b/llvm/lib/Target/BPF/BPFInstrInfo.cpp @@ -137,7 +137,7 @@ .addFrameIndex(FI) .addImm(0); else if (RC == &BPF::GPR32RegClass) - BuildMI(MBB, I, DL, get(BPF::STW32)) + BuildMI(MBB, I, DL, get(BPF::STW)) .addReg(SrcReg, getKillRegState(IsKill)) .addFrameIndex(FI) .addImm(0); @@ -158,7 +158,7 @@ if (RC == &BPF::GPRRegClass) BuildMI(MBB, I, DL, get(BPF::LDD), DestReg).addFrameIndex(FI).addImm(0); else if (RC == &BPF::GPR32RegClass) - BuildMI(MBB, I, DL, get(BPF::LDW32), DestReg).addFrameIndex(FI).addImm(0); + BuildMI(MBB, I, DL, get(BPF::LDW), DestReg).addFrameIndex(FI).addImm(0); else llvm_unreachable("Can't load this register from stack slot"); } diff --git a/llvm/lib/Target/BPF/BPFInstrInfo.td b/llvm/lib/Target/BPF/BPFInstrInfo.td --- a/llvm/lib/Target/BPF/BPFInstrInfo.td +++ b/llvm/lib/Target/BPF/BPFInstrInfo.td @@ -431,12 +431,12 @@ } // STORE instructions -class STORE Pattern> +class STORE_reg : TYPE_LD_ST { + [(OpNode GPR:$src, ADDRri:$addr)]> { bits<4> src; bits<20> addr; @@ -446,15 +446,24 @@ let BPFClass = BPF_STX; } -class STOREi64 - : STORE; +def STD : STORE_reg; +def STW : STORE_reg; +def STH : STORE_reg; +def STB : STORE_reg; -let Predicates = [BPFNoALU32] in { - def STW : STOREi64; - def STH : STOREi64; - def STB : STOREi64; +def : Pat<(store i64:$src, ADDRri:$dst), (STD i64:$src, ADDRri:$dst)>; +def : Pat<(truncstorei32 i64:$src, ADDRri:$dst), (STW i64:$src, ADDRri:$dst)>; +def : Pat<(truncstorei16 i64:$src, ADDRri:$dst), (STH i64:$src, ADDRri:$dst)>; +def : Pat<(truncstorei8 i64:$src, ADDRri:$dst), (STB i64:$src, ADDRri:$dst)>; + +let Predicates = [BPFHasALU32] in { + def : Pat<(store GPR32:$src, ADDRri:$dst), + (STW (SUBREG_TO_REG (i64 0), GPR32:$src, sub_32), ADDRri:$dst)>; + def : Pat<(truncstorei16 GPR32:$src, ADDRri:$dst), + (STH (SUBREG_TO_REG (i64 0), GPR32:$src, sub_32), ADDRri:$dst)>; + def : Pat<(truncstorei8 GPR32:$src, ADDRri:$dst), + (STB (SUBREG_TO_REG (i64 0), GPR32:$src, sub_32), ADDRri:$dst)>; } -def STD : STOREi64; // LOAD instructions class LOAD Pattern> @@ -495,10 +504,23 @@ } } -let Predicates = [BPFNoALU32] in { - def LDW : LOADi64; - def LDH : LOADi64; - def LDB : LOADi64; +def LDD : LOADi64; +def LDW : LOADi64; +def LDH : LOADi64; +def LDB : LOADi64; + +let Predicates = [BPFHasALU32] in { + def : Pat<(i32 (load ADDRri:$src)), (EXTRACT_SUBREG (LDW ADDRri:$src), sub_32)>; + + def : Pat<(i32 (zextloadi16 ADDRri:$src)), (EXTRACT_SUBREG (LDH ADDRri:$src), sub_32)>; + def : Pat<(i32 (zextloadi8 ADDRri:$src)), (EXTRACT_SUBREG (LDB ADDRri:$src), sub_32)>; + + def : Pat<(i32 (extloadi16 ADDRri:$src)), (EXTRACT_SUBREG (LDH ADDRri:$src), sub_32)>; + def : Pat<(i32 (extloadi8 ADDRri:$src)), (EXTRACT_SUBREG (LDB ADDRri:$src), sub_32)>; + + def : Pat<(i64 (extloadi32 ADDRri:$src)), (LDW ADDRri:$src)>; + def : Pat<(i64 (extloadi16 ADDRri:$src)), (LDH ADDRri:$src)>; + def : Pat<(i64 (extloadi8 ADDRri:$src)), (LDB ADDRri:$src)>; } let Predicates = [BPFHasLdsx] in { @@ -507,7 +529,10 @@ def LDBSX : LOADi64; } -def LDD : LOADi64; +let Predicates = [BPFHasALU32, BPFHasLdsx] in { + def : Pat<(i32 (sextloadi8 ADDRri:$src)), (EXTRACT_SUBREG (LDBSX ADDRri:$src), sub_32)>; + def : Pat<(i32 (sextloadi16 ADDRri:$src)), (EXTRACT_SUBREG (LDHSX ADDRri:$src), sub_32)>; +} class BRANCH Pattern> : TYPE_ALU_JMP; -class STORE32 Pattern> - : TYPE_LD_ST { - bits<4> src; - bits<20> addr; - - let Inst{51-48} = addr{19-16}; // base reg - let Inst{55-52} = src; - let Inst{47-32} = addr{15-0}; // offset - let BPFClass = BPF_STX; -} - -class STOREi32 - : STORE32; - -let Predicates = [BPFHasALU32], DecoderNamespace = "BPFALU32" in { - def STW32 : STOREi32; - def STH32 : STOREi32; - def STB32 : STOREi32; -} - -class LOAD32 Pattern> - : TYPE_LD_ST { - bits<4> dst; - bits<20> addr; - - let Inst{51-48} = dst; - let Inst{55-52} = addr{19-16}; - let Inst{47-32} = addr{15-0}; - let BPFClass = BPF_LDX; -} - -class LOADi32 - : LOAD32; - -let Predicates = [BPFHasALU32], DecoderNamespace = "BPFALU32" in { - def LDW32 : LOADi32; - def LDH32 : LOADi32; - def LDB32 : LOADi32; -} - -let Predicates = [BPFHasALU32] in { - def : Pat<(truncstorei8 GPR:$src, ADDRri:$dst), - (STB32 (EXTRACT_SUBREG GPR:$src, sub_32), ADDRri:$dst)>; - def : Pat<(truncstorei16 GPR:$src, ADDRri:$dst), - (STH32 (EXTRACT_SUBREG GPR:$src, sub_32), ADDRri:$dst)>; - def : Pat<(truncstorei32 GPR:$src, ADDRri:$dst), - (STW32 (EXTRACT_SUBREG GPR:$src, sub_32), ADDRri:$dst)>; - def : Pat<(i32 (extloadi8 ADDRri:$src)), (i32 (LDB32 ADDRri:$src))>; - def : Pat<(i32 (extloadi16 ADDRri:$src)), (i32 (LDH32 ADDRri:$src))>; - - let Predicates = [BPFHasLdsx] in { - def : Pat<(i32 (sextloadi8 ADDRri:$src)), (EXTRACT_SUBREG (LDBSX ADDRri:$src), sub_32)>; - def : Pat<(i32 (sextloadi16 ADDRri:$src)), (EXTRACT_SUBREG (LDHSX ADDRri:$src), sub_32)>; - } - - def : Pat<(i64 (zextloadi8 ADDRri:$src)), - (SUBREG_TO_REG (i64 0), (LDB32 ADDRri:$src), sub_32)>; - def : Pat<(i64 (zextloadi16 ADDRri:$src)), - (SUBREG_TO_REG (i64 0), (LDH32 ADDRri:$src), sub_32)>; - def : Pat<(i64 (zextloadi32 ADDRri:$src)), - (SUBREG_TO_REG (i64 0), (LDW32 ADDRri:$src), sub_32)>; - def : Pat<(i64 (extloadi8 ADDRri:$src)), - (SUBREG_TO_REG (i64 0), (LDB32 ADDRri:$src), sub_32)>; - def : Pat<(i64 (extloadi16 ADDRri:$src)), - (SUBREG_TO_REG (i64 0), (LDH32 ADDRri:$src), sub_32)>; - def : Pat<(i64 (extloadi32 ADDRri:$src)), - (SUBREG_TO_REG (i64 0), (LDW32 ADDRri:$src), sub_32)>; -} - let usesCustomInserter = 1, isCodeGenOnly = 1 in { def MEMCPY : Pseudo< (outs), diff --git a/llvm/lib/Target/BPF/BPFMIPeephole.cpp b/llvm/lib/Target/BPF/BPFMIPeephole.cpp --- a/llvm/lib/Target/BPF/BPFMIPeephole.cpp +++ b/llvm/lib/Target/BPF/BPFMIPeephole.cpp @@ -105,10 +105,17 @@ if (!Reg.isVirtual()) return false; + MachineInstr *DefInsn = MRI->getVRegDef(Reg); + + // 8/16/32-bit loads have GPRRegclass but there is no need to + // zero-extend values coming from such loads. + if (DefInsn->getOpcode() == BPF::LDB || DefInsn->getOpcode() == BPF::LDH || + DefInsn->getOpcode() == BPF::LDW) + return true; + if (MRI->getRegClass(Reg) == &BPF::GPRRegClass) return false; - MachineInstr *DefInsn = MRI->getVRegDef(Reg); if (!isInsnFrom32Def(DefInsn)) return false; @@ -644,13 +651,13 @@ static bool TruncSizeCompatible(int TruncSize, unsigned opcode) { if (TruncSize == 1) - return opcode == BPF::LDB || opcode == BPF::LDB32; + return opcode == BPF::LDB; if (TruncSize == 2) - return opcode == BPF::LDH || opcode == BPF::LDH32; + return opcode == BPF::LDH; if (TruncSize == 4) - return opcode == BPF::LDW || opcode == BPF::LDW32; + return opcode == BPF::LDW; return false; } diff --git a/llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp b/llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp --- a/llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp +++ b/llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp @@ -95,8 +95,7 @@ bool BPFMISimplifyPatchable::isLoadInst(unsigned Opcode) { return Opcode == BPF::LDD || Opcode == BPF::LDW || Opcode == BPF::LDH || - Opcode == BPF::LDB || Opcode == BPF::LDW32 || Opcode == BPF::LDH32 || - Opcode == BPF::LDB32 || Opcode == BPF::LDWSX || Opcode == BPF::LDHSX || + Opcode == BPF::LDB || Opcode == BPF::LDWSX || Opcode == BPF::LDHSX || Opcode == BPF::LDBSX; } @@ -123,10 +122,6 @@ Opcode == BPF::STW || Opcode == BPF::STD || Opcode == BPF::LDWSX || Opcode == BPF::LDHSX || Opcode == BPF::LDBSX) COREOp = BPF::CORE_MEM; - else if (Opcode == BPF::LDB32 || Opcode == BPF::LDH32 || - Opcode == BPF::LDW32 || Opcode == BPF::STB32 || - Opcode == BPF::STH32 || Opcode == BPF::STW32) - COREOp = BPF::CORE_ALU32_MEM; else continue; @@ -139,8 +134,7 @@ // %1 = ADD_rr %2, %3 // *(type *)(%2 + 0) = %1 if (Opcode == BPF::STB || Opcode == BPF::STH || Opcode == BPF::STW || - Opcode == BPF::STD || Opcode == BPF::STB32 || Opcode == BPF::STH32 || - Opcode == BPF::STW32) { + Opcode == BPF::STD) { const MachineOperand &Opnd = DefInst->getOperand(0); if (Opnd.isReg() && Opnd.getReg() == MO.getReg()) continue; diff --git a/llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp b/llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp --- a/llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp +++ b/llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp @@ -176,8 +176,7 @@ uint8_t InstClass = getInstClass(Insn); uint8_t InstMode = getInstMode(Insn); if ((InstClass == BPF_LDX || InstClass == BPF_STX) && - getInstSize(Insn) != BPF_DW && - (InstMode == BPF_MEM || InstMode == BPF_ATOMIC) && + InstMode == BPF_ATOMIC && getInstSize(Insn) != BPF_DW && STI.hasFeature(BPF::ALU32)) Result = decodeInstruction(DecoderTableBPFALU3264, Instr, Insn, Address, this, STI); diff --git a/llvm/test/CodeGen/BPF/32-bit-subreg-load-store.ll b/llvm/test/CodeGen/BPF/32-bit-subreg-load-store.ll --- a/llvm/test/CodeGen/BPF/32-bit-subreg-load-store.ll +++ b/llvm/test/CodeGen/BPF/32-bit-subreg-load-store.ll @@ -43,7 +43,7 @@ define dso_local zeroext i8 @loadu8(ptr nocapture readonly %p) local_unnamed_addr #0 { entry: %0 = load i8, ptr %p, align 1 -; CHECK: w{{[0-9]+}} = *(u8 *)(r{{[0-9]+}} + 0) +; CHECK: r{{[0-9]+}} = *(u8 *)(r{{[0-9]+}} + 0) ret i8 %0 } @@ -51,7 +51,7 @@ define dso_local zeroext i16 @loadu16(ptr nocapture readonly %p) local_unnamed_addr #0 { entry: %0 = load i16, ptr %p, align 2 -; CHECK: w{{[0-9]+}} = *(u16 *)(r{{[0-9]+}} + 0) +; CHECK: r{{[0-9]+}} = *(u16 *)(r{{[0-9]+}} + 0) ret i16 %0 } @@ -59,7 +59,7 @@ define dso_local i32 @loadu32(ptr nocapture readonly %p) local_unnamed_addr #0 { entry: %0 = load i32, ptr %p, align 4 -; CHECK: w{{[0-9]+}} = *(u32 *)(r{{[0-9]+}} + 0) +; CHECK: r{{[0-9]+}} = *(u32 *)(r{{[0-9]+}} + 0) ret i32 %0 } @@ -76,7 +76,7 @@ entry: %conv = trunc i64 %v to i8 store i8 %conv, ptr %p, align 1 -; CHECK: *(u8 *)(r{{[0-9]+}} + 0) = w{{[0-9]+}} +; CHECK: *(u8 *)(r{{[0-9]+}} + 0) = r{{[0-9]+}} ret void } @@ -85,7 +85,7 @@ entry: %conv = trunc i64 %v to i16 store i16 %conv, ptr %p, align 2 -; CHECK: *(u16 *)(r{{[0-9]+}} + 0) = w{{[0-9]+}} +; CHECK: *(u16 *)(r{{[0-9]+}} + 0) = r{{[0-9]+}} ret void } @@ -94,7 +94,7 @@ entry: %conv = trunc i64 %v to i32 store i32 %conv, ptr %p, align 4 -; CHECK: *(u32 *)(r{{[0-9]+}} + 0) = w{{[0-9]+}} +; CHECK: *(u32 *)(r{{[0-9]+}} + 0) = r{{[0-9]+}} ret void } diff --git a/llvm/test/CodeGen/BPF/CORE/offset-reloc-end-load.ll b/llvm/test/CodeGen/BPF/CORE/offset-reloc-end-load.ll --- a/llvm/test/CodeGen/BPF/CORE/offset-reloc-end-load.ll +++ b/llvm/test/CodeGen/BPF/CORE/offset-reloc-end-load.ll @@ -1,6 +1,6 @@ ; RUN: opt -O2 %s | llvm-dis > %t1 -; RUN: llc -filetype=asm -o - %t1 | FileCheck -check-prefixes=CHECK,CHECK-ALU64 %s -; RUN: llc -mattr=+alu32 -filetype=asm -o - %t1 | FileCheck -check-prefixes=CHECK,CHECK-ALU32 %s +; RUN: llc -filetype=asm -o - %t1 | FileCheck %s +; RUN: llc -mattr=+alu32 -filetype=asm -o - %t1 | FileCheck %s ; ; Source Code: ; #define _(x) (__builtin_preserve_access_index(x)) @@ -23,8 +23,7 @@ } ; CHECK-LABEL: test -; CHECK-ALU64: r0 = *(u32 *)(r1 + 4) -; CHECK-ALU32: w0 = *(u32 *)(r1 + 4) +; CHECK: r0 = *(u32 *)(r1 + 4) ; CHECK: exit ; ; CHECK: .long 1 # BTF_KIND_STRUCT(id = 2) diff --git a/llvm/test/CodeGen/BPF/assembler-disassembler.s b/llvm/test/CodeGen/BPF/assembler-disassembler.s --- a/llvm/test/CodeGen/BPF/assembler-disassembler.s +++ b/llvm/test/CodeGen/BPF/assembler-disassembler.s @@ -209,26 +209,18 @@ // CHECK: 95 00 00 00 00 00 00 00 exit exit -// Note: For the group below w1 is used as a destination for sizes u8, u16, u32. -// This is disassembler quirk, but is technically not wrong, as there are -// no different encodings for 'r1 = load' vs 'w1 = load'. -// -// CHECK: 71 21 2a 00 00 00 00 00 w1 = *(u8 *)(r2 + 0x2a) -// CHECK: 69 21 2a 00 00 00 00 00 w1 = *(u16 *)(r2 + 0x2a) -// CHECK: 61 21 2a 00 00 00 00 00 w1 = *(u32 *)(r2 + 0x2a) +// CHECK: 71 21 2a 00 00 00 00 00 r1 = *(u8 *)(r2 + 0x2a) +// CHECK: 69 21 2a 00 00 00 00 00 r1 = *(u16 *)(r2 + 0x2a) +// CHECK: 61 21 2a 00 00 00 00 00 r1 = *(u32 *)(r2 + 0x2a) // CHECK: 79 21 2a 00 00 00 00 00 r1 = *(u64 *)(r2 + 0x2a) r1 = *(u8*)(r2 + 42) r1 = *(u16*)(r2 + 42) r1 = *(u32*)(r2 + 42) r1 = *(u64*)(r2 + 42) -// Note: For the group below w1 is used as a source for sizes u8, u16, u32. -// This is disassembler quirk, but is technically not wrong, as there are -// no different encodings for 'store r1' vs 'store w1'. -// -// CHECK: 73 12 2a 00 00 00 00 00 *(u8 *)(r2 + 0x2a) = w1 -// CHECK: 6b 12 2a 00 00 00 00 00 *(u16 *)(r2 + 0x2a) = w1 -// CHECK: 63 12 2a 00 00 00 00 00 *(u32 *)(r2 + 0x2a) = w1 +// CHECK: 73 12 2a 00 00 00 00 00 *(u8 *)(r2 + 0x2a) = r1 +// CHECK: 6b 12 2a 00 00 00 00 00 *(u16 *)(r2 + 0x2a) = r1 +// CHECK: 63 12 2a 00 00 00 00 00 *(u32 *)(r2 + 0x2a) = r1 // CHECK: 7b 12 2a 00 00 00 00 00 *(u64 *)(r2 + 0x2a) = r1 *(u8*)(r2 + 42) = r1 *(u16*)(r2 + 42) = r1 diff --git a/llvm/test/CodeGen/BPF/disassemble-mcpu-v3.s b/llvm/test/CodeGen/BPF/disassemble-mcpu-v3.s --- a/llvm/test/CodeGen/BPF/disassemble-mcpu-v3.s +++ b/llvm/test/CodeGen/BPF/disassemble-mcpu-v3.s @@ -7,12 +7,12 @@ // RUN: llvm-objdump -d --mcpu=v2 %t | FileCheck %s --check-prefix=V2 // RUN: llvm-objdump -d --mcpu=v3 %t | FileCheck %s --check-prefix=V3 -w0 = *(u32 *)(r1 + 0) +r0 = *(u32 *)(r1 + 0) lock *(u32 *)(r1 + 0x1) &= w2 // V2: 61 10 00 00 00 00 00 00 r0 = *(u32 *)(r1 + 0x0) // V2: c3 21 01 00 50 00 00 00 -// V3: 61 10 00 00 00 00 00 00 w0 = *(u32 *)(r1 + 0x0) +// V3: 61 10 00 00 00 00 00 00 r0 = *(u32 *)(r1 + 0x0) // V3: c3 21 01 00 50 00 00 00 lock *(u32 *)(r1 + 0x1) &= w2 diff --git a/llvm/test/CodeGen/BPF/is_trunc_free.ll b/llvm/test/CodeGen/BPF/is_trunc_free.ll --- a/llvm/test/CodeGen/BPF/is_trunc_free.ll +++ b/llvm/test/CodeGen/BPF/is_trunc_free.ll @@ -57,7 +57,7 @@ ret i32 %retval.0 } -; CHECK: w{{[0-9]+}} = *(u32 *)(r{{[0-9]+}} + 0) +; CHECK: r{{[0-9]+}} = *(u32 *)(r{{[0-9]+}} + 0) ; CHECK-NOT: w{{[0-9]+}} = w{{[0-9]+}} declare dso_local i32 @work(ptr, i32) local_unnamed_addr #1 diff --git a/llvm/test/CodeGen/BPF/ldsx.ll b/llvm/test/CodeGen/BPF/ldsx.ll --- a/llvm/test/CodeGen/BPF/ldsx.ll +++ b/llvm/test/CodeGen/BPF/ldsx.ll @@ -48,7 +48,7 @@ %0 = load i32, ptr %p, align 4, !tbaa !8 ret i32 %0 } -; CHECK: w0 = *(u32 *)(r1 + 0) # encoding: [0x61,0x10,0x00,0x00,0x00,0x00,0x00,0x00] +; CHECK: r0 = *(u32 *)(r1 + 0) # encoding: [0x61,0x10,0x00,0x00,0x00,0x00,0x00,0x00] ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: read) define dso_local i64 @f4(ptr nocapture noundef readonly %p) local_unnamed_addr #0 { diff --git a/llvm/test/CodeGen/BPF/memcmp.ll b/llvm/test/CodeGen/BPF/memcmp.ll --- a/llvm/test/CodeGen/BPF/memcmp.ll +++ b/llvm/test/CodeGen/BPF/memcmp.ll @@ -49,7 +49,7 @@ ; CHECK-DAG: *(u32 *)(r10 - 12) ; CHECK-DAG: *(u32 *)(r1 + 8) ; CHECK-DAG: *(u32 *)(r1 + 12) -; CHECK-DAG: *(u32 *)(r2 + 16) +; CHECK-DAG: *(u32 *)(r{{[23]}} + 16) ; CHECK-DAG: *(u32 *)(r10 - 4) ; Function Attrs: argmemonly mustprogress nofree nosync nounwind willreturn diff --git a/llvm/test/CodeGen/BPF/remove_truncate_7.ll b/llvm/test/CodeGen/BPF/remove_truncate_7.ll --- a/llvm/test/CodeGen/BPF/remove_truncate_7.ll +++ b/llvm/test/CodeGen/BPF/remove_truncate_7.ll @@ -48,7 +48,7 @@ ret ptr %p.0 } -; CHECK: w0 = *(u32 *)(r2 + 0) -; CHECK: w0 = *(u32 *)(r2 + 4) +; CHECK: r0 = *(u32 *)(r2 + 0) +; CHECK: r0 = *(u32 *)(r2 + 4) ; CHECK-NOT: r[[#]] = w[[#]] ; CHECK: exit diff --git a/llvm/test/CodeGen/BPF/rodata_5.ll b/llvm/test/CodeGen/BPF/rodata_5.ll --- a/llvm/test/CodeGen/BPF/rodata_5.ll +++ b/llvm/test/CodeGen/BPF/rodata_5.ll @@ -34,8 +34,8 @@ } ; CHECK-NOT: w{{[0-9]+}} = *(u16 *) ; CHECK-NOT: w{{[0-9]+}} = *(u8 *) -; CHECK: *(u16 *)(r10 - 4) = w{{[0-9]+}} -; CHECK: *(u8 *)(r10 - 2) = w{{[0-9]+}} +; CHECK: *(u8 *)(r10 - 2) = r{{[0-9]+}} +; CHECK: *(u16 *)(r10 - 4) = r{{[0-9]+}} ; Function Attrs: argmemonly nounwind willreturn declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) diff --git a/llvm/test/MC/BPF/insn-unit.s b/llvm/test/MC/BPF/insn-unit.s --- a/llvm/test/MC/BPF/insn-unit.s +++ b/llvm/test/MC/BPF/insn-unit.s @@ -34,12 +34,9 @@ r6 = *(u16 *)(r1 + 8) // BPF_LDX | BPF_H r7 = *(u32 *)(r2 + 16) // BPF_LDX | BPF_W r8 = *(u64 *)(r3 - 30) // BPF_LDX | BPF_DW -// CHECK-64: 71 05 00 00 00 00 00 00 r5 = *(u8 *)(r0 + 0) -// CHECK-64: 69 16 08 00 00 00 00 00 r6 = *(u16 *)(r1 + 8) -// CHECK-64: 61 27 10 00 00 00 00 00 r7 = *(u32 *)(r2 + 16) -// CHECK-32: 71 05 00 00 00 00 00 00 w5 = *(u8 *)(r0 + 0) -// CHECK-32: 69 16 08 00 00 00 00 00 w6 = *(u16 *)(r1 + 8) -// CHECK-32: 61 27 10 00 00 00 00 00 w7 = *(u32 *)(r2 + 16) +// CHECK: 71 05 00 00 00 00 00 00 r5 = *(u8 *)(r0 + 0) +// CHECK: 69 16 08 00 00 00 00 00 r6 = *(u16 *)(r1 + 8) +// CHECK: 61 27 10 00 00 00 00 00 r7 = *(u32 *)(r2 + 16) // CHECK: 79 38 e2 ff 00 00 00 00 r8 = *(u64 *)(r3 - 30) // ======== BPF_STX Class ======== @@ -47,12 +44,9 @@ *(u16 *)(r1 + 8) = r8 // BPF_STX | BPF_H *(u32 *)(r2 + 16) = r9 // BPF_STX | BPF_W *(u64 *)(r3 - 30) = r10 // BPF_STX | BPF_DW -// CHECK-64: 73 70 00 00 00 00 00 00 *(u8 *)(r0 + 0) = r7 -// CHECK-64: 6b 81 08 00 00 00 00 00 *(u16 *)(r1 + 8) = r8 -// CHECK-64: 63 92 10 00 00 00 00 00 *(u32 *)(r2 + 16) = r9 -// CHECK-32: 73 70 00 00 00 00 00 00 *(u8 *)(r0 + 0) = w7 -// CHECK-32: 6b 81 08 00 00 00 00 00 *(u16 *)(r1 + 8) = w8 -// CHECK-32: 63 92 10 00 00 00 00 00 *(u32 *)(r2 + 16) = w9 +// CHECK: 73 70 00 00 00 00 00 00 *(u8 *)(r0 + 0) = r7 +// CHECK: 6b 81 08 00 00 00 00 00 *(u16 *)(r1 + 8) = r8 +// CHECK: 63 92 10 00 00 00 00 00 *(u32 *)(r2 + 16) = r9 // CHECK: 7b a3 e2 ff 00 00 00 00 *(u64 *)(r3 - 30) = r10 lock *(u32 *)(r2 + 16) += r9 // BPF_STX | BPF_W | BPF_XADD diff --git a/llvm/test/MC/BPF/load-store-32.s b/llvm/test/MC/BPF/load-store-32.s --- a/llvm/test/MC/BPF/load-store-32.s +++ b/llvm/test/MC/BPF/load-store-32.s @@ -1,28 +1,24 @@ # RUN: llvm-mc -triple bpfel -filetype=obj -o %t %s -# RUN: llvm-objdump --no-print-imm-hex --mattr=+alu32 -d -r %t | FileCheck --check-prefix=CHECK-32 %s -# RUN: llvm-objdump --no-print-imm-hex -d -r %t | FileCheck %s +# RUN: llvm-objdump --no-print-imm-hex --mattr=+alu32 -d -r %t \ +# RUN: | FileCheck --check-prefixes=CHECK,CHECK-32 %s +# RUN: llvm-objdump --no-print-imm-hex -d -r %t \ +# RUN: | FileCheck --check-prefixes=CHECK,CHECK-64 %s // ======== BPF_LDX Class ======== - w5 = *(u8 *)(r0 + 0) // BPF_LDX | BPF_B - w6 = *(u16 *)(r1 + 8) // BPF_LDX | BPF_H - w7 = *(u32 *)(r2 + 16) // BPF_LDX | BPF_W -// CHECK-32: 71 05 00 00 00 00 00 00 w5 = *(u8 *)(r0 + 0) -// CHECK-32: 69 16 08 00 00 00 00 00 w6 = *(u16 *)(r1 + 8) -// CHECK-32: 61 27 10 00 00 00 00 00 w7 = *(u32 *)(r2 + 16) + r5 = *(u8 *)(r0 + 0) // BPF_LDX | BPF_B + r6 = *(u16 *)(r1 + 8) // BPF_LDX | BPF_H + r7 = *(u32 *)(r2 + 16) // BPF_LDX | BPF_W // CHECK: 71 05 00 00 00 00 00 00 r5 = *(u8 *)(r0 + 0) // CHECK: 69 16 08 00 00 00 00 00 r6 = *(u16 *)(r1 + 8) // CHECK: 61 27 10 00 00 00 00 00 r7 = *(u32 *)(r2 + 16) // ======== BPF_STX Class ======== - *(u8 *)(r0 + 0) = w7 // BPF_STX | BPF_B - *(u16 *)(r1 + 8) = w8 // BPF_STX | BPF_H - *(u32 *)(r2 + 16) = w9 // BPF_STX | BPF_W + *(u8 *)(r0 + 0) = r7 // BPF_STX | BPF_B + *(u16 *)(r1 + 8) = r8 // BPF_STX | BPF_H + *(u32 *)(r2 + 16) = r9 // BPF_STX | BPF_W lock *(u32 *)(r2 + 16) += w9 // BPF_STX | BPF_W | BPF_XADD -// CHECK-32: 73 70 00 00 00 00 00 00 *(u8 *)(r0 + 0) = w7 -// CHECK-32: 6b 81 08 00 00 00 00 00 *(u16 *)(r1 + 8) = w8 -// CHECK-32: 63 92 10 00 00 00 00 00 *(u32 *)(r2 + 16) = w9 -// CHECK-32: c3 92 10 00 00 00 00 00 lock *(u32 *)(r2 + 16) += w9 // CHECK: 73 70 00 00 00 00 00 00 *(u8 *)(r0 + 0) = r7 // CHECK: 6b 81 08 00 00 00 00 00 *(u16 *)(r1 + 8) = r8 // CHECK: 63 92 10 00 00 00 00 00 *(u32 *)(r2 + 16) = r9 -// CHECK: c3 92 10 00 00 00 00 00 lock *(u32 *)(r2 + 16) += r9 +// CHECK-32: c3 92 10 00 00 00 00 00 lock *(u32 *)(r2 + 16) += w9 +// CHECK-64: c3 92 10 00 00 00 00 00 lock *(u32 *)(r2 + 16) += r9