Index: llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -462,6 +462,14 @@
 
   bool SelectCVTFixedPosOperand(SDValue N, SDValue &FixedPos, unsigned Width);
 
+  template<unsigned RegWidth>
+  bool SelectCVTFixedPosRecipOperand(SDValue N, SDValue &FixedPos) {
+    return SelectCVTFixedPosRecipOperand(N, FixedPos, RegWidth);
+  }
+
+  bool SelectCVTFixedPosRecipOperand(SDValue N, SDValue &FixedPos,
+                                     unsigned Width);
+
   bool SelectCMP_SWAP(SDNode *N);
 
   bool SelectSVEAddSubImm(SDValue N, MVT VT, SDValue &Imm, SDValue &Shift);
@@ -3669,6 +3677,60 @@
   return true;
 }
 
+bool AArch64DAGToDAGISel::SelectCVTFixedPosRecipOperand(SDValue N,
+                                                        SDValue &FixedPos,
+                                                        unsigned RegWidth) {
+  const TargetOptions &Options = CurDAG->getTarget().Options;
+  SDNodeFlags Flags = N.getNode()->getFlags();
+  if (!Options.UnsafeFPMath && !Flags.hasAllowReciprocal())
+    return false;
+
+  APFloat FVal(0.0);
+  if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N))
+    FVal = CN->getValueAPF();
+  else if (LoadSDNode *LN = dyn_cast<LoadSDNode>(N)) {
+    // Some otherwise illegal constants are allowed in this case.
+    if (LN->getOperand(1).getOpcode() != AArch64ISD::ADDlow ||
+        !isa<ConstantPoolSDNode>(LN->getOperand(1)->getOperand(1)))
+      return false;
+
+    ConstantPoolSDNode *CN =
+        dyn_cast<ConstantPoolSDNode>(LN->getOperand(1)->getOperand(1));
+    FVal = cast<ConstantFP>(CN->getConstVal())->getValueAPF();
+  } else
+    return false;
+
+  // An SCVTF instruction performs: convertToInt(Val * (1/2^fbits)) where
+  // fbits is between 1 and 32 for a destination w-register, or 1 and 64 for an
+  // x-register.
+  //
+  // By this stage, we've detected (fp_to_[su]int (fmul Val, THIS_NODE)) so we
+  // want THIS_NODE to be 1/2^fbits. This is much easier to deal with using
+  // integers.
+  bool IsExact;
+
+  APFloat InverseFVal(0.0);
+  if (!FVal.getExactInverse(&InverseFVal))
+    return false;
+
+  // fbits is between 1 and 64 in the worst-case, which means the fmul
+  // could have 2^64 as an actual operand. Need 65 bits of precision.
+  APSInt IntVal(65, true);
+  InverseFVal.convertToInteger(IntVal, APFloat::rmTowardZero, &IsExact);
+
+  // N.b. isPowerOf2 also checks for > 0.
+  if (!IsExact || !IntVal.isPowerOf2())
+    return false;
+  unsigned FBits = IntVal.logBase2();
+
+  // Checks above should have guaranteed that we haven't lost information in
+  // finding FBits, but it must still be in range.
+  if (FBits == 0 || FBits > RegWidth) return false;
+
+  FixedPos = CurDAG->getTargetConstant(FBits, SDLoc(N), MVT::i32);
+  return true;
+}
+
 // Inspects a register string of the form o0:op1:CRn:CRm:op2 gets the fields
 // of the string and obtains the integer values from them and combines these
 // into a single value to be used in the MRS/MSR instruction.
Index: llvm/lib/Target/AArch64/AArch64InstrFormats.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -703,6 +703,30 @@
 def fixedpoint_f32_i64 : fixedpoint_i64<f32>;
 def fixedpoint_f64_i64 : fixedpoint_i64<f64>;
 
+class fixedpoint_recip_i32<ValueType FloatVT>
+  : Operand<FloatVT>,
+    ComplexPattern<FloatVT, 1, "SelectCVTFixedPosRecipOperand<32>", [fpimm, ld]> {
+  let EncoderMethod = "getFixedPointScaleOpValue";
+  let DecoderMethod = "DecodeFixedPointScaleImm32";
+  let ParserMatchClass = Imm1_32Operand;
+}
+
+class fixedpoint_recip_i64<ValueType FloatVT>
+  : Operand<FloatVT>,
+    ComplexPattern<FloatVT, 1, "SelectCVTFixedPosRecipOperand<64>", [fpimm, ld]> {
+  let EncoderMethod = "getFixedPointScaleOpValue";
+  let DecoderMethod = "DecodeFixedPointScaleImm64";
+  let ParserMatchClass = Imm1_64Operand;
+}
+
+def fixedpoint_recip_f16_i32 : fixedpoint_recip_i32<f16>;
+def fixedpoint_recip_f32_i32 : fixedpoint_recip_i32<f32>;
+def fixedpoint_recip_f64_i32 : fixedpoint_recip_i32<f64>;
+
+def fixedpoint_recip_f16_i64 : fixedpoint_recip_i64<f16>;
+def fixedpoint_recip_f32_i64 : fixedpoint_recip_i64<f32>;
+def fixedpoint_recip_f64_i64 : fixedpoint_recip_i64<f64>;
+
 def vecshiftR8 : Operand<i32>, ImmLeaf<i32, [{
   return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9);
 }]> {
@@ -4981,8 +5005,8 @@
   // Scaled
   def SWHri: BaseIntegerToFP<isUnsigned, GPR32, FPR16, fixedpoint_f16_i32, asm,
                              [(set (f16 FPR16:$Rd),
-                                   (fdiv (node GPR32:$Rn),
-                                         fixedpoint_f16_i32:$scale))]> {
+                                   (fmul (node GPR32:$Rn),
+                                         fixedpoint_recip_f16_i32:$scale))]> {
     let Inst{31} = 0; // 32-bit GPR flag
     let Inst{23-22} = 0b11; // 16-bit FPR flag
     let scale{5} = 1;
@@ -4991,8 +5015,8 @@
 
   def SWSri: BaseIntegerToFP<isUnsigned, GPR32, FPR32, fixedpoint_f32_i32, asm,
                              [(set FPR32:$Rd,
-                                   (fdiv (node GPR32:$Rn),
-                                         fixedpoint_f32_i32:$scale))]> {
+                                   (fmul (node GPR32:$Rn),
+                                         fixedpoint_recip_f32_i32:$scale))]> {
     let Inst{31} = 0; // 32-bit GPR flag
     let Inst{23-22} = 0b00; // 32-bit FPR flag
     let scale{5} = 1;
@@ -5000,8 +5024,8 @@
 
   def SWDri: BaseIntegerToFP<isUnsigned, GPR32, FPR64, fixedpoint_f64_i32, asm,
                              [(set FPR64:$Rd,
-                                   (fdiv (node GPR32:$Rn),
-                                         fixedpoint_f64_i32:$scale))]> {
+                                   (fmul (node GPR32:$Rn),
+                                         fixedpoint_recip_f64_i32:$scale))]> {
     let Inst{31} = 0; // 32-bit GPR flag
     let Inst{23-22} = 0b01; // 64-bit FPR flag
     let scale{5} = 1;
@@ -5009,8 +5033,8 @@
 
   def SXHri: BaseIntegerToFP<isUnsigned, GPR64, FPR16, fixedpoint_f16_i64, asm,
                              [(set (f16 FPR16:$Rd),
-                                   (fdiv (node GPR64:$Rn),
-                                         fixedpoint_f16_i64:$scale))]> {
+                                   (fmul (node GPR64:$Rn),
+                                         fixedpoint_recip_f16_i64:$scale))]> {
     let Inst{31} = 1; // 64-bit GPR flag
     let Inst{23-22} = 0b11; // 16-bit FPR flag
     let Predicates = [HasFullFP16];
@@ -5018,16 +5042,16 @@
 
   def SXSri: BaseIntegerToFP<isUnsigned, GPR64, FPR32, fixedpoint_f32_i64, asm,
                              [(set FPR32:$Rd,
-                                   (fdiv (node GPR64:$Rn),
-                                         fixedpoint_f32_i64:$scale))]> {
+                                   (fmul (node GPR64:$Rn),
+                                         fixedpoint_recip_f32_i64:$scale))]> {
     let Inst{31} = 1; // 64-bit GPR flag
     let Inst{23-22} = 0b00; // 32-bit FPR flag
   }
 
   def SXDri: BaseIntegerToFP<isUnsigned, GPR64, FPR64, fixedpoint_f64_i64, asm,
                              [(set FPR64:$Rd,
-                                   (fdiv (node GPR64:$Rn),
-                                         fixedpoint_f64_i64:$scale))]> {
+                                   (fmul (node GPR64:$Rn),
+                                         fixedpoint_recip_f64_i64:$scale))]> {
     let Inst{31} = 1; // 64-bit GPR flag
     let Inst{23-22} = 0b01; // 64-bit FPR flag
   }
Index: llvm/test/CodeGen/AArch64/fcvt-fixed.ll
===================================================================
--- llvm/test/CodeGen/AArch64/fcvt-fixed.ll
+++ llvm/test/CodeGen/AArch64/fcvt-fixed.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s --check-prefixes=CHECK,CHECK-NO16
 ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FP16
+; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -enable-unsafe-fp-math | FileCheck %s --check-prefixes=CHECK-NO16-UNSAFE-FPMATH
+; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=+fullfp16 -enable-unsafe-fp-math | FileCheck %s --check-prefixes=CHECK-FP16-UNSAFE-FPMATH
 
 ; fptoui
 
@@ -9,6 +11,16 @@
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs w0, s0, #7
 ; CHECK-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: fcvtzs_f32_i32_7:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvtzs w0, s0, #7
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: fcvtzs_f32_i32_7:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fcvtzs w0, s0, #7
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %fix = fmul float %flt, 128.0
   %cvt = fptosi float %fix to i32
   ret i32 %cvt
@@ -19,6 +31,16 @@
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs w0, s0, #32
 ; CHECK-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: fcvtzs_f32_i32_32:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvtzs w0, s0, #32
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: fcvtzs_f32_i32_32:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fcvtzs w0, s0, #32
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %fix = fmul float %flt, 4294967296.0
   %cvt = fptosi float %fix to i32
   ret i32 %cvt
@@ -29,6 +51,16 @@
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs x0, s0, #7
 ; CHECK-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: fcvtzs_f32_i64_7:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvtzs x0, s0, #7
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: fcvtzs_f32_i64_7:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fcvtzs x0, s0, #7
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %fix = fmul float %flt, 128.0
   %cvt = fptosi float %fix to i64
   ret i64 %cvt
@@ -39,6 +71,16 @@
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs x0, s0, #64
 ; CHECK-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: fcvtzs_f32_i64_64:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvtzs x0, s0, #64
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: fcvtzs_f32_i64_64:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fcvtzs x0, s0, #64
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %fix = fmul float %flt, 18446744073709551616.0
   %cvt = fptosi float %fix to i64
   ret i64 %cvt
@@ -49,6 +91,16 @@
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs w0, d0, #7
 ; CHECK-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: fcvtzs_f64_i32_7:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvtzs w0, d0, #7
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: fcvtzs_f64_i32_7:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fcvtzs w0, d0, #7
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %fix = fmul double %dbl, 128.0
   %cvt = fptosi double %fix to i32
   ret i32 %cvt
@@ -59,6 +111,16 @@
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs w0, d0, #32
 ; CHECK-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: fcvtzs_f64_i32_32:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvtzs w0, d0, #32
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: fcvtzs_f64_i32_32:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fcvtzs w0, d0, #32
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %fix = fmul double %dbl, 4294967296.0
   %cvt = fptosi double %fix to i32
   ret i32 %cvt
@@ -69,6 +131,16 @@
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs x0, d0, #7
 ; CHECK-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: fcvtzs_f64_i64_7:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvtzs x0, d0, #7
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: fcvtzs_f64_i64_7:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fcvtzs x0, d0, #7
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %fix = fmul double %dbl, 128.0
   %cvt = fptosi double %fix to i64
   ret i64 %cvt
@@ -79,6 +151,16 @@
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs x0, d0, #64
 ; CHECK-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: fcvtzs_f64_i64_64:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvtzs x0, d0, #64
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: fcvtzs_f64_i64_64:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fcvtzs x0, d0, #64
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %fix = fmul double %dbl, 18446744073709551616.0
   %cvt = fptosi double %fix to i64
   ret i64 %cvt
@@ -99,6 +181,21 @@
 ; CHECK-FP16:       // %bb.0:
 ; CHECK-FP16-NEXT:    fcvtzs w0, h0, #7
 ; CHECK-FP16-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: fcvtzs_f16_i32_7:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    movi v1.2s, #67, lsl #24
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt s0, h0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fmul s0, s0, s1
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt h0, s0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt s0, h0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvtzs w0, s0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: fcvtzs_f16_i32_7:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fcvtzs w0, h0, #7
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %fix = fmul half %flt, 128.0
   %cvt = fptosi half %fix to i32
   ret i32 %cvt
@@ -119,6 +216,21 @@
 ; CHECK-FP16:       // %bb.0:
 ; CHECK-FP16-NEXT:    fcvtzs w0, h0, #15
 ; CHECK-FP16-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: fcvtzs_f16_i32_15:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    movi v1.2s, #71, lsl #24
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt s0, h0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fmul s0, s0, s1
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt h0, s0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt s0, h0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvtzs w0, s0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: fcvtzs_f16_i32_15:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fcvtzs w0, h0, #15
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %fix = fmul half %flt, 32768.0
   %cvt = fptosi half %fix to i32
   ret i32 %cvt
@@ -139,6 +251,21 @@
 ; CHECK-FP16:       // %bb.0:
 ; CHECK-FP16-NEXT:    fcvtzs x0, h0, #7
 ; CHECK-FP16-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: fcvtzs_f16_i64_7:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    movi v1.2s, #67, lsl #24
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt s0, h0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fmul s0, s0, s1
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt h0, s0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt s0, h0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvtzs x0, s0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: fcvtzs_f16_i64_7:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fcvtzs x0, h0, #7
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %fix = fmul half %flt, 128.0
   %cvt = fptosi half %fix to i64
   ret i64 %cvt
@@ -159,6 +286,21 @@
 ; CHECK-FP16:       // %bb.0:
 ; CHECK-FP16-NEXT:    fcvtzs x0, h0, #15
 ; CHECK-FP16-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: fcvtzs_f16_i64_15:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    movi v1.2s, #71, lsl #24
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt s0, h0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fmul s0, s0, s1
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt h0, s0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt s0, h0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvtzs x0, s0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: fcvtzs_f16_i64_15:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fcvtzs x0, h0, #15
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %fix = fmul half %flt, 32768.0
   %cvt = fptosi half %fix to i64
   ret i64 %cvt
@@ -171,6 +313,16 @@
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzu w0, s0, #7
 ; CHECK-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: fcvtzu_f32_i32_7:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvtzu w0, s0, #7
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: fcvtzu_f32_i32_7:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fcvtzu w0, s0, #7
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %fix = fmul float %flt, 128.0
   %cvt = fptoui float %fix to i32
   ret i32 %cvt
@@ -181,6 +333,16 @@
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzu w0, s0, #32
 ; CHECK-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: fcvtzu_f32_i32_32:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvtzu w0, s0, #32
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: fcvtzu_f32_i32_32:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fcvtzu w0, s0, #32
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %fix = fmul float %flt, 4294967296.0
   %cvt = fptoui float %fix to i32
   ret i32 %cvt
@@ -191,6 +353,16 @@
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzu x0, s0, #7
 ; CHECK-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: fcvtzu_f32_i64_7:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvtzu x0, s0, #7
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: fcvtzu_f32_i64_7:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fcvtzu x0, s0, #7
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %fix = fmul float %flt, 128.0
   %cvt = fptoui float %fix to i64
   ret i64 %cvt
@@ -201,6 +373,16 @@
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzu x0, s0, #64
 ; CHECK-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: fcvtzu_f32_i64_64:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvtzu x0, s0, #64
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: fcvtzu_f32_i64_64:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fcvtzu x0, s0, #64
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %fix = fmul float %flt, 18446744073709551616.0
   %cvt = fptoui float %fix to i64
   ret i64 %cvt
@@ -211,6 +393,16 @@
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzu w0, d0, #7
 ; CHECK-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: fcvtzu_f64_i32_7:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvtzu w0, d0, #7
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: fcvtzu_f64_i32_7:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fcvtzu w0, d0, #7
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %fix = fmul double %dbl, 128.0
   %cvt = fptoui double %fix to i32
   ret i32 %cvt
@@ -221,6 +413,16 @@
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzu w0, d0, #32
 ; CHECK-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: fcvtzu_f64_i32_32:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvtzu w0, d0, #32
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: fcvtzu_f64_i32_32:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fcvtzu w0, d0, #32
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %fix = fmul double %dbl, 4294967296.0
   %cvt = fptoui double %fix to i32
   ret i32 %cvt
@@ -231,6 +433,16 @@
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzu x0, d0, #7
 ; CHECK-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: fcvtzu_f64_i64_7:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvtzu x0, d0, #7
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: fcvtzu_f64_i64_7:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fcvtzu x0, d0, #7
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %fix = fmul double %dbl, 128.0
   %cvt = fptoui double %fix to i64
   ret i64 %cvt
@@ -241,6 +453,16 @@
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzu x0, d0, #64
 ; CHECK-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: fcvtzu_f64_i64_64:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvtzu x0, d0, #64
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: fcvtzu_f64_i64_64:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fcvtzu x0, d0, #64
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %fix = fmul double %dbl, 18446744073709551616.0
   %cvt = fptoui double %fix to i64
   ret i64 %cvt
@@ -261,6 +483,21 @@
 ; CHECK-FP16:       // %bb.0:
 ; CHECK-FP16-NEXT:    fcvtzu w0, h0, #7
 ; CHECK-FP16-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: fcvtzu_f16_i32_7:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    movi v1.2s, #67, lsl #24
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt s0, h0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fmul s0, s0, s1
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt h0, s0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt s0, h0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvtzu w0, s0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: fcvtzu_f16_i32_7:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fcvtzu w0, h0, #7
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %fix = fmul half %flt, 128.0
   %cvt = fptoui half %fix to i32
   ret i32 %cvt
@@ -281,6 +518,21 @@
 ; CHECK-FP16:       // %bb.0:
 ; CHECK-FP16-NEXT:    fcvtzu w0, h0, #15
 ; CHECK-FP16-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: fcvtzu_f16_i32_15:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    movi v1.2s, #71, lsl #24
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt s0, h0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fmul s0, s0, s1
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt h0, s0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt s0, h0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvtzu w0, s0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: fcvtzu_f16_i32_15:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fcvtzu w0, h0, #15
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %fix = fmul half %flt, 32768.0
   %cvt = fptoui half %fix to i32
   ret i32 %cvt
@@ -301,6 +553,21 @@
 ; CHECK-FP16:       // %bb.0:
 ; CHECK-FP16-NEXT:    fcvtzu x0, h0, #7
 ; CHECK-FP16-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: fcvtzu_f16_i64_7:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    movi v1.2s, #67, lsl #24
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt s0, h0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fmul s0, s0, s1
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt h0, s0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt s0, h0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvtzu x0, s0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: fcvtzu_f16_i64_7:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fcvtzu x0, h0, #7
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %fix = fmul half %flt, 128.0
   %cvt = fptoui half %fix to i64
   ret i64 %cvt
@@ -321,6 +588,21 @@
 ; CHECK-FP16:       // %bb.0:
 ; CHECK-FP16-NEXT:    fcvtzu x0, h0, #15
 ; CHECK-FP16-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: fcvtzu_f16_i64_15:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    movi v1.2s, #71, lsl #24
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt s0, h0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fmul s0, s0, s1
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt h0, s0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt s0, h0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvtzu x0, s0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: fcvtzu_f16_i64_15:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fcvtzu x0, h0, #15
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %fix = fmul half %flt, 32768.0
   %cvt = fptoui half %fix to i64
   ret i64 %cvt
@@ -329,80 +611,214 @@
 ; sitofp
 
 define float @scvtf_f32_i32_7(i32 %int) {
+; CHECK-UNSAFE-FPMATH-LABEL: scvtf_f32_i32_7:
+; CHECK-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-UNSAFE-FPMATH-NEXT:    scvtf s0, w0, #7
+; CHECK-UNSAFE-FPMATH-NEXT:    ret
 ; CHECK-LABEL: scvtf_f32_i32_7:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    scvtf s0, w0, #7
+; CHECK-NEXT:    movi v0.2s, #67, lsl #24
+; CHECK-NEXT:    scvtf s1, w0
+; CHECK-NEXT:    fdiv s0, s1, s0
 ; CHECK-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: scvtf_f32_i32_7:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    scvtf s0, w0, #7
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: scvtf_f32_i32_7:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    scvtf s0, w0, #7
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %cvt = sitofp i32 %int to float
   %fix = fdiv float %cvt, 128.0
   ret float %fix
 }
 
 define float @scvtf_f32_i32_32(i32 %int) {
+; CHECK-UNSAFE-FPMATH-LABEL: scvtf_f32_i32_32:
+; CHECK-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-UNSAFE-FPMATH-NEXT:    scvtf s0, w0, #32
+; CHECK-UNSAFE-FPMATH-NEXT:    ret
 ; CHECK-LABEL: scvtf_f32_i32_32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    scvtf s0, w0, #32
+; CHECK-NEXT:    mov w8, #1333788672 // =0x4f800000
+; CHECK-NEXT:    scvtf s0, w0
+; CHECK-NEXT:    fmov s1, w8
+; CHECK-NEXT:    fdiv s0, s0, s1
 ; CHECK-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: scvtf_f32_i32_32:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    scvtf s0, w0, #32
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: scvtf_f32_i32_32:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    scvtf s0, w0, #32
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %cvt = sitofp i32 %int to float
   %fix = fdiv float %cvt, 4294967296.0
   ret float %fix
 }
 
 define float @scvtf_f32_i64_7(i64 %long) {
+; CHECK-UNSAFE-FPMATH-LABEL: scvtf_f32_i64_7:
+; CHECK-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-UNSAFE-FPMATH-NEXT:    scvtf s0, x0, #7
+; CHECK-UNSAFE-FPMATH-NEXT:    ret
 ; CHECK-LABEL: scvtf_f32_i64_7:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    scvtf s0, x0, #7
+; CHECK-NEXT:    movi v0.2s, #67, lsl #24
+; CHECK-NEXT:    scvtf s1, x0
+; CHECK-NEXT:    fdiv s0, s1, s0
 ; CHECK-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: scvtf_f32_i64_7:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    scvtf s0, x0, #7
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: scvtf_f32_i64_7:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    scvtf s0, x0, #7
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %cvt = sitofp i64 %long to float
   %fix = fdiv float %cvt, 128.0
   ret float %fix
 }
 
 define float @scvtf_f32_i64_64(i64 %long) {
+; CHECK-UNSAFE-FPMATH-LABEL: scvtf_f32_i64_64:
+; CHECK-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-UNSAFE-FPMATH-NEXT:    scvtf s0, x0, #64
+; CHECK-UNSAFE-FPMATH-NEXT:    ret
 ; CHECK-LABEL: scvtf_f32_i64_64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    scvtf s0, x0, #64
+; CHECK-NEXT:    mov w8, #1602224128 // =0x5f800000
+; CHECK-NEXT:    scvtf s0, x0
+; CHECK-NEXT:    fmov s1, w8
+; CHECK-NEXT:    fdiv s0, s0, s1
 ; CHECK-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: scvtf_f32_i64_64:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    scvtf s0, x0, #64
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: scvtf_f32_i64_64:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    scvtf s0, x0, #64
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %cvt = sitofp i64 %long to float
   %fix = fdiv float %cvt, 18446744073709551616.0
   ret float %fix
 }
 
 define double @scvtf_f64_i32_7(i32 %int) {
+; CHECK-UNSAFE-FPMATH-LABEL: scvtf_f64_i32_7:
+; CHECK-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-UNSAFE-FPMATH-NEXT:    scvtf d0, w0, #7
+; CHECK-UNSAFE-FPMATH-NEXT:    ret
 ; CHECK-LABEL: scvtf_f64_i32_7:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    scvtf d0, w0, #7
+; CHECK-NEXT:    mov x8, #4638707616191610880 // =0x4060000000000000
+; CHECK-NEXT:    scvtf d0, w0
+; CHECK-NEXT:    fmov d1, x8
+; CHECK-NEXT:    fdiv d0, d0, d1
 ; CHECK-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: scvtf_f64_i32_7:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    scvtf d0, w0, #7
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: scvtf_f64_i32_7:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    scvtf d0, w0, #7
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %cvt = sitofp i32 %int to double
   %fix = fdiv double %cvt, 128.0
   ret double %fix
 }
 
 define double @scvtf_f64_i32_32(i32 %int) {
+; CHECK-UNSAFE-FPMATH-LABEL: scvtf_f64_i32_32:
+; CHECK-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-UNSAFE-FPMATH-NEXT:    scvtf d0, w0, #32
+; CHECK-UNSAFE-FPMATH-NEXT:    ret
 ; CHECK-LABEL: scvtf_f64_i32_32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    scvtf d0, w0, #32
+; CHECK-NEXT:    mov x8, #4751297606875873280 // =0x41f0000000000000
+; CHECK-NEXT:    scvtf d0, w0
+; CHECK-NEXT:    fmov d1, x8
+; CHECK-NEXT:    fdiv d0, d0, d1
 ; CHECK-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: scvtf_f64_i32_32:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    scvtf d0, w0, #32
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: scvtf_f64_i32_32:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    scvtf d0, w0, #32
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %cvt = sitofp i32 %int to double
   %fix = fdiv double %cvt, 4294967296.0
   ret double %fix
 }
 
 define double @scvtf_f64_i64_7(i64 %long) {
+; CHECK-UNSAFE-FPMATH-LABEL: scvtf_f64_i64_7:
+; CHECK-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-UNSAFE-FPMATH-NEXT:    scvtf d0, x0, #7
+; CHECK-UNSAFE-FPMATH-NEXT:    ret
 ; CHECK-LABEL: scvtf_f64_i64_7:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    scvtf d0, x0, #7
+; CHECK-NEXT:    mov x8, #4638707616191610880 // =0x4060000000000000
+; CHECK-NEXT:    scvtf d0, x0
+; CHECK-NEXT:    fmov d1, x8
+; CHECK-NEXT:    fdiv d0, d0, d1
 ; CHECK-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: scvtf_f64_i64_7:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    scvtf d0, x0, #7
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: scvtf_f64_i64_7:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    scvtf d0, x0, #7
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %cvt = sitofp i64 %long to double
   %fix = fdiv double %cvt, 128.0
   ret double %fix
 }
 
 define double @scvtf_f64_i64_64(i64 %long) {
+; CHECK-UNSAFE-FPMATH-LABEL: scvtf_f64_i64_64:
+; CHECK-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-UNSAFE-FPMATH-NEXT:    scvtf d0, x0, #64
+; CHECK-UNSAFE-FPMATH-NEXT:    ret
 ; CHECK-LABEL: scvtf_f64_i64_64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    scvtf d0, x0, #64
+; CHECK-NEXT:    mov x8, #4895412794951729152 // =0x43f0000000000000
+; CHECK-NEXT:    scvtf d0, x0
+; CHECK-NEXT:    fmov d1, x8
+; CHECK-NEXT:    fdiv d0, d0, d1
 ; CHECK-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: scvtf_f64_i64_64:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    scvtf d0, x0, #64
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: scvtf_f64_i64_64:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    scvtf d0, x0, #64
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %cvt = sitofp i64 %long to double
   %fix = fdiv double %cvt, 18446744073709551616.0
   ret double %fix
@@ -421,8 +837,26 @@
 ;
 ; CHECK-FP16-LABEL: scvtf_f16_i32_7:
 ; CHECK-FP16:       // %bb.0:
-; CHECK-FP16-NEXT:    scvtf h0, w0, #7
+; CHECK-FP16-NEXT:    mov w8, #22528 // =0x5800
+; CHECK-FP16-NEXT:    scvtf h0, w0
+; CHECK-FP16-NEXT:    fmov h1, w8
+; CHECK-FP16-NEXT:    fdiv h0, h0, h1
 ; CHECK-FP16-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: scvtf_f16_i32_7:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    scvtf s1, w0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    movi v0.2s, #60, lsl #24
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt h1, s1
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt s1, h1
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fmul s0, s1, s0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt h0, s0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: scvtf_f16_i32_7:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    scvtf h0, w0, #7
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %cvt = sitofp i32 %int to half
   %fix = fdiv half %cvt, 128.0
   ret half %fix
@@ -441,8 +875,29 @@
 ;
 ; CHECK-FP16-LABEL: scvtf_f16_i32_15:
 ; CHECK-FP16:       // %bb.0:
-; CHECK-FP16-NEXT:    scvtf h0, w0, #15
+; CHECK-FP16-NEXT:    mov w8, #30720 // =0x7800
+; CHECK-FP16-NEXT:    scvtf h0, w0
+; CHECK-FP16-NEXT:    fmov h1, w8
+; CHECK-FP16-NEXT:    fdiv h0, h0, h1
 ; CHECK-FP16-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: scvtf_f16_i32_15:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    scvtf s1, w0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    movi v0.2s, #56, lsl #24
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt h1, s1
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt s1, h1
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fmul s0, s1, s0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt h0, s0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: scvtf_f16_i32_15:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    mov w8, #512 // =0x200
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    scvtf h0, w0
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fmov h1, w8
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fmul h0, h0, h1
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %cvt = sitofp i32 %int to half
   %fix = fdiv half %cvt, 32768.0
   ret half %fix
@@ -461,8 +916,26 @@
 ;
 ; CHECK-FP16-LABEL: scvtf_f16_i64_7:
 ; CHECK-FP16:       // %bb.0:
-; CHECK-FP16-NEXT:    scvtf h0, x0, #7
+; CHECK-FP16-NEXT:    mov w8, #22528 // =0x5800
+; CHECK-FP16-NEXT:    scvtf h0, x0
+; CHECK-FP16-NEXT:    fmov h1, w8
+; CHECK-FP16-NEXT:    fdiv h0, h0, h1
 ; CHECK-FP16-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: scvtf_f16_i64_7:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    scvtf s1, x0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    movi v0.2s, #60, lsl #24
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt h1, s1
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt s1, h1
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fmul s0, s1, s0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt h0, s0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: scvtf_f16_i64_7:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    scvtf h0, x0, #7
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %cvt = sitofp i64 %long to half
   %fix = fdiv half %cvt, 128.0
   ret half %fix
@@ -481,8 +954,29 @@
 ;
 ; CHECK-FP16-LABEL: scvtf_f16_i64_15:
 ; CHECK-FP16:       // %bb.0:
-; CHECK-FP16-NEXT:    scvtf h0, x0, #15
+; CHECK-FP16-NEXT:    mov w8, #30720 // =0x7800
+; CHECK-FP16-NEXT:    scvtf h0, x0
+; CHECK-FP16-NEXT:    fmov h1, w8
+; CHECK-FP16-NEXT:    fdiv h0, h0, h1
 ; CHECK-FP16-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: scvtf_f16_i64_15:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    scvtf s1, x0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    movi v0.2s, #56, lsl #24
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt h1, s1
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt s1, h1
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fmul s0, s1, s0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt h0, s0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: scvtf_f16_i64_15:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    mov w8, #512 // =0x200
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    scvtf h0, x0
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fmov h1, w8
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fmul h0, h0, h1
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %cvt = sitofp i64 %long to half
   %fix = fdiv half %cvt, 32768.0
   ret half %fix
@@ -491,80 +985,214 @@
 ; uitofp
 
 define float @ucvtf_f32_i32_7(i32 %int) {
+; CHECK-UNSAFE-FPMATH-LABEL: ucvtf_f32_i32_7:
+; CHECK-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-UNSAFE-FPMATH-NEXT:    ucvtf s0, w0, #7
+; CHECK-UNSAFE-FPMATH-NEXT:    ret
 ; CHECK-LABEL: ucvtf_f32_i32_7:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ucvtf s0, w0, #7
+; CHECK-NEXT:    movi v0.2s, #67, lsl #24
+; CHECK-NEXT:    ucvtf s1, w0
+; CHECK-NEXT:    fdiv s0, s1, s0
 ; CHECK-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: ucvtf_f32_i32_7:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ucvtf s0, w0, #7
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: ucvtf_f32_i32_7:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ucvtf s0, w0, #7
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %cvt = uitofp i32 %int to float
   %fix = fdiv float %cvt, 128.0
   ret float %fix
 }
 
 define float @ucvtf_f32_i32_32(i32 %int) {
+; CHECK-UNSAFE-FPMATH-LABEL: ucvtf_f32_i32_32:
+; CHECK-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-UNSAFE-FPMATH-NEXT:    ucvtf s0, w0, #32
+; CHECK-UNSAFE-FPMATH-NEXT:    ret
 ; CHECK-LABEL: ucvtf_f32_i32_32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ucvtf s0, w0, #32
+; CHECK-NEXT:    mov w8, #1333788672 // =0x4f800000
+; CHECK-NEXT:    ucvtf s0, w0
+; CHECK-NEXT:    fmov s1, w8
+; CHECK-NEXT:    fdiv s0, s0, s1
 ; CHECK-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: ucvtf_f32_i32_32:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ucvtf s0, w0, #32
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: ucvtf_f32_i32_32:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ucvtf s0, w0, #32
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %cvt = uitofp i32 %int to float
   %fix = fdiv float %cvt, 4294967296.0
   ret float %fix
 }
 
 define float @ucvtf_f32_i64_7(i64 %long) {
+; CHECK-UNSAFE-FPMATH-LABEL: ucvtf_f32_i64_7:
+; CHECK-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-UNSAFE-FPMATH-NEXT:    ucvtf s0, x0, #7
+; CHECK-UNSAFE-FPMATH-NEXT:    ret
 ; CHECK-LABEL: ucvtf_f32_i64_7:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ucvtf s0, x0, #7
+; CHECK-NEXT:    movi v0.2s, #67, lsl #24
+; CHECK-NEXT:    ucvtf s1, x0
+; CHECK-NEXT:    fdiv s0, s1, s0
 ; CHECK-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: ucvtf_f32_i64_7:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ucvtf s0, x0, #7
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: ucvtf_f32_i64_7:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ucvtf s0, x0, #7
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %cvt = uitofp i64 %long to float
   %fix = fdiv float %cvt, 128.0
   ret float %fix
 }
 
 define float @ucvtf_f32_i64_64(i64 %long) {
+; CHECK-UNSAFE-FPMATH-LABEL: ucvtf_f32_i64_64:
+; CHECK-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-UNSAFE-FPMATH-NEXT:    ucvtf s0, x0, #64
+; CHECK-UNSAFE-FPMATH-NEXT:    ret
 ; CHECK-LABEL: ucvtf_f32_i64_64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ucvtf s0, x0, #64
+; CHECK-NEXT:    mov w8, #1602224128 // =0x5f800000
+; CHECK-NEXT:    ucvtf s0, x0
+; CHECK-NEXT:    fmov s1, w8
+; CHECK-NEXT:    fdiv s0, s0, s1
 ; CHECK-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: ucvtf_f32_i64_64:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ucvtf s0, x0, #64
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: ucvtf_f32_i64_64:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ucvtf s0, x0, #64
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %cvt = uitofp i64 %long to float
   %fix = fdiv float %cvt, 18446744073709551616.0
   ret float %fix
 }
 
 define double @ucvtf_f64_i32_7(i32 %int) {
+; CHECK-UNSAFE-FPMATH-LABEL: ucvtf_f64_i32_7:
+; CHECK-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-UNSAFE-FPMATH-NEXT:    ucvtf d0, w0, #7
+; CHECK-UNSAFE-FPMATH-NEXT:    ret
 ; CHECK-LABEL: ucvtf_f64_i32_7:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ucvtf d0, w0, #7
+; CHECK-NEXT:    mov x8, #4638707616191610880 // =0x4060000000000000
+; CHECK-NEXT:    ucvtf d0, w0
+; CHECK-NEXT:    fmov d1, x8
+; CHECK-NEXT:    fdiv d0, d0, d1
 ; CHECK-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: ucvtf_f64_i32_7:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ucvtf d0, w0, #7
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: ucvtf_f64_i32_7:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ucvtf d0, w0, #7
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %cvt = uitofp i32 %int to double
   %fix = fdiv double %cvt, 128.0
   ret double %fix
 }
 
 define double @ucvtf_f64_i32_32(i32 %int) {
+; CHECK-UNSAFE-FPMATH-LABEL: ucvtf_f64_i32_32:
+; CHECK-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-UNSAFE-FPMATH-NEXT:    ucvtf d0, w0, #32
+; CHECK-UNSAFE-FPMATH-NEXT:    ret
 ; CHECK-LABEL: ucvtf_f64_i32_32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ucvtf d0, w0, #32
+; CHECK-NEXT:    mov x8, #4751297606875873280 // =0x41f0000000000000
+; CHECK-NEXT:    ucvtf d0, w0
+; CHECK-NEXT:    fmov d1, x8
+; CHECK-NEXT:    fdiv d0, d0, d1
 ; CHECK-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: ucvtf_f64_i32_32:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ucvtf d0, w0, #32
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: ucvtf_f64_i32_32:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ucvtf d0, w0, #32
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %cvt = uitofp i32 %int to double
   %fix = fdiv double %cvt, 4294967296.0
   ret double %fix
 }
 
 define double @ucvtf_f64_i64_7(i64 %long) {
+; CHECK-UNSAFE-FPMATH-LABEL: ucvtf_f64_i64_7:
+; CHECK-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-UNSAFE-FPMATH-NEXT:    ucvtf d0, x0, #7
+; CHECK-UNSAFE-FPMATH-NEXT:    ret
 ; CHECK-LABEL: ucvtf_f64_i64_7:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ucvtf d0, x0, #7
+; CHECK-NEXT:    mov x8, #4638707616191610880 // =0x4060000000000000
+; CHECK-NEXT:    ucvtf d0, x0
+; CHECK-NEXT:    fmov d1, x8
+; CHECK-NEXT:    fdiv d0, d0, d1
 ; CHECK-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: ucvtf_f64_i64_7:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ucvtf d0, x0, #7
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: ucvtf_f64_i64_7:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ucvtf d0, x0, #7
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %cvt = uitofp i64 %long to double
   %fix = fdiv double %cvt, 128.0
   ret double %fix
 }
 
 define double @ucvtf_f64_i64_64(i64 %long) {
+; CHECK-UNSAFE-FPMATH-LABEL: ucvtf_f64_i64_64:
+; CHECK-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-UNSAFE-FPMATH-NEXT:    ucvtf d0, x0, #64
+; CHECK-UNSAFE-FPMATH-NEXT:    ret
 ; CHECK-LABEL: ucvtf_f64_i64_64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ucvtf d0, x0, #64
+; CHECK-NEXT:    mov x8, #4895412794951729152 // =0x43f0000000000000
+; CHECK-NEXT:    ucvtf d0, x0
+; CHECK-NEXT:    fmov d1, x8
+; CHECK-NEXT:    fdiv d0, d0, d1
 ; CHECK-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: ucvtf_f64_i64_64:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ucvtf d0, x0, #64
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: ucvtf_f64_i64_64:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ucvtf d0, x0, #64
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %cvt = uitofp i64 %long to double
   %fix = fdiv double %cvt, 18446744073709551616.0
   ret double %fix
@@ -583,8 +1211,26 @@
 ;
 ; CHECK-FP16-LABEL: ucvtf_f16_i32_7:
 ; CHECK-FP16:       // %bb.0:
-; CHECK-FP16-NEXT:    ucvtf h0, w0, #7
+; CHECK-FP16-NEXT:    mov w8, #22528 // =0x5800
+; CHECK-FP16-NEXT:    ucvtf h0, w0
+; CHECK-FP16-NEXT:    fmov h1, w8
+; CHECK-FP16-NEXT:    fdiv h0, h0, h1
 ; CHECK-FP16-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: ucvtf_f16_i32_7:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ucvtf s1, w0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    movi v0.2s, #60, lsl #24
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt h1, s1
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt s1, h1
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fmul s0, s1, s0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt h0, s0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: ucvtf_f16_i32_7:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ucvtf h0, w0, #7
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %cvt = uitofp i32 %int to half
   %fix = fdiv half %cvt, 128.0
   ret half %fix
@@ -603,8 +1249,29 @@
 ;
 ; CHECK-FP16-LABEL: ucvtf_f16_i32_15:
 ; CHECK-FP16:       // %bb.0:
-; CHECK-FP16-NEXT:    ucvtf h0, w0, #15
+; CHECK-FP16-NEXT:    mov w8, #30720 // =0x7800
+; CHECK-FP16-NEXT:    ucvtf h0, w0
+; CHECK-FP16-NEXT:    fmov h1, w8
+; CHECK-FP16-NEXT:    fdiv h0, h0, h1
 ; CHECK-FP16-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: ucvtf_f16_i32_15:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ucvtf s1, w0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    movi v0.2s, #56, lsl #24
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt h1, s1
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt s1, h1
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fmul s0, s1, s0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt h0, s0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: ucvtf_f16_i32_15:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    mov w8, #512 // =0x200
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ucvtf h0, w0
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fmov h1, w8
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fmul h0, h0, h1
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %cvt = uitofp i32 %int to half
   %fix = fdiv half %cvt, 32768.0
   ret half %fix
@@ -623,8 +1290,26 @@
 ;
 ; CHECK-FP16-LABEL: ucvtf_f16_i64_7:
 ; CHECK-FP16:       // %bb.0:
-; CHECK-FP16-NEXT:    ucvtf h0, x0, #7
+; CHECK-FP16-NEXT:    mov w8, #22528 // =0x5800
+; CHECK-FP16-NEXT:    ucvtf h0, x0
+; CHECK-FP16-NEXT:    fmov h1, w8
+; CHECK-FP16-NEXT:    fdiv h0, h0, h1
 ; CHECK-FP16-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: ucvtf_f16_i64_7:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ucvtf s1, x0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    movi v0.2s, #60, lsl #24
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt h1, s1
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt s1, h1
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fmul s0, s1, s0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt h0, s0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: ucvtf_f16_i64_7:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ucvtf h0, x0, #7
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %cvt = uitofp i64 %long to half
   %fix = fdiv half %cvt, 128.0
   ret half %fix
@@ -643,8 +1328,29 @@
 ;
 ; CHECK-FP16-LABEL: ucvtf_f16_i64_15:
 ; CHECK-FP16:       // %bb.0:
-; CHECK-FP16-NEXT:    ucvtf h0, x0, #15
+; CHECK-FP16-NEXT:    mov w8, #30720 // =0x7800
+; CHECK-FP16-NEXT:    ucvtf h0, x0
+; CHECK-FP16-NEXT:    fmov h1, w8
+; CHECK-FP16-NEXT:    fdiv h0, h0, h1
 ; CHECK-FP16-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: ucvtf_f16_i64_15:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ucvtf s1, x0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    movi v0.2s, #56, lsl #24
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt h1, s1
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt s1, h1
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fmul s0, s1, s0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt h0, s0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: ucvtf_f16_i64_15:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    mov w8, #512 // =0x200
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ucvtf h0, x0
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fmov h1, w8
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fmul h0, h0, h1
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %cvt = uitofp i64 %long to half
   %fix = fdiv half %cvt, 32768.0
   ret half %fix
@@ -665,6 +1371,16 @@
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs w0, s0, #7
 ; CHECK-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: fcvtzs_sat_f32_i32_7:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvtzs w0, s0, #7
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: fcvtzs_sat_f32_i32_7:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fcvtzs w0, s0, #7
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %fix = fmul float %flt, 128.0
   %cvt = call i32 @llvm.fptosi.sat.i32.f32(float %fix)
   ret i32 %cvt
@@ -675,6 +1391,16 @@
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs w0, s0, #32
 ; CHECK-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: fcvtzs_sat_f32_i32_32:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvtzs w0, s0, #32
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: fcvtzs_sat_f32_i32_32:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fcvtzs w0, s0, #32
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %fix = fmul float %flt, 4294967296.0
   %cvt = call i32 @llvm.fptosi.sat.i32.f32(float %fix)
   ret i32 %cvt
@@ -685,6 +1411,16 @@
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs x0, s0, #64
 ; CHECK-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: fcvtzs_sat_f32_i64_64:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvtzs x0, s0, #64
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: fcvtzs_sat_f32_i64_64:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fcvtzs x0, s0, #64
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %fix = fmul float %flt, 18446744073709551616.0
   %cvt = call i64 @llvm.fptosi.sat.i64.f32(float %fix)
   ret i64 %cvt
@@ -695,6 +1431,16 @@
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs w0, d0, #7
 ; CHECK-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: fcvtzs_sat_f64_i32_7:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvtzs w0, d0, #7
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: fcvtzs_sat_f64_i32_7:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fcvtzs w0, d0, #7
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %fix = fmul double %dbl, 128.0
   %cvt = call i32 @llvm.fptosi.sat.i32.f64(double %fix)
   ret i32 %cvt
@@ -705,6 +1451,16 @@
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs w0, d0, #32
 ; CHECK-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: fcvtzs_sat_f64_i32_32:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvtzs w0, d0, #32
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: fcvtzs_sat_f64_i32_32:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fcvtzs w0, d0, #32
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %fix = fmul double %dbl, 4294967296.0
   %cvt = call i32 @llvm.fptosi.sat.i32.f64(double %fix)
   ret i32 %cvt
@@ -715,6 +1471,16 @@
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs x0, d0, #7
 ; CHECK-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: fcvtzs_sat_f64_i64_7:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvtzs x0, d0, #7
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: fcvtzs_sat_f64_i64_7:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fcvtzs x0, d0, #7
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %fix = fmul double %dbl, 128.0
   %cvt = call i64 @llvm.fptosi.sat.i64.f64(double %fix)
   ret i64 %cvt
@@ -725,6 +1491,16 @@
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs x0, d0, #64
 ; CHECK-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: fcvtzs_sat_f64_i64_64:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvtzs x0, d0, #64
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: fcvtzs_sat_f64_i64_64:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fcvtzs x0, d0, #64
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %fix = fmul double %dbl, 18446744073709551616.0
   %cvt = call i64 @llvm.fptosi.sat.i64.f64(double %fix)
   ret i64 %cvt
@@ -745,6 +1521,21 @@
 ; CHECK-FP16:       // %bb.0:
 ; CHECK-FP16-NEXT:    fcvtzs w0, h0, #7
 ; CHECK-FP16-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: fcvtzs_sat_f16_i32_7:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    movi v1.2s, #67, lsl #24
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt s0, h0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fmul s0, s0, s1
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt h0, s0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt s0, h0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvtzs w0, s0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: fcvtzs_sat_f16_i32_7:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fcvtzs w0, h0, #7
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %fix = fmul half %dbl, 128.0
   %cvt = call i32 @llvm.fptosi.sat.i32.f16(half %fix)
   ret i32 %cvt
@@ -765,6 +1556,21 @@
 ; CHECK-FP16:       // %bb.0:
 ; CHECK-FP16-NEXT:    fcvtzs w0, h0, #15
 ; CHECK-FP16-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: fcvtzs_sat_f16_i32_15:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    movi v1.2s, #71, lsl #24
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt s0, h0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fmul s0, s0, s1
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt h0, s0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt s0, h0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvtzs w0, s0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: fcvtzs_sat_f16_i32_15:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fcvtzs w0, h0, #15
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %fix = fmul half %dbl, 32768.0
   %cvt = call i32 @llvm.fptosi.sat.i32.f16(half %fix)
   ret i32 %cvt
@@ -785,6 +1591,21 @@
 ; CHECK-FP16:       // %bb.0:
 ; CHECK-FP16-NEXT:    fcvtzs x0, h0, #7
 ; CHECK-FP16-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: fcvtzs_sat_f16_i64_7:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    movi v1.2s, #67, lsl #24
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt s0, h0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fmul s0, s0, s1
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt h0, s0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt s0, h0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvtzs x0, s0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: fcvtzs_sat_f16_i64_7:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fcvtzs x0, h0, #7
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %fix = fmul half %dbl, 128.0
   %cvt = call i64 @llvm.fptosi.sat.i64.f16(half %fix)
   ret i64 %cvt
@@ -805,6 +1626,21 @@
 ; CHECK-FP16:       // %bb.0:
 ; CHECK-FP16-NEXT:    fcvtzs x0, h0, #15
 ; CHECK-FP16-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: fcvtzs_sat_f16_i64_15:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    movi v1.2s, #71, lsl #24
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt s0, h0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fmul s0, s0, s1
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt h0, s0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt s0, h0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvtzs x0, s0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: fcvtzs_sat_f16_i64_15:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fcvtzs x0, h0, #15
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %fix = fmul half %dbl, 32768.0
   %cvt = call i64 @llvm.fptosi.sat.i64.f16(half %fix)
   ret i64 %cvt
@@ -824,6 +1660,16 @@
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzu w0, s0, #7
 ; CHECK-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: fcvtzu_sat_f32_i32_7:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvtzu w0, s0, #7
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: fcvtzu_sat_f32_i32_7:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fcvtzu w0, s0, #7
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %fix = fmul float %flt, 128.0
   %cvt = call i32 @llvm.fptoui.sat.i32.f32(float %fix)
   ret i32 %cvt
@@ -834,6 +1680,16 @@
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzu w0, s0, #32
 ; CHECK-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: fcvtzu_sat_f32_i32_32:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvtzu w0, s0, #32
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: fcvtzu_sat_f32_i32_32:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fcvtzu w0, s0, #32
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %fix = fmul float %flt, 4294967296.0
   %cvt = call i32 @llvm.fptoui.sat.i32.f32(float %fix)
   ret i32 %cvt
@@ -844,6 +1700,16 @@
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzu x0, s0, #64
 ; CHECK-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: fcvtzu_sat_f32_i64_64:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvtzu x0, s0, #64
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: fcvtzu_sat_f32_i64_64:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fcvtzu x0, s0, #64
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %fix = fmul float %flt, 18446744073709551616.0
   %cvt = call i64 @llvm.fptoui.sat.i64.f32(float %fix)
   ret i64 %cvt
@@ -854,6 +1720,16 @@
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzu w0, d0, #7
 ; CHECK-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: fcvtzu_sat_f64_i32_7:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvtzu w0, d0, #7
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: fcvtzu_sat_f64_i32_7:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fcvtzu w0, d0, #7
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %fix = fmul double %dbl, 128.0
   %cvt = call i32 @llvm.fptoui.sat.i32.f64(double %fix)
   ret i32 %cvt
@@ -864,6 +1740,16 @@
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzu w0, d0, #32
 ; CHECK-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: fcvtzu_sat_f64_i32_32:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvtzu w0, d0, #32
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: fcvtzu_sat_f64_i32_32:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fcvtzu w0, d0, #32
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %fix = fmul double %dbl, 4294967296.0
   %cvt = call i32 @llvm.fptoui.sat.i32.f64(double %fix)
   ret i32 %cvt
@@ -874,6 +1760,16 @@
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzu x0, d0, #7
 ; CHECK-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: fcvtzu_sat_f64_i64_7:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvtzu x0, d0, #7
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: fcvtzu_sat_f64_i64_7:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fcvtzu x0, d0, #7
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %fix = fmul double %dbl, 128.0
   %cvt = call i64 @llvm.fptoui.sat.i64.f64(double %fix)
   ret i64 %cvt
@@ -884,6 +1780,16 @@
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzu x0, d0, #64
 ; CHECK-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: fcvtzu_sat_f64_i64_64:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvtzu x0, d0, #64
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: fcvtzu_sat_f64_i64_64:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fcvtzu x0, d0, #64
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %fix = fmul double %dbl, 18446744073709551616.0
   %cvt = call i64 @llvm.fptoui.sat.i64.f64(double %fix)
   ret i64 %cvt
@@ -904,6 +1810,21 @@
 ; CHECK-FP16:       // %bb.0:
 ; CHECK-FP16-NEXT:    fcvtzu w0, h0, #7
 ; CHECK-FP16-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: fcvtzu_sat_f16_i32_7:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    movi v1.2s, #67, lsl #24
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt s0, h0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fmul s0, s0, s1
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt h0, s0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt s0, h0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvtzu w0, s0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: fcvtzu_sat_f16_i32_7:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fcvtzu w0, h0, #7
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %fix = fmul half %dbl, 128.0
   %cvt = call i32 @llvm.fptoui.sat.i32.f16(half %fix)
   ret i32 %cvt
@@ -924,6 +1845,21 @@
 ; CHECK-FP16:       // %bb.0:
 ; CHECK-FP16-NEXT:    fcvtzu w0, h0, #15
 ; CHECK-FP16-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: fcvtzu_sat_f16_i32_15:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    movi v1.2s, #71, lsl #24
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt s0, h0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fmul s0, s0, s1
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt h0, s0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt s0, h0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvtzu w0, s0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: fcvtzu_sat_f16_i32_15:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fcvtzu w0, h0, #15
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %fix = fmul half %dbl, 32768.0
   %cvt = call i32 @llvm.fptoui.sat.i32.f16(half %fix)
   ret i32 %cvt
@@ -944,6 +1880,21 @@
 ; CHECK-FP16:       // %bb.0:
 ; CHECK-FP16-NEXT:    fcvtzu x0, h0, #7
 ; CHECK-FP16-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: fcvtzu_sat_f16_i64_7:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    movi v1.2s, #67, lsl #24
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt s0, h0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fmul s0, s0, s1
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt h0, s0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt s0, h0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvtzu x0, s0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: fcvtzu_sat_f16_i64_7:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fcvtzu x0, h0, #7
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %fix = fmul half %dbl, 128.0
   %cvt = call i64 @llvm.fptoui.sat.i64.f16(half %fix)
   ret i64 %cvt
@@ -964,6 +1915,21 @@
 ; CHECK-FP16:       // %bb.0:
 ; CHECK-FP16-NEXT:    fcvtzu x0, h0, #15
 ; CHECK-FP16-NEXT:    ret
+;
+; CHECK-NO16-UNSAFE-FPMATH-LABEL: fcvtzu_sat_f16_i64_15:
+; CHECK-NO16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    movi v1.2s, #71, lsl #24
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt s0, h0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fmul s0, s0, s1
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt h0, s0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvt s0, h0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    fcvtzu x0, s0
+; CHECK-NO16-UNSAFE-FPMATH-NEXT:    ret
+;
+; CHECK-FP16-UNSAFE-FPMATH-LABEL: fcvtzu_sat_f16_i64_15:
+; CHECK-FP16-UNSAFE-FPMATH:       // %bb.0:
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    fcvtzu x0, h0, #15
+; CHECK-FP16-UNSAFE-FPMATH-NEXT:    ret
   %fix = fmul half %dbl, 32768.0
   %cvt = call i64 @llvm.fptoui.sat.i64.f16(half %fix)
   ret i64 %cvt
Index: llvm/test/CodeGen/AArch64/svtcf-fmul-fdiv-combine.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/svtcf-fmul-fdiv-combine.ll
@@ -0,0 +1,112 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -mtriple aarch64-none-linux-gnu -enable-unsafe-fp-math < %s | FileCheck %s
+
+define float @scvtf_f32_2(i32 %state) {
+; CHECK-LABEL: scvtf_f32_2:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    scvtf s0, w0, #1
+; CHECK-NEXT:    ret
+entry:
+  %conv = sitofp i32 %state to float
+  %div = fmul float %conv, 5.000000e-01
+  ret float %div
+}
+
+define float @scvtf_f32_4(i32 %state) {
+; CHECK-LABEL: scvtf_f32_4:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    scvtf s0, w0, #2
+; CHECK-NEXT:    ret
+entry:
+  %conv = sitofp i32 %state to float
+  %div = fmul float %conv, 2.500000e-01
+  ret float %div
+}
+
+define float @scvtf_f32_8(i32 %state) {
+; CHECK-LABEL: scvtf_f32_8:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    scvtf s0, w0, #3
+; CHECK-NEXT:    ret
+entry:
+  %conv = sitofp i32 %state to float
+  %div = fmul float %conv, 1.250000e-01
+  ret float %div
+}
+
+define float @scvtf_f32_16(i32 %state) {
+; CHECK-LABEL: scvtf_f32_16:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    scvtf s0, w0, #4
+; CHECK-NEXT:    ret
+entry:
+  %conv = sitofp i32 %state to float
+  %div = fmul float %conv, 6.250000e-02
+  ret float %div
+}
+
+define float @scvtf_f32_32(i32 %state) {
+; CHECK-LABEL: scvtf_f32_32:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    scvtf s0, w0, #5
+; CHECK-NEXT:    ret
+entry:
+  %conv = sitofp i32 %state to float
+  %div = fmul float %conv, 3.125000e-02
+  ret float %div
+}
+
+define double @scvtf_f64_2(i64 %state) {
+; CHECK-LABEL: scvtf_f64_2:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    scvtf d0, x0, #1
+; CHECK-NEXT:    ret
+entry:
+  %conv = sitofp i64 %state to double
+  %div = fmul double %conv, 5.000000e-01
+  ret double %div
+}
+
+define double @scvtf_f64_4(i64 %state) {
+; CHECK-LABEL: scvtf_f64_4:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    scvtf d0, x0, #2
+; CHECK-NEXT:    ret
+entry:
+  %conv = sitofp i64 %state to double
+  %div = fmul double %conv, 2.500000e-01
+  ret double %div
+}
+
+define double @scvtf_f64_8(i64 %state) {
+; CHECK-LABEL: scvtf_f64_8:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    scvtf d0, x0, #3
+; CHECK-NEXT:    ret
+entry:
+  %conv = sitofp i64 %state to double
+  %div = fmul double %conv, 1.250000e-01
+  ret double %div
+}
+
+define double @scvtf_f64_16(i64 %state) {
+; CHECK-LABEL: scvtf_f64_16:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    scvtf d0, x0, #4
+; CHECK-NEXT:    ret
+entry:
+  %conv = sitofp i64 %state to double
+  %div = fmul double %conv, 6.250000e-02
+  ret double %div
+}
+
+define double @scvtf_f64_32(i64 %state) {
+; CHECK-LABEL: scvtf_f64_32:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    scvtf d0, x0, #5
+; CHECK-NEXT:    ret
+entry:
+  %conv = sitofp i64 %state to double
+  %div = fmul double %conv, 3.125000e-02
+  ret double %div
+}