diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.cpp --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.cpp +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.cpp @@ -17,11 +17,10 @@ // //===----------------------------------------------------------------------===// - #include "PPCELFStreamer.h" #include "PPCFixupKinds.h" -#include "PPCInstrInfo.h" #include "PPCMCCodeEmitter.h" +#include "PPCMCTargetDesc.h" #include "llvm/BinaryFormat/ELF.h" #include "llvm/MC/MCAsmBackend.h" #include "llvm/MC/MCAssembler.h" diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp @@ -13,14 +13,13 @@ #include "MCTargetDesc/PPCInstPrinter.h" #include "MCTargetDesc/PPCMCTargetDesc.h" #include "MCTargetDesc/PPCPredicates.h" -#include "PPCInstrInfo.h" -#include "llvm/CodeGen/TargetOpcodes.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCSymbol.h" +#include "llvm/Support/Casting.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/raw_ostream.h" using namespace llvm; @@ -646,8 +645,7 @@ if (Op.isReg()) { unsigned Reg = Op.getReg(); if (!ShowVSRNumsAsVR) - Reg = PPCInstrInfo::getRegNumForOperand(MII.get(MI->getOpcode()), - Reg, OpNo); + Reg = PPC::getRegNumForOperand(MII.get(MI->getOpcode()), Reg, OpNo); const char *RegName; RegName = getVerboseConditionRegName(Reg, MRI.getEncodingValue(Reg)); @@ -656,7 +654,7 @@ if (showRegistersWithPercentPrefix(RegName)) O << "%"; if (!showRegistersWithPrefix()) - RegName = PPCRegisterInfo::stripRegisterPrefix(RegName); + RegName = PPC::stripRegisterPrefix(RegName); O << RegName; return; diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.h b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.h --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.h +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.h @@ -121,6 +121,10 @@ // Is this instruction a prefixed instruction. bool isPrefixedInstruction(const MCInst &MI) const; + + /// Check if Opcode corresponds to a call instruction that should be marked + /// with the NOTOC relocation. + bool isNoTOCCallInstr(const MCInst &MI) const; }; } // namespace llvm diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp @@ -12,12 +12,14 @@ #include "PPCMCCodeEmitter.h" #include "MCTargetDesc/PPCFixupKinds.h" -#include "PPCInstrInfo.h" +#include "PPCMCTargetDesc.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/Statistic.h" +#include "llvm/MC/MCExpr.h" #include "llvm/MC/MCFixup.h" #include "llvm/MC/MCInstrDesc.h" #include "llvm/MC/MCRegisterInfo.h" +#include "llvm/Support/Casting.h" #include "llvm/Support/Endian.h" #include "llvm/Support/EndianStream.h" #include "llvm/Support/ErrorHandling.h" @@ -47,16 +49,108 @@ if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); - const PPCInstrInfo *InstrInfo = static_cast(&MCII); - unsigned Opcode = MI.getOpcode(); // Add a fixup for the branch target. Fixups.push_back(MCFixup::create(0, MO.getExpr(), - (InstrInfo->isNoTOCCallInstr(Opcode) + (isNoTOCCallInstr(MI) ? (MCFixupKind)PPC::fixup_ppc_br24_notoc : (MCFixupKind)PPC::fixup_ppc_br24))); return 0; } +/// Check if Opcode corresponds to a call instruction that should be marked +/// with the NOTOC relocation. +bool PPCMCCodeEmitter::isNoTOCCallInstr(const MCInst &MI) const { + unsigned Opcode = MI.getOpcode(); + if (!MCII.get(Opcode).isCall()) + return false; + + switch (Opcode) { + default: +#ifndef NDEBUG + llvm_unreachable("Unknown call opcode"); +#endif + return false; + case PPC::BL8_NOTOC: + case PPC::BL8_NOTOC_TLS: + case PPC::BL8_NOTOC_RM: + return true; +#ifndef NDEBUG + case PPC::BL8: + case PPC::BL: + case PPC::BL8_TLS: + case PPC::BL_TLS: + case PPC::BLA8: + case PPC::BLA: + case PPC::BCCL: + case PPC::BCCLA: + case PPC::BCL: + case PPC::BCLn: + case PPC::BL8_NOP: + case PPC::BL_NOP: + case PPC::BL8_NOP_TLS: + case PPC::BLA8_NOP: + case PPC::BCTRL8: + case PPC::BCTRL: + case PPC::BCCCTRL8: + case PPC::BCCCTRL: + case PPC::BCCTRL8: + case PPC::BCCTRL: + case PPC::BCCTRL8n: + case PPC::BCCTRLn: + case PPC::BL8_RM: + case PPC::BLA8_RM: + case PPC::BL8_NOP_RM: + case PPC::BLA8_NOP_RM: + case PPC::BCTRL8_RM: + case PPC::BCTRL8_LDinto_toc: + case PPC::BCTRL8_LDinto_toc_RM: + case PPC::BL8_TLS_: + case PPC::TCRETURNdi8: + case PPC::TCRETURNai8: + case PPC::TCRETURNri8: + case PPC::TAILBCTR8: + case PPC::TAILB8: + case PPC::TAILBA8: + case PPC::BCLalways: + case PPC::BLRL: + case PPC::BCCLRL: + case PPC::BCLRL: + case PPC::BCLRLn: + case PPC::BDZL: + case PPC::BDNZL: + case PPC::BDZLA: + case PPC::BDNZLA: + case PPC::BDZLp: + case PPC::BDNZLp: + case PPC::BDZLAp: + case PPC::BDNZLAp: + case PPC::BDZLm: + case PPC::BDNZLm: + case PPC::BDZLAm: + case PPC::BDNZLAm: + case PPC::BDZLRL: + case PPC::BDNZLRL: + case PPC::BDZLRLp: + case PPC::BDNZLRLp: + case PPC::BDZLRLm: + case PPC::BDNZLRLm: + case PPC::BL_RM: + case PPC::BLA_RM: + case PPC::BL_NOP_RM: + case PPC::BCTRL_RM: + case PPC::TCRETURNdi: + case PPC::TCRETURNai: + case PPC::TCRETURNri: + case PPC::BCTRL_LWZinto_toc: + case PPC::BCTRL_LWZinto_toc_RM: + case PPC::TAILBCTR: + case PPC::TAILB: + case PPC::TAILBA: + return false; +#endif + } +} + unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const { @@ -372,7 +466,7 @@ } // Get the index for this operand in this instruction. This is needed for -// computing the register number in PPCInstrInfo::getRegNumForOperand() for +// computing the register number in PPC::getRegNumForOperand() for // any instructions that use a different numbering scheme for registers in // different operands. static unsigned getOpIdxForMO(const MCInst &MI, const MCOperand &MO) { @@ -397,8 +491,7 @@ MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7); unsigned OpNo = getOpIdxForMO(MI, MO); unsigned Reg = - PPCInstrInfo::getRegNumForOperand(MCII.get(MI.getOpcode()), - MO.getReg(), OpNo); + PPC::getRegNumForOperand(MCII.get(MI.getOpcode()), MO.getReg(), OpNo); return CTX.getRegisterInfo()->getEncodingValue(Reg); } @@ -443,9 +536,7 @@ } bool PPCMCCodeEmitter::isPrefixedInstruction(const MCInst &MI) const { - unsigned Opcode = MI.getOpcode(); - const PPCInstrInfo *InstrInfo = static_cast(&MCII); - return InstrInfo->isPrefixed(Opcode); + return MCII.get(MI.getOpcode()).TSFlags & PPCII::Prefixed; } #include "PPCGenMCCodeEmitter.inc" diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h @@ -26,6 +26,7 @@ class MCAsmBackend; class MCCodeEmitter; class MCContext; +class MCInstrDesc; class MCInstrInfo; class MCObjectTargetWriter; class MCRegisterInfo; @@ -33,6 +34,24 @@ class MCTargetOptions; class Target; +namespace PPC { +/// stripRegisterPrefix - This method strips the character prefix from a +/// register name so that only the number is left. Used by for linux asm. +const char *stripRegisterPrefix(const char *RegName); + +/// getRegNumForOperand - some operands use different numbering schemes +/// for the same registers. For example, a VSX instruction may have any of +/// vs0-vs63 allocated whereas an Altivec instruction could only have +/// vs32-vs63 allocated (numbered as v0-v31). This function returns the actual +/// register number needed for the opcode/operand number combination. +/// The operand number argument will be useful when we need to extend this +/// to instructions that use both Altivec and VSX numbering (for different +/// operands). +unsigned getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg, + unsigned OpNo); + +} // namespace PPC + MCCodeEmitter *createPPCMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx); @@ -102,11 +121,61 @@ return false; } -} // end namespace llvm +/// PPCII - This namespace holds all of the PowerPC target-specific +/// per-instruction flags. These must match the corresponding definitions in +/// PPC.td and PPCInstrFormats.td. +namespace PPCII { +enum { + // PPC970 Instruction Flags. These flags describe the characteristics of the + // PowerPC 970 (aka G5) dispatch groups and how they are formed out of + // raw machine instructions. -// Generated files will use "namespace PPC". To avoid symbol clash, -// undefine PPC here. PPC may be predefined on some hosts. -#undef PPC + /// PPC970_First - This instruction starts a new dispatch group, so it will + /// always be the first one in the group. + PPC970_First = 0x1, + + /// PPC970_Single - This instruction starts a new dispatch group and + /// terminates it, so it will be the sole instruction in the group. + PPC970_Single = 0x2, + + /// PPC970_Cracked - This instruction is cracked into two pieces, requiring + /// two dispatch pipes to be available to issue. + PPC970_Cracked = 0x4, + + /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that + /// an instruction is issued to. + PPC970_Shift = 3, + PPC970_Mask = 0x07 << PPC970_Shift +}; +enum PPC970_Unit { + /// These are the various PPC970 execution unit pipelines. Each instruction + /// is one of these. + PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction + PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit + PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit + PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit + PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit + PPC970_VALU = 5 << PPC970_Shift, // Vector ALU + PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit + PPC970_BRU = 7 << PPC970_Shift // Branch Unit +}; + +enum { + /// Shift count to bypass PPC970 flags + NewDef_Shift = 6, + + /// This instruction is an X-Form memory operation. + XFormMemOp = 0x1 << NewDef_Shift, + /// This instruction is prefixed. + Prefixed = 0x1 << (NewDef_Shift + 1), + /// This instruction produced a sign extended result. + SExt32To64 = 0x1 << (NewDef_Shift + 2), + /// This instruction produced a zero extended result. + ZExt32To64 = 0x1 << (NewDef_Shift + 3) +}; +} // end namespace PPCII + +} // end namespace llvm // Defines symbolic names for PowerPC registers. This defines a mapping from // register name to register number. @@ -214,4 +283,16 @@ static const MCPhysReg DMRRegs[8] = PPC_REGS0_7(PPC::DMR); \ static const MCPhysReg DMRpRegs[4] = PPC_REGS0_3(PPC::DMRp); +namespace llvm { +namespace PPC { +static inline bool isVFRegister(unsigned Reg) { + return Reg >= PPC::VF0 && Reg <= PPC::VF31; +} + +static inline bool isVRRegister(unsigned Reg) { + return Reg >= PPC::V0 && Reg <= PPC::V31; +} +} // namespace PPC +} // namespace llvm + #endif // LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCMCTARGETDESC_H diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp @@ -57,6 +57,90 @@ #define GET_REGINFO_MC_DESC #include "PPCGenRegisterInfo.inc" +/// stripRegisterPrefix - This method strips the character prefix from a +/// register name so that only the number is left. Used by for linux asm. +const char *PPC::stripRegisterPrefix(const char *RegName) { + switch (RegName[0]) { + case 'a': + if (RegName[1] == 'c' && RegName[2] == 'c') + return RegName + 3; + break; + case 'f': + if (RegName[1] == 'p') + return RegName + 2; + [[fallthrough]]; + case 'r': + case 'v': + if (RegName[1] == 's') { + if (RegName[2] == 'p') + return RegName + 3; + return RegName + 2; + } + return RegName + 1; + case 'c': + if (RegName[1] == 'r') + return RegName + 2; + break; + case 'w': + // For wacc and wacc_hi + if (RegName[1] == 'a' && RegName[2] == 'c' && RegName[3] == 'c') { + if (RegName[4] == '_') + return RegName + 7; + else + return RegName + 4; + } + break; + case 'd': + // For dmr, dmrp, dmrrow, dmrrowp + if (RegName[1] == 'm' && RegName[2] == 'r') { + if (RegName[3] == 'r' && RegName[4] == 'o' && RegName[5] == 'w' && + RegName[6] == 'p') + return RegName + 7; + else if (RegName[3] == 'r' && RegName[4] == 'o' && RegName[5] == 'w') + return RegName + 6; + else if (RegName[3] == 'p') + return RegName + 4; + else + return RegName + 3; + } + break; + } + + return RegName; +} + +/// getRegNumForOperand - some operands use different numbering schemes +/// for the same registers. For example, a VSX instruction may have any of +/// vs0-vs63 allocated whereas an Altivec instruction could only have +/// vs32-vs63 allocated (numbered as v0-v31). This function returns the actual +/// register number needed for the opcode/operand number combination. +/// The operand number argument will be useful when we need to extend this +/// to instructions that use both Altivec and VSX numbering (for different +/// operands). +unsigned PPC::getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg, + unsigned OpNo) { + int16_t regClass = Desc.operands()[OpNo].RegClass; + switch (regClass) { + // We store F0-F31, VF0-VF31 in MCOperand and it should be F0-F31, + // VSX32-VSX63 during encoding/disassembling + case PPC::VSSRCRegClassID: + case PPC::VSFRCRegClassID: + if (PPC::isVFRegister(Reg)) + return PPC::VSX32 + (Reg - PPC::VF0); + break; + // We store VSL0-VSL31, V0-V31 in MCOperand and it should be VSL0-VSL31, + // VSX32-VSX63 during encoding/disassembling + case PPC::VSRCRegClassID: + if (PPC::isVRRegister(Reg)) + return PPC::VSX32 + (Reg - PPC::V0); + break; + // Other RegClass doesn't need mapping + default: + break; + } + return Reg; +} + PPCTargetStreamer::PPCTargetStreamer(MCStreamer &S) : MCTargetStreamer(S) {} // Pin the vtable to this file. diff --git a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp --- a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp +++ b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp @@ -316,7 +316,7 @@ // Linux assembler (Others?) does not take register mnemonics. // FIXME - What about special registers used in mfspr/mtspr? - O << PPCRegisterInfo::stripRegisterPrefix(RegName); + O << PPC::stripRegisterPrefix(RegName); return; } case MachineOperand::MO_Immediate: @@ -376,13 +376,13 @@ // This operand uses VSX numbering. // If the operand is a VMX register, convert it to a VSX register. Register Reg = MI->getOperand(OpNo).getReg(); - if (PPCInstrInfo::isVRRegister(Reg)) + if (PPC::isVRRegister(Reg)) Reg = PPC::VSX32 + (Reg - PPC::V0); - else if (PPCInstrInfo::isVFRegister(Reg)) + else if (PPC::isVFRegister(Reg)) Reg = PPC::VSX32 + (Reg - PPC::VF0); const char *RegName; RegName = PPCInstPrinter::getRegisterName(Reg); - RegName = PPCRegisterInfo::stripRegisterPrefix(RegName); + RegName = PPC::stripRegisterPrefix(RegName); O << RegName; return false; } diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.h b/llvm/lib/Target/PowerPC/PPCInstrInfo.h --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.h +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.h @@ -13,6 +13,7 @@ #ifndef LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H #define LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H +#include "MCTargetDesc/PPCMCTargetDesc.h" #include "PPCRegisterInfo.h" #include "llvm/CodeGen/TargetInstrInfo.h" @@ -21,60 +22,6 @@ namespace llvm { -/// PPCII - This namespace holds all of the PowerPC target-specific -/// per-instruction flags. These must match the corresponding definitions in -/// PPC.td and PPCInstrFormats.td. -namespace PPCII { -enum { - // PPC970 Instruction Flags. These flags describe the characteristics of the - // PowerPC 970 (aka G5) dispatch groups and how they are formed out of - // raw machine instructions. - - /// PPC970_First - This instruction starts a new dispatch group, so it will - /// always be the first one in the group. - PPC970_First = 0x1, - - /// PPC970_Single - This instruction starts a new dispatch group and - /// terminates it, so it will be the sole instruction in the group. - PPC970_Single = 0x2, - - /// PPC970_Cracked - This instruction is cracked into two pieces, requiring - /// two dispatch pipes to be available to issue. - PPC970_Cracked = 0x4, - - /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that - /// an instruction is issued to. - PPC970_Shift = 3, - PPC970_Mask = 0x07 << PPC970_Shift -}; -enum PPC970_Unit { - /// These are the various PPC970 execution unit pipelines. Each instruction - /// is one of these. - PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction - PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit - PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit - PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit - PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit - PPC970_VALU = 5 << PPC970_Shift, // Vector ALU - PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit - PPC970_BRU = 7 << PPC970_Shift // Branch Unit -}; - -enum { - /// Shift count to bypass PPC970 flags - NewDef_Shift = 6, - - /// This instruction is an X-Form memory operation. - XFormMemOp = 0x1 << NewDef_Shift, - /// This instruction is prefixed. - Prefixed = 0x1 << (NewDef_Shift + 1), - /// This instruction produced a sign extended result. - SExt32To64 = 0x1 << (NewDef_Shift + 2), - /// This instruction produced a zero extended result. - ZExt32To64 = 0x1 << (NewDef_Shift + 3) -}; -} // end namespace PPCII - // Instructions that have an immediate form might be convertible to that // form if the correct input is a result of a load immediate. In order to // know whether the transformation is special, we might need to know some @@ -324,99 +271,6 @@ return get(Opcode).TSFlags & PPCII::ZExt32To64; } - /// Check if Opcode corresponds to a call instruction that should be marked - /// with the NOTOC relocation. - bool isNoTOCCallInstr(unsigned Opcode) const { - if (!get(Opcode).isCall()) - return false; - - switch (Opcode) { - default: -#ifndef NDEBUG - llvm_unreachable("Unknown call opcode"); -#endif - return false; - case PPC::BL8_NOTOC: - case PPC::BL8_NOTOC_TLS: - case PPC::BL8_NOTOC_RM: - return true; -#ifndef NDEBUG - case PPC::BL8: - case PPC::BL: - case PPC::BL8_TLS: - case PPC::BL_TLS: - case PPC::BLA8: - case PPC::BLA: - case PPC::BCCL: - case PPC::BCCLA: - case PPC::BCL: - case PPC::BCLn: - case PPC::BL8_NOP: - case PPC::BL_NOP: - case PPC::BL8_NOP_TLS: - case PPC::BLA8_NOP: - case PPC::BCTRL8: - case PPC::BCTRL: - case PPC::BCCCTRL8: - case PPC::BCCCTRL: - case PPC::BCCTRL8: - case PPC::BCCTRL: - case PPC::BCCTRL8n: - case PPC::BCCTRLn: - case PPC::BL8_RM: - case PPC::BLA8_RM: - case PPC::BL8_NOP_RM: - case PPC::BLA8_NOP_RM: - case PPC::BCTRL8_RM: - case PPC::BCTRL8_LDinto_toc: - case PPC::BCTRL8_LDinto_toc_RM: - case PPC::BL8_TLS_: - case PPC::TCRETURNdi8: - case PPC::TCRETURNai8: - case PPC::TCRETURNri8: - case PPC::TAILBCTR8: - case PPC::TAILB8: - case PPC::TAILBA8: - case PPC::BCLalways: - case PPC::BLRL: - case PPC::BCCLRL: - case PPC::BCLRL: - case PPC::BCLRLn: - case PPC::BDZL: - case PPC::BDNZL: - case PPC::BDZLA: - case PPC::BDNZLA: - case PPC::BDZLp: - case PPC::BDNZLp: - case PPC::BDZLAp: - case PPC::BDNZLAp: - case PPC::BDZLm: - case PPC::BDNZLm: - case PPC::BDZLAm: - case PPC::BDNZLAm: - case PPC::BDZLRL: - case PPC::BDNZLRL: - case PPC::BDZLRLp: - case PPC::BDNZLRLp: - case PPC::BDZLRLm: - case PPC::BDNZLRLm: - case PPC::BL_RM: - case PPC::BLA_RM: - case PPC::BL_NOP_RM: - case PPC::BCTRL_RM: - case PPC::TCRETURNdi: - case PPC::TCRETURNai: - case PPC::TCRETURNri: - case PPC::BCTRL_LWZinto_toc: - case PPC::BCTRL_LWZinto_toc_RM: - case PPC::TAILBCTR: - case PPC::TAILB: - case PPC::TAILBA: - return false; -#endif - } - } - static bool isSameClassPhysRegCopy(unsigned Opcode) { unsigned CopyOpcodes[] = {PPC::OR, PPC::OR8, PPC::FMR, PPC::VOR, PPC::XXLOR, PPC::XXLORf, @@ -709,12 +563,6 @@ // Lower pseudo instructions after register allocation. bool expandPostRAPseudo(MachineInstr &MI) const override; - static bool isVFRegister(unsigned Reg) { - return Reg >= PPC::VF0 && Reg <= PPC::VF31; - } - static bool isVRRegister(unsigned Reg) { - return Reg >= PPC::V0 && Reg <= PPC::V31; - } const TargetRegisterClass *updatedRC(const TargetRegisterClass *RC) const; static int getRecordFormOpcode(unsigned Opcode); @@ -785,38 +633,6 @@ const DebugLoc &DL, Register Reg, int64_t Imm) const; - /// getRegNumForOperand - some operands use different numbering schemes - /// for the same registers. For example, a VSX instruction may have any of - /// vs0-vs63 allocated whereas an Altivec instruction could only have - /// vs32-vs63 allocated (numbered as v0-v31). This function returns the actual - /// register number needed for the opcode/operand number combination. - /// The operand number argument will be useful when we need to extend this - /// to instructions that use both Altivec and VSX numbering (for different - /// operands). - static unsigned getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg, - unsigned OpNo) { - int16_t regClass = Desc.operands()[OpNo].RegClass; - switch (regClass) { - // We store F0-F31, VF0-VF31 in MCOperand and it should be F0-F31, - // VSX32-VSX63 during encoding/disassembling - case PPC::VSSRCRegClassID: - case PPC::VSFRCRegClassID: - if (isVFRegister(Reg)) - return PPC::VSX32 + (Reg - PPC::VF0); - break; - // We store VSL0-VSL31, V0-V31 in MCOperand and it should be VSL0-VSL31, - // VSX32-VSX63 during encoding/disassembling - case PPC::VSRCRegClassID: - if (isVRRegister(Reg)) - return PPC::VSX32 + (Reg - PPC::V0); - break; - // Other RegClass doesn't need mapping - default: - break; - } - return Reg; - } - /// Check \p Opcode is BDNZ (Decrement CTR and branch if it is still nonzero). bool isBDNZ(unsigned Opcode) const; diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -3412,7 +3412,7 @@ Opc == PPC::RLWINM || Opc == PPC::RLWINM_rec || Opc == PPC::RLWINM8 || Opc == PPC::RLWINM8_rec; bool IsVFReg = (MI.getNumOperands() && MI.getOperand(0).isReg()) - ? isVFRegister(MI.getOperand(0).getReg()) + ? PPC::isVFRegister(MI.getOperand(0).getReg()) : false; if (!ConvertibleImmForm && !instrHasImmForm(Opc, IsVFReg, III, true)) return nullptr; @@ -3725,8 +3725,8 @@ return false; // TODO: sync the logic between instrHasImmForm() and ImmToIdxMap. - if (!instrHasImmForm(XFormOpcode, isVFRegister(MI.getOperand(0).getReg()), - III, true)) + if (!instrHasImmForm(XFormOpcode, + PPC::isVFRegister(MI.getOperand(0).getReg()), III, true)) return false; if (!III.IsSummingOperands) @@ -3822,7 +3822,7 @@ ImmInstrInfo III; bool IsVFReg = MI.getOperand(0).isReg() - ? isVFRegister(MI.getOperand(0).getReg()) + ? PPC::isVFRegister(MI.getOperand(0).getReg()) : false; bool HasImmForm = instrHasImmForm(MI.getOpcode(), IsVFReg, III, PostRA); // If this is a reg+reg instruction that has a reg+imm form, @@ -4864,7 +4864,7 @@ // get Imm Form info. ImmInstrInfo III; bool IsVFReg = MI.getOperand(0).isReg() - ? isVFRegister(MI.getOperand(0).getReg()) + ? PPC::isVFRegister(MI.getOperand(0).getReg()) : false; if (!instrHasImmForm(XFormOpcode, IsVFReg, III, PostRA)) diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.h b/llvm/lib/Target/PowerPC/PPCRegisterInfo.h --- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.h +++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.h @@ -172,58 +172,6 @@ Register getBaseRegister(const MachineFunction &MF) const; bool hasBasePointer(const MachineFunction &MF) const; - /// stripRegisterPrefix - This method strips the character prefix from a - /// register name so that only the number is left. Used by for linux asm. - static const char *stripRegisterPrefix(const char *RegName) { - switch (RegName[0]) { - case 'a': - if (RegName[1] == 'c' && RegName[2] == 'c') - return RegName + 3; - break; - case 'f': - if (RegName[1] == 'p') - return RegName + 2; - [[fallthrough]]; - case 'r': - case 'v': - if (RegName[1] == 's') { - if (RegName[2] == 'p') - return RegName + 3; - return RegName + 2; - } - return RegName + 1; - case 'c': - if (RegName[1] == 'r') - return RegName + 2; - break; - case 'w': - // For wacc and wacc_hi - if (RegName[1] == 'a' && RegName[2] == 'c' && RegName[3] == 'c') { - if (RegName[4] == '_') - return RegName + 7; - else - return RegName + 4; - } - break; - case 'd': - // For dmr, dmrp, dmrrow, dmrrowp - if (RegName[1] == 'm' && RegName[2] == 'r') { - if (RegName[3] == 'r' && RegName[4] == 'o' && RegName[5] == 'w' && - RegName[6] == 'p') - return RegName + 7; - else if (RegName[3] == 'r' && RegName[4] == 'o' && RegName[5] == 'w') - return RegName + 6; - else if (RegName[3] == 'p') - return RegName + 4; - else - return RegName + 3; - } - break; - } - - return RegName; - } - bool isNonallocatableRegisterCalleeSave(MCRegister Reg) const override { return Reg == PPC::LR || Reg == PPC::LR8; }