diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp --- a/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp @@ -1233,9 +1233,15 @@ if (Instruction *Result = commonCastTransforms(Zext)) return Result; + Value *Src = Zext.getOperand(0); Type *SrcTy = Src->getType(), *DestTy = Zext.getType(); + // if the value is Non Negative set the nneg flag + if(isKnownNonNegative(Src, DL, 0, &AC, &Zext)){ + Zext.setNonNeg(true); + } + // Try to extend the entire expression tree to the wide destination type. unsigned BitsToClear; if (shouldChangeType(SrcTy, DestTy) && @@ -1507,8 +1513,11 @@ unsigned DestBitSize = DestTy->getScalarSizeInBits(); // If the value being extended is zero or positive, use a zext instead. - if (isKnownNonNegative(Src, DL, 0, &AC, &Sext, &DT)) - return CastInst::Create(Instruction::ZExt, Src, DestTy); + if (isKnownNonNegative(Src, DL, 0, &AC, &Sext, &DT)) { + auto *ZExtInst = CastInst::Create(Instruction::ZExt, Src, DestTy); + ZExtInst->setNonNeg(true); + return ZExtInst; + } // Try to extend the entire expression tree to the wide destination type. if (shouldChangeType(SrcTy, DestTy) && canEvaluateSExtd(Src, DestTy)) { diff --git a/llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp b/llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp --- a/llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp +++ b/llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp @@ -71,6 +71,7 @@ STATISTIC(NumAShrsRemoved, "Number of ashr removed"); STATISTIC(NumSRems, "Number of srem converted to urem"); STATISTIC(NumSExt, "Number of sext converted to zext"); +STATISTIC(NumZExtNNeg, "Number of non-negative zext deductions"); STATISTIC(NumSICmps, "Number of signed icmp preds simplified to unsigned"); STATISTIC(NumAnd, "Number of ands removed"); STATISTIC(NumNW, "Number of no-wrap deductions"); @@ -1035,6 +1036,19 @@ return true; } +static bool processZExt(ZExtInst *SDI, LazyValueInfo *LVI) { + if (SDI->getType()->isVectorTy()) + return false; + + const Use &Base = SDI->getOperandUse(0); + if(!LVI->getConstantRangeAtUse(Base).isAllNonNegative()) + return false; + + ++NumZExtNNeg; + SDI->setNonNeg(true); + return true; +} + static bool processSExt(SExtInst *SDI, LazyValueInfo *LVI) { if (SDI->getType()->isVectorTy()) return false; @@ -1047,6 +1061,7 @@ auto *ZExt = CastInst::CreateZExtOrBitCast(Base, SDI->getType(), "", SDI); ZExt->takeName(SDI); ZExt->setDebugLoc(SDI->getDebugLoc()); + ZExt->setNonNeg(true); SDI->replaceAllUsesWith(ZExt); SDI->eraseFromParent(); @@ -1183,6 +1198,9 @@ case Instruction::SExt: BBChanged |= processSExt(cast(&II), LVI); break; + case Instruction::ZExt: + BBChanged |= processZExt(cast(&II), LVI); + break; case Instruction::Add: case Instruction::Sub: case Instruction::Mul: diff --git a/llvm/lib/Transforms/Utils/SCCPSolver.cpp b/llvm/lib/Transforms/Utils/SCCPSolver.cpp --- a/llvm/lib/Transforms/Utils/SCCPSolver.cpp +++ b/llvm/lib/Transforms/Utils/SCCPSolver.cpp @@ -142,6 +142,7 @@ if (InsertedValues.count(Op0) || !isNonNegative(Op0)) return false; NewInst = new ZExtInst(Op0, Inst.getType(), "", &Inst); + NewInst->setNonNeg(true); break; } case Instruction::AShr: { diff --git a/llvm/lib/Transforms/Utils/SimplifyIndVar.cpp b/llvm/lib/Transforms/Utils/SimplifyIndVar.cpp --- a/llvm/lib/Transforms/Utils/SimplifyIndVar.cpp +++ b/llvm/lib/Transforms/Utils/SimplifyIndVar.cpp @@ -514,6 +514,12 @@ ICmpUsers.push_back(ICI); } + auto IsOperandsNonNeg = [&](ICmpInst *ICI){ + const SCEV *SCEVOP1 = SE->getSCEV(ICI->getOperand(0)); + const SCEV *SCEVOP2 = SE->getSCEV(ICI->getOperand(1)); + return SE->isKnownNonNegative(SCEVOP1) && SE->isKnownNonNegative(SCEVOP2); + }; + auto CanUseZExt = [&](ICmpInst *ICI) { // Unsigned comparison can be widened as unsigned. if (ICI->isUnsigned()) @@ -528,9 +534,7 @@ // negative values. But in practice, we will never pass DoesZExtCollapse // check for a negative value, because zext(trunc(x)) is non-negative. So // it only make sense to check for non-negativity here. - const SCEV *SCEVOP1 = SE->getSCEV(ICI->getOperand(0)); - const SCEV *SCEVOP2 = SE->getSCEV(ICI->getOperand(1)); - return SE->isKnownNonNegative(SCEVOP1) && SE->isKnownNonNegative(SCEVOP2); + return IsOperandsNonNeg(ICI); }; // Replace all comparisons against trunc with comparisons against IV. for (auto *ICI : ICmpUsers) { @@ -548,6 +552,8 @@ if (CanUseZExt(ICI)) { assert(DoesZExtCollapse && "Unprofitable zext?"); Ext = new ZExtInst(Op1, IVTy, "zext", ICI); + if(IsOperandsNonNeg(ICI)) + Ext->setNonNeg(true); Pred = ICmpInst::getUnsignedPredicate(Pred); } else { assert(DoesSExtCollapse && "Unprofitable sext?"); diff --git a/llvm/test/Assembler/flags.ll b/llvm/test/Assembler/flags.ll --- a/llvm/test/Assembler/flags.ll +++ b/llvm/test/Assembler/flags.ll @@ -266,3 +266,4 @@ ret i64 %res } + diff --git a/llvm/test/Transforms/CorrelatedValuePropagation/cond-at-use.ll b/llvm/test/Transforms/CorrelatedValuePropagation/cond-at-use.ll --- a/llvm/test/Transforms/CorrelatedValuePropagation/cond-at-use.ll +++ b/llvm/test/Transforms/CorrelatedValuePropagation/cond-at-use.ll @@ -520,7 +520,7 @@ define i32 @sext_convert(i16 %x) { ; CHECK-LABEL: @sext_convert( -; CHECK-NEXT: [[EXT:%.*]] = zext i16 [[X:%.*]] to i32 +; CHECK-NEXT: [[EXT:%.*]] = zext nneg i16 [[X:%.*]] to i32 ; CHECK-NEXT: [[CMP:%.*]] = icmp sge i16 [[X]], 0 ; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 [[EXT]], i32 24 ; CHECK-NEXT: ret i32 [[SEL]] diff --git a/llvm/test/Transforms/CorrelatedValuePropagation/sext.ll b/llvm/test/Transforms/CorrelatedValuePropagation/sext.ll --- a/llvm/test/Transforms/CorrelatedValuePropagation/sext.ll +++ b/llvm/test/Transforms/CorrelatedValuePropagation/sext.ll @@ -18,13 +18,32 @@ ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[A]], -1 ; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_END:%.*]] ; CHECK: for.body: -; CHECK-NEXT: [[EXT_WIDE1:%.*]] = zext i32 [[A]] to i64 -; CHECK-NEXT: call void @use64(i64 [[EXT_WIDE1]]) -; CHECK-NEXT: [[EXT]] = trunc i64 [[EXT_WIDE1]] to i32 +; CHECK-NEXT: [[EXT_WIDE:%.*]] = zext nneg i32 [[A]] to i64 +; CHECK-NEXT: call void @use64(i64 [[EXT_WIDE]]) +; CHECK-NEXT: [[EXT]] = trunc i64 [[EXT_WIDE]] to i32 ; CHECK-NEXT: br label [[FOR_COND]] ; CHECK: for.end: ; CHECK-NEXT: ret void ; +; DEBUG-LABEL: @test1( +; DEBUG-NEXT: entry: +; DEBUG-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG16:![0-9]+]] +; DEBUG: for.cond: +; DEBUG-NEXT: [[A:%.*]] = phi i32 [ [[N:%.*]], [[ENTRY:%.*]] ], [ [[EXT:%.*]], [[FOR_BODY:%.*]] ], !dbg [[DBG17:![0-9]+]] +; DEBUG-NEXT: call void @llvm.dbg.value(metadata i32 [[A]], metadata [[META9:![0-9]+]], metadata !DIExpression()), !dbg [[DBG17]] +; DEBUG-NEXT: [[CMP:%.*]] = icmp sgt i32 [[A]], -1, !dbg [[DBG18:![0-9]+]] +; DEBUG-NEXT: call void @llvm.dbg.value(metadata i1 [[CMP]], metadata [[META11:![0-9]+]], metadata !DIExpression()), !dbg [[DBG18]] +; DEBUG-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_END:%.*]], !dbg [[DBG19:![0-9]+]] +; DEBUG: for.body: +; DEBUG-NEXT: [[EXT_WIDE:%.*]] = zext nneg i32 [[A]] to i64, !dbg [[DBG20:![0-9]+]] +; DEBUG-NEXT: call void @llvm.dbg.value(metadata i64 [[EXT_WIDE]], metadata [[META13:![0-9]+]], metadata !DIExpression()), !dbg [[DBG20]] +; DEBUG-NEXT: call void @use64(i64 [[EXT_WIDE]]), !dbg [[DBG21:![0-9]+]] +; DEBUG-NEXT: [[EXT]] = trunc i64 [[EXT_WIDE]] to i32, !dbg [[DBG22:![0-9]+]] +; DEBUG-NEXT: call void @llvm.dbg.value(metadata i32 [[EXT]], metadata [[META15:![0-9]+]], metadata !DIExpression()), !dbg [[DBG22]] +; DEBUG-NEXT: br label [[FOR_COND]], !dbg [[DBG23:![0-9]+]] +; DEBUG: for.end: +; DEBUG-NEXT: ret void, !dbg [[DBG24:![0-9]+]] +; entry: br label %for.cond @@ -60,6 +79,25 @@ ; CHECK: for.end: ; CHECK-NEXT: ret void ; +; DEBUG-LABEL: @test2( +; DEBUG-NEXT: entry: +; DEBUG-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG31:![0-9]+]] +; DEBUG: for.cond: +; DEBUG-NEXT: [[A:%.*]] = phi i32 [ [[N:%.*]], [[ENTRY:%.*]] ], [ [[EXT:%.*]], [[FOR_BODY:%.*]] ], !dbg [[DBG32:![0-9]+]] +; DEBUG-NEXT: call void @llvm.dbg.value(metadata i32 [[A]], metadata [[META27:![0-9]+]], metadata !DIExpression()), !dbg [[DBG32]] +; DEBUG-NEXT: [[CMP:%.*]] = icmp sgt i32 [[A]], -2, !dbg [[DBG33:![0-9]+]] +; DEBUG-NEXT: call void @llvm.dbg.value(metadata i1 [[CMP]], metadata [[META28:![0-9]+]], metadata !DIExpression()), !dbg [[DBG33]] +; DEBUG-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_END:%.*]], !dbg [[DBG34:![0-9]+]] +; DEBUG: for.body: +; DEBUG-NEXT: [[EXT_WIDE:%.*]] = sext i32 [[A]] to i64, !dbg [[DBG35:![0-9]+]] +; DEBUG-NEXT: call void @llvm.dbg.value(metadata i64 [[EXT_WIDE]], metadata [[META29:![0-9]+]], metadata !DIExpression()), !dbg [[DBG35]] +; DEBUG-NEXT: call void @use64(i64 [[EXT_WIDE]]), !dbg [[DBG36:![0-9]+]] +; DEBUG-NEXT: [[EXT]] = trunc i64 [[EXT_WIDE]] to i32, !dbg [[DBG37:![0-9]+]] +; DEBUG-NEXT: call void @llvm.dbg.value(metadata i32 [[EXT]], metadata [[META30:![0-9]+]], metadata !DIExpression()), !dbg [[DBG37]] +; DEBUG-NEXT: br label [[FOR_COND]], !dbg [[DBG38:![0-9]+]] +; DEBUG: for.end: +; DEBUG-NEXT: ret void, !dbg [[DBG39:![0-9]+]] +; entry: br label %for.cond @@ -85,13 +123,28 @@ ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[N:%.*]], -1 ; CHECK-NEXT: br i1 [[CMP]], label [[BB:%.*]], label [[EXIT:%.*]] ; CHECK: bb: -; CHECK-NEXT: [[EXT_WIDE1:%.*]] = zext i32 [[N]] to i64 -; CHECK-NEXT: call void @use64(i64 [[EXT_WIDE1]]) -; CHECK-NEXT: [[EXT:%.*]] = trunc i64 [[EXT_WIDE1]] to i32 +; CHECK-NEXT: [[EXT_WIDE:%.*]] = zext nneg i32 [[N]] to i64 +; CHECK-NEXT: call void @use64(i64 [[EXT_WIDE]]) +; CHECK-NEXT: [[EXT:%.*]] = trunc i64 [[EXT_WIDE]] to i32 ; CHECK-NEXT: br label [[EXIT]] ; CHECK: exit: ; CHECK-NEXT: ret void ; +; DEBUG-LABEL: @test3( +; DEBUG-NEXT: entry: +; DEBUG-NEXT: [[CMP:%.*]] = icmp sgt i32 [[N:%.*]], -1, !dbg [[DBG45:![0-9]+]] +; DEBUG-NEXT: call void @llvm.dbg.value(metadata i1 [[CMP]], metadata [[META42:![0-9]+]], metadata !DIExpression()), !dbg [[DBG45]] +; DEBUG-NEXT: br i1 [[CMP]], label [[BB:%.*]], label [[EXIT:%.*]], !dbg [[DBG46:![0-9]+]] +; DEBUG: bb: +; DEBUG-NEXT: [[EXT_WIDE:%.*]] = zext nneg i32 [[N]] to i64, !dbg [[DBG47:![0-9]+]] +; DEBUG-NEXT: call void @llvm.dbg.value(metadata i64 [[EXT_WIDE]], metadata [[META43:![0-9]+]], metadata !DIExpression()), !dbg [[DBG47]] +; DEBUG-NEXT: call void @use64(i64 [[EXT_WIDE]]), !dbg [[DBG48:![0-9]+]] +; DEBUG-NEXT: [[EXT:%.*]] = trunc i64 [[EXT_WIDE]] to i32, !dbg [[DBG49:![0-9]+]] +; DEBUG-NEXT: call void @llvm.dbg.value(metadata i32 [[EXT]], metadata [[META44:![0-9]+]], metadata !DIExpression()), !dbg [[DBG49]] +; DEBUG-NEXT: br label [[EXIT]], !dbg [[DBG50:![0-9]+]] +; DEBUG: exit: +; DEBUG-NEXT: ret void, !dbg [[DBG51:![0-9]+]] +; entry: %cmp = icmp sgt i32 %n, -1 br i1 %cmp, label %bb, label %exit @@ -120,6 +173,21 @@ ; CHECK: exit: ; CHECK-NEXT: ret void ; +; DEBUG-LABEL: @test4( +; DEBUG-NEXT: entry: +; DEBUG-NEXT: [[CMP:%.*]] = icmp sgt i32 [[N:%.*]], -2, !dbg [[DBG57:![0-9]+]] +; DEBUG-NEXT: call void @llvm.dbg.value(metadata i1 [[CMP]], metadata [[META54:![0-9]+]], metadata !DIExpression()), !dbg [[DBG57]] +; DEBUG-NEXT: br i1 [[CMP]], label [[BB:%.*]], label [[EXIT:%.*]], !dbg [[DBG58:![0-9]+]] +; DEBUG: bb: +; DEBUG-NEXT: [[EXT_WIDE:%.*]] = sext i32 [[N]] to i64, !dbg [[DBG59:![0-9]+]] +; DEBUG-NEXT: call void @llvm.dbg.value(metadata i64 [[EXT_WIDE]], metadata [[META55:![0-9]+]], metadata !DIExpression()), !dbg [[DBG59]] +; DEBUG-NEXT: call void @use64(i64 [[EXT_WIDE]]), !dbg [[DBG60:![0-9]+]] +; DEBUG-NEXT: [[EXT:%.*]] = trunc i64 [[EXT_WIDE]] to i32, !dbg [[DBG61:![0-9]+]] +; DEBUG-NEXT: call void @llvm.dbg.value(metadata i32 [[EXT]], metadata [[META56:![0-9]+]], metadata !DIExpression()), !dbg [[DBG61]] +; DEBUG-NEXT: br label [[EXIT]], !dbg [[DBG62:![0-9]+]] +; DEBUG: exit: +; DEBUG-NEXT: ret void, !dbg [[DBG63:![0-9]+]] +; entry: %cmp = icmp sgt i32 %n, -2 br i1 %cmp, label %bb, label %exit diff --git a/llvm/test/Transforms/InstCombine/2010-11-01-lshr-mask.ll b/llvm/test/Transforms/InstCombine/2010-11-01-lshr-mask.ll --- a/llvm/test/Transforms/InstCombine/2010-11-01-lshr-mask.ll +++ b/llvm/test/Transforms/InstCombine/2010-11-01-lshr-mask.ll @@ -8,7 +8,7 @@ ; CHECK-NEXT: [[T3163:%.*]] = xor i8 [[T3151]], -1 ; CHECK-NEXT: [[TMP1:%.*]] = shl i8 [[T3163]], 5 ; CHECK-NEXT: [[T4127:%.*]] = and i8 [[TMP1]], 64 -; CHECK-NEXT: [[T4086:%.*]] = zext i8 [[T4127]] to i32 +; CHECK-NEXT: [[T4086:%.*]] = zext nneg i8 [[T4127]] to i32 ; CHECK-NEXT: ret i32 [[T4086]] ; %t3151 = trunc i32 %argc to i8 diff --git a/llvm/test/Transforms/InstCombine/adjust-for-minmax.ll b/llvm/test/Transforms/InstCombine/adjust-for-minmax.ll --- a/llvm/test/Transforms/InstCombine/adjust-for-minmax.ll +++ b/llvm/test/Transforms/InstCombine/adjust-for-minmax.ll @@ -7,8 +7,8 @@ define i32 @smax1(i32 %n) { ; CHECK-LABEL: @smax1( -; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[N:%.*]], i32 0) -; CHECK-NEXT: ret i32 [[TMP1]] +; CHECK-NEXT: [[M:%.*]] = call i32 @llvm.smax.i32(i32 [[N:%.*]], i32 0) +; CHECK-NEXT: ret i32 [[M]] ; %t = icmp sgt i32 %n, 0 %m = select i1 %t, i32 %n, i32 0 @@ -19,8 +19,8 @@ define i32 @smin1(i32 %n) { ; CHECK-LABEL: @smin1( -; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smin.i32(i32 [[N:%.*]], i32 0) -; CHECK-NEXT: ret i32 [[TMP1]] +; CHECK-NEXT: [[M:%.*]] = call i32 @llvm.smin.i32(i32 [[N:%.*]], i32 0) +; CHECK-NEXT: ret i32 [[M]] ; %t = icmp slt i32 %n, 0 %m = select i1 %t, i32 %n, i32 0 @@ -31,8 +31,8 @@ define i32 @smax2(i32 %n) { ; CHECK-LABEL: @smax2( -; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[N:%.*]], i32 0) -; CHECK-NEXT: ret i32 [[TMP1]] +; CHECK-NEXT: [[M:%.*]] = call i32 @llvm.smax.i32(i32 [[N:%.*]], i32 0) +; CHECK-NEXT: ret i32 [[M]] ; %t = icmp sge i32 %n, 1 %m = select i1 %t, i32 %n, i32 0 @@ -43,8 +43,8 @@ define i32 @smin2(i32 %n) { ; CHECK-LABEL: @smin2( -; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smin.i32(i32 [[N:%.*]], i32 0) -; CHECK-NEXT: ret i32 [[TMP1]] +; CHECK-NEXT: [[M:%.*]] = call i32 @llvm.smin.i32(i32 [[N:%.*]], i32 0) +; CHECK-NEXT: ret i32 [[M]] ; %t = icmp sle i32 %n, -1 %m = select i1 %t, i32 %n, i32 0 @@ -55,8 +55,8 @@ define i32 @smax3(i32 %n) { ; CHECK-LABEL: @smax3( -; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[N:%.*]], i32 0) -; CHECK-NEXT: ret i32 [[TMP1]] +; CHECK-NEXT: [[M:%.*]] = call i32 @llvm.smax.i32(i32 [[N:%.*]], i32 0) +; CHECK-NEXT: ret i32 [[M]] ; %t = icmp sgt i32 %n, -1 %m = select i1 %t, i32 %n, i32 0 @@ -67,8 +67,8 @@ define <2 x i32> @smax3_vec(<2 x i32> %n) { ; CHECK-LABEL: @smax3_vec( -; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.smax.v2i32(<2 x i32> [[N:%.*]], <2 x i32> zeroinitializer) -; CHECK-NEXT: ret <2 x i32> [[TMP1]] +; CHECK-NEXT: [[M:%.*]] = call <2 x i32> @llvm.smax.v2i32(<2 x i32> [[N:%.*]], <2 x i32> zeroinitializer) +; CHECK-NEXT: ret <2 x i32> [[M]] ; %t = icmp sgt <2 x i32> %n, %m = select <2 x i1> %t, <2 x i32> %n, <2 x i32> zeroinitializer @@ -79,8 +79,8 @@ define i32 @smin3(i32 %n) { ; CHECK-LABEL: @smin3( -; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smin.i32(i32 [[N:%.*]], i32 0) -; CHECK-NEXT: ret i32 [[TMP1]] +; CHECK-NEXT: [[M:%.*]] = call i32 @llvm.smin.i32(i32 [[N:%.*]], i32 0) +; CHECK-NEXT: ret i32 [[M]] ; %t = icmp slt i32 %n, 1 %m = select i1 %t, i32 %n, i32 0 @@ -91,8 +91,8 @@ define <2 x i32> @smin3_vec(<2 x i32> %n) { ; CHECK-LABEL: @smin3_vec( -; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.smin.v2i32(<2 x i32> [[N:%.*]], <2 x i32> zeroinitializer) -; CHECK-NEXT: ret <2 x i32> [[TMP1]] +; CHECK-NEXT: [[M:%.*]] = call <2 x i32> @llvm.smin.v2i32(<2 x i32> [[N:%.*]], <2 x i32> zeroinitializer) +; CHECK-NEXT: ret <2 x i32> [[M]] ; %t = icmp slt <2 x i32> %n, %m = select <2 x i1> %t, <2 x i32> %n, <2 x i32> zeroinitializer @@ -103,8 +103,8 @@ define i32 @umax3(i32 %n) { ; CHECK-LABEL: @umax3( -; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.umax.i32(i32 [[N:%.*]], i32 5) -; CHECK-NEXT: ret i32 [[TMP1]] +; CHECK-NEXT: [[M:%.*]] = call i32 @llvm.umax.i32(i32 [[N:%.*]], i32 5) +; CHECK-NEXT: ret i32 [[M]] ; %t = icmp ugt i32 %n, 4 %m = select i1 %t, i32 %n, i32 5 @@ -115,8 +115,8 @@ define <2 x i32> @umax3_vec(<2 x i32> %n) { ; CHECK-LABEL: @umax3_vec( -; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.umax.v2i32(<2 x i32> [[N:%.*]], <2 x i32> ) -; CHECK-NEXT: ret <2 x i32> [[TMP1]] +; CHECK-NEXT: [[M:%.*]] = call <2 x i32> @llvm.umax.v2i32(<2 x i32> [[N:%.*]], <2 x i32> ) +; CHECK-NEXT: ret <2 x i32> [[M]] ; %t = icmp ugt <2 x i32> %n, %m = select <2 x i1> %t, <2 x i32> %n, <2 x i32> @@ -127,8 +127,8 @@ define i32 @umin3(i32 %n) { ; CHECK-LABEL: @umin3( -; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.umin.i32(i32 [[N:%.*]], i32 6) -; CHECK-NEXT: ret i32 [[TMP1]] +; CHECK-NEXT: [[M:%.*]] = call i32 @llvm.umin.i32(i32 [[N:%.*]], i32 6) +; CHECK-NEXT: ret i32 [[M]] ; %t = icmp ult i32 %n, 7 %m = select i1 %t, i32 %n, i32 6 @@ -139,8 +139,8 @@ define <2 x i32> @umin3_vec(<2 x i32> %n) { ; CHECK-LABEL: @umin3_vec( -; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.umin.v2i32(<2 x i32> [[N:%.*]], <2 x i32> ) -; CHECK-NEXT: ret <2 x i32> [[TMP1]] +; CHECK-NEXT: [[M:%.*]] = call <2 x i32> @llvm.umin.v2i32(<2 x i32> [[N:%.*]], <2 x i32> ) +; CHECK-NEXT: ret <2 x i32> [[M]] ; %t = icmp ult <2 x i32> %n, %m = select <2 x i1> %t, <2 x i32> %n, <2 x i32> @@ -151,8 +151,8 @@ define i32 @smax4(i32 %n) { ; CHECK-LABEL: @smax4( -; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[N:%.*]], i32 0) -; CHECK-NEXT: ret i32 [[TMP1]] +; CHECK-NEXT: [[M:%.*]] = call i32 @llvm.smax.i32(i32 [[N:%.*]], i32 0) +; CHECK-NEXT: ret i32 [[M]] ; %t = icmp sge i32 %n, 0 %m = select i1 %t, i32 %n, i32 0 @@ -163,8 +163,8 @@ define <2 x i32> @smax4_vec(<2 x i32> %n) { ; CHECK-LABEL: @smax4_vec( -; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.smax.v2i32(<2 x i32> [[N:%.*]], <2 x i32> zeroinitializer) -; CHECK-NEXT: ret <2 x i32> [[TMP1]] +; CHECK-NEXT: [[M:%.*]] = call <2 x i32> @llvm.smax.v2i32(<2 x i32> [[N:%.*]], <2 x i32> zeroinitializer) +; CHECK-NEXT: ret <2 x i32> [[M]] ; %t = icmp sge <2 x i32> %n, zeroinitializer %m = select <2 x i1> %t, <2 x i32> %n, <2 x i32> zeroinitializer @@ -175,8 +175,8 @@ define i32 @smin4(i32 %n) { ; CHECK-LABEL: @smin4( -; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smin.i32(i32 [[N:%.*]], i32 0) -; CHECK-NEXT: ret i32 [[TMP1]] +; CHECK-NEXT: [[M:%.*]] = call i32 @llvm.smin.i32(i32 [[N:%.*]], i32 0) +; CHECK-NEXT: ret i32 [[M]] ; %t = icmp sle i32 %n, 0 %m = select i1 %t, i32 %n, i32 0 @@ -187,8 +187,8 @@ define <2 x i32> @smin4_vec(<2 x i32> %n) { ; CHECK-LABEL: @smin4_vec( -; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.smin.v2i32(<2 x i32> [[N:%.*]], <2 x i32> zeroinitializer) -; CHECK-NEXT: ret <2 x i32> [[TMP1]] +; CHECK-NEXT: [[M:%.*]] = call <2 x i32> @llvm.smin.v2i32(<2 x i32> [[N:%.*]], <2 x i32> zeroinitializer) +; CHECK-NEXT: ret <2 x i32> [[M]] ; %t = icmp sle <2 x i32> %n, zeroinitializer %m = select <2 x i1> %t, <2 x i32> %n, <2 x i32> zeroinitializer @@ -199,8 +199,8 @@ define i32 @umax4(i32 %n) { ; CHECK-LABEL: @umax4( -; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.umax.i32(i32 [[N:%.*]], i32 8) -; CHECK-NEXT: ret i32 [[TMP1]] +; CHECK-NEXT: [[M:%.*]] = call i32 @llvm.umax.i32(i32 [[N:%.*]], i32 8) +; CHECK-NEXT: ret i32 [[M]] ; %t = icmp uge i32 %n, 8 %m = select i1 %t, i32 %n, i32 8 @@ -211,8 +211,8 @@ define <2 x i32> @umax4_vec(<2 x i32> %n) { ; CHECK-LABEL: @umax4_vec( -; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.umax.v2i32(<2 x i32> [[N:%.*]], <2 x i32> ) -; CHECK-NEXT: ret <2 x i32> [[TMP1]] +; CHECK-NEXT: [[M:%.*]] = call <2 x i32> @llvm.umax.v2i32(<2 x i32> [[N:%.*]], <2 x i32> ) +; CHECK-NEXT: ret <2 x i32> [[M]] ; %t = icmp uge <2 x i32> %n, %m = select <2 x i1> %t, <2 x i32> %n, <2 x i32> @@ -223,8 +223,8 @@ define i32 @umin4(i32 %n) { ; CHECK-LABEL: @umin4( -; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.umin.i32(i32 [[N:%.*]], i32 9) -; CHECK-NEXT: ret i32 [[TMP1]] +; CHECK-NEXT: [[M:%.*]] = call i32 @llvm.umin.i32(i32 [[N:%.*]], i32 9) +; CHECK-NEXT: ret i32 [[M]] ; %t = icmp ule i32 %n, 9 %m = select i1 %t, i32 %n, i32 9 @@ -235,8 +235,8 @@ define <2 x i32> @umin4_vec(<2 x i32> %n) { ; CHECK-LABEL: @umin4_vec( -; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.umin.v2i32(<2 x i32> [[N:%.*]], <2 x i32> ) -; CHECK-NEXT: ret <2 x i32> [[TMP1]] +; CHECK-NEXT: [[M:%.*]] = call <2 x i32> @llvm.umin.v2i32(<2 x i32> [[N:%.*]], <2 x i32> ) +; CHECK-NEXT: ret <2 x i32> [[M]] ; %t = icmp ule <2 x i32> %n, %m = select <2 x i1> %t, <2 x i32> %n, <2 x i32> @@ -246,8 +246,8 @@ define i64 @smax_sext(i32 %a) { ; CHECK-LABEL: @smax_sext( ; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[A:%.*]], i32 0) -; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -; CHECK-NEXT: ret i64 [[TMP2]] +; CHECK-NEXT: [[MAX:%.*]] = zext nneg i32 [[TMP1]] to i64 +; CHECK-NEXT: ret i64 [[MAX]] ; %a_ext = sext i32 %a to i64 %cmp = icmp sgt i32 %a, -1 @@ -258,8 +258,8 @@ define <2 x i64> @smax_sext_vec(<2 x i32> %a) { ; CHECK-LABEL: @smax_sext_vec( ; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.smax.v2i32(<2 x i32> [[A:%.*]], <2 x i32> zeroinitializer) -; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64> -; CHECK-NEXT: ret <2 x i64> [[TMP2]] +; CHECK-NEXT: [[MAX:%.*]] = zext nneg <2 x i32> [[TMP1]] to <2 x i64> +; CHECK-NEXT: ret <2 x i64> [[MAX]] ; %a_ext = sext <2 x i32> %a to <2 x i64> %cmp = icmp sgt <2 x i32> %a, @@ -270,8 +270,8 @@ define i64 @smin_sext(i32 %a) { ; CHECK-LABEL: @smin_sext( ; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smin.i32(i32 [[A:%.*]], i32 0) -; CHECK-NEXT: [[TMP2:%.*]] = sext i32 [[TMP1]] to i64 -; CHECK-NEXT: ret i64 [[TMP2]] +; CHECK-NEXT: [[MIN:%.*]] = sext i32 [[TMP1]] to i64 +; CHECK-NEXT: ret i64 [[MIN]] ; %a_ext = sext i32 %a to i64 %cmp = icmp slt i32 %a, 1 @@ -282,8 +282,8 @@ define <2 x i64>@smin_sext_vec(<2 x i32> %a) { ; CHECK-LABEL: @smin_sext_vec( ; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.smin.v2i32(<2 x i32> [[A:%.*]], <2 x i32> zeroinitializer) -; CHECK-NEXT: [[TMP2:%.*]] = sext <2 x i32> [[TMP1]] to <2 x i64> -; CHECK-NEXT: ret <2 x i64> [[TMP2]] +; CHECK-NEXT: [[MIN:%.*]] = sext <2 x i32> [[TMP1]] to <2 x i64> +; CHECK-NEXT: ret <2 x i64> [[MIN]] ; %a_ext = sext <2 x i32> %a to <2 x i64> %cmp = icmp slt <2 x i32> %a, @@ -294,8 +294,8 @@ define i64 @umax_sext(i32 %a) { ; CHECK-LABEL: @umax_sext( ; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.umax.i32(i32 [[A:%.*]], i32 3) -; CHECK-NEXT: [[TMP2:%.*]] = sext i32 [[TMP1]] to i64 -; CHECK-NEXT: ret i64 [[TMP2]] +; CHECK-NEXT: [[MAX:%.*]] = sext i32 [[TMP1]] to i64 +; CHECK-NEXT: ret i64 [[MAX]] ; %a_ext = sext i32 %a to i64 %cmp = icmp ugt i32 %a, 2 @@ -306,8 +306,8 @@ define <2 x i64> @umax_sext_vec(<2 x i32> %a) { ; CHECK-LABEL: @umax_sext_vec( ; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.umax.v2i32(<2 x i32> [[A:%.*]], <2 x i32> ) -; CHECK-NEXT: [[TMP2:%.*]] = sext <2 x i32> [[TMP1]] to <2 x i64> -; CHECK-NEXT: ret <2 x i64> [[TMP2]] +; CHECK-NEXT: [[MAX:%.*]] = sext <2 x i32> [[TMP1]] to <2 x i64> +; CHECK-NEXT: ret <2 x i64> [[MAX]] ; %a_ext = sext <2 x i32> %a to <2 x i64> %cmp = icmp ugt <2 x i32> %a, @@ -318,8 +318,8 @@ define i64 @umin_sext(i32 %a) { ; CHECK-LABEL: @umin_sext( ; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.umin.i32(i32 [[A:%.*]], i32 2) -; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -; CHECK-NEXT: ret i64 [[TMP2]] +; CHECK-NEXT: [[MIN:%.*]] = zext nneg i32 [[TMP1]] to i64 +; CHECK-NEXT: ret i64 [[MIN]] ; %a_ext = sext i32 %a to i64 %cmp = icmp ult i32 %a, 3 @@ -330,8 +330,8 @@ define <2 x i64> @umin_sext_vec(<2 x i32> %a) { ; CHECK-LABEL: @umin_sext_vec( ; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.umin.v2i32(<2 x i32> [[A:%.*]], <2 x i32> ) -; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64> -; CHECK-NEXT: ret <2 x i64> [[TMP2]] +; CHECK-NEXT: [[MIN:%.*]] = zext nneg <2 x i32> [[TMP1]] to <2 x i64> +; CHECK-NEXT: ret <2 x i64> [[MIN]] ; %a_ext = sext <2 x i32> %a to <2 x i64> %cmp = icmp ult <2 x i32> %a, @@ -342,8 +342,8 @@ define i64 @umax_sext2(i32 %a) { ; CHECK-LABEL: @umax_sext2( ; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.umax.i32(i32 [[A:%.*]], i32 2) -; CHECK-NEXT: [[TMP2:%.*]] = sext i32 [[TMP1]] to i64 -; CHECK-NEXT: ret i64 [[TMP2]] +; CHECK-NEXT: [[MIN:%.*]] = sext i32 [[TMP1]] to i64 +; CHECK-NEXT: ret i64 [[MIN]] ; %a_ext = sext i32 %a to i64 %cmp = icmp ult i32 %a, 3 @@ -354,8 +354,8 @@ define <2 x i64> @umax_sext2_vec(<2 x i32> %a) { ; CHECK-LABEL: @umax_sext2_vec( ; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.umax.v2i32(<2 x i32> [[A:%.*]], <2 x i32> ) -; CHECK-NEXT: [[TMP2:%.*]] = sext <2 x i32> [[TMP1]] to <2 x i64> -; CHECK-NEXT: ret <2 x i64> [[TMP2]] +; CHECK-NEXT: [[MIN:%.*]] = sext <2 x i32> [[TMP1]] to <2 x i64> +; CHECK-NEXT: ret <2 x i64> [[MIN]] ; %a_ext = sext <2 x i32> %a to <2 x i64> %cmp = icmp ult <2 x i32> %a, @@ -366,8 +366,8 @@ define i64 @umin_sext2(i32 %a) { ; CHECK-LABEL: @umin_sext2( ; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.umin.i32(i32 [[A:%.*]], i32 3) -; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -; CHECK-NEXT: ret i64 [[TMP2]] +; CHECK-NEXT: [[MIN:%.*]] = zext nneg i32 [[TMP1]] to i64 +; CHECK-NEXT: ret i64 [[MIN]] ; %a_ext = sext i32 %a to i64 %cmp = icmp ugt i32 %a, 2 @@ -378,8 +378,8 @@ define <2 x i64> @umin_sext2_vec(<2 x i32> %a) { ; CHECK-LABEL: @umin_sext2_vec( ; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.umin.v2i32(<2 x i32> [[A:%.*]], <2 x i32> ) -; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64> -; CHECK-NEXT: ret <2 x i64> [[TMP2]] +; CHECK-NEXT: [[MIN:%.*]] = zext nneg <2 x i32> [[TMP1]] to <2 x i64> +; CHECK-NEXT: ret <2 x i64> [[MIN]] ; %a_ext = sext <2 x i32> %a to <2 x i64> %cmp = icmp ugt <2 x i32> %a, @@ -390,8 +390,8 @@ define i64 @umax_zext(i32 %a) { ; CHECK-LABEL: @umax_zext( ; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.umax.i32(i32 [[A:%.*]], i32 3) -; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -; CHECK-NEXT: ret i64 [[TMP2]] +; CHECK-NEXT: [[MAX:%.*]] = zext i32 [[TMP1]] to i64 +; CHECK-NEXT: ret i64 [[MAX]] ; %a_ext = zext i32 %a to i64 %cmp = icmp ugt i32 %a, 2 @@ -402,8 +402,8 @@ define <2 x i64> @umax_zext_vec(<2 x i32> %a) { ; CHECK-LABEL: @umax_zext_vec( ; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.umax.v2i32(<2 x i32> [[A:%.*]], <2 x i32> ) -; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64> -; CHECK-NEXT: ret <2 x i64> [[TMP2]] +; CHECK-NEXT: [[MAX:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64> +; CHECK-NEXT: ret <2 x i64> [[MAX]] ; %a_ext = zext <2 x i32> %a to <2 x i64> %cmp = icmp ugt <2 x i32> %a, @@ -414,8 +414,8 @@ define i64 @umin_zext(i32 %a) { ; CHECK-LABEL: @umin_zext( ; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.umin.i32(i32 [[A:%.*]], i32 2) -; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -; CHECK-NEXT: ret i64 [[TMP2]] +; CHECK-NEXT: [[MIN:%.*]] = zext nneg i32 [[TMP1]] to i64 +; CHECK-NEXT: ret i64 [[MIN]] ; %a_ext = zext i32 %a to i64 %cmp = icmp ult i32 %a, 3 @@ -426,8 +426,8 @@ define <2 x i64> @umin_zext_vec(<2 x i32> %a) { ; CHECK-LABEL: @umin_zext_vec( ; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.umin.v2i32(<2 x i32> [[A:%.*]], <2 x i32> ) -; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64> -; CHECK-NEXT: ret <2 x i64> [[TMP2]] +; CHECK-NEXT: [[MIN:%.*]] = zext nneg <2 x i32> [[TMP1]] to <2 x i64> +; CHECK-NEXT: ret <2 x i64> [[MIN]] ; %a_ext = zext <2 x i32> %a to <2 x i64> %cmp = icmp ult <2 x i32> %a, diff --git a/llvm/test/Transforms/InstCombine/and-narrow.ll b/llvm/test/Transforms/InstCombine/and-narrow.ll --- a/llvm/test/Transforms/InstCombine/and-narrow.ll +++ b/llvm/test/Transforms/InstCombine/and-narrow.ll @@ -47,7 +47,7 @@ ; CHECK-LABEL: @zext_lshr( ; CHECK-NEXT: [[TMP1:%.*]] = lshr i8 [[X:%.*]], 4 ; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X]] -; CHECK-NEXT: [[R:%.*]] = zext i8 [[TMP2]] to i16 +; CHECK-NEXT: [[R:%.*]] = zext nneg i8 [[TMP2]] to i16 ; CHECK-NEXT: ret i16 [[R]] ; %z = zext i8 %x to i16 @@ -60,7 +60,7 @@ ; CHECK-LABEL: @zext_ashr( ; CHECK-NEXT: [[TMP1:%.*]] = lshr i8 [[X:%.*]], 2 ; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X]] -; CHECK-NEXT: [[R:%.*]] = zext i8 [[TMP2]] to i16 +; CHECK-NEXT: [[R:%.*]] = zext nneg i8 [[TMP2]] to i16 ; CHECK-NEXT: ret i16 [[R]] ; %z = zext i8 %x to i16 @@ -125,7 +125,7 @@ ; CHECK-LABEL: @zext_lshr_vec( ; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i8> [[X:%.*]], ; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i8> [[TMP1]], [[X]] -; CHECK-NEXT: [[R:%.*]] = zext <2 x i8> [[TMP2]] to <2 x i16> +; CHECK-NEXT: [[R:%.*]] = zext nneg <2 x i8> [[TMP2]] to <2 x i16> ; CHECK-NEXT: ret <2 x i16> [[R]] ; %z = zext <2 x i8> %x to <2 x i16> @@ -138,7 +138,7 @@ ; CHECK-LABEL: @zext_ashr_vec( ; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i8> [[X:%.*]], ; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i8> [[TMP1]], [[X]] -; CHECK-NEXT: [[R:%.*]] = zext <2 x i8> [[TMP2]] to <2 x i16> +; CHECK-NEXT: [[R:%.*]] = zext nneg <2 x i8> [[TMP2]] to <2 x i16> ; CHECK-NEXT: ret <2 x i16> [[R]] ; %z = zext <2 x i8> %x to <2 x i16> diff --git a/llvm/test/Transforms/InstCombine/and-xor-or.ll b/llvm/test/Transforms/InstCombine/and-xor-or.ll --- a/llvm/test/Transforms/InstCombine/and-xor-or.ll +++ b/llvm/test/Transforms/InstCombine/and-xor-or.ll @@ -4210,7 +4210,7 @@ ; CHECK-SAME: (i8 [[X:%.*]], i4 [[Y:%.*]]) { ; CHECK-NEXT: [[TMP1:%.*]] = zext i4 [[Y]] to i8 ; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X]] -; CHECK-NEXT: [[R:%.*]] = zext i8 [[TMP2]] to i16 +; CHECK-NEXT: [[R:%.*]] = zext nneg i8 [[TMP2]] to i16 ; CHECK-NEXT: ret i16 [[R]] ; %zx = zext i8 %x to i16 diff --git a/llvm/test/Transforms/InstCombine/and.ll b/llvm/test/Transforms/InstCombine/and.ll --- a/llvm/test/Transforms/InstCombine/and.ll +++ b/llvm/test/Transforms/InstCombine/and.ll @@ -525,7 +525,7 @@ define i32 @and_zext_demanded(i16 %x, i32 %y) { ; CHECK-LABEL: @and_zext_demanded( ; CHECK-NEXT: [[S:%.*]] = lshr i16 [[X:%.*]], 8 -; CHECK-NEXT: [[Z:%.*]] = zext i16 [[S]] to i32 +; CHECK-NEXT: [[Z:%.*]] = zext nneg i16 [[S]] to i32 ; CHECK-NEXT: ret i32 [[Z]] ; %s = lshr i16 %x, 8 @@ -618,7 +618,7 @@ ; CHECK-LABEL: @test35( ; CHECK-NEXT: [[TMP1:%.*]] = sub i32 0, [[X:%.*]] ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 240 -; CHECK-NEXT: [[RES:%.*]] = zext i32 [[TMP2]] to i64 +; CHECK-NEXT: [[RES:%.*]] = zext nneg i32 [[TMP2]] to i64 ; CHECK-NEXT: ret i64 [[RES]] ; %zext = zext i32 %X to i64 @@ -631,7 +631,7 @@ ; CHECK-LABEL: @test35_uniform( ; CHECK-NEXT: [[TMP1:%.*]] = sub <2 x i32> zeroinitializer, [[X:%.*]] ; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i32> [[TMP1]], -; CHECK-NEXT: [[RES:%.*]] = zext <2 x i32> [[TMP2]] to <2 x i64> +; CHECK-NEXT: [[RES:%.*]] = zext nneg <2 x i32> [[TMP2]] to <2 x i64> ; CHECK-NEXT: ret <2 x i64> [[RES]] ; %zext = zext <2 x i32> %X to <2 x i64> @@ -644,7 +644,7 @@ ; CHECK-LABEL: @test36( ; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], 7 ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 240 -; CHECK-NEXT: [[RES:%.*]] = zext i32 [[TMP2]] to i64 +; CHECK-NEXT: [[RES:%.*]] = zext nneg i32 [[TMP2]] to i64 ; CHECK-NEXT: ret i64 [[RES]] ; %zext = zext i32 %X to i64 @@ -657,7 +657,7 @@ ; CHECK-LABEL: @test36_uniform( ; CHECK-NEXT: [[TMP1:%.*]] = add <2 x i32> [[X:%.*]], ; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i32> [[TMP1]], -; CHECK-NEXT: [[RES:%.*]] = zext <2 x i32> [[TMP2]] to <2 x i64> +; CHECK-NEXT: [[RES:%.*]] = zext nneg <2 x i32> [[TMP2]] to <2 x i64> ; CHECK-NEXT: ret <2 x i64> [[RES]] ; %zext = zext <2 x i32> %X to <2 x i64> @@ -683,7 +683,7 @@ ; CHECK-LABEL: @test37( ; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[X:%.*]], 7 ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 240 -; CHECK-NEXT: [[RES:%.*]] = zext i32 [[TMP2]] to i64 +; CHECK-NEXT: [[RES:%.*]] = zext nneg i32 [[TMP2]] to i64 ; CHECK-NEXT: ret i64 [[RES]] ; %zext = zext i32 %X to i64 @@ -696,7 +696,7 @@ ; CHECK-LABEL: @test37_uniform( ; CHECK-NEXT: [[TMP1:%.*]] = mul <2 x i32> [[X:%.*]], ; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i32> [[TMP1]], -; CHECK-NEXT: [[RES:%.*]] = zext <2 x i32> [[TMP2]] to <2 x i64> +; CHECK-NEXT: [[RES:%.*]] = zext nneg <2 x i32> [[TMP2]] to <2 x i64> ; CHECK-NEXT: ret <2 x i64> [[RES]] ; %zext = zext <2 x i32> %X to <2 x i64> @@ -721,7 +721,7 @@ define i64 @test38(i32 %X) { ; CHECK-LABEL: @test38( ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 240 -; CHECK-NEXT: [[RES:%.*]] = zext i32 [[TMP1]] to i64 +; CHECK-NEXT: [[RES:%.*]] = zext nneg i32 [[TMP1]] to i64 ; CHECK-NEXT: ret i64 [[RES]] ; %zext = zext i32 %X to i64 @@ -733,7 +733,7 @@ define i64 @test39(i32 %X) { ; CHECK-LABEL: @test39( ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 240 -; CHECK-NEXT: [[RES:%.*]] = zext i32 [[TMP1]] to i64 +; CHECK-NEXT: [[RES:%.*]] = zext nneg i32 [[TMP1]] to i64 ; CHECK-NEXT: ret i64 [[RES]] ; %zext = zext i32 %X to i64 diff --git a/llvm/test/Transforms/InstCombine/assoc-cast-assoc.ll b/llvm/test/Transforms/InstCombine/assoc-cast-assoc.ll --- a/llvm/test/Transforms/InstCombine/assoc-cast-assoc.ll +++ b/llvm/test/Transforms/InstCombine/assoc-cast-assoc.ll @@ -3,7 +3,7 @@ define i5 @XorZextXor(i3 %a) { ; CHECK-LABEL: @XorZextXor( -; CHECK-NEXT: [[CAST:%.*]] = zext i3 %a to i5 +; CHECK-NEXT: [[CAST:%.*]] = zext i3 [[A:%.*]] to i5 ; CHECK-NEXT: [[OP2:%.*]] = xor i5 [[CAST]], 15 ; CHECK-NEXT: ret i5 [[OP2]] ; @@ -15,7 +15,7 @@ define <2 x i32> @XorZextXorVec(<2 x i1> %a) { ; CHECK-LABEL: @XorZextXorVec( -; CHECK-NEXT: [[CAST:%.*]] = zext <2 x i1> %a to <2 x i32> +; CHECK-NEXT: [[CAST:%.*]] = zext <2 x i1> [[A:%.*]] to <2 x i32> ; CHECK-NEXT: [[OP2:%.*]] = xor <2 x i32> [[CAST]], ; CHECK-NEXT: ret <2 x i32> [[OP2]] ; @@ -27,7 +27,7 @@ define i5 @OrZextOr(i3 %a) { ; CHECK-LABEL: @OrZextOr( -; CHECK-NEXT: [[CAST:%.*]] = zext i3 %a to i5 +; CHECK-NEXT: [[CAST:%.*]] = zext i3 [[A:%.*]] to i5 ; CHECK-NEXT: [[OP2:%.*]] = or i5 [[CAST]], 11 ; CHECK-NEXT: ret i5 [[OP2]] ; @@ -39,7 +39,7 @@ define <2 x i32> @OrZextOrVec(<2 x i2> %a) { ; CHECK-LABEL: @OrZextOrVec( -; CHECK-NEXT: [[CAST:%.*]] = zext <2 x i2> %a to <2 x i32> +; CHECK-NEXT: [[CAST:%.*]] = zext <2 x i2> [[A:%.*]] to <2 x i32> ; CHECK-NEXT: [[OP2:%.*]] = or <2 x i32> [[CAST]], ; CHECK-NEXT: ret <2 x i32> [[OP2]] ; @@ -53,8 +53,8 @@ define i5 @AndZextAnd(i3 %a) { ; CHECK-LABEL: @AndZextAnd( -; CHECK-NEXT: [[TMP1:%.*]] = and i3 %a, 2 -; CHECK-NEXT: [[OP2:%.*]] = zext i3 [[TMP1]] to i5 +; CHECK-NEXT: [[TMP1:%.*]] = and i3 [[A:%.*]], 2 +; CHECK-NEXT: [[OP2:%.*]] = zext nneg i3 [[TMP1]] to i5 ; CHECK-NEXT: ret i5 [[OP2]] ; %op1 = and i3 %a, 3 @@ -65,8 +65,8 @@ define <2 x i32> @AndZextAndVec(<2 x i8> %a) { ; CHECK-LABEL: @AndZextAndVec( -; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i8> %a, -; CHECK-NEXT: [[OP2:%.*]] = zext <2 x i8> [[TMP1]] to <2 x i32> +; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i8> [[A:%.*]], +; CHECK-NEXT: [[OP2:%.*]] = zext nneg <2 x i8> [[TMP1]] to <2 x i32> ; CHECK-NEXT: ret <2 x i32> [[OP2]] ; %op1 = and <2 x i8> %a, diff --git a/llvm/test/Transforms/InstCombine/cast-mul-select.ll b/llvm/test/Transforms/InstCombine/cast-mul-select.ll --- a/llvm/test/Transforms/InstCombine/cast-mul-select.ll +++ b/llvm/test/Transforms/InstCombine/cast-mul-select.ll @@ -9,17 +9,20 @@ ; CHECK-NEXT: [[C:%.*]] = mul i32 [[X:%.*]], [[Y:%.*]] ; CHECK-NEXT: [[D:%.*]] = and i32 [[C]], 255 ; CHECK-NEXT: ret i32 [[D]] +; +; DBGINFO-LABEL: @mul( +; DBGINFO-NEXT: call void @llvm.dbg.value(metadata i32 [[X:%.*]], metadata [[META9:![0-9]+]], metadata !DIExpression(DW_OP_LLVM_convert, 32, DW_ATE_unsigned, DW_OP_LLVM_convert, 8, DW_ATE_unsigned, DW_OP_stack_value)), !dbg [[DBG15:![0-9]+]] +; DBGINFO-NEXT: call void @llvm.dbg.value(metadata i32 [[Y:%.*]], metadata [[META11:![0-9]+]], metadata !DIExpression(DW_OP_LLVM_convert, 32, DW_ATE_unsigned, DW_OP_LLVM_convert, 8, DW_ATE_unsigned, DW_OP_stack_value)), !dbg [[DBG16:![0-9]+]] +; DBGINFO-NEXT: [[C:%.*]] = mul i32 [[X]], [[Y]], !dbg [[DBG17:![0-9]+]] +; DBGINFO-NEXT: [[D:%.*]] = and i32 [[C]], 255, !dbg [[DBG18:![0-9]+]] +; DBGINFO-NEXT: call void @llvm.dbg.value(metadata i32 [[C]], metadata [[META12:![0-9]+]], metadata !DIExpression()), !dbg [[DBG17]] +; DBGINFO-NEXT: call void @llvm.dbg.value(metadata i32 [[D]], metadata [[META13:![0-9]+]], metadata !DIExpression()), !dbg [[DBG18]] +; DBGINFO-NEXT: ret i32 [[D]], !dbg [[DBG19:![0-9]+]] +; ; Test that when zext is evaluated in different type ; we preserve the debug information in the resulting ; instruction. -; DBGINFO-LABEL: @mul( -; DBGINFO-NEXT: call void @llvm.dbg.value(metadata i32 %x, {{.*}} !DIExpression(DW_OP_LLVM_convert, 32, DW_ATE_unsigned, DW_OP_LLVM_convert, 8, DW_ATE_unsigned, DW_OP_stack_value)) -; DBGINFO-NEXT: call void @llvm.dbg.value(metadata i32 %y, {{.*}} !DIExpression(DW_OP_LLVM_convert, 32, DW_ATE_unsigned, DW_OP_LLVM_convert, 8, DW_ATE_unsigned, DW_OP_stack_value)) -; DBGINFO-NEXT: [[C:%.*]] = mul i32 {{.*}} -; DBGINFO-NEXT: [[D:%.*]] = and i32 {{.*}} -; DBGINFO-NEXT: call void @llvm.dbg.value(metadata i32 [[C]] -; DBGINFO-NEXT: call void @llvm.dbg.value(metadata i32 [[D]] %A = trunc i32 %x to i8 %B = trunc i32 %y to i8 @@ -34,6 +37,18 @@ ; CHECK-NEXT: [[E:%.*]] = select i1 [[COND:%.*]], i32 [[Z:%.*]], i32 [[D]] ; CHECK-NEXT: [[F:%.*]] = and i32 [[E]], 255 ; CHECK-NEXT: ret i32 [[F]] +; +; DBGINFO-LABEL: @select1( +; DBGINFO-NEXT: call void @llvm.dbg.value(metadata i32 [[X:%.*]], metadata [[META22:![0-9]+]], metadata !DIExpression(DW_OP_LLVM_convert, 32, DW_ATE_unsigned, DW_OP_LLVM_convert, 8, DW_ATE_unsigned, DW_OP_stack_value)), !dbg [[DBG28:![0-9]+]] +; DBGINFO-NEXT: call void @llvm.dbg.value(metadata i32 [[Y:%.*]], metadata [[META23:![0-9]+]], metadata !DIExpression(DW_OP_LLVM_convert, 32, DW_ATE_unsigned, DW_OP_LLVM_convert, 8, DW_ATE_unsigned, DW_OP_stack_value)), !dbg [[DBG29:![0-9]+]] +; DBGINFO-NEXT: call void @llvm.dbg.value(metadata i32 [[Z:%.*]], metadata [[META24:![0-9]+]], metadata !DIExpression(DW_OP_LLVM_convert, 32, DW_ATE_unsigned, DW_OP_LLVM_convert, 8, DW_ATE_unsigned, DW_OP_stack_value)), !dbg [[DBG30:![0-9]+]] +; DBGINFO-NEXT: [[D:%.*]] = add i32 [[X]], [[Y]], !dbg [[DBG31:![0-9]+]] +; DBGINFO-NEXT: call void @llvm.dbg.value(metadata !DIArgList(i32 [[X]], i32 [[Y]]), metadata [[META25:![0-9]+]], metadata !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_convert, 32, DW_ATE_unsigned, DW_OP_LLVM_convert, 8, DW_ATE_unsigned, DW_OP_LLVM_arg, 1, DW_OP_LLVM_convert, 32, DW_ATE_unsigned, DW_OP_LLVM_convert, 8, DW_ATE_unsigned, DW_OP_plus, DW_OP_stack_value)), !dbg [[DBG31]] +; DBGINFO-NEXT: [[E:%.*]] = select i1 [[COND:%.*]], i32 [[Z]], i32 [[D]], !dbg [[DBG32:![0-9]+]] +; DBGINFO-NEXT: [[F:%.*]] = and i32 [[E]], 255, !dbg [[DBG33:![0-9]+]] +; DBGINFO-NEXT: call void @llvm.dbg.value(metadata i32 [[E]], metadata [[META26:![0-9]+]], metadata !DIExpression()), !dbg [[DBG32]] +; DBGINFO-NEXT: call void @llvm.dbg.value(metadata i32 [[F]], metadata [[META27:![0-9]+]], metadata !DIExpression()), !dbg [[DBG33]] +; DBGINFO-NEXT: ret i32 [[F]], !dbg [[DBG34:![0-9]+]] ; %A = trunc i32 %x to i8 %B = trunc i32 %y to i8 @@ -49,6 +64,17 @@ ; CHECK-NEXT: [[D:%.*]] = add i8 [[X:%.*]], [[Y:%.*]] ; CHECK-NEXT: [[E:%.*]] = select i1 [[COND:%.*]], i8 [[Z:%.*]], i8 [[D]] ; CHECK-NEXT: ret i8 [[E]] +; +; DBGINFO-LABEL: @select2( +; DBGINFO-NEXT: call void @llvm.dbg.value(metadata i8 [[X:%.*]], metadata [[META37:![0-9]+]], metadata !DIExpression(DW_OP_LLVM_convert, 8, DW_ATE_unsigned, DW_OP_LLVM_convert, 32, DW_ATE_unsigned, DW_OP_stack_value)), !dbg [[DBG43:![0-9]+]] +; DBGINFO-NEXT: call void @llvm.dbg.value(metadata i8 [[Y:%.*]], metadata [[META38:![0-9]+]], metadata !DIExpression(DW_OP_LLVM_convert, 8, DW_ATE_unsigned, DW_OP_LLVM_convert, 32, DW_ATE_unsigned, DW_OP_stack_value)), !dbg [[DBG44:![0-9]+]] +; DBGINFO-NEXT: call void @llvm.dbg.value(metadata i8 [[Z:%.*]], metadata [[META39:![0-9]+]], metadata !DIExpression(DW_OP_LLVM_convert, 8, DW_ATE_unsigned, DW_OP_LLVM_convert, 32, DW_ATE_unsigned, DW_OP_stack_value)), !dbg [[DBG45:![0-9]+]] +; DBGINFO-NEXT: [[D:%.*]] = add i8 [[X]], [[Y]], !dbg [[DBG46:![0-9]+]] +; DBGINFO-NEXT: call void @llvm.dbg.value(metadata !DIArgList(i8 [[X]], i8 [[Y]]), metadata [[META40:![0-9]+]], metadata !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_convert, 8, DW_ATE_unsigned, DW_OP_LLVM_convert, 32, DW_ATE_unsigned, DW_OP_LLVM_arg, 1, DW_OP_LLVM_convert, 8, DW_ATE_unsigned, DW_OP_LLVM_convert, 32, DW_ATE_unsigned, DW_OP_plus, DW_OP_stack_value)), !dbg [[DBG46]] +; DBGINFO-NEXT: [[E:%.*]] = select i1 [[COND:%.*]], i8 [[Z]], i8 [[D]], !dbg [[DBG47:![0-9]+]] +; DBGINFO-NEXT: call void @llvm.dbg.value(metadata i32 poison, metadata [[META41:![0-9]+]], metadata !DIExpression()), !dbg [[DBG47]] +; DBGINFO-NEXT: call void @llvm.dbg.value(metadata i8 [[E]], metadata [[META42:![0-9]+]], metadata !DIExpression()), !dbg [[DBG48:![0-9]+]] +; DBGINFO-NEXT: ret i8 [[E]], !dbg [[DBG49:![0-9]+]] ; %A = zext i8 %x to i32 %B = zext i8 %y to i32 @@ -69,6 +95,17 @@ ; CHECK-NEXT: [[M:%.*]] = mul i64 [[A]], [[A]] ; CHECK-NEXT: [[T:%.*]] = trunc i64 [[M]] to i32 ; CHECK-NEXT: ret i32 [[T]] +; +; DBGINFO-LABEL: @eval_trunc_multi_use_in_one_inst( +; DBGINFO-NEXT: [[Z:%.*]] = zext i32 [[X:%.*]] to i64, !dbg [[DBG57:![0-9]+]] +; DBGINFO-NEXT: call void @llvm.dbg.value(metadata i64 [[Z]], metadata [[META52:![0-9]+]], metadata !DIExpression()), !dbg [[DBG57]] +; DBGINFO-NEXT: [[A:%.*]] = add nuw nsw i64 [[Z]], 15, !dbg [[DBG58:![0-9]+]] +; DBGINFO-NEXT: call void @llvm.dbg.value(metadata i64 [[A]], metadata [[META54:![0-9]+]], metadata !DIExpression()), !dbg [[DBG58]] +; DBGINFO-NEXT: [[M:%.*]] = mul i64 [[A]], [[A]], !dbg [[DBG59:![0-9]+]] +; DBGINFO-NEXT: call void @llvm.dbg.value(metadata i64 [[M]], metadata [[META55:![0-9]+]], metadata !DIExpression()), !dbg [[DBG59]] +; DBGINFO-NEXT: [[T:%.*]] = trunc i64 [[M]] to i32, !dbg [[DBG60:![0-9]+]] +; DBGINFO-NEXT: call void @llvm.dbg.value(metadata i32 [[T]], metadata [[META56:![0-9]+]], metadata !DIExpression()), !dbg [[DBG60]] +; DBGINFO-NEXT: ret i32 [[T]], !dbg [[DBG61:![0-9]+]] ; %z = zext i32 %x to i64 %a = add nsw nuw i64 %z, 15 @@ -82,8 +119,19 @@ ; CHECK-NEXT: [[T:%.*]] = trunc i32 [[X:%.*]] to i16 ; CHECK-NEXT: [[A:%.*]] = and i16 [[T]], 5 ; CHECK-NEXT: [[M:%.*]] = mul nuw nsw i16 [[A]], [[A]] -; CHECK-NEXT: [[R:%.*]] = zext i16 [[M]] to i32 +; CHECK-NEXT: [[R:%.*]] = zext nneg i16 [[M]] to i32 ; CHECK-NEXT: ret i32 [[R]] +; +; DBGINFO-LABEL: @eval_zext_multi_use_in_one_inst( +; DBGINFO-NEXT: [[T:%.*]] = trunc i32 [[X:%.*]] to i16, !dbg [[DBG69:![0-9]+]] +; DBGINFO-NEXT: call void @llvm.dbg.value(metadata i16 [[T]], metadata [[META64:![0-9]+]], metadata !DIExpression()), !dbg [[DBG69]] +; DBGINFO-NEXT: [[A:%.*]] = and i16 [[T]], 5, !dbg [[DBG70:![0-9]+]] +; DBGINFO-NEXT: call void @llvm.dbg.value(metadata i16 [[A]], metadata [[META66:![0-9]+]], metadata !DIExpression()), !dbg [[DBG70]] +; DBGINFO-NEXT: [[M:%.*]] = mul nuw nsw i16 [[A]], [[A]], !dbg [[DBG71:![0-9]+]] +; DBGINFO-NEXT: call void @llvm.dbg.value(metadata i16 [[M]], metadata [[META67:![0-9]+]], metadata !DIExpression()), !dbg [[DBG71]] +; DBGINFO-NEXT: [[R:%.*]] = zext nneg i16 [[M]] to i32, !dbg [[DBG72:![0-9]+]] +; DBGINFO-NEXT: call void @llvm.dbg.value(metadata i32 [[R]], metadata [[META68:![0-9]+]], metadata !DIExpression()), !dbg [[DBG72]] +; DBGINFO-NEXT: ret i32 [[R]], !dbg [[DBG73:![0-9]+]] ; %t = trunc i32 %x to i16 %a = and i16 %t, 5 @@ -100,6 +148,19 @@ ; CHECK-NEXT: [[O:%.*]] = or i16 [[M]], -32768 ; CHECK-NEXT: [[R:%.*]] = sext i16 [[O]] to i32 ; CHECK-NEXT: ret i32 [[R]] +; +; DBGINFO-LABEL: @eval_sext_multi_use_in_one_inst( +; DBGINFO-NEXT: [[T:%.*]] = trunc i32 [[X:%.*]] to i16, !dbg [[DBG81:![0-9]+]] +; DBGINFO-NEXT: call void @llvm.dbg.value(metadata i16 [[T]], metadata [[META76:![0-9]+]], metadata !DIExpression()), !dbg [[DBG81]] +; DBGINFO-NEXT: [[A:%.*]] = and i16 [[T]], 14, !dbg [[DBG82:![0-9]+]] +; DBGINFO-NEXT: call void @llvm.dbg.value(metadata i16 [[A]], metadata [[META77:![0-9]+]], metadata !DIExpression()), !dbg [[DBG82]] +; DBGINFO-NEXT: [[M:%.*]] = mul nuw nsw i16 [[A]], [[A]], !dbg [[DBG83:![0-9]+]] +; DBGINFO-NEXT: call void @llvm.dbg.value(metadata i16 [[M]], metadata [[META78:![0-9]+]], metadata !DIExpression()), !dbg [[DBG83]] +; DBGINFO-NEXT: [[O:%.*]] = or i16 [[M]], -32768, !dbg [[DBG84:![0-9]+]] +; DBGINFO-NEXT: call void @llvm.dbg.value(metadata i16 [[O]], metadata [[META79:![0-9]+]], metadata !DIExpression()), !dbg [[DBG84]] +; DBGINFO-NEXT: [[R:%.*]] = sext i16 [[O]] to i32, !dbg [[DBG85:![0-9]+]] +; DBGINFO-NEXT: call void @llvm.dbg.value(metadata i32 [[R]], metadata [[META80:![0-9]+]], metadata !DIExpression()), !dbg [[DBG85]] +; DBGINFO-NEXT: ret i32 [[R]], !dbg [[DBG86:![0-9]+]] ; %t = trunc i32 %x to i16 %a = and i16 %t, 14 @@ -132,7 +193,7 @@ ; CHECK-NEXT: ] ; CHECK: for.end: ; CHECK-NEXT: [[H:%.*]] = phi i8 [ [[SPEC_SELECT]], [[FOR_BODY3_US]] ], [ [[SPEC_SELECT]], [[FOR_BODY3_US]] ], [ 0, [[FOR_BODY3]] ], [ 0, [[FOR_BODY3]] ] -; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[H]] to i32 +; CHECK-NEXT: [[CONV:%.*]] = zext nneg i8 [[H]] to i32 ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], [[A:%.*]] ; CHECK-NEXT: br i1 [[CMP]], label [[EXIT]], label [[EXIT2:%.*]] ; CHECK: exit2: @@ -140,6 +201,39 @@ ; CHECK: exit: ; CHECK-NEXT: unreachable ; +; DBGINFO-LABEL: @PR36225( +; DBGINFO-NEXT: entry: +; DBGINFO-NEXT: br label [[WHILE_BODY:%.*]], !dbg [[DBG94:![0-9]+]] +; DBGINFO: while.body: +; DBGINFO-NEXT: call void @llvm.dbg.value(metadata i1 poison, metadata [[META89:![0-9]+]], metadata !DIExpression()), !dbg [[DBG95:![0-9]+]] +; DBGINFO-NEXT: br i1 [[C1:%.*]], label [[FOR_BODY3_US:%.*]], label [[FOR_BODY3:%.*]], !dbg [[DBG96:![0-9]+]] +; DBGINFO: for.body3.us: +; DBGINFO-NEXT: [[TOBOOL:%.*]] = icmp eq i32 [[B:%.*]], 0, !dbg [[DBG95]] +; DBGINFO-NEXT: call void @llvm.dbg.value(metadata i1 [[TOBOOL]], metadata [[META89]], metadata !DIExpression()), !dbg [[DBG95]] +; DBGINFO-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[TOBOOL]], i8 0, i8 4, !dbg [[DBG97:![0-9]+]] +; DBGINFO-NEXT: call void @llvm.dbg.value(metadata i8 [[SPEC_SELECT]], metadata [[META90:![0-9]+]], metadata !DIExpression()), !dbg [[DBG97]] +; DBGINFO-NEXT: switch i3 [[V1:%.*]], label [[EXIT:%.*]] [ +; DBGINFO-NEXT: i3 0, label [[FOR_END:%.*]] +; DBGINFO-NEXT: i3 -1, label [[FOR_END]] +; DBGINFO-NEXT: ], !dbg [[DBG98:![0-9]+]] +; DBGINFO: for.body3: +; DBGINFO-NEXT: switch i3 [[V2:%.*]], label [[EXIT]] [ +; DBGINFO-NEXT: i3 0, label [[FOR_END]] +; DBGINFO-NEXT: i3 -1, label [[FOR_END]] +; DBGINFO-NEXT: ], !dbg [[DBG99:![0-9]+]] +; DBGINFO: for.end: +; DBGINFO-NEXT: [[H:%.*]] = phi i8 [ [[SPEC_SELECT]], [[FOR_BODY3_US]] ], [ [[SPEC_SELECT]], [[FOR_BODY3_US]] ], [ 0, [[FOR_BODY3]] ], [ 0, [[FOR_BODY3]] ], !dbg [[DBG100:![0-9]+]] +; DBGINFO-NEXT: call void @llvm.dbg.value(metadata i8 [[H]], metadata [[META91:![0-9]+]], metadata !DIExpression()), !dbg [[DBG100]] +; DBGINFO-NEXT: [[CONV:%.*]] = zext nneg i8 [[H]] to i32, !dbg [[DBG101:![0-9]+]] +; DBGINFO-NEXT: call void @llvm.dbg.value(metadata i32 [[CONV]], metadata [[META92:![0-9]+]], metadata !DIExpression()), !dbg [[DBG101]] +; DBGINFO-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], [[A:%.*]], !dbg [[DBG102:![0-9]+]] +; DBGINFO-NEXT: call void @llvm.dbg.value(metadata i1 [[CMP]], metadata [[META93:![0-9]+]], metadata !DIExpression()), !dbg [[DBG102]] +; DBGINFO-NEXT: br i1 [[CMP]], label [[EXIT]], label [[EXIT2:%.*]], !dbg [[DBG103:![0-9]+]] +; DBGINFO: exit2: +; DBGINFO-NEXT: unreachable, !dbg [[DBG104:![0-9]+]] +; DBGINFO: exit: +; DBGINFO-NEXT: unreachable, !dbg [[DBG105:![0-9]+]] +; entry: br label %while.body diff --git a/llvm/test/Transforms/InstCombine/cast.ll b/llvm/test/Transforms/InstCombine/cast.ll --- a/llvm/test/Transforms/InstCombine/cast.ll +++ b/llvm/test/Transforms/InstCombine/cast.ll @@ -619,7 +619,7 @@ ; ALL-NEXT: [[B:%.*]] = trunc <2 x i64> [[A:%.*]] to <2 x i32> ; ALL-NEXT: [[C:%.*]] = shl <2 x i32> [[B]], ; ALL-NEXT: [[D:%.*]] = and <2 x i32> [[C]], -; ALL-NEXT: [[E:%.*]] = zext <2 x i32> [[D]] to <2 x i64> +; ALL-NEXT: [[E:%.*]] = zext nneg <2 x i32> [[D]] to <2 x i64> ; ALL-NEXT: ret <2 x i64> [[E]] ; %B = trunc <2 x i64> %A to <2 x i32> @@ -647,7 +647,7 @@ ; ALL-NEXT: [[Z2:%.*]] = zext i8 [[A1:%.*]] to i32 ; ALL-NEXT: [[C:%.*]] = shl nuw nsw i32 [[Z2]], 8 ; ALL-NEXT: [[D:%.*]] = or i32 [[C]], [[Z2]] -; ALL-NEXT: [[E:%.*]] = zext i32 [[D]] to i64 +; ALL-NEXT: [[E:%.*]] = zext nneg i32 [[D]] to i64 ; ALL-NEXT: ret i64 [[E]] ; %Z1 = zext i8 %a2 to i32 @@ -721,7 +721,7 @@ ; ALL-LABEL: @test53( ; ALL-NEXT: [[TMP1:%.*]] = and i32 [[A:%.*]], 7224 ; ALL-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], 32962 -; ALL-NEXT: [[D:%.*]] = zext i32 [[TMP2]] to i64 +; ALL-NEXT: [[D:%.*]] = zext nneg i32 [[TMP2]] to i64 ; ALL-NEXT: ret i64 [[D]] ; %B = trunc i32 %A to i16 @@ -748,7 +748,7 @@ define i64 @test55(i32 %A) { ; ALL-LABEL: @test55( ; ALL-NEXT: [[TMP1:%.*]] = and i32 [[A:%.*]], 7224 -; ALL-NEXT: [[C:%.*]] = zext i32 [[TMP1]] to i64 +; ALL-NEXT: [[C:%.*]] = zext nneg i32 [[TMP1]] to i64 ; ALL-NEXT: [[D:%.*]] = or i64 [[C]], -32574 ; ALL-NEXT: ret i64 [[D]] ; @@ -776,7 +776,7 @@ ; ALL-LABEL: @test56vec( ; ALL-NEXT: [[P353:%.*]] = sext <2 x i16> [[A:%.*]] to <2 x i32> ; ALL-NEXT: [[P354:%.*]] = lshr <2 x i32> [[P353]], -; ALL-NEXT: [[P355:%.*]] = zext <2 x i32> [[P354]] to <2 x i64> +; ALL-NEXT: [[P355:%.*]] = zext nneg <2 x i32> [[P354]] to <2 x i64> ; ALL-NEXT: ret <2 x i64> [[P355]] ; %p353 = sext <2 x i16> %A to <2 x i32> @@ -801,7 +801,7 @@ ; ALL-LABEL: @test57vec( ; ALL-NEXT: [[B:%.*]] = trunc <2 x i64> [[A:%.*]] to <2 x i32> ; ALL-NEXT: [[C:%.*]] = lshr <2 x i32> [[B]], -; ALL-NEXT: [[E:%.*]] = zext <2 x i32> [[C]] to <2 x i64> +; ALL-NEXT: [[E:%.*]] = zext nneg <2 x i32> [[C]] to <2 x i64> ; ALL-NEXT: ret <2 x i64> [[E]] ; %B = trunc <2 x i64> %A to <2 x i32> @@ -831,7 +831,7 @@ ; ALL-NEXT: [[D:%.*]] = shl nuw nsw i64 [[C]], 4 ; ALL-NEXT: [[E:%.*]] = and i64 [[D]], 48 ; ALL-NEXT: [[TMP1:%.*]] = lshr i8 [[B:%.*]], 4 -; ALL-NEXT: [[G:%.*]] = zext i8 [[TMP1]] to i64 +; ALL-NEXT: [[G:%.*]] = zext nneg i8 [[TMP1]] to i64 ; ALL-NEXT: [[H:%.*]] = or i64 [[E]], [[G]] ; ALL-NEXT: ret i64 [[H]] ; diff --git a/llvm/test/Transforms/InstCombine/ctpop.ll b/llvm/test/Transforms/InstCombine/ctpop.ll --- a/llvm/test/Transforms/InstCombine/ctpop.ll +++ b/llvm/test/Transforms/InstCombine/ctpop.ll @@ -206,8 +206,8 @@ define i32 @ctpop_add_no_common_bits(i32 %a, i32 %b) { ; CHECK-LABEL: @ctpop_add_no_common_bits( ; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.fshl.i32(i32 [[A:%.*]], i32 [[B:%.*]], i32 16) -; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ctpop.i32(i32 [[TMP1]]), !range [[RNG1]] -; CHECK-NEXT: ret i32 [[TMP2]] +; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.ctpop.i32(i32 [[TMP1]]), !range [[RNG1]] +; CHECK-NEXT: ret i32 [[RES]] ; %shl16 = shl i32 %a, 16 %ctpop1 = tail call i32 @llvm.ctpop.i32(i32 %shl16) @@ -220,8 +220,8 @@ define <2 x i32> @ctpop_add_no_common_bits_vec(<2 x i32> %a, <2 x i32> %b) { ; CHECK-LABEL: @ctpop_add_no_common_bits_vec( ; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.fshl.v2i32(<2 x i32> [[A:%.*]], <2 x i32> [[B:%.*]], <2 x i32> ) -; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> [[TMP1]]) -; CHECK-NEXT: ret <2 x i32> [[TMP2]] +; CHECK-NEXT: [[RES:%.*]] = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> [[TMP1]]) +; CHECK-NEXT: ret <2 x i32> [[RES]] ; %shl16 = shl <2 x i32> %a, %ctpop1 = tail call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> %shl16) @@ -295,8 +295,8 @@ define i8 @sub_ctpop(i8 %a) { ; CHECK-LABEL: @sub_ctpop( ; CHECK-NEXT: [[TMP1:%.*]] = xor i8 [[A:%.*]], -1 -; CHECK-NEXT: [[TMP2:%.*]] = call i8 @llvm.ctpop.i8(i8 [[TMP1]]), !range [[RNG0]] -; CHECK-NEXT: ret i8 [[TMP2]] +; CHECK-NEXT: [[RES:%.*]] = call i8 @llvm.ctpop.i8(i8 [[TMP1]]), !range [[RNG0]] +; CHECK-NEXT: ret i8 [[RES]] ; %cnt = tail call i8 @llvm.ctpop.i8(i8 %a) %res = sub i8 8, %cnt @@ -328,8 +328,8 @@ define <2 x i32> @sub_ctpop_vec(<2 x i32> %a) { ; CHECK-LABEL: @sub_ctpop_vec( ; CHECK-NEXT: [[TMP1:%.*]] = xor <2 x i32> [[A:%.*]], -; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> [[TMP1]]) -; CHECK-NEXT: ret <2 x i32> [[TMP2]] +; CHECK-NEXT: [[RES:%.*]] = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> [[TMP1]]) +; CHECK-NEXT: ret <2 x i32> [[RES]] ; %cnt = tail call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> %a) %res = sub <2 x i32> , %cnt @@ -352,7 +352,7 @@ define i32 @zext_ctpop(i16 %x) { ; CHECK-LABEL: @zext_ctpop( ; CHECK-NEXT: [[TMP1:%.*]] = call i16 @llvm.ctpop.i16(i16 [[X:%.*]]), !range [[RNG3:![0-9]+]] -; CHECK-NEXT: [[P:%.*]] = zext i16 [[TMP1]] to i32 +; CHECK-NEXT: [[P:%.*]] = zext nneg i16 [[TMP1]] to i32 ; CHECK-NEXT: ret i32 [[P]] ; %z = zext i16 %x to i32 @@ -363,7 +363,7 @@ define <2 x i32> @zext_ctpop_vec(<2 x i7> %x) { ; CHECK-LABEL: @zext_ctpop_vec( ; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i7> @llvm.ctpop.v2i7(<2 x i7> [[X:%.*]]) -; CHECK-NEXT: [[P:%.*]] = zext <2 x i7> [[TMP1]] to <2 x i32> +; CHECK-NEXT: [[P:%.*]] = zext nneg <2 x i7> [[TMP1]] to <2 x i32> ; CHECK-NEXT: ret <2 x i32> [[P]] ; %z = zext <2 x i7> %x to <2 x i32> diff --git a/llvm/test/Transforms/InstCombine/cttz.ll b/llvm/test/Transforms/InstCombine/cttz.ll --- a/llvm/test/Transforms/InstCombine/cttz.ll +++ b/llvm/test/Transforms/InstCombine/cttz.ll @@ -8,8 +8,8 @@ define i32 @cttz_zext_zero_undef(i16 %x) { ; CHECK-LABEL: @cttz_zext_zero_undef( ; CHECK-NEXT: [[TMP1:%.*]] = call i16 @llvm.cttz.i16(i16 [[X:%.*]], i1 true), !range [[RNG0:![0-9]+]] -; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[TMP1]] to i32 -; CHECK-NEXT: ret i32 [[TMP2]] +; CHECK-NEXT: [[TZ:%.*]] = zext nneg i16 [[TMP1]] to i32 +; CHECK-NEXT: ret i32 [[TZ]] ; %z = zext i16 %x to i32 %tz = call i32 @llvm.cttz.i32(i32 %z, i1 true) @@ -43,8 +43,8 @@ define <2 x i64> @cttz_zext_zero_undef_vec(<2 x i32> %x) { ; CHECK-LABEL: @cttz_zext_zero_undef_vec( ; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[X:%.*]], i1 true) -; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64> -; CHECK-NEXT: ret <2 x i64> [[TMP2]] +; CHECK-NEXT: [[TZ:%.*]] = zext nneg <2 x i32> [[TMP1]] to <2 x i64> +; CHECK-NEXT: ret <2 x i64> [[TZ]] ; %z = zext <2 x i32> %x to <2 x i64> %tz = tail call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %z, i1 true) @@ -65,8 +65,8 @@ define i32 @cttz_sext_zero_undef(i16 %x) { ; CHECK-LABEL: @cttz_sext_zero_undef( ; CHECK-NEXT: [[TMP1:%.*]] = call i16 @llvm.cttz.i16(i16 [[X:%.*]], i1 true), !range [[RNG0]] -; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[TMP1]] to i32 -; CHECK-NEXT: ret i32 [[TMP2]] +; CHECK-NEXT: [[TZ:%.*]] = zext nneg i16 [[TMP1]] to i32 +; CHECK-NEXT: ret i32 [[TZ]] ; %s = sext i16 %x to i32 %tz = call i32 @llvm.cttz.i32(i32 %s, i1 true) @@ -76,8 +76,8 @@ define i32 @cttz_sext_zero_def(i16 %x) { ; CHECK-LABEL: @cttz_sext_zero_def( ; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[X:%.*]] to i32 -; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP1]], i1 false), !range [[RNG1]] -; CHECK-NEXT: ret i32 [[TMP2]] +; CHECK-NEXT: [[TZ:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP1]], i1 false), !range [[RNG1]] +; CHECK-NEXT: ret i32 [[TZ]] ; %s = sext i16 %x to i32 %tz = call i32 @llvm.cttz.i32(i32 %s, i1 false) @@ -100,8 +100,8 @@ define <2 x i64> @cttz_sext_zero_undef_vec(<2 x i32> %x) { ; CHECK-LABEL: @cttz_sext_zero_undef_vec( ; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[X:%.*]], i1 true) -; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64> -; CHECK-NEXT: ret <2 x i64> [[TMP2]] +; CHECK-NEXT: [[TZ:%.*]] = zext nneg <2 x i32> [[TMP1]] to <2 x i64> +; CHECK-NEXT: ret <2 x i64> [[TZ]] ; %s = sext <2 x i32> %x to <2 x i64> %tz = tail call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %s, i1 true) @@ -111,8 +111,8 @@ define <2 x i64> @cttz_sext_zero_def_vec(<2 x i32> %x) { ; CHECK-LABEL: @cttz_sext_zero_def_vec( ; CHECK-NEXT: [[TMP1:%.*]] = zext <2 x i32> [[X:%.*]] to <2 x i64> -; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> [[TMP1]], i1 false) -; CHECK-NEXT: ret <2 x i64> [[TMP2]] +; CHECK-NEXT: [[TZ:%.*]] = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> [[TMP1]], i1 false) +; CHECK-NEXT: ret <2 x i64> [[TZ]] ; %s = sext <2 x i32> %x to <2 x i64> %tz = tail call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %s, i1 false) diff --git a/llvm/test/Transforms/InstCombine/freeze.ll b/llvm/test/Transforms/InstCombine/freeze.ll --- a/llvm/test/Transforms/InstCombine/freeze.ll +++ b/llvm/test/Transforms/InstCombine/freeze.ll @@ -493,10 +493,10 @@ ; CHECK-LABEL: @fully_propagate_freeze( ; CHECK-NEXT: [[DOTFR:%.*]] = freeze i32 [[TMP0:%.*]] ; CHECK-NEXT: [[DR:%.*]] = lshr i32 [[DOTFR]], 2 -; CHECK-NEXT: [[IDX1:%.*]] = zext i32 [[DR]] to i64 +; CHECK-NEXT: [[IDX1:%.*]] = zext nneg i32 [[DR]] to i64 ; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[DR]], 1 ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[ADD]], [[TMP1:%.*]] -; CHECK-NEXT: [[IDX2:%.*]] = zext i32 [[DR]] to i64 +; CHECK-NEXT: [[IDX2:%.*]] = zext nneg i32 [[DR]] to i64 ; CHECK-NEXT: [[V:%.*]] = call i1 @mock_use(i64 [[IDX1]], i64 [[IDX2]]) ; CHECK-NEXT: [[RET:%.*]] = and i1 [[V]], [[CMP]] ; CHECK-NEXT: ret i1 [[RET]] diff --git a/llvm/test/Transforms/InstCombine/icmp-ext-ext.ll b/llvm/test/Transforms/InstCombine/icmp-ext-ext.ll --- a/llvm/test/Transforms/InstCombine/icmp-ext-ext.ll +++ b/llvm/test/Transforms/InstCombine/icmp-ext-ext.ll @@ -289,7 +289,7 @@ define i1 @zext_sext_sle_known_nonneg_op0_narrow(i8 %x, i16 %y) { ; CHECK-LABEL: @zext_sext_sle_known_nonneg_op0_narrow( ; CHECK-NEXT: [[N:%.*]] = and i8 [[X:%.*]], 12 -; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[N]] to i16 +; CHECK-NEXT: [[TMP1:%.*]] = zext nneg i8 [[N]] to i16 ; CHECK-NEXT: [[C:%.*]] = icmp sle i16 [[TMP1]], [[Y:%.*]] ; CHECK-NEXT: ret i1 [[C]] ; @@ -370,7 +370,7 @@ define i1 @sext_zext_uge_known_nonneg_op0_wide(i16 %x, i8 %y) { ; CHECK-LABEL: @sext_zext_uge_known_nonneg_op0_wide( ; CHECK-NEXT: [[N:%.*]] = and i8 [[Y:%.*]], 12 -; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[N]] to i16 +; CHECK-NEXT: [[TMP1:%.*]] = zext nneg i8 [[N]] to i16 ; CHECK-NEXT: [[C:%.*]] = icmp ule i16 [[TMP1]], [[X:%.*]] ; CHECK-NEXT: ret i1 [[C]] ; diff --git a/llvm/test/Transforms/InstCombine/load-bitcast-select.ll b/llvm/test/Transforms/InstCombine/load-bitcast-select.ll --- a/llvm/test/Transforms/InstCombine/load-bitcast-select.ll +++ b/llvm/test/Transforms/InstCombine/load-bitcast-select.ll @@ -15,14 +15,14 @@ ; CHECK: for.cond.cleanup: ; CHECK-NEXT: ret void ; CHECK: for.body: -; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[I_0]] to i64 +; CHECK-NEXT: [[TMP0:%.*]] = zext nneg i32 [[I_0]] to i64 ; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x float], ptr @a, i64 0, i64 [[TMP0]] ; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [1000 x float], ptr @b, i64 0, i64 [[TMP0]] ; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[ARRAYIDX]], align 4 ; CHECK-NEXT: [[TMP2:%.*]] = load float, ptr [[ARRAYIDX2]], align 4 ; CHECK-NEXT: [[CMP_I:%.*]] = fcmp fast olt float [[TMP1]], [[TMP2]] -; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[CMP_I]], float [[TMP2]], float [[TMP1]] -; CHECK-NEXT: store float [[TMP3]], ptr [[ARRAYIDX]], align 4 +; CHECK-NEXT: [[DOTV:%.*]] = select i1 [[CMP_I]], float [[TMP2]], float [[TMP1]] +; CHECK-NEXT: store float [[DOTV]], ptr [[ARRAYIDX]], align 4 ; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[I_0]], 1 ; CHECK-NEXT: br label [[FOR_COND]] ; @@ -80,8 +80,8 @@ ; CHECK-NEXT: [[LD1:%.*]] = load float, ptr [[LOADADDR1:%.*]], align 4 ; CHECK-NEXT: [[LD2:%.*]] = load float, ptr [[LOADADDR2:%.*]], align 4 ; CHECK-NEXT: [[COND:%.*]] = fcmp ogt float [[LD1]], [[LD2]] -; CHECK-NEXT: [[LD3:%.*]] = select i1 [[COND]], float [[LD1]], float [[LD2]] -; CHECK-NEXT: store float [[LD3]], ptr [[STOREADDR:%.*]], align 4 +; CHECK-NEXT: [[LD_V:%.*]] = select i1 [[COND]], float [[LD1]], float [[LD2]] +; CHECK-NEXT: store float [[LD_V]], ptr [[STOREADDR:%.*]], align 4 ; CHECK-NEXT: ret void ; %ld1 = load float, ptr %loadaddr1, align 4 diff --git a/llvm/test/Transforms/InstCombine/lshr.ll b/llvm/test/Transforms/InstCombine/lshr.ll --- a/llvm/test/Transforms/InstCombine/lshr.ll +++ b/llvm/test/Transforms/InstCombine/lshr.ll @@ -290,7 +290,7 @@ define i18 @fake_sext(i3 %x) { ; CHECK-LABEL: @fake_sext( ; CHECK-NEXT: [[TMP1:%.*]] = lshr i3 [[X:%.*]], 2 -; CHECK-NEXT: [[SH:%.*]] = zext i3 [[TMP1]] to i18 +; CHECK-NEXT: [[SH:%.*]] = zext nneg i3 [[TMP1]] to i18 ; CHECK-NEXT: ret i18 [[SH]] ; %sext = sext i3 %x to i18 @@ -314,7 +314,7 @@ define <2 x i8> @fake_sext_splat(<2 x i3> %x) { ; CHECK-LABEL: @fake_sext_splat( ; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i3> [[X:%.*]], -; CHECK-NEXT: [[SH:%.*]] = zext <2 x i3> [[TMP1]] to <2 x i8> +; CHECK-NEXT: [[SH:%.*]] = zext nneg <2 x i3> [[TMP1]] to <2 x i8> ; CHECK-NEXT: ret <2 x i8> [[SH]] ; %sext = sext <2 x i3> %x to <2 x i8> @@ -327,7 +327,7 @@ define <2 x i32> @narrow_lshr_constant(<2 x i8> %x, <2 x i8> %y) { ; CHECK-LABEL: @narrow_lshr_constant( ; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i8> [[X:%.*]], -; CHECK-NEXT: [[SH:%.*]] = zext <2 x i8> [[TMP1]] to <2 x i32> +; CHECK-NEXT: [[SH:%.*]] = zext nneg <2 x i8> [[TMP1]] to <2 x i32> ; CHECK-NEXT: ret <2 x i32> [[SH]] ; %zx = zext <2 x i8> %x to <2 x i32> @@ -908,7 +908,7 @@ ; CHECK-LABEL: @narrow_bswap_overshift( ; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.bswap.v2i32(<2 x i32> [[X:%.*]]) ; CHECK-NEXT: [[TMP2:%.*]] = lshr <2 x i32> [[TMP1]], -; CHECK-NEXT: [[S:%.*]] = zext <2 x i32> [[TMP2]] to <2 x i64> +; CHECK-NEXT: [[S:%.*]] = zext nneg <2 x i32> [[TMP2]] to <2 x i64> ; CHECK-NEXT: ret <2 x i64> [[S]] ; %z = zext <2 x i32> %x to <2 x i64> @@ -921,7 +921,7 @@ ; CHECK-LABEL: @narrow_bswap_overshift2( ; CHECK-NEXT: [[TMP1:%.*]] = call i96 @llvm.bswap.i96(i96 [[X:%.*]]) ; CHECK-NEXT: [[TMP2:%.*]] = lshr i96 [[TMP1]], 29 -; CHECK-NEXT: [[S:%.*]] = zext i96 [[TMP2]] to i128 +; CHECK-NEXT: [[S:%.*]] = zext nneg i96 [[TMP2]] to i128 ; CHECK-NEXT: ret i128 [[S]] ; %z = zext i96 %x to i128 diff --git a/llvm/test/Transforms/InstCombine/memcpy-from-global.ll b/llvm/test/Transforms/InstCombine/memcpy-from-global.ll --- a/llvm/test/Transforms/InstCombine/memcpy-from-global.ll +++ b/llvm/test/Transforms/InstCombine/memcpy-from-global.ll @@ -8,25 +8,25 @@ ; CHECK-NEXT: entry: ; CHECK-NEXT: [[TMP3:%.*]] = shl i32 [[HASH:%.*]], 2 ; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP3]], 124 -; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[TMP5]] to i64 +; CHECK-NEXT: [[TMP0:%.*]] = zext nneg i32 [[TMP5]] to i64 ; CHECK-NEXT: [[TMP753:%.*]] = getelementptr [128 x float], ptr @C.0.1248, i64 0, i64 [[TMP0]] ; CHECK-NEXT: [[TMP9:%.*]] = load float, ptr [[TMP753]], align 16 ; CHECK-NEXT: [[TMP11:%.*]] = fmul float [[TMP9]], [[X:%.*]] ; CHECK-NEXT: [[TMP13:%.*]] = fadd float [[TMP11]], 0.000000e+00 ; CHECK-NEXT: [[TMP17_SUM52:%.*]] = or i32 [[TMP5]], 1 -; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[TMP17_SUM52]] to i64 +; CHECK-NEXT: [[TMP1:%.*]] = zext nneg i32 [[TMP17_SUM52]] to i64 ; CHECK-NEXT: [[TMP1851:%.*]] = getelementptr [128 x float], ptr @C.0.1248, i64 0, i64 [[TMP1]] ; CHECK-NEXT: [[TMP19:%.*]] = load float, ptr [[TMP1851]], align 4 ; CHECK-NEXT: [[TMP21:%.*]] = fmul float [[TMP19]], [[Y:%.*]] ; CHECK-NEXT: [[TMP23:%.*]] = fadd float [[TMP21]], [[TMP13]] ; CHECK-NEXT: [[TMP27_SUM50:%.*]] = or i32 [[TMP5]], 2 -; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP27_SUM50]] to i64 +; CHECK-NEXT: [[TMP2:%.*]] = zext nneg i32 [[TMP27_SUM50]] to i64 ; CHECK-NEXT: [[TMP2849:%.*]] = getelementptr [128 x float], ptr @C.0.1248, i64 0, i64 [[TMP2]] ; CHECK-NEXT: [[TMP29:%.*]] = load float, ptr [[TMP2849]], align 8 ; CHECK-NEXT: [[TMP31:%.*]] = fmul float [[TMP29]], [[Z:%.*]] ; CHECK-NEXT: [[TMP33:%.*]] = fadd float [[TMP31]], [[TMP23]] ; CHECK-NEXT: [[TMP37_SUM48:%.*]] = or i32 [[TMP5]], 3 -; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP37_SUM48]] to i64 +; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP37_SUM48]] to i64 ; CHECK-NEXT: [[TMP3847:%.*]] = getelementptr [128 x float], ptr @C.0.1248, i64 0, i64 [[TMP3]] ; CHECK-NEXT: [[TMP39:%.*]] = load float, ptr [[TMP3847]], align 4 ; CHECK-NEXT: [[TMP41:%.*]] = fmul float [[TMP39]], [[W:%.*]] diff --git a/llvm/test/Transforms/InstCombine/minmax-fold.ll b/llvm/test/Transforms/InstCombine/minmax-fold.ll --- a/llvm/test/Transforms/InstCombine/minmax-fold.ll +++ b/llvm/test/Transforms/InstCombine/minmax-fold.ll @@ -57,7 +57,7 @@ define i64 @t5(i32 %a) { ; CHECK-LABEL: @t5( ; CHECK-NEXT: [[NARROW:%.*]] = call i32 @llvm.smax.i32(i32 [[A:%.*]], i32 5) -; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[NARROW]] to i64 +; CHECK-NEXT: [[TMP1:%.*]] = zext nneg i32 [[NARROW]] to i64 ; CHECK-NEXT: ret i64 [[TMP1]] ; %1 = icmp slt i32 %a, 5 diff --git a/llvm/test/Transforms/InstCombine/minmax-intrinsics.ll b/llvm/test/Transforms/InstCombine/minmax-intrinsics.ll --- a/llvm/test/Transforms/InstCombine/minmax-intrinsics.ll +++ b/llvm/test/Transforms/InstCombine/minmax-intrinsics.ll @@ -217,7 +217,7 @@ define i8 @smax_sext_constant(i5 %x) { ; CHECK-LABEL: @smax_sext_constant( ; CHECK-NEXT: [[TMP1:%.*]] = call i5 @llvm.smax.i5(i5 [[X:%.*]], i5 7) -; CHECK-NEXT: [[M:%.*]] = zext i5 [[TMP1]] to i8 +; CHECK-NEXT: [[M:%.*]] = zext nneg i5 [[TMP1]] to i8 ; CHECK-NEXT: ret i8 [[M]] ; %e = sext i5 %x to i8 @@ -322,7 +322,7 @@ define i8 @umin_sext_constant(i5 %x) { ; CHECK-LABEL: @umin_sext_constant( ; CHECK-NEXT: [[TMP1:%.*]] = call i5 @llvm.umin.i5(i5 [[X:%.*]], i5 7) -; CHECK-NEXT: [[M:%.*]] = zext i5 [[TMP1]] to i8 +; CHECK-NEXT: [[M:%.*]] = zext nneg i5 [[TMP1]] to i8 ; CHECK-NEXT: ret i8 [[M]] ; %e = sext i5 %x to i8 @@ -346,7 +346,7 @@ define i8 @umin_zext_constant(i5 %x) { ; CHECK-LABEL: @umin_zext_constant( ; CHECK-NEXT: [[TMP1:%.*]] = call i5 @llvm.umin.i5(i5 [[X:%.*]], i5 7) -; CHECK-NEXT: [[M:%.*]] = zext i5 [[TMP1]] to i8 +; CHECK-NEXT: [[M:%.*]] = zext nneg i5 [[TMP1]] to i8 ; CHECK-NEXT: ret i8 [[M]] ; %e = zext i5 %x to i8 @@ -584,8 +584,8 @@ ; CHECK-NEXT: call void @use(i8 [[NOTX]]) ; CHECK-NEXT: [[NOTY:%.*]] = xor i8 [[Y:%.*]], -1 ; CHECK-NEXT: call void @use(i8 [[NOTY]]) -; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.smin.i8(i8 [[X]], i8 [[Y]]) -; CHECK-NEXT: ret i8 [[TMP1]] +; CHECK-NEXT: [[NOTM:%.*]] = call i8 @llvm.smin.i8(i8 [[X]], i8 [[Y]]) +; CHECK-NEXT: ret i8 [[NOTM]] ; %notx = xor i8 %x, -1 call void @use(i8 %notx) @@ -622,8 +622,8 @@ ; CHECK-NEXT: [[NOTX:%.*]] = xor i8 [[X:%.*]], -1 ; CHECK-NEXT: call void @use(i8 [[NOTX]]) ; CHECK-NEXT: [[TMP1:%.*]] = xor i8 [[Y:%.*]], -1 -; CHECK-NEXT: [[TMP2:%.*]] = call i8 @llvm.umin.i8(i8 [[X]], i8 [[TMP1]]) -; CHECK-NEXT: ret i8 [[TMP2]] +; CHECK-NEXT: [[NOTM:%.*]] = call i8 @llvm.umin.i8(i8 [[X]], i8 [[TMP1]]) +; CHECK-NEXT: ret i8 [[NOTM]] ; %notx = xor i8 %x, -1 call void @use(i8 %notx) @@ -655,8 +655,8 @@ ; CHECK-LABEL: @not_umin_of_not_constant_op( ; CHECK-NEXT: [[NOTX:%.*]] = xor i8 [[X:%.*]], -1 ; CHECK-NEXT: call void @use(i8 [[NOTX]]) -; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.umax.i8(i8 [[X]], i8 -43) -; CHECK-NEXT: ret i8 [[TMP1]] +; CHECK-NEXT: [[NOTM:%.*]] = call i8 @llvm.umax.i8(i8 [[X]], i8 -43) +; CHECK-NEXT: ret i8 [[NOTM]] ; %notx = xor i8 %x, -1 call void @use(i8 %notx) @@ -668,8 +668,8 @@ define i8 @smax_negation(i8 %x, i8 %y) { ; CHECK-LABEL: @smax_negation( ; CHECK-NEXT: [[S1:%.*]] = sub i8 [[X:%.*]], [[Y:%.*]] -; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.abs.i8(i8 [[S1]], i1 false) -; CHECK-NEXT: ret i8 [[TMP1]] +; CHECK-NEXT: [[R:%.*]] = call i8 @llvm.abs.i8(i8 [[S1]], i1 false) +; CHECK-NEXT: ret i8 [[R]] ; %s1 = sub i8 %x, %y %s2 = sub i8 %y, %x @@ -680,8 +680,8 @@ define i8 @smax_negation_nsw(i8 %x, i8 %y) { ; CHECK-LABEL: @smax_negation_nsw( ; CHECK-NEXT: [[S1:%.*]] = sub nsw i8 [[X:%.*]], [[Y:%.*]] -; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.abs.i8(i8 [[S1]], i1 true) -; CHECK-NEXT: ret i8 [[TMP1]] +; CHECK-NEXT: [[R:%.*]] = call i8 @llvm.abs.i8(i8 [[S1]], i1 true) +; CHECK-NEXT: ret i8 [[R]] ; %s1 = sub nsw i8 %x, %y %s2 = sub nsw i8 %y, %x @@ -692,8 +692,8 @@ define i8 @smax_negation_not_nsw(i8 %x, i8 %y) { ; CHECK-LABEL: @smax_negation_not_nsw( ; CHECK-NEXT: [[S1:%.*]] = sub nsw i8 [[X:%.*]], [[Y:%.*]] -; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.abs.i8(i8 [[S1]], i1 false) -; CHECK-NEXT: ret i8 [[TMP1]] +; CHECK-NEXT: [[R:%.*]] = call i8 @llvm.abs.i8(i8 [[S1]], i1 false) +; CHECK-NEXT: ret i8 [[R]] ; %s1 = sub nsw i8 %x, %y %s2 = sub nuw i8 %y, %x @@ -703,8 +703,8 @@ define <3 x i8> @smax_negation_vec(<3 x i8> %x) { ; CHECK-LABEL: @smax_negation_vec( -; CHECK-NEXT: [[TMP1:%.*]] = call <3 x i8> @llvm.abs.v3i8(<3 x i8> [[X:%.*]], i1 false) -; CHECK-NEXT: ret <3 x i8> [[TMP1]] +; CHECK-NEXT: [[R:%.*]] = call <3 x i8> @llvm.abs.v3i8(<3 x i8> [[X:%.*]], i1 false) +; CHECK-NEXT: ret <3 x i8> [[R]] ; %s = sub <3 x i8> , %x %r = call <3 x i8> @llvm.smax.v3i8(<3 x i8> %x, <3 x i8> %s) @@ -739,8 +739,8 @@ define i8 @umin_negation(i8 %x) { ; CHECK-LABEL: @umin_negation( -; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.abs.i8(i8 [[X:%.*]], i1 true) -; CHECK-NEXT: ret i8 [[TMP1]] +; CHECK-NEXT: [[R:%.*]] = call i8 @llvm.abs.i8(i8 [[X:%.*]], i1 true) +; CHECK-NEXT: ret i8 [[R]] ; %s = sub nsw i8 0, %x %r = call i8 @llvm.umin.i8(i8 %s, i8 %x) @@ -751,8 +751,8 @@ ; CHECK-LABEL: @smax_negation_uses( ; CHECK-NEXT: [[S2:%.*]] = sub i8 [[Y:%.*]], [[X:%.*]] ; CHECK-NEXT: call void @use(i8 [[S2]]) -; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.abs.i8(i8 [[S2]], i1 false) -; CHECK-NEXT: ret i8 [[TMP1]] +; CHECK-NEXT: [[R:%.*]] = call i8 @llvm.abs.i8(i8 [[S2]], i1 false) +; CHECK-NEXT: ret i8 [[R]] ; %s1 = sub i8 %x, %y %s2 = sub i8 %y, %x @@ -1263,8 +1263,8 @@ ; CHECK-NEXT: call void @use(i8 [[NY]]) ; CHECK-NEXT: call void @use(i8 [[NZ]]) ; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.umin.i8(i8 [[X]], i8 [[Y]]) -; CHECK-NEXT: [[TMP2:%.*]] = call i8 @llvm.smax.i8(i8 [[TMP1]], i8 [[Z]]) -; CHECK-NEXT: ret i8 [[TMP2]] +; CHECK-NEXT: [[NOT:%.*]] = call i8 @llvm.smax.i8(i8 [[TMP1]], i8 [[Z]]) +; CHECK-NEXT: ret i8 [[NOT]] ; %nx = xor i8 %x, -1 %ny = xor i8 %y, -1 @@ -1289,8 +1289,8 @@ ; CHECK-NEXT: [[M1:%.*]] = call i8 @llvm.umax.i8(i8 [[NX]], i8 [[NY]]) ; CHECK-NEXT: call void @use(i8 [[M1]]) ; CHECK-NEXT: [[TMP1:%.*]] = xor i8 [[M1]], -1 -; CHECK-NEXT: [[TMP2:%.*]] = call i8 @llvm.smax.i8(i8 [[Z]], i8 [[TMP1]]) -; CHECK-NEXT: ret i8 [[TMP2]] +; CHECK-NEXT: [[NOT:%.*]] = call i8 @llvm.smax.i8(i8 [[Z]], i8 [[TMP1]]) +; CHECK-NEXT: ret i8 [[NOT]] ; %nx = xor i8 %x, -1 %ny = xor i8 %y, -1 @@ -1373,8 +1373,8 @@ ; CHECK-NEXT: call void @use(i8 [[NW]]) ; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.umin.i8(i8 [[X]], i8 [[Y]]) ; CHECK-NEXT: [[TMP2:%.*]] = call i8 @llvm.smin.i8(i8 [[W]], i8 [[Z]]) -; CHECK-NEXT: [[TMP3:%.*]] = call i8 @llvm.smax.i8(i8 [[TMP1]], i8 [[TMP2]]) -; CHECK-NEXT: ret i8 [[TMP3]] +; CHECK-NEXT: [[NOT:%.*]] = call i8 @llvm.smax.i8(i8 [[TMP1]], i8 [[TMP2]]) +; CHECK-NEXT: ret i8 [[NOT]] ; %nx = xor i8 %x, -1 %ny = xor i8 %y, -1 diff --git a/llvm/test/Transforms/InstCombine/narrow-math.ll b/llvm/test/Transforms/InstCombine/narrow-math.ll --- a/llvm/test/Transforms/InstCombine/narrow-math.ll +++ b/llvm/test/Transforms/InstCombine/narrow-math.ll @@ -28,7 +28,7 @@ ; CHECK-NEXT: [[B:%.*]] = ashr i32 [[A:%.*]], 7 ; CHECK-NEXT: [[C:%.*]] = lshr i32 [[A]], 9 ; CHECK-NEXT: [[D:%.*]] = sext i32 [[B]] to i64 -; CHECK-NEXT: [[E:%.*]] = zext i32 [[C]] to i64 +; CHECK-NEXT: [[E:%.*]] = zext nneg i32 [[C]] to i64 ; CHECK-NEXT: [[F:%.*]] = add nsw i64 [[D]], [[E]] ; CHECK-NEXT: ret i64 [[F]] ; @@ -122,10 +122,10 @@ define i64 @test1(i32 %V) { ; CHECK-LABEL: @test1( -; CHECK-NEXT: [[CALL1:%.*]] = call i32 @callee(), [[RNG0:!range !.*]] -; CHECK-NEXT: [[CALL2:%.*]] = call i32 @callee(), [[RNG0]] +; CHECK-NEXT: [[CALL1:%.*]] = call i32 @callee(), !range [[RNG0:![0-9]+]] +; CHECK-NEXT: [[CALL2:%.*]] = call i32 @callee(), !range [[RNG0]] ; CHECK-NEXT: [[NARROW:%.*]] = add nuw nsw i32 [[CALL1]], [[CALL2]] -; CHECK-NEXT: [[ADD:%.*]] = zext i32 [[NARROW]] to i64 +; CHECK-NEXT: [[ADD:%.*]] = zext nneg i32 [[NARROW]] to i64 ; CHECK-NEXT: ret i64 [[ADD]] ; %call1 = call i32 @callee(), !range !0 @@ -138,10 +138,10 @@ define i64 @test2(i32 %V) { ; CHECK-LABEL: @test2( -; CHECK-NEXT: [[CALL1:%.*]] = call i32 @callee(), [[RNG0]] -; CHECK-NEXT: [[CALL2:%.*]] = call i32 @callee(), [[RNG0]] +; CHECK-NEXT: [[CALL1:%.*]] = call i32 @callee(), !range [[RNG0]] +; CHECK-NEXT: [[CALL2:%.*]] = call i32 @callee(), !range [[RNG0]] ; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[CALL1]], [[CALL2]] -; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 [[ADD]] to i64 +; CHECK-NEXT: [[ZEXT:%.*]] = zext nneg i32 [[ADD]] to i64 ; CHECK-NEXT: ret i64 [[ZEXT]] ; %call1 = call i32 @callee(), !range !0 @@ -153,10 +153,10 @@ define i64 @test3(i32 %V) { ; CHECK-LABEL: @test3( -; CHECK-NEXT: [[CALL1:%.*]] = call i32 @callee(), [[RNG0]] -; CHECK-NEXT: [[CALL2:%.*]] = call i32 @callee(), [[RNG0]] +; CHECK-NEXT: [[CALL1:%.*]] = call i32 @callee(), !range [[RNG0]] +; CHECK-NEXT: [[CALL2:%.*]] = call i32 @callee(), !range [[RNG0]] ; CHECK-NEXT: [[NARROW:%.*]] = mul nuw nsw i32 [[CALL1]], [[CALL2]] -; CHECK-NEXT: [[ADD:%.*]] = zext i32 [[NARROW]] to i64 +; CHECK-NEXT: [[ADD:%.*]] = zext nneg i32 [[NARROW]] to i64 ; CHECK-NEXT: ret i64 [[ADD]] ; %call1 = call i32 @callee(), !range !0 @@ -169,10 +169,10 @@ define i64 @test4(i32 %V) { ; CHECK-LABEL: @test4( -; CHECK-NEXT: [[CALL1:%.*]] = call i32 @callee(), [[RNG0]] -; CHECK-NEXT: [[CALL2:%.*]] = call i32 @callee(), [[RNG0]] +; CHECK-NEXT: [[CALL1:%.*]] = call i32 @callee(), !range [[RNG0]] +; CHECK-NEXT: [[CALL2:%.*]] = call i32 @callee(), !range [[RNG0]] ; CHECK-NEXT: [[ADD:%.*]] = mul nuw nsw i32 [[CALL1]], [[CALL2]] -; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 [[ADD]] to i64 +; CHECK-NEXT: [[ZEXT:%.*]] = zext nneg i32 [[ADD]] to i64 ; CHECK-NEXT: ret i64 [[ZEXT]] ; %call1 = call i32 @callee(), !range !0 @@ -461,8 +461,8 @@ define i64 @test11(i32 %V) { ; CHECK-LABEL: @test11( -; CHECK-NEXT: [[CALL1:%.*]] = call i32 @callee(), [[RNG1:!range !.*]] -; CHECK-NEXT: [[CALL2:%.*]] = call i32 @callee(), [[RNG1]] +; CHECK-NEXT: [[CALL1:%.*]] = call i32 @callee(), !range [[RNG1:![0-9]+]] +; CHECK-NEXT: [[CALL2:%.*]] = call i32 @callee(), !range [[RNG1]] ; CHECK-NEXT: [[NARROW:%.*]] = add nsw i32 [[CALL1]], [[CALL2]] ; CHECK-NEXT: [[ADD:%.*]] = sext i32 [[NARROW]] to i64 ; CHECK-NEXT: ret i64 [[ADD]] @@ -477,10 +477,10 @@ define i64 @test12(i32 %V) { ; CHECK-LABEL: @test12( -; CHECK-NEXT: [[CALL1:%.*]] = call i32 @callee(), [[RNG1]] -; CHECK-NEXT: [[CALL2:%.*]] = call i32 @callee(), [[RNG1]] +; CHECK-NEXT: [[CALL1:%.*]] = call i32 @callee(), !range [[RNG1]] +; CHECK-NEXT: [[CALL2:%.*]] = call i32 @callee(), !range [[RNG1]] ; CHECK-NEXT: [[NARROW:%.*]] = mul nsw i32 [[CALL1]], [[CALL2]] -; CHECK-NEXT: [[ADD:%.*]] = zext i32 [[NARROW]] to i64 +; CHECK-NEXT: [[ADD:%.*]] = zext nneg i32 [[NARROW]] to i64 ; CHECK-NEXT: ret i64 [[ADD]] ; %call1 = call i32 @callee(), !range !1 @@ -493,8 +493,8 @@ define i64 @test13(i32 %V) { ; CHECK-LABEL: @test13( -; CHECK-NEXT: [[CALL1:%.*]] = call i32 @callee(), [[RNG2:!range !.*]] -; CHECK-NEXT: [[CALL2:%.*]] = call i32 @callee(), [[RNG3:!range !.*]] +; CHECK-NEXT: [[CALL1:%.*]] = call i32 @callee(), !range [[RNG2:![0-9]+]] +; CHECK-NEXT: [[CALL2:%.*]] = call i32 @callee(), !range [[RNG3:![0-9]+]] ; CHECK-NEXT: [[NARROW:%.*]] = sub nsw i32 [[CALL1]], [[CALL2]] ; CHECK-NEXT: [[SUB:%.*]] = sext i32 [[NARROW]] to i64 ; CHECK-NEXT: ret i64 [[SUB]] @@ -509,8 +509,8 @@ define i64 @test14(i32 %V) { ; CHECK-LABEL: @test14( -; CHECK-NEXT: [[CALL1:%.*]] = call i32 @callee(), [[RNG2]] -; CHECK-NEXT: [[CALL2:%.*]] = call i32 @callee(), [[RNG0]] +; CHECK-NEXT: [[CALL1:%.*]] = call i32 @callee(), !range [[RNG2]] +; CHECK-NEXT: [[CALL2:%.*]] = call i32 @callee(), !range [[RNG0]] ; CHECK-NEXT: [[NARROW:%.*]] = sub nuw nsw i32 [[CALL1]], [[CALL2]] ; CHECK-NEXT: [[SUB:%.*]] = zext i32 [[NARROW]] to i64 ; CHECK-NEXT: ret i64 [[SUB]] @@ -579,10 +579,10 @@ ; won't wrap. define i64 @test17(i32 %V) { ; CHECK-LABEL: @test17( -; CHECK-NEXT: [[CALL1:%.*]] = call i32 @callee(), [[RNG0]] -; CHECK-NEXT: [[CALL2:%.*]] = call i32 @callee(), [[RNG0]] -; CHECK-NEXT: [[SEXT1:%.*]] = zext i32 [[CALL1]] to i64 -; CHECK-NEXT: [[SEXT2:%.*]] = zext i32 [[CALL2]] to i64 +; CHECK-NEXT: [[CALL1:%.*]] = call i32 @callee(), !range [[RNG0]] +; CHECK-NEXT: [[CALL2:%.*]] = call i32 @callee(), !range [[RNG0]] +; CHECK-NEXT: [[SEXT1:%.*]] = zext nneg i32 [[CALL1]] to i64 +; CHECK-NEXT: [[SEXT2:%.*]] = zext nneg i32 [[CALL2]] to i64 ; CHECK-NEXT: [[SUB:%.*]] = sub nsw i64 [[SEXT1]], [[SEXT2]] ; CHECK-NEXT: ret i64 [[SUB]] ; @@ -598,7 +598,7 @@ ; cause overflow. define i64 @test18(i32 %V) { ; CHECK-LABEL: @test18( -; CHECK-NEXT: [[CALL1:%.*]] = call i32 @callee(), [[RNG1]] +; CHECK-NEXT: [[CALL1:%.*]] = call i32 @callee(), !range [[RNG1]] ; CHECK-NEXT: [[SEXT1:%.*]] = sext i32 [[CALL1]] to i64 ; CHECK-NEXT: [[SUB:%.*]] = sub nsw i64 2147481648, [[SEXT1]] ; CHECK-NEXT: ret i64 [[SUB]] @@ -613,8 +613,8 @@ ; cause overflow. define i64 @test19(i32 %V) { ; CHECK-LABEL: @test19( -; CHECK-NEXT: [[CALL1:%.*]] = call i32 @callee(), [[RNG0]] -; CHECK-NEXT: [[SEXT1:%.*]] = zext i32 [[CALL1]] to i64 +; CHECK-NEXT: [[CALL1:%.*]] = call i32 @callee(), !range [[RNG0]] +; CHECK-NEXT: [[SEXT1:%.*]] = zext nneg i32 [[CALL1]] to i64 ; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i64 -2147481648, [[SEXT1]] ; CHECK-NEXT: ret i64 [[SUB]] ; diff --git a/llvm/test/Transforms/InstCombine/negated-bitmask.ll b/llvm/test/Transforms/InstCombine/negated-bitmask.ll --- a/llvm/test/Transforms/InstCombine/negated-bitmask.ll +++ b/llvm/test/Transforms/InstCombine/negated-bitmask.ll @@ -216,7 +216,7 @@ define i8 @neg_signbit_use2(i5 %x) { ; CHECK-LABEL: @neg_signbit_use2( ; CHECK-NEXT: [[S:%.*]] = lshr i5 [[X:%.*]], 4 -; CHECK-NEXT: [[Z:%.*]] = zext i5 [[S]] to i8 +; CHECK-NEXT: [[Z:%.*]] = zext nneg i5 [[S]] to i8 ; CHECK-NEXT: call void @usei8(i8 [[Z]]) ; CHECK-NEXT: [[R:%.*]] = sub nsw i8 0, [[Z]] ; CHECK-NEXT: ret i8 [[R]] @@ -248,7 +248,7 @@ define i32 @neg_not_signbit2(i8 %x) { ; CHECK-LABEL: @neg_not_signbit2( ; CHECK-NEXT: [[S:%.*]] = lshr i8 [[X:%.*]], 6 -; CHECK-NEXT: [[Z:%.*]] = zext i8 [[S]] to i32 +; CHECK-NEXT: [[Z:%.*]] = zext nneg i8 [[S]] to i32 ; CHECK-NEXT: [[R:%.*]] = sub nsw i32 0, [[Z]] ; CHECK-NEXT: ret i32 [[R]] ; diff --git a/llvm/test/Transforms/InstCombine/reduction-add-sext-zext-i1.ll b/llvm/test/Transforms/InstCombine/reduction-add-sext-zext-i1.ll --- a/llvm/test/Transforms/InstCombine/reduction-add-sext-zext-i1.ll +++ b/llvm/test/Transforms/InstCombine/reduction-add-sext-zext-i1.ll @@ -6,8 +6,8 @@ ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i8 ; CHECK-NEXT: [[TMP2:%.*]] = call i8 @llvm.ctpop.i8(i8 [[TMP1]]), !range [[RNG0:![0-9]+]] ; CHECK-NEXT: [[TMP3:%.*]] = and i8 [[TMP2]], 1 -; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i8 [[TMP3]], 0 -; CHECK-NEXT: ret i1 [[TMP4]] +; CHECK-NEXT: [[RES:%.*]] = icmp ne i8 [[TMP3]], 0 +; CHECK-NEXT: ret i1 [[RES]] ; %res = call i1 @llvm.vector.reduce.add.v8i32(<8 x i1> %x) ret i1 %res @@ -17,9 +17,9 @@ ; CHECK-LABEL: @reduce_add_sext( ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i1> [[X:%.*]] to i4 ; CHECK-NEXT: [[TMP2:%.*]] = call i4 @llvm.ctpop.i4(i4 [[TMP1]]), !range [[RNG1:![0-9]+]] -; CHECK-NEXT: [[TMP3:%.*]] = zext i4 [[TMP2]] to i32 -; CHECK-NEXT: [[TMP4:%.*]] = sub nsw i32 0, [[TMP3]] -; CHECK-NEXT: ret i32 [[TMP4]] +; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i4 [[TMP2]] to i32 +; CHECK-NEXT: [[RES:%.*]] = sub nsw i32 0, [[TMP3]] +; CHECK-NEXT: ret i32 [[RES]] ; %sext = sext <4 x i1> %x to <4 x i32> %res = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %sext) @@ -30,8 +30,8 @@ ; CHECK-LABEL: @reduce_add_zext( ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i8 ; CHECK-NEXT: [[TMP2:%.*]] = call i8 @llvm.ctpop.i8(i8 [[TMP1]]), !range [[RNG0]] -; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i64 -; CHECK-NEXT: ret i64 [[TMP3]] +; CHECK-NEXT: [[RES:%.*]] = zext nneg i8 [[TMP2]] to i64 +; CHECK-NEXT: ret i64 [[RES]] ; %zext = zext <8 x i1> %x to <8 x i64> %res = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %zext) @@ -42,8 +42,8 @@ ; CHECK-LABEL: @reduce_add_sext_same( ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i1> [[X:%.*]] to i16 ; CHECK-NEXT: [[TMP2:%.*]] = call i16 @llvm.ctpop.i16(i16 [[TMP1]]), !range [[RNG2:![0-9]+]] -; CHECK-NEXT: [[TMP3:%.*]] = sub nsw i16 0, [[TMP2]] -; CHECK-NEXT: ret i16 [[TMP3]] +; CHECK-NEXT: [[RES:%.*]] = sub nsw i16 0, [[TMP2]] +; CHECK-NEXT: ret i16 [[RES]] ; %sext = sext <16 x i1> %x to <16 x i16> %res = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %sext) @@ -55,8 +55,8 @@ ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <128 x i1> [[X:%.*]] to i128 ; CHECK-NEXT: [[TMP2:%.*]] = call i128 @llvm.ctpop.i128(i128 [[TMP1]]), !range [[RNG3:![0-9]+]] ; CHECK-NEXT: [[TMP3:%.*]] = trunc i128 [[TMP2]] to i8 -; CHECK-NEXT: [[TMP4:%.*]] = sub i8 0, [[TMP3]] -; CHECK-NEXT: ret i8 [[TMP4]] +; CHECK-NEXT: [[RES:%.*]] = sub i8 0, [[TMP3]] +; CHECK-NEXT: ret i8 [[RES]] ; %sext = sext <128 x i1> %x to <128 x i8> %res = call i8 @llvm.vector.reduce.add.v128i8(<128 x i8> %sext) @@ -69,11 +69,11 @@ ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <128 x i1> [[X:%.*]] to i128 ; CHECK-NEXT: [[TMP2:%.*]] = call i128 @llvm.ctpop.i128(i128 [[TMP1]]), !range [[RNG3]] ; CHECK-NEXT: [[TMP3:%.*]] = trunc i128 [[TMP2]] to i8 -; CHECK-NEXT: [[TMP4:%.*]] = sub i8 0, [[TMP3]] -; CHECK-NEXT: [[TMP5:%.*]] = extractelement <128 x i1> [[X]], i64 0 -; CHECK-NEXT: [[EXT:%.*]] = sext i1 [[TMP5]] to i8 +; CHECK-NEXT: [[RES:%.*]] = sub i8 0, [[TMP3]] +; CHECK-NEXT: [[TMP4:%.*]] = extractelement <128 x i1> [[X]], i64 0 +; CHECK-NEXT: [[EXT:%.*]] = sext i1 [[TMP4]] to i8 ; CHECK-NEXT: store i8 [[EXT]], ptr @glob, align 1 -; CHECK-NEXT: ret i8 [[TMP4]] +; CHECK-NEXT: ret i8 [[RES]] ; %sext = sext <128 x i1> %x to <128 x i8> %res = call i8 @llvm.vector.reduce.add.v128i8(<128 x i8> %sext) @@ -87,11 +87,11 @@ ; CHECK-LABEL: @reduce_add_zext_external_use( ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i8 ; CHECK-NEXT: [[TMP2:%.*]] = call i8 @llvm.ctpop.i8(i8 [[TMP1]]), !range [[RNG0]] -; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i64 -; CHECK-NEXT: [[TMP4:%.*]] = extractelement <8 x i1> [[X]], i64 0 -; CHECK-NEXT: [[EXT:%.*]] = zext i1 [[TMP4]] to i64 +; CHECK-NEXT: [[RES:%.*]] = zext nneg i8 [[TMP2]] to i64 +; CHECK-NEXT: [[TMP3:%.*]] = extractelement <8 x i1> [[X]], i64 0 +; CHECK-NEXT: [[EXT:%.*]] = zext i1 [[TMP3]] to i64 ; CHECK-NEXT: store i64 [[EXT]], ptr @glob1, align 8 -; CHECK-NEXT: ret i64 [[TMP3]] +; CHECK-NEXT: ret i64 [[RES]] ; %zext = zext <8 x i1> %x to <8 x i64> %res = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %zext) diff --git a/llvm/test/Transforms/InstCombine/reduction-xor-sext-zext-i1.ll b/llvm/test/Transforms/InstCombine/reduction-xor-sext-zext-i1.ll --- a/llvm/test/Transforms/InstCombine/reduction-xor-sext-zext-i1.ll +++ b/llvm/test/Transforms/InstCombine/reduction-xor-sext-zext-i1.ll @@ -6,8 +6,8 @@ ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i8 ; CHECK-NEXT: [[TMP2:%.*]] = call i8 @llvm.ctpop.i8(i8 [[TMP1]]), !range [[RNG0:![0-9]+]] ; CHECK-NEXT: [[TMP3:%.*]] = and i8 [[TMP2]], 1 -; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i8 [[TMP3]], 0 -; CHECK-NEXT: ret i1 [[TMP4]] +; CHECK-NEXT: [[RES:%.*]] = icmp ne i8 [[TMP3]], 0 +; CHECK-NEXT: ret i1 [[RES]] ; %res = call i1 @llvm.vector.reduce.xor.v8i32(<8 x i1> %x) ret i1 %res @@ -19,8 +19,8 @@ ; CHECK-NEXT: [[TMP2:%.*]] = call i4 @llvm.ctpop.i4(i4 [[TMP1]]), !range [[RNG1:![0-9]+]] ; CHECK-NEXT: [[TMP3:%.*]] = and i4 [[TMP2]], 1 ; CHECK-NEXT: [[SEXT:%.*]] = sub nsw i4 0, [[TMP3]] -; CHECK-NEXT: [[TMP4:%.*]] = sext i4 [[SEXT]] to i32 -; CHECK-NEXT: ret i32 [[TMP4]] +; CHECK-NEXT: [[RES:%.*]] = sext i4 [[SEXT]] to i32 +; CHECK-NEXT: ret i32 [[RES]] ; %sext = sext <4 x i1> %x to <4 x i32> %res = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> %sext) @@ -32,8 +32,8 @@ ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i8 ; CHECK-NEXT: [[TMP2:%.*]] = call i8 @llvm.ctpop.i8(i8 [[TMP1]]), !range [[RNG0]] ; CHECK-NEXT: [[TMP3:%.*]] = and i8 [[TMP2]], 1 -; CHECK-NEXT: [[TMP4:%.*]] = zext i8 [[TMP3]] to i64 -; CHECK-NEXT: ret i64 [[TMP4]] +; CHECK-NEXT: [[RES:%.*]] = zext nneg i8 [[TMP3]] to i64 +; CHECK-NEXT: ret i64 [[RES]] ; %zext = zext <8 x i1> %x to <8 x i64> %res = call i64 @llvm.vector.reduce.xor.v8i64(<8 x i64> %zext) @@ -59,8 +59,8 @@ ; CHECK-NEXT: [[TMP2:%.*]] = call i128 @llvm.ctpop.i128(i128 [[TMP1]]), !range [[RNG3:![0-9]+]] ; CHECK-NEXT: [[TMP3:%.*]] = trunc i128 [[TMP2]] to i8 ; CHECK-NEXT: [[TMP4:%.*]] = and i8 [[TMP3]], 1 -; CHECK-NEXT: [[TMP5:%.*]] = sub nsw i8 0, [[TMP4]] -; CHECK-NEXT: ret i8 [[TMP5]] +; CHECK-NEXT: [[RES:%.*]] = sub nsw i8 0, [[TMP4]] +; CHECK-NEXT: ret i8 [[RES]] ; %sext = sext <128 x i1> %x to <128 x i8> %res = call i8 @llvm.vector.reduce.xor.v128i8(<128 x i8> %sext) @@ -74,11 +74,11 @@ ; CHECK-NEXT: [[TMP2:%.*]] = call i128 @llvm.ctpop.i128(i128 [[TMP1]]), !range [[RNG3]] ; CHECK-NEXT: [[TMP3:%.*]] = trunc i128 [[TMP2]] to i8 ; CHECK-NEXT: [[TMP4:%.*]] = and i8 [[TMP3]], 1 -; CHECK-NEXT: [[TMP5:%.*]] = sub nsw i8 0, [[TMP4]] -; CHECK-NEXT: [[TMP6:%.*]] = extractelement <128 x i1> [[X]], i64 0 -; CHECK-NEXT: [[EXT:%.*]] = sext i1 [[TMP6]] to i8 +; CHECK-NEXT: [[RES:%.*]] = sub nsw i8 0, [[TMP4]] +; CHECK-NEXT: [[TMP5:%.*]] = extractelement <128 x i1> [[X]], i64 0 +; CHECK-NEXT: [[EXT:%.*]] = sext i1 [[TMP5]] to i8 ; CHECK-NEXT: store i8 [[EXT]], ptr @glob, align 1 -; CHECK-NEXT: ret i8 [[TMP5]] +; CHECK-NEXT: ret i8 [[RES]] ; %sext = sext <128 x i1> %x to <128 x i8> %res = call i8 @llvm.vector.reduce.xor.v128i8(<128 x i8> %sext) @@ -93,11 +93,11 @@ ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i8 ; CHECK-NEXT: [[TMP2:%.*]] = call i8 @llvm.ctpop.i8(i8 [[TMP1]]), !range [[RNG0]] ; CHECK-NEXT: [[TMP3:%.*]] = and i8 [[TMP2]], 1 -; CHECK-NEXT: [[TMP4:%.*]] = zext i8 [[TMP3]] to i64 -; CHECK-NEXT: [[TMP5:%.*]] = extractelement <8 x i1> [[X]], i64 0 -; CHECK-NEXT: [[EXT:%.*]] = zext i1 [[TMP5]] to i64 +; CHECK-NEXT: [[RES:%.*]] = zext nneg i8 [[TMP3]] to i64 +; CHECK-NEXT: [[TMP4:%.*]] = extractelement <8 x i1> [[X]], i64 0 +; CHECK-NEXT: [[EXT:%.*]] = zext i1 [[TMP4]] to i64 ; CHECK-NEXT: store i64 [[EXT]], ptr @glob1, align 8 -; CHECK-NEXT: ret i64 [[TMP4]] +; CHECK-NEXT: ret i64 [[RES]] ; %zext = zext <8 x i1> %x to <8 x i64> %res = call i64 @llvm.vector.reduce.xor.v8i64(<8 x i64> %zext) diff --git a/llvm/test/Transforms/InstCombine/rotate.ll b/llvm/test/Transforms/InstCombine/rotate.ll --- a/llvm/test/Transforms/InstCombine/rotate.ll +++ b/llvm/test/Transforms/InstCombine/rotate.ll @@ -631,7 +631,7 @@ define i64 @rotateright_64_zext_neg_mask_amount(i64 %0, i32 %1) { ; CHECK-LABEL: @rotateright_64_zext_neg_mask_amount( -; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP1:%.*]] to i64 +; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP1:%.*]] to i64 ; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP0:%.*]], i64 [[TMP0]], i64 [[TMP3]]) ; CHECK-NEXT: ret i64 [[TMP4]] ; @@ -682,7 +682,7 @@ define i64 @rotateleft_64_zext_neg_mask_amount(i64 %0, i32 %1) { ; CHECK-LABEL: @rotateleft_64_zext_neg_mask_amount( -; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP1:%.*]] to i64 +; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP1:%.*]] to i64 ; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.fshl.i64(i64 [[TMP0:%.*]], i64 [[TMP0]], i64 [[TMP3]]) ; CHECK-NEXT: ret i64 [[TMP4]] ; @@ -852,7 +852,7 @@ define i32 @rotl_select_zext_shamt(i32 %x, i8 %y) { ; CHECK-LABEL: @rotl_select_zext_shamt( -; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[Y:%.*]] to i32 +; CHECK-NEXT: [[TMP1:%.*]] = zext nneg i8 [[Y:%.*]] to i32 ; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.fshl.i32(i32 [[X:%.*]], i32 [[X]], i32 [[TMP1]]) ; CHECK-NEXT: ret i32 [[R]] ; @@ -870,7 +870,7 @@ define i64 @rotr_select_zext_shamt(i64 %x, i32 %y) { ; CHECK-LABEL: @rotr_select_zext_shamt( -; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[Y:%.*]] to i64 +; CHECK-NEXT: [[TMP1:%.*]] = zext nneg i32 [[Y:%.*]] to i64 ; CHECK-NEXT: [[R:%.*]] = call i64 @llvm.fshr.i64(i64 [[X:%.*]], i64 [[X]], i64 [[TMP1]]) ; CHECK-NEXT: ret i64 [[R]] ; @@ -907,7 +907,7 @@ define i32 @rotateleft32_doubleand1(i32 %v, i8 %r) { ; CHECK-LABEL: @rotateleft32_doubleand1( -; CHECK-NEXT: [[Z:%.*]] = zext i8 [[R:%.*]] to i32 +; CHECK-NEXT: [[Z:%.*]] = zext nneg i8 [[R:%.*]] to i32 ; CHECK-NEXT: [[OR:%.*]] = call i32 @llvm.fshl.i32(i32 [[V:%.*]], i32 [[V]], i32 [[Z]]) ; CHECK-NEXT: ret i32 [[OR]] ; @@ -923,7 +923,7 @@ define i32 @rotateright32_doubleand1(i32 %v, i16 %r) { ; CHECK-LABEL: @rotateright32_doubleand1( -; CHECK-NEXT: [[Z:%.*]] = zext i16 [[R:%.*]] to i32 +; CHECK-NEXT: [[Z:%.*]] = zext nneg i16 [[R:%.*]] to i32 ; CHECK-NEXT: [[OR:%.*]] = call i32 @llvm.fshr.i32(i32 [[V:%.*]], i32 [[V]], i32 [[Z]]) ; CHECK-NEXT: ret i32 [[OR]] ; diff --git a/llvm/test/Transforms/InstCombine/select-bitext-bitwise-ops.ll b/llvm/test/Transforms/InstCombine/select-bitext-bitwise-ops.ll --- a/llvm/test/Transforms/InstCombine/select-bitext-bitwise-ops.ll +++ b/llvm/test/Transforms/InstCombine/select-bitext-bitwise-ops.ll @@ -5,7 +5,7 @@ ; CHECK-LABEL: @sel_false_val_is_a_masked_shl_of_true_val1( ; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2 ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 60 -; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 +; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64 ; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] ; CHECK-NEXT: ret i64 [[TMP4]] ; @@ -22,7 +22,7 @@ ; CHECK-LABEL: @sel_false_val_is_a_masked_shl_of_true_val2( ; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2 ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 60 -; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 +; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64 ; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] ; CHECK-NEXT: ret i64 [[TMP4]] ; @@ -39,7 +39,7 @@ ; CHECK-LABEL: @sel_false_val_is_a_masked_lshr_of_true_val1( ; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 2 ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 15 -; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 +; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64 ; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] ; CHECK-NEXT: ret i64 [[TMP4]] ; @@ -56,7 +56,7 @@ ; CHECK-LABEL: @sel_false_val_is_a_masked_lshr_of_true_val2( ; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 2 ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 15 -; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 +; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64 ; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] ; CHECK-NEXT: ret i64 [[TMP4]] ; diff --git a/llvm/test/Transforms/InstCombine/select-bitext.ll b/llvm/test/Transforms/InstCombine/select-bitext.ll --- a/llvm/test/Transforms/InstCombine/select-bitext.ll +++ b/llvm/test/Transforms/InstCombine/select-bitext.ll @@ -166,7 +166,7 @@ define i64 @trunc_sel_larger_zext(i32 %a, i1 %cmp) { ; CHECK-LABEL: @trunc_sel_larger_zext( ; CHECK-NEXT: [[TRUNC_MASK:%.*]] = and i32 [[A:%.*]], 65535 -; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[TRUNC_MASK]] to i64 +; CHECK-NEXT: [[TMP1:%.*]] = zext nneg i32 [[TRUNC_MASK]] to i64 ; CHECK-NEXT: [[EXT:%.*]] = select i1 [[CMP:%.*]], i64 [[TMP1]], i64 42 ; CHECK-NEXT: ret i64 [[EXT]] ; @@ -179,7 +179,7 @@ define <2 x i64> @trunc_sel_larger_zext_vec(<2 x i32> %a, <2 x i1> %cmp) { ; CHECK-LABEL: @trunc_sel_larger_zext_vec( ; CHECK-NEXT: [[TRUNC_MASK:%.*]] = and <2 x i32> [[A:%.*]], -; CHECK-NEXT: [[TMP1:%.*]] = zext <2 x i32> [[TRUNC_MASK]] to <2 x i64> +; CHECK-NEXT: [[TMP1:%.*]] = zext nneg <2 x i32> [[TRUNC_MASK]] to <2 x i64> ; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> [[CMP:%.*]], <2 x i64> [[TMP1]], <2 x i64> ; CHECK-NEXT: ret <2 x i64> [[EXT]] ; diff --git a/llvm/test/Transforms/InstCombine/select-cmp-cttz-ctlz.ll b/llvm/test/Transforms/InstCombine/select-cmp-cttz-ctlz.ll --- a/llvm/test/Transforms/InstCombine/select-cmp-cttz-ctlz.ll +++ b/llvm/test/Transforms/InstCombine/select-cmp-cttz-ctlz.ll @@ -142,7 +142,7 @@ define i32 @test1c(i16 %x) { ; CHECK-LABEL: @test1c( ; CHECK-NEXT: [[CT:%.*]] = tail call i16 @llvm.cttz.i16(i16 [[X:%.*]], i1 false), !range [[RNG0]] -; CHECK-NEXT: [[CAST2:%.*]] = zext i16 [[CT]] to i32 +; CHECK-NEXT: [[CAST2:%.*]] = zext nneg i16 [[CT]] to i32 ; CHECK-NEXT: ret i32 [[CAST2]] ; %ct = tail call i16 @llvm.cttz.i16(i16 %x, i1 true) @@ -155,7 +155,7 @@ define i64 @test2c(i16 %x) { ; CHECK-LABEL: @test2c( ; CHECK-NEXT: [[CT:%.*]] = tail call i16 @llvm.cttz.i16(i16 [[X:%.*]], i1 false), !range [[RNG0]] -; CHECK-NEXT: [[CONV:%.*]] = zext i16 [[CT]] to i64 +; CHECK-NEXT: [[CONV:%.*]] = zext nneg i16 [[CT]] to i64 ; CHECK-NEXT: ret i64 [[CONV]] ; %ct = tail call i16 @llvm.cttz.i16(i16 %x, i1 true) @@ -168,7 +168,7 @@ define i64 @test3c(i32 %x) { ; CHECK-LABEL: @test3c( ; CHECK-NEXT: [[CT:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false), !range [[RNG1]] -; CHECK-NEXT: [[CONV:%.*]] = zext i32 [[CT]] to i64 +; CHECK-NEXT: [[CONV:%.*]] = zext nneg i32 [[CT]] to i64 ; CHECK-NEXT: ret i64 [[CONV]] ; %ct = tail call i32 @llvm.cttz.i32(i32 %x, i1 true) @@ -181,7 +181,7 @@ define i32 @test4c(i16 %x) { ; CHECK-LABEL: @test4c( ; CHECK-NEXT: [[CT:%.*]] = tail call i16 @llvm.ctlz.i16(i16 [[X:%.*]], i1 false), !range [[RNG0]] -; CHECK-NEXT: [[CAST:%.*]] = zext i16 [[CT]] to i32 +; CHECK-NEXT: [[CAST:%.*]] = zext nneg i16 [[CT]] to i32 ; CHECK-NEXT: ret i32 [[CAST]] ; %ct = tail call i16 @llvm.ctlz.i16(i16 %x, i1 true) @@ -194,7 +194,7 @@ define i64 @test5c(i16 %x) { ; CHECK-LABEL: @test5c( ; CHECK-NEXT: [[CT:%.*]] = tail call i16 @llvm.ctlz.i16(i16 [[X:%.*]], i1 false), !range [[RNG0]] -; CHECK-NEXT: [[CAST:%.*]] = zext i16 [[CT]] to i64 +; CHECK-NEXT: [[CAST:%.*]] = zext nneg i16 [[CT]] to i64 ; CHECK-NEXT: ret i64 [[CAST]] ; %ct = tail call i16 @llvm.ctlz.i16(i16 %x, i1 true) @@ -207,7 +207,7 @@ define i64 @test6c(i32 %x) { ; CHECK-LABEL: @test6c( ; CHECK-NEXT: [[CT:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 false), !range [[RNG1]] -; CHECK-NEXT: [[CAST:%.*]] = zext i32 [[CT]] to i64 +; CHECK-NEXT: [[CAST:%.*]] = zext nneg i32 [[CT]] to i64 ; CHECK-NEXT: ret i64 [[CAST]] ; %ct = tail call i32 @llvm.ctlz.i32(i32 %x, i1 true) @@ -387,7 +387,7 @@ define i64 @select_bug1(i32 %x) { ; CHECK-LABEL: @select_bug1( ; CHECK-NEXT: [[CT:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false), !range [[RNG1]] -; CHECK-NEXT: [[CONV:%.*]] = zext i32 [[CT]] to i64 +; CHECK-NEXT: [[CONV:%.*]] = zext nneg i32 [[CT]] to i64 ; CHECK-NEXT: ret i64 [[CONV]] ; %ct = tail call i32 @llvm.cttz.i32(i32 %x, i1 false) @@ -565,7 +565,7 @@ define i64 @test_multiuse_zext_def(i32 %x, ptr %p) { ; CHECK-LABEL: @test_multiuse_zext_def( ; CHECK-NEXT: [[CT:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false), !range [[RNG1]] -; CHECK-NEXT: [[CONV:%.*]] = zext i32 [[CT]] to i64 +; CHECK-NEXT: [[CONV:%.*]] = zext nneg i32 [[CT]] to i64 ; CHECK-NEXT: store i64 [[CONV]], ptr [[P:%.*]], align 4 ; CHECK-NEXT: ret i64 [[CONV]] ; @@ -580,7 +580,7 @@ define i64 @test_multiuse_zext_undef(i32 %x, ptr %p) { ; CHECK-LABEL: @test_multiuse_zext_undef( ; CHECK-NEXT: [[CT:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false), !range [[RNG1]] -; CHECK-NEXT: [[CONV:%.*]] = zext i32 [[CT]] to i64 +; CHECK-NEXT: [[CONV:%.*]] = zext nneg i32 [[CT]] to i64 ; CHECK-NEXT: store i64 [[CONV]], ptr [[P:%.*]], align 4 ; CHECK-NEXT: ret i64 [[CONV]] ; diff --git a/llvm/test/Transforms/InstCombine/select-ctlz-to-cttz.ll b/llvm/test/Transforms/InstCombine/select-ctlz-to-cttz.ll --- a/llvm/test/Transforms/InstCombine/select-ctlz-to-cttz.ll +++ b/llvm/test/Transforms/InstCombine/select-ctlz-to-cttz.ll @@ -220,10 +220,10 @@ define i4 @PR45762(i3 %x4) { ; CHECK-LABEL: @PR45762( ; CHECK-NEXT: [[T4:%.*]] = call i3 @llvm.cttz.i3(i3 [[X4:%.*]], i1 false), !range [[RNG2:![0-9]+]] -; CHECK-NEXT: [[T7:%.*]] = zext i3 [[T4]] to i4 +; CHECK-NEXT: [[T7:%.*]] = zext nneg i3 [[T4]] to i4 ; CHECK-NEXT: [[ONE_HOT_16:%.*]] = shl nuw i4 1, [[T7]] -; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i3 [[X4]], 0 -; CHECK-NEXT: [[UMUL_231:%.*]] = select i1 [[DOTNOT]], i4 0, i4 [[T7]] +; CHECK-NEXT: [[OR_69_NOT:%.*]] = icmp eq i3 [[X4]], 0 +; CHECK-NEXT: [[UMUL_231:%.*]] = select i1 [[OR_69_NOT]], i4 0, i4 [[T7]] ; CHECK-NEXT: [[SEL_71:%.*]] = shl i4 [[ONE_HOT_16]], [[UMUL_231]] ; CHECK-NEXT: ret i4 [[SEL_71]] ; @@ -249,10 +249,10 @@ define i4 @PR45762_logical(i3 %x4) { ; CHECK-LABEL: @PR45762_logical( ; CHECK-NEXT: [[T4:%.*]] = call i3 @llvm.cttz.i3(i3 [[X4:%.*]], i1 false), !range [[RNG2]] -; CHECK-NEXT: [[T7:%.*]] = zext i3 [[T4]] to i4 +; CHECK-NEXT: [[T7:%.*]] = zext nneg i3 [[T4]] to i4 ; CHECK-NEXT: [[ONE_HOT_16:%.*]] = shl nuw i4 1, [[T7]] -; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i3 [[X4]], 0 -; CHECK-NEXT: [[UMUL_231:%.*]] = select i1 [[DOTNOT]], i4 0, i4 [[T7]] +; CHECK-NEXT: [[OR_69_NOT:%.*]] = icmp eq i3 [[X4]], 0 +; CHECK-NEXT: [[UMUL_231:%.*]] = select i1 [[OR_69_NOT]], i4 0, i4 [[T7]] ; CHECK-NEXT: [[SEL_71:%.*]] = shl i4 [[ONE_HOT_16]], [[UMUL_231]] ; CHECK-NEXT: ret i4 [[SEL_71]] ; diff --git a/llvm/test/Transforms/InstCombine/select-obo-peo-ops.ll b/llvm/test/Transforms/InstCombine/select-obo-peo-ops.ll --- a/llvm/test/Transforms/InstCombine/select-obo-peo-ops.ll +++ b/llvm/test/Transforms/InstCombine/select-obo-peo-ops.ll @@ -5,7 +5,7 @@ ; CHECK-LABEL: @test_shl_nuw_nsw__all_are_safe( ; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2 ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 60 -; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 +; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64 ; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] ; CHECK-NEXT: ret i64 [[TMP4]] ; @@ -22,7 +22,7 @@ ; CHECK-LABEL: @test_shl_nuw__all_are_safe( ; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2 ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 60 -; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 +; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64 ; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] ; CHECK-NEXT: ret i64 [[TMP4]] ; @@ -39,7 +39,7 @@ ; CHECK-LABEL: @test_shl_nsw__all_are_safe( ; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2 ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 60 -; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 +; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64 ; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] ; CHECK-NEXT: ret i64 [[TMP4]] ; @@ -56,7 +56,7 @@ ; CHECK-LABEL: @test_shl__all_are_safe( ; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2 ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 60 -; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 +; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64 ; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] ; CHECK-NEXT: ret i64 [[TMP4]] ; @@ -278,7 +278,7 @@ ; CHECK-LABEL: @test_lshr_exact__exact_is_safe( ; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 2 ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 15 -; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 +; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64 ; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] ; CHECK-NEXT: ret i64 [[TMP4]] ; @@ -295,7 +295,7 @@ ; CHECK-LABEL: @test_lshr__exact_is_safe( ; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 2 ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 15 -; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 +; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64 ; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] ; CHECK-NEXT: ret i64 [[TMP4]] ; @@ -312,7 +312,7 @@ ; CHECK-LABEL: @test_lshr_exact__exact_is_unsafe( ; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 2 ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 15 -; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 +; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64 ; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] ; CHECK-NEXT: ret i64 [[TMP4]] ; @@ -329,7 +329,7 @@ ; CHECK-LABEL: @test_lshr__exact_is_unsafe( ; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 2 ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 15 -; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 +; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64 ; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] ; CHECK-NEXT: ret i64 [[TMP4]] ; diff --git a/llvm/test/Transforms/InstCombine/select-with-bitwise-ops.ll b/llvm/test/Transforms/InstCombine/select-with-bitwise-ops.ll --- a/llvm/test/Transforms/InstCombine/select-with-bitwise-ops.ll +++ b/llvm/test/Transforms/InstCombine/select-with-bitwise-ops.ll @@ -10,8 +10,8 @@ ; CHECK-LABEL: @select_icmp_eq_and_1_0_or_2( ; CHECK-NEXT: [[AND:%.*]] = shl i32 [[X:%.*]], 1 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[AND]], 2 -; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], [[Y:%.*]] -; CHECK-NEXT: ret i32 [[TMP2]] +; CHECK-NEXT: [[SELECT:%.*]] = or i32 [[TMP1]], [[Y:%.*]] +; CHECK-NEXT: ret i32 [[SELECT]] ; %and = and i32 %x, 1 %cmp = icmp eq i32 %and, 0 @@ -24,8 +24,8 @@ ; CHECK-LABEL: @select_icmp_eq_and_1_0_or_2_vec( ; CHECK-NEXT: [[AND:%.*]] = shl <2 x i32> [[X:%.*]], ; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[AND]], -; CHECK-NEXT: [[TMP2:%.*]] = or <2 x i32> [[TMP1]], [[Y:%.*]] -; CHECK-NEXT: ret <2 x i32> [[TMP2]] +; CHECK-NEXT: [[SELECT:%.*]] = or <2 x i32> [[TMP1]], [[Y:%.*]] +; CHECK-NEXT: ret <2 x i32> [[SELECT]] ; %and = and <2 x i32> %x, %cmp = icmp eq <2 x i32> %and, zeroinitializer @@ -68,8 +68,8 @@ ; CHECK-LABEL: @select_icmp_eq_and_32_0_or_8( ; CHECK-NEXT: [[AND:%.*]] = lshr i32 [[X:%.*]], 2 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[AND]], 8 -; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], [[Y:%.*]] -; CHECK-NEXT: ret i32 [[TMP2]] +; CHECK-NEXT: [[SELECT:%.*]] = or i32 [[TMP1]], [[Y:%.*]] +; CHECK-NEXT: ret i32 [[SELECT]] ; %and = and i32 %x, 32 %cmp = icmp eq i32 %and, 0 @@ -82,8 +82,8 @@ ; CHECK-LABEL: @select_icmp_eq_and_32_0_or_8_vec( ; CHECK-NEXT: [[AND:%.*]] = lshr <2 x i32> [[X:%.*]], ; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[AND]], -; CHECK-NEXT: [[TMP2:%.*]] = or <2 x i32> [[TMP1]], [[Y:%.*]] -; CHECK-NEXT: ret <2 x i32> [[TMP2]] +; CHECK-NEXT: [[SELECT:%.*]] = or <2 x i32> [[TMP1]], [[Y:%.*]] +; CHECK-NEXT: ret <2 x i32> [[SELECT]] ; %and = and <2 x i32> %x, %cmp = icmp eq <2 x i32> %and, zeroinitializer @@ -126,8 +126,8 @@ ; CHECK-LABEL: @select_icmp_ne_0_and_4096_or_4096( ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096 ; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[AND]], 4096 -; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], [[Y:%.*]] -; CHECK-NEXT: ret i32 [[TMP2]] +; CHECK-NEXT: [[SELECT:%.*]] = or i32 [[TMP1]], [[Y:%.*]] +; CHECK-NEXT: ret i32 [[SELECT]] ; %and = and i32 %x, 4096 %cmp = icmp ne i32 0, %and @@ -140,8 +140,8 @@ ; CHECK-LABEL: @select_icmp_ne_0_and_4096_or_4096_vec( ; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[X:%.*]], ; CHECK-NEXT: [[TMP1:%.*]] = xor <2 x i32> [[AND]], -; CHECK-NEXT: [[TMP2:%.*]] = or <2 x i32> [[TMP1]], [[Y:%.*]] -; CHECK-NEXT: ret <2 x i32> [[TMP2]] +; CHECK-NEXT: [[SELECT:%.*]] = or <2 x i32> [[TMP1]], [[Y:%.*]] +; CHECK-NEXT: ret <2 x i32> [[SELECT]] ; %and = and <2 x i32> %x, %cmp = icmp ne <2 x i32> zeroinitializer, %and @@ -183,8 +183,8 @@ define i32 @select_icmp_eq_and_4096_0_or_4096(i32 %x, i32 %y) { ; CHECK-LABEL: @select_icmp_eq_and_4096_0_or_4096( ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096 -; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[AND]], [[Y:%.*]] -; CHECK-NEXT: ret i32 [[TMP1]] +; CHECK-NEXT: [[SELECT:%.*]] = or i32 [[AND]], [[Y:%.*]] +; CHECK-NEXT: ret i32 [[SELECT]] ; %and = and i32 %x, 4096 %cmp = icmp eq i32 %and, 0 @@ -196,8 +196,8 @@ define <2 x i32> @select_icmp_eq_and_4096_0_or_4096_vec(<2 x i32> %x, <2 x i32> %y) { ; CHECK-LABEL: @select_icmp_eq_and_4096_0_or_4096_vec( ; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[X:%.*]], -; CHECK-NEXT: [[TMP1:%.*]] = or <2 x i32> [[AND]], [[Y:%.*]] -; CHECK-NEXT: ret <2 x i32> [[TMP1]] +; CHECK-NEXT: [[SELECT:%.*]] = or <2 x i32> [[AND]], [[Y:%.*]] +; CHECK-NEXT: ret <2 x i32> [[SELECT]] ; %and = and <2 x i32> %x, %cmp = icmp eq <2 x i32> %and, zeroinitializer @@ -240,8 +240,8 @@ ; CHECK-LABEL: @select_icmp_eq_0_and_1_or_1( ; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[X:%.*]] to i32 ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 1 -; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP2]], [[Y:%.*]] -; CHECK-NEXT: ret i32 [[TMP3]] +; CHECK-NEXT: [[SELECT:%.*]] = or i32 [[TMP2]], [[Y:%.*]] +; CHECK-NEXT: ret i32 [[SELECT]] ; %and = and i64 %x, 1 %cmp = icmp eq i64 %and, 0 @@ -254,8 +254,8 @@ ; CHECK-LABEL: @select_icmp_eq_0_and_1_or_1_vec( ; CHECK-NEXT: [[TMP1:%.*]] = trunc <2 x i64> [[X:%.*]] to <2 x i32> ; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i32> [[TMP1]], -; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i32> [[TMP2]], [[Y:%.*]] -; CHECK-NEXT: ret <2 x i32> [[TMP3]] +; CHECK-NEXT: [[SELECT:%.*]] = or <2 x i32> [[TMP2]], [[Y:%.*]] +; CHECK-NEXT: ret <2 x i32> [[SELECT]] ; %and = and <2 x i64> %x, %cmp = icmp eq <2 x i64> %and, zeroinitializer @@ -267,8 +267,8 @@ define i32 @select_icmp_eq_0_and_1_xor_1(i64 %x, i32 %y) { ; CHECK-LABEL: @select_icmp_eq_0_and_1_xor_1( ; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[X:%.*]] to i32 -; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 1 -; CHECK-NEXT: [[SELECT:%.*]] = xor i32 [[TMP2]], [[Y:%.*]] +; CHECK-NEXT: [[XOR:%.*]] = and i32 [[TMP1]], 1 +; CHECK-NEXT: [[SELECT:%.*]] = xor i32 [[XOR]], [[Y:%.*]] ; CHECK-NEXT: ret i32 [[SELECT]] ; %and = and i64 %x, 1 @@ -298,8 +298,8 @@ ; CHECK-NEXT: [[AND:%.*]] = lshr i32 [[X:%.*]], 7 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[AND]], 32 ; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 32 -; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP2]], [[Y:%.*]] -; CHECK-NEXT: ret i32 [[TMP3]] +; CHECK-NEXT: [[SELECT:%.*]] = or i32 [[TMP2]], [[Y:%.*]] +; CHECK-NEXT: ret i32 [[SELECT]] ; %and = and i32 %x, 4096 %cmp = icmp ne i32 0, %and @@ -343,8 +343,8 @@ ; CHECK-NEXT: [[AND:%.*]] = shl i32 [[X:%.*]], 7 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[AND]], 4096 ; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 4096 -; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP2]], [[Y:%.*]] -; CHECK-NEXT: ret i32 [[TMP3]] +; CHECK-NEXT: [[SELECT:%.*]] = or i32 [[TMP2]], [[Y:%.*]] +; CHECK-NEXT: ret i32 [[SELECT]] ; %and = and i32 %x, 32 %cmp = icmp ne i32 0, %and @@ -358,8 +358,8 @@ ; CHECK-NEXT: [[AND:%.*]] = shl <2 x i32> [[X:%.*]], ; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[AND]], ; CHECK-NEXT: [[TMP2:%.*]] = xor <2 x i32> [[TMP1]], -; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i32> [[TMP2]], [[Y:%.*]] -; CHECK-NEXT: ret <2 x i32> [[TMP3]] +; CHECK-NEXT: [[SELECT:%.*]] = or <2 x i32> [[TMP2]], [[Y:%.*]] +; CHECK-NEXT: ret <2 x i32> [[SELECT]] ; %and = and <2 x i32> %x, %cmp = icmp ne <2 x i32> zeroinitializer, %and @@ -507,8 +507,8 @@ define i32 @select_icmp_and_8_ne_0_xor_8(i32 %x) { ; CHECK-LABEL: @select_icmp_and_8_ne_0_xor_8( -; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], -9 -; CHECK-NEXT: ret i32 [[TMP1]] +; CHECK-NEXT: [[X_XOR:%.*]] = and i32 [[X:%.*]], -9 +; CHECK-NEXT: ret i32 [[X_XOR]] ; %and = and i32 %x, 8 %cmp = icmp eq i32 %and, 0 @@ -519,8 +519,8 @@ define i32 @select_icmp_and_8_eq_0_xor_8(i32 %x) { ; CHECK-LABEL: @select_icmp_and_8_eq_0_xor_8( -; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[X:%.*]], 8 -; CHECK-NEXT: ret i32 [[TMP1]] +; CHECK-NEXT: [[XOR_X:%.*]] = or i32 [[X:%.*]], 8 +; CHECK-NEXT: ret i32 [[XOR_X]] ; %and = and i32 %x, 8 %cmp = icmp eq i32 %and, 0 @@ -563,9 +563,9 @@ ; CHECK-LABEL: @select_icmp_x_and_8_ne_0_y_or_8( ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 8 ; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[AND]], 8 -; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -; CHECK-NEXT: [[TMP3:%.*]] = or i64 [[TMP2]], [[Y:%.*]] -; CHECK-NEXT: ret i64 [[TMP3]] +; CHECK-NEXT: [[TMP2:%.*]] = zext nneg i32 [[TMP1]] to i64 +; CHECK-NEXT: [[OR_Y:%.*]] = or i64 [[TMP2]], [[Y:%.*]] +; CHECK-NEXT: ret i64 [[OR_Y]] ; %and = and i32 %x, 8 %cmp = icmp eq i32 %and, 0 @@ -578,9 +578,9 @@ ; CHECK-LABEL: @select_icmp_x_and_8_ne_0_y_or_8_vec( ; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[X:%.*]], ; CHECK-NEXT: [[TMP1:%.*]] = xor <2 x i32> [[AND]], -; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64> -; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP2]], [[Y:%.*]] -; CHECK-NEXT: ret <2 x i64> [[TMP3]] +; CHECK-NEXT: [[TMP2:%.*]] = zext nneg <2 x i32> [[TMP1]] to <2 x i64> +; CHECK-NEXT: [[OR_Y:%.*]] = or <2 x i64> [[TMP2]], [[Y:%.*]] +; CHECK-NEXT: ret <2 x i64> [[OR_Y]] ; %and = and <2 x i32> %x, %cmp = icmp eq <2 x i32> %and, zeroinitializer @@ -606,8 +606,8 @@ define i32 @select_icmp_and_2147483648_ne_0_xor_2147483648(i32 %x) { ; CHECK-LABEL: @select_icmp_and_2147483648_ne_0_xor_2147483648( -; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 2147483647 -; CHECK-NEXT: ret i32 [[TMP1]] +; CHECK-NEXT: [[X_XOR:%.*]] = and i32 [[X:%.*]], 2147483647 +; CHECK-NEXT: ret i32 [[X_XOR]] ; %and = and i32 %x, 2147483648 %cmp = icmp eq i32 %and, 0 @@ -618,8 +618,8 @@ define i32 @select_icmp_and_2147483648_eq_0_xor_2147483648(i32 %x) { ; CHECK-LABEL: @select_icmp_and_2147483648_eq_0_xor_2147483648( -; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[X:%.*]], -2147483648 -; CHECK-NEXT: ret i32 [[TMP1]] +; CHECK-NEXT: [[XOR_X:%.*]] = or i32 [[X:%.*]], -2147483648 +; CHECK-NEXT: ret i32 [[XOR_X]] ; %and = and i32 %x, 2147483648 %cmp = icmp eq i32 %and, 0 @@ -644,8 +644,8 @@ ; CHECK-LABEL: @test68( ; CHECK-NEXT: [[AND:%.*]] = lshr i32 [[X:%.*]], 6 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[AND]], 2 -; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], [[Y:%.*]] -; CHECK-NEXT: ret i32 [[TMP2]] +; CHECK-NEXT: [[SELECT:%.*]] = or i32 [[TMP1]], [[Y:%.*]] +; CHECK-NEXT: ret i32 [[SELECT]] ; %and = and i32 %x, 128 %cmp = icmp eq i32 %and, 0 @@ -658,8 +658,8 @@ ; CHECK-LABEL: @test68vec( ; CHECK-NEXT: [[AND:%.*]] = lshr <2 x i32> [[X:%.*]], ; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[AND]], -; CHECK-NEXT: [[TMP2:%.*]] = or <2 x i32> [[TMP1]], [[Y:%.*]] -; CHECK-NEXT: ret <2 x i32> [[TMP2]] +; CHECK-NEXT: [[SELECT:%.*]] = or <2 x i32> [[TMP1]], [[Y:%.*]] +; CHECK-NEXT: ret <2 x i32> [[SELECT]] ; %and = and <2 x i32> %x, %cmp = icmp eq <2 x i32> %and, zeroinitializer @@ -703,8 +703,8 @@ ; CHECK-NEXT: [[AND:%.*]] = lshr i32 [[X:%.*]], 6 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[AND]], 2 ; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 2 -; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP2]], [[Y:%.*]] -; CHECK-NEXT: ret i32 [[TMP3]] +; CHECK-NEXT: [[SELECT:%.*]] = or i32 [[TMP2]], [[Y:%.*]] +; CHECK-NEXT: ret i32 [[SELECT]] ; %and = and i32 %x, 128 %cmp = icmp ne i32 %and, 0 @@ -718,8 +718,8 @@ ; CHECK-NEXT: [[AND:%.*]] = lshr <2 x i32> [[X:%.*]], ; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[AND]], ; CHECK-NEXT: [[TMP2:%.*]] = xor <2 x i32> [[TMP1]], -; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i32> [[TMP2]], [[Y:%.*]] -; CHECK-NEXT: ret <2 x i32> [[TMP3]] +; CHECK-NEXT: [[SELECT:%.*]] = or <2 x i32> [[TMP2]], [[Y:%.*]] +; CHECK-NEXT: ret <2 x i32> [[SELECT]] ; %and = and <2 x i32> %x, %cmp = icmp ne <2 x i32> %and, zeroinitializer @@ -776,8 +776,8 @@ ; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 2 ; CHECK-NEXT: [[AND:%.*]] = shl i32 [[X:%.*]], 1 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[AND]], 2 -; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], [[Y]] -; CHECK-NEXT: [[RES:%.*]] = mul i32 [[TMP2]], [[OR]] +; CHECK-NEXT: [[SELECT:%.*]] = or i32 [[TMP1]], [[Y]] +; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[OR]] ; CHECK-NEXT: ret i32 [[RES]] ; %and = and i32 %x, 1 @@ -826,8 +826,8 @@ ; CHECK-LABEL: @no_shift_no_xor_multiuse_or( ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096 ; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 4096 -; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[AND]], [[Y]] -; CHECK-NEXT: [[RES:%.*]] = mul i32 [[TMP1]], [[OR]] +; CHECK-NEXT: [[SELECT:%.*]] = or i32 [[AND]], [[Y]] +; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[OR]] ; CHECK-NEXT: ret i32 [[RES]] ; %and = and i32 %x, 4096 @@ -877,8 +877,8 @@ ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096 ; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 4096 ; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[AND]], 4096 -; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], [[Y]] -; CHECK-NEXT: [[RES:%.*]] = mul i32 [[TMP2]], [[OR]] +; CHECK-NEXT: [[SELECT:%.*]] = or i32 [[TMP1]], [[Y]] +; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[OR]] ; CHECK-NEXT: ret i32 [[RES]] ; %and = and i32 %x, 4096 @@ -979,9 +979,9 @@ ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0 ; CHECK-NEXT: [[TMP1:%.*]] = shl nuw nsw i32 [[AND]], 1 -; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], [[Y:%.*]] +; CHECK-NEXT: [[SELECT:%.*]] = or i32 [[TMP1]], [[Y:%.*]] ; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]] -; CHECK-NEXT: [[RES:%.*]] = mul i32 [[TMP2]], [[SELECT2]] +; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]] ; CHECK-NEXT: ret i32 [[RES]] ; %and = and i32 %x, 1 @@ -1035,9 +1035,9 @@ ; CHECK-LABEL: @no_shift_no_xor_multiuse_cmp( ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0 -; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[AND]], [[Y:%.*]] +; CHECK-NEXT: [[SELECT:%.*]] = or i32 [[AND]], [[Y:%.*]] ; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]] -; CHECK-NEXT: [[RES:%.*]] = mul i32 [[TMP1]], [[SELECT2]] +; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]] ; CHECK-NEXT: ret i32 [[RES]] ; %and = and i32 %x, 4096 @@ -1092,9 +1092,9 @@ ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096 ; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0 ; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[AND]], 4096 -; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], [[Y:%.*]] +; CHECK-NEXT: [[SELECT:%.*]] = or i32 [[TMP1]], [[Y:%.*]] ; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP_NOT]], i32 [[W:%.*]], i32 [[Z:%.*]] -; CHECK-NEXT: [[RES:%.*]] = mul i32 [[TMP2]], [[SELECT2]] +; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]] ; CHECK-NEXT: ret i32 [[RES]] ; %and = and i32 %x, 4096 @@ -1269,9 +1269,9 @@ ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0 ; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 4096 -; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[AND]], [[Y]] +; CHECK-NEXT: [[SELECT:%.*]] = or i32 [[AND]], [[Y]] ; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]] -; CHECK-NEXT: [[RES:%.*]] = mul i32 [[TMP1]], [[SELECT2]] +; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]] ; CHECK-NEXT: [[RES2:%.*]] = mul i32 [[RES]], [[OR]] ; CHECK-NEXT: ret i32 [[RES2]] ; diff --git a/llvm/test/Transforms/InstCombine/select_meta.ll b/llvm/test/Transforms/InstCombine/select_meta.ll --- a/llvm/test/Transforms/InstCombine/select_meta.ll +++ b/llvm/test/Transforms/InstCombine/select_meta.ll @@ -65,8 +65,8 @@ define i64 @test43(i32 %a) nounwind { ; CHECK-LABEL: @test43( ; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[A:%.*]], i32 0) -; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -; CHECK-NEXT: ret i64 [[TMP2]] +; CHECK-NEXT: [[MAX:%.*]] = zext nneg i32 [[TMP1]] to i64 +; CHECK-NEXT: ret i64 [[MAX]] ; %a_ext = sext i32 %a to i64 %is_a_nonnegative = icmp sgt i32 %a, -1 @@ -131,8 +131,8 @@ ; SMAX(SMAX(x, y), x) -> SMAX(x, y) define i32 @test30(i32 %x, i32 %y) { ; CHECK-LABEL: @test30( -; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[X:%.*]], i32 [[Y:%.*]]) -; CHECK-NEXT: ret i32 [[TMP1]] +; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.smax.i32(i32 [[X:%.*]], i32 [[Y:%.*]]) +; CHECK-NEXT: ret i32 [[COND]] ; %cmp = icmp sgt i32 %x, %y %cond = select i1 %cmp, i32 %x, i32 %y, !prof !1 @@ -144,8 +144,8 @@ ; SMAX(SMAX(75, X), 36) -> SMAX(X, 75) define i32 @test70(i32 %x) { ; CHECK-LABEL: @test70( -; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[X:%.*]], i32 75) -; CHECK-NEXT: ret i32 [[TMP1]] +; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.smax.i32(i32 [[X:%.*]], i32 75) +; CHECK-NEXT: ret i32 [[COND]] ; %cmp = icmp slt i32 %x, 75 %cond = select i1 %cmp, i32 75, i32 %x, !prof !1 @@ -158,8 +158,8 @@ ; SMIN(SMIN(X, 92), 11) -> SMIN(X, 11) define i32 @test72(i32 %x) { ; CHECK-LABEL: @test72( -; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smin.i32(i32 [[X:%.*]], i32 11) -; CHECK-NEXT: ret i32 [[TMP1]] +; CHECK-NEXT: [[RETVAL:%.*]] = call i32 @llvm.smin.i32(i32 [[X:%.*]], i32 11) +; CHECK-NEXT: ret i32 [[RETVAL]] ; %cmp = icmp sgt i32 %x, 92 %cond = select i1 %cmp, i32 92, i32 %x, !prof !1 @@ -172,9 +172,9 @@ ; SMAX(SMAX(X, 36), 75) -> SMAX(X, 75) define i32 @test74(i32 %x) { ; CHECK-LABEL: @test74( -; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[X:%.*]], i32 36) -; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.umax.i32(i32 [[TMP1]], i32 75) -; CHECK-NEXT: ret i32 [[TMP2]] +; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.smax.i32(i32 [[X:%.*]], i32 36) +; CHECK-NEXT: [[RETVAL:%.*]] = call i32 @llvm.umax.i32(i32 [[COND]], i32 75) +; CHECK-NEXT: ret i32 [[RETVAL]] ; %cmp = icmp slt i32 %x, 36 %cond = select i1 %cmp, i32 36, i32 %x, !prof !1 @@ -187,8 +187,8 @@ define i32 @smin1(i32 %x) { ; CHECK-LABEL: @smin1( ; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[X:%.*]], i32 0) -; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], -1 -; CHECK-NEXT: ret i32 [[TMP2]] +; CHECK-NEXT: [[SEL:%.*]] = xor i32 [[TMP1]], -1 +; CHECK-NEXT: ret i32 [[SEL]] ; %not_x = xor i32 %x, -1 %cmp = icmp sgt i32 %x, 0 @@ -200,8 +200,8 @@ define i32 @smin2(i32 %x) { ; CHECK-LABEL: @smin2( ; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[X:%.*]], i32 0) -; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], -1 -; CHECK-NEXT: ret i32 [[TMP2]] +; CHECK-NEXT: [[SEL:%.*]] = xor i32 [[TMP1]], -1 +; CHECK-NEXT: ret i32 [[SEL]] ; %not_x = xor i32 %x, -1 %cmp = icmp slt i32 %x, 0 @@ -213,8 +213,8 @@ define i32 @smax1(i32 %x) { ; CHECK-LABEL: @smax1( ; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smin.i32(i32 [[X:%.*]], i32 0) -; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], -1 -; CHECK-NEXT: ret i32 [[TMP2]] +; CHECK-NEXT: [[SEL:%.*]] = xor i32 [[TMP1]], -1 +; CHECK-NEXT: ret i32 [[SEL]] ; %not_x = xor i32 %x, -1 %cmp = icmp slt i32 %x, 0 @@ -226,8 +226,8 @@ define i32 @smax2(i32 %x) { ; CHECK-LABEL: @smax2( ; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smin.i32(i32 [[X:%.*]], i32 0) -; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], -1 -; CHECK-NEXT: ret i32 [[TMP2]] +; CHECK-NEXT: [[SEL:%.*]] = xor i32 [[TMP1]], -1 +; CHECK-NEXT: ret i32 [[SEL]] ; %not_x = xor i32 %x, -1 %cmp = icmp sgt i32 %x, 0 @@ -238,8 +238,8 @@ ; The compare should change, but the metadata remains the same because the select operands are not swapped. define i32 @umin1(i32 %x) { ; CHECK-LABEL: @umin1( -; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.umin.i32(i32 [[X:%.*]], i32 -2147483648) -; CHECK-NEXT: ret i32 [[TMP1]] +; CHECK-NEXT: [[SEL:%.*]] = call i32 @llvm.umin.i32(i32 [[X:%.*]], i32 -2147483648) +; CHECK-NEXT: ret i32 [[SEL]] ; %cmp = icmp sgt i32 %x, -1 %sel = select i1 %cmp, i32 %x, i32 -2147483648, !prof !1 @@ -249,8 +249,8 @@ ; The compare should change, and the metadata is swapped because the select operands are swapped. define i32 @umin2(i32 %x) { ; CHECK-LABEL: @umin2( -; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.umin.i32(i32 [[X:%.*]], i32 2147483647) -; CHECK-NEXT: ret i32 [[TMP1]] +; CHECK-NEXT: [[SEL:%.*]] = call i32 @llvm.umin.i32(i32 [[X:%.*]], i32 2147483647) +; CHECK-NEXT: ret i32 [[SEL]] ; %cmp = icmp slt i32 %x, 0 %sel = select i1 %cmp, i32 2147483647, i32 %x, !prof !1 @@ -260,8 +260,8 @@ ; The compare should change, but the metadata remains the same because the select operands are not swapped. define i32 @umax1(i32 %x) { ; CHECK-LABEL: @umax1( -; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.umax.i32(i32 [[X:%.*]], i32 2147483647) -; CHECK-NEXT: ret i32 [[TMP1]] +; CHECK-NEXT: [[SEL:%.*]] = call i32 @llvm.umax.i32(i32 [[X:%.*]], i32 2147483647) +; CHECK-NEXT: ret i32 [[SEL]] ; %cmp = icmp slt i32 %x, 0 %sel = select i1 %cmp, i32 %x, i32 2147483647, !prof !1 @@ -271,8 +271,8 @@ ; The compare should change, and the metadata is swapped because the select operands are swapped. define i32 @umax2(i32 %x) { ; CHECK-LABEL: @umax2( -; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.umax.i32(i32 [[X:%.*]], i32 -2147483648) -; CHECK-NEXT: ret i32 [[TMP1]] +; CHECK-NEXT: [[SEL:%.*]] = call i32 @llvm.umax.i32(i32 [[X:%.*]], i32 -2147483648) +; CHECK-NEXT: ret i32 [[SEL]] ; %cmp = icmp sgt i32 %x, -1 %sel = select i1 %cmp, i32 -2147483648, i32 %x, !prof !1 diff --git a/llvm/test/Transforms/InstCombine/sext.ll b/llvm/test/Transforms/InstCombine/sext.ll --- a/llvm/test/Transforms/InstCombine/sext.ll +++ b/llvm/test/Transforms/InstCombine/sext.ll @@ -12,7 +12,7 @@ define i64 @test1(i32 %x) { ; CHECK-LABEL: @test1( ; CHECK-NEXT: [[T:%.*]] = call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0:![0-9]+]] -; CHECK-NEXT: [[S:%.*]] = zext i32 [[T]] to i64 +; CHECK-NEXT: [[S:%.*]] = zext nneg i32 [[T]] to i64 ; CHECK-NEXT: ret i64 [[S]] ; %t = call i32 @llvm.ctpop.i32(i32 %x) @@ -23,7 +23,7 @@ define i64 @test2(i32 %x) { ; CHECK-LABEL: @test2( ; CHECK-NEXT: [[T:%.*]] = call i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 true), !range [[RNG0]] -; CHECK-NEXT: [[S:%.*]] = zext i32 [[T]] to i64 +; CHECK-NEXT: [[S:%.*]] = zext nneg i32 [[T]] to i64 ; CHECK-NEXT: ret i64 [[S]] ; %t = call i32 @llvm.ctlz.i32(i32 %x, i1 true) @@ -34,7 +34,7 @@ define i64 @test3(i32 %x) { ; CHECK-LABEL: @test3( ; CHECK-NEXT: [[T:%.*]] = call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 true), !range [[RNG0]] -; CHECK-NEXT: [[S:%.*]] = zext i32 [[T]] to i64 +; CHECK-NEXT: [[S:%.*]] = zext nneg i32 [[T]] to i64 ; CHECK-NEXT: ret i64 [[S]] ; %t = call i32 @llvm.cttz.i32(i32 %x, i1 true) @@ -45,7 +45,7 @@ define i64 @test4(i32 %x) { ; CHECK-LABEL: @test4( ; CHECK-NEXT: [[T:%.*]] = udiv i32 [[X:%.*]], 3 -; CHECK-NEXT: [[S:%.*]] = zext i32 [[T]] to i64 +; CHECK-NEXT: [[S:%.*]] = zext nneg i32 [[T]] to i64 ; CHECK-NEXT: ret i64 [[S]] ; %t = udiv i32 %x, 3 @@ -56,7 +56,7 @@ define i64 @test5(i32 %x) { ; CHECK-LABEL: @test5( ; CHECK-NEXT: [[T:%.*]] = urem i32 [[X:%.*]], 30000 -; CHECK-NEXT: [[S:%.*]] = zext i32 [[T]] to i64 +; CHECK-NEXT: [[S:%.*]] = zext nneg i32 [[T]] to i64 ; CHECK-NEXT: ret i64 [[S]] ; %t = urem i32 %x, 30000 @@ -68,7 +68,7 @@ ; CHECK-LABEL: @test6( ; CHECK-NEXT: [[U:%.*]] = lshr i32 [[X:%.*]], 3 ; CHECK-NEXT: [[T:%.*]] = mul nuw nsw i32 [[U]], 3 -; CHECK-NEXT: [[S:%.*]] = zext i32 [[T]] to i64 +; CHECK-NEXT: [[S:%.*]] = zext nneg i32 [[T]] to i64 ; CHECK-NEXT: ret i64 [[S]] ; %u = lshr i32 %x, 3 @@ -81,7 +81,7 @@ ; CHECK-LABEL: @test7( ; CHECK-NEXT: [[T:%.*]] = and i32 [[X:%.*]], 511 ; CHECK-NEXT: [[U:%.*]] = sub nuw nsw i32 20000, [[T]] -; CHECK-NEXT: [[S:%.*]] = zext i32 [[U]] to i64 +; CHECK-NEXT: [[S:%.*]] = zext nneg i32 [[U]] to i64 ; CHECK-NEXT: ret i64 [[S]] ; %t = and i32 %x, 511 @@ -295,8 +295,8 @@ define i32 @test18(i16 %x) { ; CHECK-LABEL: @test18( -; CHECK-NEXT: [[TMP1:%.*]] = call i16 @llvm.smax.i16(i16 [[X:%.*]], i16 0) -; CHECK-NEXT: [[EXT:%.*]] = zext i16 [[TMP1]] to i32 +; CHECK-NEXT: [[SEL:%.*]] = call i16 @llvm.smax.i16(i16 [[X:%.*]], i16 0) +; CHECK-NEXT: [[EXT:%.*]] = zext nneg i16 [[SEL]] to i32 ; CHECK-NEXT: ret i32 [[EXT]] ; %cmp = icmp slt i16 %x, 0 diff --git a/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest-with-truncation-shl.ll b/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest-with-truncation-shl.ll --- a/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest-with-truncation-shl.ll +++ b/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest-with-truncation-shl.ll @@ -16,10 +16,10 @@ define i1 @t0_const_after_fold_lshr_shl_ne(i32 %x, i64 %y, i32 %len) { ; CHECK-LABEL: @t0_const_after_fold_lshr_shl_ne( ; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 31 -; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 +; CHECK-NEXT: [[TMP2:%.*]] = zext nneg i32 [[TMP1]] to i64 ; CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], [[Y:%.*]] -; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[TMP3]], 0 -; CHECK-NEXT: ret i1 [[TMP4]] +; CHECK-NEXT: [[T5:%.*]] = icmp ne i64 [[TMP3]], 0 +; CHECK-NEXT: ret i1 [[T5]] ; %t0 = sub i32 32, %len %t1 = lshr i32 %x, %t0 @@ -39,10 +39,10 @@ define <2 x i1> @t1_vec_splat(<2 x i32> %x, <2 x i64> %y, <2 x i32> %len) { ; CHECK-LABEL: @t1_vec_splat( ; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i32> [[X:%.*]], -; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64> +; CHECK-NEXT: [[TMP2:%.*]] = zext nneg <2 x i32> [[TMP1]] to <2 x i64> ; CHECK-NEXT: [[TMP3:%.*]] = and <2 x i64> [[TMP2]], [[Y:%.*]] -; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <2 x i64> [[TMP3]], zeroinitializer -; CHECK-NEXT: ret <2 x i1> [[TMP4]] +; CHECK-NEXT: [[T5:%.*]] = icmp ne <2 x i64> [[TMP3]], zeroinitializer +; CHECK-NEXT: ret <2 x i1> [[T5]] ; %t0 = sub <2 x i32> , %len %t1 = lshr <2 x i32> %x, %t0 @@ -60,8 +60,8 @@ ; CHECK-NEXT: [[TMP1:%.*]] = zext <2 x i32> [[X:%.*]] to <2 x i64> ; CHECK-NEXT: [[TMP2:%.*]] = lshr <2 x i64> [[TMP1]], ; CHECK-NEXT: [[TMP3:%.*]] = and <2 x i64> [[TMP2]], [[Y:%.*]] -; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <2 x i64> [[TMP3]], zeroinitializer -; CHECK-NEXT: ret <2 x i1> [[TMP4]] +; CHECK-NEXT: [[T5:%.*]] = icmp ne <2 x i64> [[TMP3]], zeroinitializer +; CHECK-NEXT: ret <2 x i1> [[T5]] ; %t0 = sub <2 x i32> , %len %t1 = lshr <2 x i32> %x, %t0 @@ -211,10 +211,10 @@ ; CHECK-NEXT: [[T3:%.*]] = shl i64 [[Y:%.*]], [[T2_WIDE]] ; CHECK-NEXT: call void @use64(i64 [[T3]]) ; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 31 -; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 +; CHECK-NEXT: [[TMP2:%.*]] = zext nneg i32 [[TMP1]] to i64 ; CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], [[Y]] -; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[TMP3]], 0 -; CHECK-NEXT: ret i1 [[TMP4]] +; CHECK-NEXT: [[T5:%.*]] = icmp ne i64 [[TMP3]], 0 +; CHECK-NEXT: ret i1 [[T5]] ; %t0 = sub i32 32, %len call void @use32(i32 %t0) @@ -243,10 +243,10 @@ ; CHECK-NEXT: [[T3_TRUNC:%.*]] = trunc i64 [[T3]] to i32 ; CHECK-NEXT: call void @use32(i32 [[T3_TRUNC]]) ; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 31 -; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 +; CHECK-NEXT: [[TMP2:%.*]] = zext nneg i32 [[TMP1]] to i64 ; CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], [[Y]] -; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[TMP3]], 0 -; CHECK-NEXT: ret i1 [[TMP4]] +; CHECK-NEXT: [[T5:%.*]] = icmp ne i64 [[TMP3]], 0 +; CHECK-NEXT: ret i1 [[T5]] ; %t0 = sub i32 32, %len ; no extra uses %t1 = lshr i32 %x, %t0 ; no extra uses @@ -279,8 +279,8 @@ ; CHECK-NEXT: [[T3_TRUNC:%.*]] = trunc i64 [[T3]] to i32 ; CHECK-NEXT: call void @use32(i32 [[T3_TRUNC]]) ; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[Y]], 1 -; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[TMP1]], 0 -; CHECK-NEXT: ret i1 [[TMP2]] +; CHECK-NEXT: [[T5:%.*]] = icmp ne i64 [[TMP1]], 0 +; CHECK-NEXT: ret i1 [[T5]] ; %t0 = sub i32 32, %len call void @use32(i32 %t0) @@ -349,8 +349,8 @@ ; CHECK-NEXT: [[Y_TR:%.*]] = trunc i64 [[Y:%.*]] to i32 ; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 26 ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[Y_TR]] -; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -; CHECK-NEXT: ret i1 [[TMP3]] +; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[TMP2]], 0 +; CHECK-NEXT: ret i1 [[T3]] ; %t0 = lshr i32 %x, 12 %t1 = shl i64 %y, 14 @@ -365,8 +365,8 @@ ; CHECK-NEXT: [[Y_TR:%.*]] = trunc <2 x i64> [[Y:%.*]] to <2 x i32> ; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i32> [[X:%.*]], ; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i32> [[TMP1]], [[Y_TR]] -; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <2 x i32> [[TMP2]], zeroinitializer -; CHECK-NEXT: ret <2 x i1> [[TMP3]] +; CHECK-NEXT: [[T3:%.*]] = icmp ne <2 x i32> [[TMP2]], zeroinitializer +; CHECK-NEXT: ret <2 x i1> [[T3]] ; %t0 = lshr <2 x i32> %x, %t1 = shl <2 x i64> %y, @@ -380,8 +380,8 @@ ; CHECK-NEXT: [[Y_TR:%.*]] = trunc <2 x i64> [[Y:%.*]] to <2 x i32> ; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i32> [[X:%.*]], ; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i32> [[TMP1]], [[Y_TR]] -; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <2 x i32> [[TMP2]], zeroinitializer -; CHECK-NEXT: ret <2 x i1> [[TMP3]] +; CHECK-NEXT: [[T3:%.*]] = icmp ne <2 x i32> [[TMP2]], zeroinitializer +; CHECK-NEXT: ret <2 x i1> [[T3]] ; %t0 = lshr <2 x i32> %x, %t1 = shl <2 x i64> %y, diff --git a/llvm/test/Transforms/InstCombine/shift.ll b/llvm/test/Transforms/InstCombine/shift.ll --- a/llvm/test/Transforms/InstCombine/shift.ll +++ b/llvm/test/Transforms/InstCombine/shift.ll @@ -110,8 +110,8 @@ ;; (A >> 8) << 8 === A & -256 define i32 @test12(i32 %A) { ; CHECK-LABEL: @test12( -; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A:%.*]], -256 -; CHECK-NEXT: ret i32 [[TMP1]] +; CHECK-NEXT: [[C:%.*]] = and i32 [[A:%.*]], -256 +; CHECK-NEXT: ret i32 [[C]] ; %B = ashr i32 %A, 8 %C = shl i32 %B, 8 @@ -1252,7 +1252,7 @@ define i64 @shl_zext_extra_use(i32 %t) { ; CHECK-LABEL: @shl_zext_extra_use( ; CHECK-NEXT: [[AND:%.*]] = and i32 [[T:%.*]], 16777215 -; CHECK-NEXT: [[EXT:%.*]] = zext i32 [[AND]] to i64 +; CHECK-NEXT: [[EXT:%.*]] = zext nneg i32 [[AND]] to i64 ; CHECK-NEXT: call void @use(i64 [[EXT]]) ; CHECK-NEXT: [[SHL:%.*]] = shl nuw nsw i64 [[EXT]], 8 ; CHECK-NEXT: ret i64 [[SHL]] diff --git a/llvm/test/Transforms/InstCombine/trunc-inseltpoison.ll b/llvm/test/Transforms/InstCombine/trunc-inseltpoison.ll --- a/llvm/test/Transforms/InstCombine/trunc-inseltpoison.ll +++ b/llvm/test/Transforms/InstCombine/trunc-inseltpoison.ll @@ -243,7 +243,7 @@ define i92 @test7(i64 %A) { ; CHECK-LABEL: @test7( ; CHECK-NEXT: [[TMP1:%.*]] = lshr i64 [[A:%.*]], 32 -; CHECK-NEXT: [[D:%.*]] = zext i64 [[TMP1]] to i92 +; CHECK-NEXT: [[D:%.*]] = zext nneg i64 [[TMP1]] to i92 ; CHECK-NEXT: ret i92 [[D]] ; %B = zext i64 %A to i128 @@ -344,7 +344,7 @@ ; CHECK-LABEL: @test11( ; CHECK-NEXT: [[C:%.*]] = zext i32 [[A:%.*]] to i64 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[B:%.*]], 31 -; CHECK-NEXT: [[E:%.*]] = zext i32 [[TMP1]] to i64 +; CHECK-NEXT: [[E:%.*]] = zext nneg i32 [[TMP1]] to i64 ; CHECK-NEXT: [[F:%.*]] = shl i64 [[C]], [[E]] ; CHECK-NEXT: ret i64 [[F]] ; @@ -360,7 +360,7 @@ ; CHECK-LABEL: @test11_vec( ; CHECK-NEXT: [[C:%.*]] = zext <2 x i32> [[A:%.*]] to <2 x i64> ; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[B:%.*]], -; CHECK-NEXT: [[E:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64> +; CHECK-NEXT: [[E:%.*]] = zext nneg <2 x i32> [[TMP1]] to <2 x i64> ; CHECK-NEXT: [[F:%.*]] = shl <2 x i64> [[C]], [[E]] ; CHECK-NEXT: ret <2 x i64> [[F]] ; @@ -376,7 +376,7 @@ ; CHECK-LABEL: @test11_vec_nonuniform( ; CHECK-NEXT: [[C:%.*]] = zext <2 x i32> [[A:%.*]] to <2 x i64> ; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[B:%.*]], -; CHECK-NEXT: [[E:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64> +; CHECK-NEXT: [[E:%.*]] = zext nneg <2 x i32> [[TMP1]] to <2 x i64> ; CHECK-NEXT: [[F:%.*]] = shl <2 x i64> [[C]], [[E]] ; CHECK-NEXT: ret <2 x i64> [[F]] ; @@ -409,7 +409,7 @@ ; CHECK-LABEL: @test12( ; CHECK-NEXT: [[C:%.*]] = zext i32 [[A:%.*]] to i64 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[B:%.*]], 31 -; CHECK-NEXT: [[E:%.*]] = zext i32 [[TMP1]] to i64 +; CHECK-NEXT: [[E:%.*]] = zext nneg i32 [[TMP1]] to i64 ; CHECK-NEXT: [[F:%.*]] = lshr i64 [[C]], [[E]] ; CHECK-NEXT: ret i64 [[F]] ; @@ -425,7 +425,7 @@ ; CHECK-LABEL: @test12_vec( ; CHECK-NEXT: [[C:%.*]] = zext <2 x i32> [[A:%.*]] to <2 x i64> ; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[B:%.*]], -; CHECK-NEXT: [[E:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64> +; CHECK-NEXT: [[E:%.*]] = zext nneg <2 x i32> [[TMP1]] to <2 x i64> ; CHECK-NEXT: [[F:%.*]] = lshr <2 x i64> [[C]], [[E]] ; CHECK-NEXT: ret <2 x i64> [[F]] ; @@ -441,7 +441,7 @@ ; CHECK-LABEL: @test12_vec_nonuniform( ; CHECK-NEXT: [[C:%.*]] = zext <2 x i32> [[A:%.*]] to <2 x i64> ; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[B:%.*]], -; CHECK-NEXT: [[E:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64> +; CHECK-NEXT: [[E:%.*]] = zext nneg <2 x i32> [[TMP1]] to <2 x i64> ; CHECK-NEXT: [[F:%.*]] = lshr <2 x i64> [[C]], [[E]] ; CHECK-NEXT: ret <2 x i64> [[F]] ; @@ -474,7 +474,7 @@ ; CHECK-LABEL: @test13( ; CHECK-NEXT: [[C:%.*]] = sext i32 [[A:%.*]] to i64 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[B:%.*]], 31 -; CHECK-NEXT: [[E:%.*]] = zext i32 [[TMP1]] to i64 +; CHECK-NEXT: [[E:%.*]] = zext nneg i32 [[TMP1]] to i64 ; CHECK-NEXT: [[F:%.*]] = ashr i64 [[C]], [[E]] ; CHECK-NEXT: ret i64 [[F]] ; @@ -490,7 +490,7 @@ ; CHECK-LABEL: @test13_vec( ; CHECK-NEXT: [[C:%.*]] = sext <2 x i32> [[A:%.*]] to <2 x i64> ; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[B:%.*]], -; CHECK-NEXT: [[E:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64> +; CHECK-NEXT: [[E:%.*]] = zext nneg <2 x i32> [[TMP1]] to <2 x i64> ; CHECK-NEXT: [[F:%.*]] = ashr <2 x i64> [[C]], [[E]] ; CHECK-NEXT: ret <2 x i64> [[F]] ; @@ -506,7 +506,7 @@ ; CHECK-LABEL: @test13_vec_nonuniform( ; CHECK-NEXT: [[C:%.*]] = sext <2 x i32> [[A:%.*]] to <2 x i64> ; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[B:%.*]], -; CHECK-NEXT: [[E:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64> +; CHECK-NEXT: [[E:%.*]] = zext nneg <2 x i32> [[TMP1]] to <2 x i64> ; CHECK-NEXT: [[F:%.*]] = ashr <2 x i64> [[C]], [[E]] ; CHECK-NEXT: ret <2 x i64> [[F]] ; diff --git a/llvm/test/Transforms/InstCombine/trunc.ll b/llvm/test/Transforms/InstCombine/trunc.ll --- a/llvm/test/Transforms/InstCombine/trunc.ll +++ b/llvm/test/Transforms/InstCombine/trunc.ll @@ -243,7 +243,7 @@ define i92 @test7(i64 %A) { ; CHECK-LABEL: @test7( ; CHECK-NEXT: [[TMP1:%.*]] = lshr i64 [[A:%.*]], 32 -; CHECK-NEXT: [[D:%.*]] = zext i64 [[TMP1]] to i92 +; CHECK-NEXT: [[D:%.*]] = zext nneg i64 [[TMP1]] to i92 ; CHECK-NEXT: ret i92 [[D]] ; %B = zext i64 %A to i128 @@ -344,7 +344,7 @@ ; CHECK-LABEL: @test11( ; CHECK-NEXT: [[C:%.*]] = zext i32 [[A:%.*]] to i64 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[B:%.*]], 31 -; CHECK-NEXT: [[E:%.*]] = zext i32 [[TMP1]] to i64 +; CHECK-NEXT: [[E:%.*]] = zext nneg i32 [[TMP1]] to i64 ; CHECK-NEXT: [[F:%.*]] = shl i64 [[C]], [[E]] ; CHECK-NEXT: ret i64 [[F]] ; @@ -360,7 +360,7 @@ ; CHECK-LABEL: @test11_vec( ; CHECK-NEXT: [[C:%.*]] = zext <2 x i32> [[A:%.*]] to <2 x i64> ; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[B:%.*]], -; CHECK-NEXT: [[E:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64> +; CHECK-NEXT: [[E:%.*]] = zext nneg <2 x i32> [[TMP1]] to <2 x i64> ; CHECK-NEXT: [[F:%.*]] = shl <2 x i64> [[C]], [[E]] ; CHECK-NEXT: ret <2 x i64> [[F]] ; @@ -376,7 +376,7 @@ ; CHECK-LABEL: @test11_vec_nonuniform( ; CHECK-NEXT: [[C:%.*]] = zext <2 x i32> [[A:%.*]] to <2 x i64> ; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[B:%.*]], -; CHECK-NEXT: [[E:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64> +; CHECK-NEXT: [[E:%.*]] = zext nneg <2 x i32> [[TMP1]] to <2 x i64> ; CHECK-NEXT: [[F:%.*]] = shl <2 x i64> [[C]], [[E]] ; CHECK-NEXT: ret <2 x i64> [[F]] ; @@ -409,7 +409,7 @@ ; CHECK-LABEL: @test12( ; CHECK-NEXT: [[C:%.*]] = zext i32 [[A:%.*]] to i64 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[B:%.*]], 31 -; CHECK-NEXT: [[E:%.*]] = zext i32 [[TMP1]] to i64 +; CHECK-NEXT: [[E:%.*]] = zext nneg i32 [[TMP1]] to i64 ; CHECK-NEXT: [[F:%.*]] = lshr i64 [[C]], [[E]] ; CHECK-NEXT: ret i64 [[F]] ; @@ -425,7 +425,7 @@ ; CHECK-LABEL: @test12_vec( ; CHECK-NEXT: [[C:%.*]] = zext <2 x i32> [[A:%.*]] to <2 x i64> ; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[B:%.*]], -; CHECK-NEXT: [[E:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64> +; CHECK-NEXT: [[E:%.*]] = zext nneg <2 x i32> [[TMP1]] to <2 x i64> ; CHECK-NEXT: [[F:%.*]] = lshr <2 x i64> [[C]], [[E]] ; CHECK-NEXT: ret <2 x i64> [[F]] ; @@ -441,7 +441,7 @@ ; CHECK-LABEL: @test12_vec_nonuniform( ; CHECK-NEXT: [[C:%.*]] = zext <2 x i32> [[A:%.*]] to <2 x i64> ; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[B:%.*]], -; CHECK-NEXT: [[E:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64> +; CHECK-NEXT: [[E:%.*]] = zext nneg <2 x i32> [[TMP1]] to <2 x i64> ; CHECK-NEXT: [[F:%.*]] = lshr <2 x i64> [[C]], [[E]] ; CHECK-NEXT: ret <2 x i64> [[F]] ; @@ -474,7 +474,7 @@ ; CHECK-LABEL: @test13( ; CHECK-NEXT: [[C:%.*]] = sext i32 [[A:%.*]] to i64 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[B:%.*]], 31 -; CHECK-NEXT: [[E:%.*]] = zext i32 [[TMP1]] to i64 +; CHECK-NEXT: [[E:%.*]] = zext nneg i32 [[TMP1]] to i64 ; CHECK-NEXT: [[F:%.*]] = ashr i64 [[C]], [[E]] ; CHECK-NEXT: ret i64 [[F]] ; @@ -490,7 +490,7 @@ ; CHECK-LABEL: @test13_vec( ; CHECK-NEXT: [[C:%.*]] = sext <2 x i32> [[A:%.*]] to <2 x i64> ; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[B:%.*]], -; CHECK-NEXT: [[E:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64> +; CHECK-NEXT: [[E:%.*]] = zext nneg <2 x i32> [[TMP1]] to <2 x i64> ; CHECK-NEXT: [[F:%.*]] = ashr <2 x i64> [[C]], [[E]] ; CHECK-NEXT: ret <2 x i64> [[F]] ; @@ -506,7 +506,7 @@ ; CHECK-LABEL: @test13_vec_nonuniform( ; CHECK-NEXT: [[C:%.*]] = sext <2 x i32> [[A:%.*]] to <2 x i64> ; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[B:%.*]], -; CHECK-NEXT: [[E:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64> +; CHECK-NEXT: [[E:%.*]] = zext nneg <2 x i32> [[TMP1]] to <2 x i64> ; CHECK-NEXT: [[F:%.*]] = ashr <2 x i64> [[C]], [[E]] ; CHECK-NEXT: ret <2 x i64> [[F]] ; diff --git a/llvm/test/Transforms/InstCombine/udiv-simplify.ll b/llvm/test/Transforms/InstCombine/udiv-simplify.ll --- a/llvm/test/Transforms/InstCombine/udiv-simplify.ll +++ b/llvm/test/Transforms/InstCombine/udiv-simplify.ll @@ -27,7 +27,7 @@ ; CHECK-LABEL: @test1_PR2274( ; CHECK-NEXT: [[Y:%.*]] = lshr i32 [[X:%.*]], 30 ; CHECK-NEXT: [[R:%.*]] = udiv i32 [[Y]], [[G:%.*]] -; CHECK-NEXT: [[Z:%.*]] = zext i32 [[R]] to i64 +; CHECK-NEXT: [[Z:%.*]] = zext nneg i32 [[R]] to i64 ; CHECK-NEXT: ret i64 [[Z]] ; %y = lshr i32 %x, 30 @@ -39,7 +39,7 @@ ; CHECK-LABEL: @test2_PR2274( ; CHECK-NEXT: [[Y:%.*]] = lshr i32 [[X:%.*]], 31 ; CHECK-NEXT: [[R:%.*]] = udiv i32 [[Y]], [[V:%.*]] -; CHECK-NEXT: [[Z:%.*]] = zext i32 [[R]] to i64 +; CHECK-NEXT: [[Z:%.*]] = zext nneg i32 [[R]] to i64 ; CHECK-NEXT: ret i64 [[Z]] ; %y = lshr i32 %x, 31 diff --git a/llvm/test/Transforms/InstCombine/udivrem-change-width.ll b/llvm/test/Transforms/InstCombine/udivrem-change-width.ll --- a/llvm/test/Transforms/InstCombine/udivrem-change-width.ll +++ b/llvm/test/Transforms/InstCombine/udivrem-change-width.ll @@ -161,7 +161,7 @@ define i32 @udiv_i32_c(i8 %a) { ; CHECK-LABEL: @udiv_i32_c( ; CHECK-NEXT: [[TMP1:%.*]] = udiv i8 [[A:%.*]], 10 -; CHECK-NEXT: [[UDIV:%.*]] = zext i8 [[TMP1]] to i32 +; CHECK-NEXT: [[UDIV:%.*]] = zext nneg i8 [[TMP1]] to i32 ; CHECK-NEXT: ret i32 [[UDIV]] ; %za = zext i8 %a to i32 @@ -196,7 +196,7 @@ define i32 @udiv_illegal_type_c(i9 %a) { ; CHECK-LABEL: @udiv_illegal_type_c( ; CHECK-NEXT: [[TMP1:%.*]] = udiv i9 [[A:%.*]], 10 -; CHECK-NEXT: [[UDIV:%.*]] = zext i9 [[TMP1]] to i32 +; CHECK-NEXT: [[UDIV:%.*]] = zext nneg i9 [[TMP1]] to i32 ; CHECK-NEXT: ret i32 [[UDIV]] ; %za = zext i9 %a to i32 @@ -207,7 +207,7 @@ define i32 @urem_i32_c(i8 %a) { ; CHECK-LABEL: @urem_i32_c( ; CHECK-NEXT: [[TMP1:%.*]] = urem i8 [[A:%.*]], 10 -; CHECK-NEXT: [[UREM:%.*]] = zext i8 [[TMP1]] to i32 +; CHECK-NEXT: [[UREM:%.*]] = zext nneg i8 [[TMP1]] to i32 ; CHECK-NEXT: ret i32 [[UREM]] ; %za = zext i8 %a to i32 @@ -218,7 +218,7 @@ define <2 x i32> @urem_i32_c_vec(<2 x i8> %a) { ; CHECK-LABEL: @urem_i32_c_vec( ; CHECK-NEXT: [[TMP1:%.*]] = urem <2 x i8> [[A:%.*]], -; CHECK-NEXT: [[UREM:%.*]] = zext <2 x i8> [[TMP1]] to <2 x i32> +; CHECK-NEXT: [[UREM:%.*]] = zext nneg <2 x i8> [[TMP1]] to <2 x i32> ; CHECK-NEXT: ret <2 x i32> [[UREM]] ; %za = zext <2 x i8> %a to <2 x i32> @@ -242,7 +242,7 @@ define i32 @urem_illegal_type_c(i9 %a) { ; CHECK-LABEL: @urem_illegal_type_c( ; CHECK-NEXT: [[TMP1:%.*]] = urem i9 [[A:%.*]], 10 -; CHECK-NEXT: [[UREM:%.*]] = zext i9 [[TMP1]] to i32 +; CHECK-NEXT: [[UREM:%.*]] = zext nneg i9 [[TMP1]] to i32 ; CHECK-NEXT: ret i32 [[UREM]] ; %za = zext i9 %a to i32 @@ -253,7 +253,7 @@ define i32 @udiv_c_i32(i8 %a) { ; CHECK-LABEL: @udiv_c_i32( ; CHECK-NEXT: [[TMP1:%.*]] = udiv i8 10, [[A:%.*]] -; CHECK-NEXT: [[UDIV:%.*]] = zext i8 [[TMP1]] to i32 +; CHECK-NEXT: [[UDIV:%.*]] = zext nneg i8 [[TMP1]] to i32 ; CHECK-NEXT: ret i32 [[UDIV]] ; %za = zext i8 %a to i32 @@ -264,7 +264,7 @@ define i32 @urem_c_i32(i8 %a) { ; CHECK-LABEL: @urem_c_i32( ; CHECK-NEXT: [[TMP1:%.*]] = urem i8 10, [[A:%.*]] -; CHECK-NEXT: [[UREM:%.*]] = zext i8 [[TMP1]] to i32 +; CHECK-NEXT: [[UREM:%.*]] = zext nneg i8 [[TMP1]] to i32 ; CHECK-NEXT: ret i32 [[UREM]] ; %za = zext i8 %a to i32 diff --git a/llvm/test/Transforms/InstCombine/vector-casts-inseltpoison.ll b/llvm/test/Transforms/InstCombine/vector-casts-inseltpoison.ll --- a/llvm/test/Transforms/InstCombine/vector-casts-inseltpoison.ll +++ b/llvm/test/Transforms/InstCombine/vector-casts-inseltpoison.ll @@ -53,8 +53,8 @@ define <2 x i64> @test2(<2 x i64> %a) { ; CHECK-LABEL: @test2( ; CHECK-NEXT: [[B:%.*]] = lshr <2 x i64> [[A:%.*]], -; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i64> [[B]], -; CHECK-NEXT: ret <2 x i64> [[TMP1]] +; CHECK-NEXT: [[T:%.*]] = and <2 x i64> [[B]], +; CHECK-NEXT: ret <2 x i64> [[T]] ; %b = and <2 x i64> %a, %t = ashr <2 x i64> %b, @@ -63,8 +63,8 @@ define <2 x i64> @test3(<4 x float> %a, <4 x float> %b) { ; CHECK-LABEL: @test3( -; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord <4 x float> [[A:%.*]], [[B:%.*]] -; CHECK-NEXT: [[AND:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i32> +; CHECK-NEXT: [[AND1:%.*]] = fcmp ord <4 x float> [[A:%.*]], [[B:%.*]] +; CHECK-NEXT: [[AND:%.*]] = sext <4 x i1> [[AND1]] to <4 x i32> ; CHECK-NEXT: [[CONV:%.*]] = bitcast <4 x i32> [[AND]] to <2 x i64> ; CHECK-NEXT: ret <2 x i64> [[CONV]] ; @@ -79,8 +79,8 @@ define <2 x i64> @test4(<4 x float> %a, <4 x float> %b) { ; CHECK-LABEL: @test4( -; CHECK-NEXT: [[TMP1:%.*]] = fcmp uno <4 x float> [[A:%.*]], [[B:%.*]] -; CHECK-NEXT: [[OR:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i32> +; CHECK-NEXT: [[OR1:%.*]] = fcmp uno <4 x float> [[A:%.*]], [[B:%.*]] +; CHECK-NEXT: [[OR:%.*]] = sext <4 x i1> [[OR1]] to <4 x i32> ; CHECK-NEXT: [[CONV:%.*]] = bitcast <4 x i32> [[OR]] to <2 x i64> ; CHECK-NEXT: ret <2 x i64> [[CONV]] ; @@ -164,7 +164,7 @@ define <2 x i65> @foo(<2 x i64> %t) { ; CHECK-LABEL: @foo( ; CHECK-NEXT: [[A_MASK:%.*]] = and <2 x i64> [[T:%.*]], -; CHECK-NEXT: [[B:%.*]] = zext <2 x i64> [[A_MASK]] to <2 x i65> +; CHECK-NEXT: [[B:%.*]] = zext nneg <2 x i64> [[A_MASK]] to <2 x i65> ; CHECK-NEXT: ret <2 x i65> [[B]] ; %a = trunc <2 x i64> %t to <2 x i32> diff --git a/llvm/test/Transforms/InstCombine/vector-casts.ll b/llvm/test/Transforms/InstCombine/vector-casts.ll --- a/llvm/test/Transforms/InstCombine/vector-casts.ll +++ b/llvm/test/Transforms/InstCombine/vector-casts.ll @@ -53,8 +53,8 @@ define <2 x i64> @test2(<2 x i64> %a) { ; CHECK-LABEL: @test2( ; CHECK-NEXT: [[B:%.*]] = lshr <2 x i64> [[A:%.*]], -; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i64> [[B]], -; CHECK-NEXT: ret <2 x i64> [[TMP1]] +; CHECK-NEXT: [[T:%.*]] = and <2 x i64> [[B]], +; CHECK-NEXT: ret <2 x i64> [[T]] ; %b = and <2 x i64> %a, %t = ashr <2 x i64> %b, @@ -63,8 +63,8 @@ define <2 x i64> @test3(<4 x float> %a, <4 x float> %b) { ; CHECK-LABEL: @test3( -; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord <4 x float> [[A:%.*]], [[B:%.*]] -; CHECK-NEXT: [[AND:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i32> +; CHECK-NEXT: [[AND1:%.*]] = fcmp ord <4 x float> [[A:%.*]], [[B:%.*]] +; CHECK-NEXT: [[AND:%.*]] = sext <4 x i1> [[AND1]] to <4 x i32> ; CHECK-NEXT: [[CONV:%.*]] = bitcast <4 x i32> [[AND]] to <2 x i64> ; CHECK-NEXT: ret <2 x i64> [[CONV]] ; @@ -79,8 +79,8 @@ define <2 x i64> @test4(<4 x float> %a, <4 x float> %b) { ; CHECK-LABEL: @test4( -; CHECK-NEXT: [[TMP1:%.*]] = fcmp uno <4 x float> [[A:%.*]], [[B:%.*]] -; CHECK-NEXT: [[OR:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i32> +; CHECK-NEXT: [[OR1:%.*]] = fcmp uno <4 x float> [[A:%.*]], [[B:%.*]] +; CHECK-NEXT: [[OR:%.*]] = sext <4 x i1> [[OR1]] to <4 x i32> ; CHECK-NEXT: [[CONV:%.*]] = bitcast <4 x i32> [[OR]] to <2 x i64> ; CHECK-NEXT: ret <2 x i64> [[CONV]] ; @@ -164,7 +164,7 @@ define <2 x i65> @foo(<2 x i64> %t) { ; CHECK-LABEL: @foo( ; CHECK-NEXT: [[A_MASK:%.*]] = and <2 x i64> [[T:%.*]], -; CHECK-NEXT: [[B:%.*]] = zext <2 x i64> [[A_MASK]] to <2 x i65> +; CHECK-NEXT: [[B:%.*]] = zext nneg <2 x i64> [[A_MASK]] to <2 x i65> ; CHECK-NEXT: ret <2 x i65> [[B]] ; %a = trunc <2 x i64> %t to <2 x i32> diff --git a/llvm/test/Transforms/InstCombine/wcslen-1.ll b/llvm/test/Transforms/InstCombine/wcslen-1.ll --- a/llvm/test/Transforms/InstCombine/wcslen-1.ll +++ b/llvm/test/Transforms/InstCombine/wcslen-1.ll @@ -96,8 +96,8 @@ define i64 @test_simplify9(i1 %x) { ; CHECK-LABEL: @test_simplify9( -; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[X:%.*]], i64 5, i64 6 -; CHECK-NEXT: ret i64 [[TMP1]] +; CHECK-NEXT: [[L:%.*]] = select i1 [[X:%.*]], i64 5, i64 6 +; CHECK-NEXT: ret i64 [[L]] ; %s = select i1 %x, ptr @hello, ptr @longer %l = call i64 @wcslen(ptr %s) @@ -110,8 +110,8 @@ define i64 @test_simplify10(i32 %x) { ; CHECK-LABEL: @test_simplify10( ; CHECK-NEXT: [[TMP1:%.*]] = sext i32 [[X:%.*]] to i64 -; CHECK-NEXT: [[TMP2:%.*]] = sub nsw i64 5, [[TMP1]] -; CHECK-NEXT: ret i64 [[TMP2]] +; CHECK-NEXT: [[HELLO_L:%.*]] = sub nsw i64 5, [[TMP1]] +; CHECK-NEXT: ret i64 [[HELLO_L]] ; %hello_p = getelementptr inbounds [6 x i32], ptr @hello, i32 0, i32 %x %hello_l = call i64 @wcslen(ptr %hello_p) @@ -124,8 +124,8 @@ ; CHECK-LABEL: @test_simplify11( ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 7 ; CHECK-NEXT: [[NARROW:%.*]] = sub nuw nsw i32 9, [[AND]] -; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[NARROW]] to i64 -; CHECK-NEXT: ret i64 [[TMP1]] +; CHECK-NEXT: [[HELLO_L:%.*]] = zext nneg i32 [[NARROW]] to i64 +; CHECK-NEXT: ret i64 [[HELLO_L]] ; %and = and i32 %x, 7 %hello_p = getelementptr inbounds [13 x i32], ptr @null_hello_mid, i32 0, i32 %and @@ -175,7 +175,7 @@ define i64 @test_no_simplify3(i32 %x) { ; CHECK-LABEL: @test_no_simplify3( ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 15 -; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[AND]] to i64 +; CHECK-NEXT: [[TMP1:%.*]] = zext nneg i32 [[AND]] to i64 ; CHECK-NEXT: [[HELLO_P:%.*]] = getelementptr inbounds [13 x i32], ptr @null_hello_mid, i64 0, i64 [[TMP1]] ; CHECK-NEXT: [[HELLO_L:%.*]] = call i64 @wcslen(ptr nonnull [[HELLO_P]]) ; CHECK-NEXT: ret i64 [[HELLO_L]] @@ -189,7 +189,7 @@ define i64 @test_no_simplify3_no_null_opt(i32 %x) #0 { ; CHECK-LABEL: @test_no_simplify3_no_null_opt( ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 15 -; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[AND]] to i64 +; CHECK-NEXT: [[TMP1:%.*]] = zext nneg i32 [[AND]] to i64 ; CHECK-NEXT: [[HELLO_P:%.*]] = getelementptr inbounds [13 x i32], ptr @null_hello_mid, i64 0, i64 [[TMP1]] ; CHECK-NEXT: [[HELLO_L:%.*]] = call i64 @wcslen(ptr [[HELLO_P]]) ; CHECK-NEXT: ret i64 [[HELLO_L]] @@ -231,8 +231,8 @@ ; with an offset that isn't a multiple of the element size). define i64 @no_fold_wcslen_1() { ; CHECK-LABEL: @no_fold_wcslen_1( -; CHECK-NEXT: %len = tail call i64 @wcslen(ptr nonnull getelementptr inbounds ([15 x i8], ptr @ws, i64 0, i64 3)) -; CHECK-NEXT: ret i64 %len +; CHECK-NEXT: [[LEN:%.*]] = tail call i64 @wcslen(ptr nonnull getelementptr inbounds ([15 x i8], ptr @ws, i64 0, i64 3)) +; CHECK-NEXT: ret i64 [[LEN]] ; %p = getelementptr [15 x i8], ptr @ws, i64 0, i64 3 %len = tail call i64 @wcslen(ptr %p) @@ -246,8 +246,8 @@ ; with an offset that isn't a multiple of the element size). define i64 @no_fold_wcslen_2() { ; CHECK-LABEL: @no_fold_wcslen_2( -; CHECK-NEXT: %len = tail call i64 @wcslen(ptr nonnull getelementptr inbounds ([10 x i8], ptr @s8, i64 0, i64 3)) -; CHECK-NEXT: ret i64 %len +; CHECK-NEXT: [[LEN:%.*]] = tail call i64 @wcslen(ptr nonnull getelementptr inbounds ([10 x i8], ptr @s8, i64 0, i64 3)) +; CHECK-NEXT: ret i64 [[LEN]] ; %p = getelementptr [10 x i8], ptr @s8, i64 0, i64 3 %len = tail call i64 @wcslen(ptr %p) diff --git a/llvm/test/Transforms/InstCombine/wcslen-3.ll b/llvm/test/Transforms/InstCombine/wcslen-3.ll --- a/llvm/test/Transforms/InstCombine/wcslen-3.ll +++ b/llvm/test/Transforms/InstCombine/wcslen-3.ll @@ -97,8 +97,8 @@ define i64 @test_simplify9(i1 %x) { ; CHECK-LABEL: @test_simplify9( -; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[X:%.*]], i64 5, i64 6 -; CHECK-NEXT: ret i64 [[TMP1]] +; CHECK-NEXT: [[L:%.*]] = select i1 [[X:%.*]], i64 5, i64 6 +; CHECK-NEXT: ret i64 [[L]] ; %s = select i1 %x, ptr @hello, ptr @longer %l = call i64 @wcslen(ptr %s) @@ -111,8 +111,8 @@ define i64 @test_simplify10(i16 %x) { ; CHECK-LABEL: @test_simplify10( ; CHECK-NEXT: [[TMP1:%.*]] = sext i16 [[X:%.*]] to i64 -; CHECK-NEXT: [[TMP2:%.*]] = sub nsw i64 5, [[TMP1]] -; CHECK-NEXT: ret i64 [[TMP2]] +; CHECK-NEXT: [[HELLO_L:%.*]] = sub nsw i64 5, [[TMP1]] +; CHECK-NEXT: ret i64 [[HELLO_L]] ; %hello_p = getelementptr inbounds [6 x i16], ptr @hello, i16 0, i16 %x %hello_l = call i64 @wcslen(ptr %hello_p) @@ -125,8 +125,8 @@ ; CHECK-LABEL: @test_simplify11( ; CHECK-NEXT: [[AND:%.*]] = and i16 [[X:%.*]], 7 ; CHECK-NEXT: [[NARROW:%.*]] = sub nuw nsw i16 9, [[AND]] -; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[NARROW]] to i64 -; CHECK-NEXT: ret i64 [[TMP1]] +; CHECK-NEXT: [[HELLO_L:%.*]] = zext nneg i16 [[NARROW]] to i64 +; CHECK-NEXT: ret i64 [[HELLO_L]] ; %and = and i16 %x, 7 %hello_p = getelementptr inbounds [13 x i16], ptr @null_hello_mid, i16 0, i16 %and @@ -164,7 +164,7 @@ define i64 @test_no_simplify3(i16 %x) { ; CHECK-LABEL: @test_no_simplify3( ; CHECK-NEXT: [[AND:%.*]] = and i16 [[X:%.*]], 15 -; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[AND]] to i64 +; CHECK-NEXT: [[TMP1:%.*]] = zext nneg i16 [[AND]] to i64 ; CHECK-NEXT: [[HELLO_P:%.*]] = getelementptr inbounds [13 x i16], ptr @null_hello_mid, i64 0, i64 [[TMP1]] ; CHECK-NEXT: [[HELLO_L:%.*]] = call i64 @wcslen(ptr nonnull [[HELLO_P]]) ; CHECK-NEXT: ret i64 [[HELLO_L]] diff --git a/llvm/test/Transforms/InstCombine/zeroext-and-reduce.ll b/llvm/test/Transforms/InstCombine/zeroext-and-reduce.ll --- a/llvm/test/Transforms/InstCombine/zeroext-and-reduce.ll +++ b/llvm/test/Transforms/InstCombine/zeroext-and-reduce.ll @@ -3,8 +3,8 @@ define i32 @test1(i8 %X) { ; CHECK-LABEL: @test1( -; CHECK-NEXT: [[TMP1:%.*]] = and i8 %X, 8 -; CHECK-NEXT: [[Z:%.*]] = zext i8 [[TMP1]] to i32 +; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[X:%.*]], 8 +; CHECK-NEXT: [[Z:%.*]] = zext nneg i8 [[TMP1]] to i32 ; CHECK-NEXT: ret i32 [[Z]] ; %Y = zext i8 %X to i32 diff --git a/llvm/test/Transforms/InstCombine/zext-or-icmp.ll b/llvm/test/Transforms/InstCombine/zext-or-icmp.ll --- a/llvm/test/Transforms/InstCombine/zext-or-icmp.ll +++ b/llvm/test/Transforms/InstCombine/zext-or-icmp.ll @@ -123,8 +123,8 @@ define i32 @zext_or_eq_ult_add(i32 %i) { ; CHECK-LABEL: @zext_or_eq_ult_add( ; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[I:%.*]], -3 -; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], 3 -; CHECK-NEXT: [[R:%.*]] = zext i1 [[TMP2]] to i32 +; CHECK-NEXT: [[O:%.*]] = icmp ult i32 [[TMP1]], 3 +; CHECK-NEXT: [[R:%.*]] = zext i1 [[O]] to i32 ; CHECK-NEXT: ret i32 [[R]] ; %a = add i32 %i, -3 @@ -138,8 +138,8 @@ define i32 @select_zext_or_eq_ult_add(i32 %i) { ; CHECK-LABEL: @select_zext_or_eq_ult_add( ; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[I:%.*]], -3 -; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], 3 -; CHECK-NEXT: [[R:%.*]] = zext i1 [[TMP2]] to i32 +; CHECK-NEXT: [[NARROW:%.*]] = icmp ult i32 [[TMP1]], 3 +; CHECK-NEXT: [[R:%.*]] = zext i1 [[NARROW]] to i32 ; CHECK-NEXT: ret i32 [[R]] ; %a = add i32 %i, -3 @@ -179,7 +179,7 @@ ; CHECK-NEXT: [[EXT:%.*]] = zext i1 [[T1]] to i32 ; CHECK-NEXT: [[AND:%.*]] = and i32 [[EXT]], [[T0]] ; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[AND]], 140 -; CHECK-NEXT: [[XOR1:%.*]] = zext i32 [[TMP1]] to i64 +; CHECK-NEXT: [[XOR1:%.*]] = zext nneg i32 [[TMP1]] to i64 ; CHECK-NEXT: [[CONV16:%.*]] = sext i8 [[I162:%.*]] to i64 ; CHECK-NEXT: [[SUB17:%.*]] = sub i64 [[CONV16]], [[E:%.*]] ; CHECK-NEXT: [[SEXT:%.*]] = shl i64 [[SUB17]], 32 @@ -247,7 +247,7 @@ ; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[T3]], [[CONV17]] ; CHECK-NEXT: store i32 [[ADD]], ptr [[F]], align 4 ; CHECK-NEXT: [[REM18:%.*]] = srem i32 [[LOR_EXT]], [[ADD]] -; CHECK-NEXT: [[CONV19:%.*]] = zext i32 [[REM18]] to i64 +; CHECK-NEXT: [[CONV19:%.*]] = zext nneg i32 [[REM18]] to i64 ; CHECK-NEXT: store i32 0, ptr [[D]], align 8 ; CHECK-NEXT: [[R:%.*]] = icmp ult i64 [[INSERT_INSERT41]], [[CONV19]] ; CHECK-NEXT: call void @llvm.assume(i1 [[R]]) diff --git a/llvm/test/Transforms/LoopVectorize/induction.ll b/llvm/test/Transforms/LoopVectorize/induction.ll --- a/llvm/test/Transforms/LoopVectorize/induction.ll +++ b/llvm/test/Transforms/LoopVectorize/induction.ll @@ -2095,7 +2095,7 @@ ; IND: for.body: ; IND-NEXT: [[I:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[I_NEXT:%.*]], [[IF_END:%.*]] ] ; IND-NEXT: [[SUM:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[VAR4:%.*]], [[IF_END]] ] -; IND-NEXT: [[TMP16:%.*]] = zext i32 [[I]] to i64 +; IND-NEXT: [[TMP16:%.*]] = zext nneg i32 [[I]] to i64 ; IND-NEXT: [[VAR0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP16]] ; IND-NEXT: [[VAR1:%.*]] = load i32, ptr [[VAR0]], align 4 ; IND-NEXT: br i1 [[C]], label [[IF_THEN:%.*]], label [[IF_END]] @@ -2189,7 +2189,7 @@ ; UNROLL: for.body: ; UNROLL-NEXT: [[I:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[I_NEXT:%.*]], [[IF_END:%.*]] ] ; UNROLL-NEXT: [[SUM:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[VAR4:%.*]], [[IF_END]] ] -; UNROLL-NEXT: [[TMP30:%.*]] = zext i32 [[I]] to i64 +; UNROLL-NEXT: [[TMP30:%.*]] = zext nneg i32 [[I]] to i64 ; UNROLL-NEXT: [[VAR0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP30]] ; UNROLL-NEXT: [[VAR1:%.*]] = load i32, ptr [[VAR0]], align 4 ; UNROLL-NEXT: br i1 [[C]], label [[IF_THEN:%.*]], label [[IF_END]] @@ -2419,7 +2419,7 @@ ; INTERLEAVE: for.body: ; INTERLEAVE-NEXT: [[I:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[I_NEXT:%.*]], [[IF_END:%.*]] ] ; INTERLEAVE-NEXT: [[SUM:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[VAR4:%.*]], [[IF_END]] ] -; INTERLEAVE-NEXT: [[TMP50:%.*]] = zext i32 [[I]] to i64 +; INTERLEAVE-NEXT: [[TMP50:%.*]] = zext nneg i32 [[I]] to i64 ; INTERLEAVE-NEXT: [[VAR0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP50]] ; INTERLEAVE-NEXT: [[VAR1:%.*]] = load i32, ptr [[VAR0]], align 4 ; INTERLEAVE-NEXT: br i1 [[C]], label [[IF_THEN:%.*]], label [[IF_END]] diff --git a/llvm/test/Transforms/LoopVectorize/reduction-inloop.ll b/llvm/test/Transforms/LoopVectorize/reduction-inloop.ll --- a/llvm/test/Transforms/LoopVectorize/reduction-inloop.ll +++ b/llvm/test/Transforms/LoopVectorize/reduction-inloop.ll @@ -24,7 +24,7 @@ ; CHECK: scalar.ph: ; CHECK-NEXT: br label [[DOTLR_PH:%.*]] ; CHECK: .lr.ph: -; CHECK-NEXT: br i1 poison, label [[DOT_CRIT_EDGE]], label [[DOTLR_PH]], !llvm.loop [[LOOP2:![0-9]+]] +; CHECK-NEXT: br i1 poison, label [[DOT_CRIT_EDGE]], label [[DOTLR_PH]], !llvm.loop [[LOOP3:![0-9]+]] ; CHECK: ._crit_edge: ; CHECK-NEXT: [[SUM_0_LCSSA:%.*]] = phi i32 [ poison, [[DOTLR_PH]] ], [ [[TMP2]], [[MIDDLE_BLOCK]] ] ; CHECK-NEXT: ret i32 [[SUM_0_LCSSA]] @@ -1143,7 +1143,7 @@ ; CHECK-NEXT: [[TMP3:%.*]] = shl nuw nsw <4 x i8> [[TMP2]], ; CHECK-NEXT: [[TMP4:%.*]] = udiv <4 x i8> [[TMP3]], ; CHECK-NEXT: [[NARROW:%.*]] = select <4 x i1> [[DOTNOT]], <4 x i8> zeroinitializer, <4 x i8> [[TMP4]] -; CHECK-NEXT: [[TMP5:%.*]] = zext <4 x i8> [[NARROW]] to <4 x i32> +; CHECK-NEXT: [[TMP5:%.*]] = zext nneg <4 x i8> [[NARROW]] to <4 x i32> ; CHECK-NEXT: [[TMP6:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP5]]) ; CHECK-NEXT: [[TMP7]] = add i32 [[TMP6]], [[VEC_PHI]] ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4 @@ -1168,7 +1168,7 @@ ; CHECK-NEXT: [[TMP11:%.*]] = udiv i8 [[TMP10]], 31 ; CHECK-NEXT: [[TMP12:%.*]] = shl nuw nsw i8 [[TMP11]], 3 ; CHECK-NEXT: [[TMP13:%.*]] = udiv i8 [[TMP12]], 31 -; CHECK-NEXT: [[DIV4:%.*]] = zext i8 [[TMP13]] to i32 +; CHECK-NEXT: [[DIV4:%.*]] = zext nneg i8 [[TMP13]] to i32 ; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[G_016]], [[DIV4]] ; CHECK-NEXT: br label [[FOR_INC5]] ; CHECK: for.inc5: @@ -1228,7 +1228,7 @@ ; CHECK-NEXT: [[TMP2:%.*]] = udiv <4 x i8> [[WIDE_LOAD]], ; CHECK-NEXT: [[TMP3:%.*]] = shl nuw nsw <4 x i8> [[TMP2]], ; CHECK-NEXT: [[TMP4:%.*]] = udiv <4 x i8> [[TMP3]], -; CHECK-NEXT: [[TMP5:%.*]] = zext <4 x i8> [[TMP4]] to <4 x i32> +; CHECK-NEXT: [[TMP5:%.*]] = zext nneg <4 x i8> [[TMP4]] to <4 x i32> ; CHECK-NEXT: [[TMP6:%.*]] = select <4 x i1> [[DOTNOT]], <4 x i32> zeroinitializer, <4 x i32> [[TMP5]] ; CHECK-NEXT: [[TMP7:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP6]]) ; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP7]], [[VEC_PHI]] @@ -1258,7 +1258,7 @@ ; CHECK-NEXT: [[TMP16:%.*]] = shl nuw nsw i8 [[TMP15]], 3 ; CHECK-NEXT: [[TMP17:%.*]] = udiv i8 [[TMP16]], 31 ; CHECK-NEXT: [[TMP18:%.*]] = shl nuw nsw i8 [[TMP17]], 1 -; CHECK-NEXT: [[REASS_ADD:%.*]] = zext i8 [[TMP18]] to i32 +; CHECK-NEXT: [[REASS_ADD:%.*]] = zext nneg i8 [[TMP18]] to i32 ; CHECK-NEXT: [[ADD:%.*]] = add i32 [[G_016]], [[REASS_ADD]] ; CHECK-NEXT: br label [[FOR_INC5]] ; CHECK: for.inc5: @@ -1377,7 +1377,7 @@ ; CHECK-NEXT: [[TMP47:%.*]] = or <4 x i1> [[TMP45]], [[TMP46]] ; CHECK-NEXT: [[TMP48:%.*]] = bitcast <4 x i1> [[TMP47]] to i4 ; CHECK-NEXT: [[TMP49:%.*]] = call i4 @llvm.ctpop.i4(i4 [[TMP48]]), !range [[RNG46:![0-9]+]] -; CHECK-NEXT: [[TMP50:%.*]] = zext i4 [[TMP49]] to i32 +; CHECK-NEXT: [[TMP50:%.*]] = zext nneg i4 [[TMP49]] to i32 ; CHECK-NEXT: [[TMP51]] = add i32 [[VEC_PHI]], [[TMP50]] ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4 ; CHECK-NEXT: [[TMP52:%.*]] = icmp eq i32 [[INDEX_NEXT]], 1000 diff --git a/llvm/test/Transforms/PhaseOrdering/lto-licm.ll b/llvm/test/Transforms/PhaseOrdering/lto-licm.ll --- a/llvm/test/Transforms/PhaseOrdering/lto-licm.ll +++ b/llvm/test/Transforms/PhaseOrdering/lto-licm.ll @@ -10,7 +10,7 @@ ; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[I_0]], 1024 ; CHECK-NEXT: br i1 [[CMP_NOT]], label [[FOR_END:%.*]], label [[FOR_INC]] ; CHECK: for.inc: -; CHECK-NEXT: [[IDXPROM:%.*]] = zext i32 [[I_0]] to i64 +; CHECK-NEXT: [[IDXPROM:%.*]] = zext nneg i32 [[I_0]] to i64 ; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[A:%.*]], i64 [[IDXPROM]] ; CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[ARRAYIDX]], align 4 ; CHECK-NEXT: [[TMP1:%.*]] = fdiv fast float [[TMP0]], [[B:%.*]] diff --git a/llvm/test/Transforms/SCCP/ip-ranges-casts.ll b/llvm/test/Transforms/SCCP/ip-ranges-casts.ll --- a/llvm/test/Transforms/SCCP/ip-ranges-casts.ll +++ b/llvm/test/Transforms/SCCP/ip-ranges-casts.ll @@ -112,7 +112,7 @@ ; x = [100, 301) define internal i1 @f.sext(i32 %x, i32 %y) { ; CHECK-LABEL: @f.sext( -; CHECK-NEXT: [[T_1:%.*]] = zext i32 [[X:%.*]] to i64 +; CHECK-NEXT: [[T_1:%.*]] = zext nneg i32 [[X:%.*]] to i64 ; CHECK-NEXT: [[C_2:%.*]] = icmp sgt i64 [[T_1]], 299 ; CHECK-NEXT: [[C_4:%.*]] = icmp slt i64 [[T_1]], 101 ; CHECK-NEXT: [[RES_1:%.*]] = add i1 false, [[C_2]] @@ -318,7 +318,7 @@ define internal i64 @f.sext_to_zext(i32 %t) { ; CHECK-LABEL: @f.sext_to_zext( -; CHECK-NEXT: [[A:%.*]] = zext i32 [[T:%.*]] to i64 +; CHECK-NEXT: [[A:%.*]] = zext nneg i32 [[T:%.*]] to i64 ; CHECK-NEXT: ret i64 [[A]] ; %a = sext i32 %t to i64 diff --git a/llvm/test/Transforms/SCCP/ip-ranges-sext.ll b/llvm/test/Transforms/SCCP/ip-ranges-sext.ll --- a/llvm/test/Transforms/SCCP/ip-ranges-sext.ll +++ b/llvm/test/Transforms/SCCP/ip-ranges-sext.ll @@ -6,7 +6,7 @@ ; CHECK-NEXT: [[C:%.*]] = icmp sgt i32 [[X:%.*]], 0 ; CHECK-NEXT: br i1 [[C]], label [[TRUE:%.*]], label [[FALSE:%.*]] ; CHECK: true: -; CHECK-NEXT: [[EXT_1:%.*]] = zext i32 [[X]] to i64 +; CHECK-NEXT: [[EXT_1:%.*]] = zext nneg i32 [[X]] to i64 ; CHECK-NEXT: ret i64 [[EXT_1]] ; CHECK: false: ; CHECK-NEXT: [[EXT_2:%.*]] = sext i32 [[X]] to i64 @@ -29,7 +29,7 @@ ; CHECK-NEXT: [[C:%.*]] = icmp sge i32 [[X:%.*]], 0 ; CHECK-NEXT: br i1 [[C]], label [[TRUE:%.*]], label [[FALSE:%.*]] ; CHECK: true: -; CHECK-NEXT: [[EXT_1:%.*]] = zext i32 [[X]] to i64 +; CHECK-NEXT: [[EXT_1:%.*]] = zext nneg i32 [[X]] to i64 ; CHECK-NEXT: ret i64 [[EXT_1]] ; CHECK: false: ; CHECK-NEXT: [[EXT_2:%.*]] = sext i32 [[X]] to i64 @@ -105,7 +105,7 @@ define i64 @test5(i32 %x) { ; CHECK-LABEL: @test5( ; CHECK-NEXT: [[P:%.*]] = and i32 [[X:%.*]], 15 -; CHECK-NEXT: [[EXT:%.*]] = zext i32 [[P]] to i64 +; CHECK-NEXT: [[EXT:%.*]] = zext nneg i32 [[P]] to i64 ; CHECK-NEXT: ret i64 [[EXT]] ; %p = and i32 %x, 15 @@ -126,7 +126,7 @@ define i64 @test7(i16 %x) { ; CHECK-LABEL: @test7( ; CHECK-NEXT: [[P:%.*]] = and i16 [[X:%.*]], 15 -; CHECK-NEXT: [[EXT_1:%.*]] = zext i16 [[P]] to i32 +; CHECK-NEXT: [[EXT_1:%.*]] = zext nneg i16 [[P]] to i32 ; CHECK-NEXT: [[EXT_2:%.*]] = sext i32 [[EXT_1]] to i64 ; CHECK-NEXT: ret i64 [[EXT_2]] ; diff --git a/llvm/test/Transforms/SCCP/ranges-sext.ll b/llvm/test/Transforms/SCCP/ranges-sext.ll --- a/llvm/test/Transforms/SCCP/ranges-sext.ll +++ b/llvm/test/Transforms/SCCP/ranges-sext.ll @@ -68,8 +68,8 @@ define i64 @test2(i32 %x) { ; CHECK-LABEL: @test2( ; CHECK-NEXT: [[P:%.*]] = and i32 [[X:%.*]], 15 -; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[P]] to i64 -; CHECK-NEXT: ret i64 [[TMP1]] +; CHECK-NEXT: [[EXT:%.*]] = zext nneg i32 [[P]] to i64 +; CHECK-NEXT: ret i64 [[EXT]] ; %p = and i32 %x, 15 %ext = sext i32 %p to i64 @@ -87,8 +87,8 @@ ; CHECK-NEXT: br label [[EXIT]] ; CHECK: exit: ; CHECK-NEXT: [[P:%.*]] = phi i32 [ 0, [[TRUE_1]] ], [ 1, [[TRUE_2]] ], [ 3, [[FALSE]] ] -; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[P]] to i64 -; CHECK-NEXT: ret i64 [[TMP1]] +; CHECK-NEXT: [[EXT:%.*]] = zext nneg i32 [[P]] to i64 +; CHECK-NEXT: ret i64 [[EXT]] ; br i1 %c.1, label %true.1, label %false diff --git a/llvm/test/Transforms/SCCP/widening.ll b/llvm/test/Transforms/SCCP/widening.ll --- a/llvm/test/Transforms/SCCP/widening.ll +++ b/llvm/test/Transforms/SCCP/widening.ll @@ -450,7 +450,7 @@ ; SCCP-NEXT: [[TMP7:%.*]] = sub i64 3, [[TMP6]] ; SCCP-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 1 ; SCCP-NEXT: [[TMP9:%.*]] = trunc i64 [[TMP8]] to i32 -; SCCP-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +; SCCP-NEXT: [[TMP10:%.*]] = zext nneg i32 [[TMP9]] to i64 ; SCCP-NEXT: br label [[BB11:%.*]] ; SCCP: bb11: ; SCCP-NEXT: [[TMP12:%.*]] = phi i64 [ [[TMP10]], [[BB4]] ], [ [[TMP17:%.*]], [[BB18:%.*]] ] @@ -487,7 +487,7 @@ ; IPSCCP-NEXT: [[TMP7:%.*]] = sub i64 3, [[TMP6]] ; IPSCCP-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 1 ; IPSCCP-NEXT: [[TMP9:%.*]] = trunc i64 [[TMP8]] to i32 -; IPSCCP-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +; IPSCCP-NEXT: [[TMP10:%.*]] = zext nneg i32 [[TMP9]] to i64 ; IPSCCP-NEXT: br label [[BB11:%.*]] ; IPSCCP: bb11: ; IPSCCP-NEXT: [[TMP12:%.*]] = phi i64 [ [[TMP10]], [[BB4]] ], [ [[TMP17:%.*]], [[BB18:%.*]] ]