diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -79,6 +79,7 @@
 unsigned AArch64InstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
   const MachineBasicBlock &MBB = *MI.getParent();
   const MachineFunction *MF = MBB.getParent();
+  const Function &F = MF->getFunction();
   const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
 
   {
@@ -127,10 +128,17 @@
       NumBytes = 4;
     break;
   case TargetOpcode::PATCHABLE_FUNCTION_ENTER:
+    NumBytes =
+        F.getFnAttributeAsParsedInteger("patchable-function-entry", 9) * 4;
+    break;
   case TargetOpcode::PATCHABLE_FUNCTION_EXIT:
+  case TargetOpcode::PATCHABLE_TYPED_EVENT_CALL:
     // An XRay sled can be 4 bytes of alignment plus a 32-byte block.
     NumBytes = 36;
     break;
+  case TargetOpcode::PATCHABLE_EVENT_CALL:
+    NumBytes = 24;
+    break;
 
   case AArch64::SPACE:
     NumBytes = MI.getOperand(1).getImm();
diff --git a/llvm/test/CodeGen/AArch64/branch-relax-xray.ll b/llvm/test/CodeGen/AArch64/branch-relax-xray.ll
--- a/llvm/test/CodeGen/AArch64/branch-relax-xray.ll
+++ b/llvm/test/CodeGen/AArch64/branch-relax-xray.ll
@@ -39,4 +39,19 @@
 }
 
 declare i32 @bar()
-declare i32 @baz()
\ No newline at end of file
+declare i32 @baz()
+
+;; Construct call site entries for PATCHABLE_EVENT_CALL.
+; DBG:      DW_TAG_subprogram
+; DBG:      DW_AT_name
+; DBG-SAME:            ("customevent")
+; DBG:        DW_TAG_call_site
+; DBG-NEXT:     DW_AT_call_target (DW_OP_reg0 {{.*}})
+; DBG-NEXT:     DW_AT_call_return_pc
+; DBG-EMPTY:
+; DBG:        DW_TAG_call_site
+; DBG-NEXT:     DW_AT_call_target (DW_OP_reg2 {{.*}})
+; DBG-NEXT:     DW_AT_call_return_pc
+
+declare void @llvm.xray.customevent(ptr, i64)
+declare void @llvm.xray.typedevent(i64, ptr, i64)