Index: lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
===================================================================
--- lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+++ lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
@@ -130,14 +130,13 @@
   if (ShaderType == ShaderType::COMPUTE)
     return true;
 
-  // For non-compute shaders, the inreg attribute is used to mark inputs,
-  // which pre-loaded into SGPRs.
-  if (F->getAttributes().hasAttribute(A->getArgNo(), Attribute::InReg))
+  // For non-compute shaders, SGPR inputs are marekd with either inreg or byval.
+  if (F->getAttributes().hasAttribute(A->getArgNo() + 1, Attribute::InReg) ||
+      F->getAttributes().hasAttribute(A->getArgNo() + 1, Attribute::ByVal))
     return true;
 
-  // For non-compute shaders, 32-bit values are pre-loaded into vgprs, all
-  // other value types use SGPRS.
-  return !A->getType()->isIntegerTy(32) && !A->getType()->isFloatTy();
+  // Everything else is in VGPRs.
+  return false;
 }
 
 ///
Index: test/Analysis/DivergenceAnalysis/AMDGPU/kernel-args.ll
===================================================================
--- /dev/null
+++ test/Analysis/DivergenceAnalysis/AMDGPU/kernel-args.ll
@@ -0,0 +1,18 @@
+; RUN: opt %s -analyze -divergence | FileCheck %s
+
+target triple = "amdgcn--"
+
+; CHECK: DIVERGENT:
+; CHECK-NOT: %arg0
+; CHECK-NOT: %arg1
+; CHECK-NOT; %arg2
+; CHECK: <2 x i32> %arg3
+; CHECK: DIVERGENT:  <3 x i32> %arg4
+; CHECK: DIVERGENT:  float %arg5
+; CHECK: DIVERGENT:  i32 %arg6
+
+define void @main([4 x <16 x i8>] addrspace(2)* byval %arg0, float inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <3 x i32> %arg4, float %arg5, i32 %arg6) #0 {
+  ret void
+}
+
+attributes #0 = { "ShaderType"="0" }
Index: test/Analysis/DivergenceAnalysis/AMDGPU/lit.local.cfg
===================================================================
--- /dev/null
+++ test/Analysis/DivergenceAnalysis/AMDGPU/lit.local.cfg
@@ -0,0 +1,2 @@
+if not 'NVPTX' in config.root.targets:
+    config.unsupported = True