Index: llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
===================================================================
--- llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+++ llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
@@ -460,8 +460,8 @@
   setBF16OperationAction(ISD::SETCC, MVT::bf16, Legal, Promote);
   setBF16OperationAction(ISD::SETCC, MVT::v2bf16, Legal, Expand);
   // Operations not directly supported by NVPTX.
-  for (MVT VT : {MVT::f16, MVT::v2f16, MVT::f32, MVT::f64, MVT::i1, MVT::i8,
-                 MVT::i16, MVT::i32, MVT::i64}) {
+  for (MVT VT : {MVT::bf16, MVT::f16, MVT::v2bf16, MVT::v2f16, MVT::f32,
+                 MVT::f64, MVT::i1, MVT::i8, MVT::i16, MVT::i32, MVT::i64}) {
     setOperationAction(ISD::SELECT_CC, VT, Expand);
     setOperationAction(ISD::BR_CC, VT, Expand);
   }
Index: llvm/test/CodeGen/NVPTX/bf16-instructions.ll
===================================================================
--- llvm/test/CodeGen/NVPTX/bf16-instructions.ll
+++ llvm/test/CodeGen/NVPTX/bf16-instructions.ll
@@ -192,3 +192,18 @@
   %r = fadd bfloat %a, 1.0
   ret bfloat %r
 }
+
+; CHECK-LABEL: test_select_cc_bf16_f64(
+; CHECK-DAG:      ld.param.f64    [[A:%fd[0-9]+]], [test_select_cc_bf16_f64_param_0];
+; CHECK-DAG:      ld.param.f64    [[B:%fd[0-9]+]], [test_select_cc_bf16_f64_param_1];
+; CHECK:          setp.lt.f64     [[P:%p[0-9]+]], [[A]], [[B]];
+; CHECK-DAG:      ld.param.b16    [[C:%rs[0-9]+]], [test_select_cc_bf16_f64_param_2];
+; CHECK-DAG:      ld.param.b16    [[D:%rs[0-9]+]], [test_select_cc_bf16_f64_param_3];
+; CHECK:          selp.b16        [[R:%rs[0-9]+]], [[C]], [[D]], [[P]];
+; CHECK-NEXT:     st.param.b16    [func_retval0+0], [[R]];
+; CHECK-NEXT:     ret;
+define bfloat @test_select_cc_bf16_f64(double %a, double %b, bfloat %c, bfloat %d) #0 {
+  %cc = fcmp olt double %a, %b
+  %r = select i1 %cc, bfloat %c, bfloat %d
+  ret bfloat %r
+}