diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -1989,6 +1989,45 @@
   }
 }
 
+class SchedBinary<string write, string read0, string read1,
+                  string mx, int sew = 0>: Sched<[]> {
+  defvar Write = !cast<SchedWrite>(!if(sew,
+                                       write # "_" # mx # "_E" # sew,
+                                       write # "_" # mx));
+  defvar Read0 = !cast<SchedRead>(!if(sew,
+                                      read0 # "_" # mx # "_E" # sew,
+                                      read0 # "_" # mx));
+  defvar Read1 = !cast<SchedRead>(!if(sew,
+                                      read1 # "_" # mx # "_E" # sew,
+                                      read1 # "_" # mx));
+  defvar SchedRWList = [Write, Read0, Read1];
+  defvar SchedRWListMasked = [Write, Read0, Read1, ReadVMask];
+  defvar IsMasked = !ne(!find(NAME, "_MASK"), -1);
+  let SchedRW = !if(IsMasked, SchedRWListMasked, SchedRWList);
+}
+
+class SchedBinaryVV<string write, string read0, string read1,
+                    string mx, int sew = 0>:
+                  SchedBinary<write, read0, read1, mx, sew>;
+
+class SchedBinaryVX<string write, string read0, string read1,
+                    string mx, int sew = 0>:
+                  SchedBinary<write, read0, read1, mx, sew>;
+
+class SchedBinaryVI<string write, string read0, 
+                    string mx, int sew = 0>: Sched<[]> {
+  defvar Write = !cast<SchedWrite>(!if(sew,
+                                       write # "_" # mx # "_E" # sew,
+                                       write # "_" # mx));
+  defvar Read0 = !cast<SchedRead>(!if(sew,
+                                      read0 # "_" # mx # "_E" # sew,
+                                      read0 # "_" # mx));
+  defvar SchedRWList = [Write, Read0];
+  defvar SchedRWListMasked = [Write, Read0, ReadVMask];
+  defvar IsMasked = !find(NAME, "_MASK");
+  let SchedRW = !if(IsMasked, SchedRWListMasked, SchedRWList);
+}
+
 multiclass VPseudoBinaryRoundingMode<VReg RetClass,
                                      VReg Op1Class,
                                      DAGOperand Op2Class,
@@ -2098,11 +2137,8 @@
         defvar emul = !cast<LMULInfo>("V_" # emulMX);
         defvar sews = SchedSEWSet<mx>.val;
         foreach e = sews in {
-          defvar WriteVRGatherVV_MX_E = !cast<SchedWrite>("WriteVRGatherVV_" # mx # "_E" # e);
-          defvar ReadVRGatherVV_data_MX_E = !cast<SchedRead>("ReadVRGatherVV_data_" # mx # "_E" # e);
-          defvar ReadVRGatherVV_index_MX_E = !cast<SchedRead>("ReadVRGatherVV_index_" # mx # "_E" # e);
           defm _VV : VPseudoBinaryEmul<m.vrclass, m.vrclass, emul.vrclass, m, emul, Constraint, e>,
-                     Sched<[WriteVRGatherVV_MX_E, ReadVRGatherVV_data_MX_E, ReadVRGatherVV_index_MX_E]>;
+                     SchedBinaryVV<"WriteVRGatherVV", "ReadVRGatherVV_data", "ReadVRGatherVV_index", mx, e>;
         }
       }
     }
@@ -2143,14 +2179,9 @@
 multiclass VPseudoVSLD1_VF<string Constraint = ""> {
   foreach f = FPList in {
     foreach m = f.MxList in {
-      defvar mx = m.MX;
-      defvar WriteVFSlide1F_MX = !cast<SchedWrite>("WriteVFSlide1F_" # mx);
-      defvar ReadVFSlideV_MX = !cast<SchedRead>("ReadVFSlideV_" # mx);
-      defvar ReadVFSlideF_MX = !cast<SchedRead>("ReadVFSlideF_" # mx);
-
       defm "_V" # f.FX :
         VPseudoBinary<m.vrclass, m.vrclass, f.fprclass, m, Constraint>,
-        Sched<[WriteVFSlide1F_MX, ReadVFSlideV_MX, ReadVFSlideF_MX, ReadVMask]>;
+        SchedBinaryVV<"WriteVFSlide1F", "ReadVFSlideV", "ReadVFSlideF", m.MX>;
     }
   }
 }
@@ -2542,26 +2573,17 @@
 multiclass VPseudoVGTR_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
   foreach m = MxList in {
     defvar mx = m.MX;
-    defvar WriteVRGatherVX_MX = !cast<SchedWrite>("WriteVRGatherVX_" # mx);
-    defvar WriteVRGatherVI_MX = !cast<SchedWrite>("WriteVRGatherVI_" # mx);
-    defvar ReadVRGatherVX_data_MX = !cast<SchedRead>("ReadVRGatherVX_data_" # mx);
-    defvar ReadVRGatherVX_index_MX = !cast<SchedRead>("ReadVRGatherVX_index_" # mx);
-    defvar ReadVRGatherVI_data_MX = !cast<SchedRead>("ReadVRGatherVI_data_" # mx);
-
     defm "" : VPseudoBinaryV_VX<m, Constraint>,
-              Sched<[WriteVRGatherVX_MX, ReadVRGatherVX_data_MX,
-                     ReadVRGatherVX_index_MX, ReadVMask]>;
+              SchedBinaryVX<"WriteVRGatherVX", "ReadVRGatherVX_data",
+                            "ReadVRGatherVX_index", mx>;
     defm "" : VPseudoBinaryV_VI<ImmType, m, Constraint>,
-              Sched<[WriteVRGatherVI_MX, ReadVRGatherVI_data_MX, ReadVMask]>;
+              SchedBinaryVI<"WriteVRGatherVI", "ReadVRGatherVI_data", mx>;
 
     defvar sews = SchedSEWSet<mx>.val;
     foreach e = sews in {
-      defvar WriteVRGatherVV_MX_E = !cast<SchedWrite>("WriteVRGatherVV_" # mx # "_E" # e);
-      defvar ReadVRGatherVV_data_MX_E = !cast<SchedRead>("ReadVRGatherVV_data_" # mx # "_E" # e);
-      defvar ReadVRGatherVV_index_MX_E = !cast<SchedRead>("ReadVRGatherVV_index_" # mx # "_E" # e);
       defm "" : VPseudoBinaryV_VV<m, Constraint, e>,
-                Sched<[WriteVRGatherVV_MX_E, ReadVRGatherVV_data_MX_E,
-                       ReadVRGatherVV_index_MX_E, ReadVMask]>;
+                SchedBinaryVV<"WriteVRGatherVV", "ReadVRGatherVV_data",
+                              "ReadVRGatherVV_index", mx, e>;
     }
   }
 }
@@ -2569,18 +2591,12 @@
 multiclass VPseudoVSALU_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
   foreach m = MxList in {
     defvar mx = m.MX;
-    defvar WriteVSALUV_MX = !cast<SchedWrite>("WriteVSALUV_" # mx);
-    defvar WriteVSALUX_MX = !cast<SchedWrite>("WriteVSALUX_" # mx);
-    defvar WriteVSALUI_MX = !cast<SchedWrite>("WriteVSALUI_" # mx);
-    defvar ReadVSALUV_MX = !cast<SchedRead>("ReadVSALUV_" # mx);
-    defvar ReadVSALUX_MX = !cast<SchedRead>("ReadVSALUX_" # mx);
-
     defm "" : VPseudoBinaryV_VV<m, Constraint>,
-              Sched<[WriteVSALUV_MX, ReadVSALUV_MX, ReadVSALUV_MX, ReadVMask]>;
+              SchedBinaryVV<"WriteVSALUV", "ReadVSALUV", "ReadVSALUX", mx>;
     defm "" : VPseudoBinaryV_VX<m, Constraint>,
-              Sched<[WriteVSALUX_MX, ReadVSALUV_MX, ReadVSALUX_MX, ReadVMask]>;
+              SchedBinaryVX<"WriteVSALUX", "ReadVSALUV", "ReadVSALUX", mx>;
     defm "" : VPseudoBinaryV_VI<ImmType, m, Constraint>,
-              Sched<[WriteVSALUI_MX, ReadVSALUV_MX, ReadVMask]>;
+              SchedBinaryVI<"WriteVSALUI", "ReadVSALUV", mx>;
   }
 }