diff --git a/llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp b/llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp --- a/llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp +++ b/llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp @@ -1185,7 +1185,8 @@ return Match_RequiresLAORdDifferRj; break; } - case LoongArch::CSRXCHG: { + case LoongArch::CSRXCHG: + case LoongArch::GCSRXCHG: { unsigned Rj = Inst.getOperand(2).getReg(); if (Rj == LoongArch::R0 || Rj == LoongArch::R1) return Match_RequiresOpnd2NotR0R1; @@ -1347,6 +1348,9 @@ /*Upper=*/(1 << 12) - 1, "operand must be a symbol with modifier (e.g. %abs_lo12) or an " "integer in the range"); + case Match_InvalidUImm14: + return generateImmOutOfRangeError(Operands, ErrorInfo, /*Lower=*/0, + /*Upper=*/(1 << 14) - 1); case Match_InvalidUImm15: return generateImmOutOfRangeError(Operands, ErrorInfo, /*Lower=*/0, /*Upper=*/(1 << 15) - 1); diff --git a/llvm/lib/Target/LoongArch/Disassembler/LoongArchDisassembler.cpp b/llvm/lib/Target/LoongArch/Disassembler/LoongArchDisassembler.cpp --- a/llvm/lib/Target/LoongArch/Disassembler/LoongArchDisassembler.cpp +++ b/llvm/lib/Target/LoongArch/Disassembler/LoongArchDisassembler.cpp @@ -118,6 +118,15 @@ return MCDisassembler::Success; } +static DecodeStatus DecodeSCRRegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const MCDisassembler *Decoder) { + if (RegNo >= 4) + return MCDisassembler::Fail; + Inst.addOperand(MCOperand::createReg(LoongArch::SCR0 + RegNo)); + return MCDisassembler::Success; +} + template static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, diff --git a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td --- a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td +++ b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td @@ -527,6 +527,7 @@ include "LoongArchFloatInstrFormats.td" include "LoongArchLSXInstrFormats.td" include "LoongArchLASXInstrFormats.td" +include "LoongArchLBTInstrFormats.td" //===----------------------------------------------------------------------===// // Instruction Class Templates @@ -2036,3 +2037,13 @@ // LASX Instructions //===----------------------------------------------------------------------===// include "LoongArchLASXInstrInfo.td" + +//===----------------------------------------------------------------------===// +// LVZ Instructions +//===----------------------------------------------------------------------===// +include "LoongArchLVZInstrInfo.td" + +//===----------------------------------------------------------------------===// +// LBT Instructions +//===----------------------------------------------------------------------===// +include "LoongArchLBTInstrInfo.td" diff --git a/llvm/lib/Target/LoongArch/LoongArchLBTInstrFormats.td b/llvm/lib/Target/LoongArch/LoongArchLBTInstrFormats.td new file mode 100644 --- /dev/null +++ b/llvm/lib/Target/LoongArch/LoongArchLBTInstrFormats.td @@ -0,0 +1,250 @@ +// LoongArchLBTInstrFormats.td - LoongArch LBT Instr Formats -*- tablegen -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Describe LoongArch LBT instructions format +// +// opcode - operation code. +// rd/sd - destination register operand. +// rj/rk/sj - source register operand. +// immN/ptr - immediate data operand. +// +//===----------------------------------------------------------------------===// + +// 1R-type (no outs) +// +class NoDstFmt1R op> + : LAInst<(outs), (ins GPR:$rj), + deriveInsnMnemonic.ret, "$rj"> { + bits<5> rj; + + let Inst{31-0} = op; + let Inst{9-5} = rj; +} + +// 1RI3-type (no outs) +// +class NoDstFmt1RI3 op> + : LAInst<(outs), (ins GPR:$rj, uimm3:$imm3), + deriveInsnMnemonic.ret, "$rj, $imm3"> { + bits<3> imm3; + bits<5> rj; + + let Inst{31-0} = op; + let Inst{12-10} = imm3; + let Inst{9-5} = rj; +} + +// 1RI4-type (no outs) +// +class NoDstFmt1RI4 op> + : LAInst<(outs), (ins GPR:$rj, uimm4:$imm4), + deriveInsnMnemonic.ret, "$rj, $imm4"> { + bits<4> imm4; + bits<5> rj; + + let Inst{31-0} = op; + let Inst{13-10} = imm4; + let Inst{9-5} = rj; +} + +// 1RI4-type +// +class Fmt1RI4 op> + : LAInst<(outs GPR:$rd), (ins uimm4:$imm4), + deriveInsnMnemonic.ret, "$rd, $imm4"> { + bits<4> imm4; + bits<5> rd; + + let Inst{31-0} = op; + let Inst{13-10} = imm4; + let Inst{4-0} = rd; +} + +// 1RI5-type (no outs) +// +class NoDstFmt1RI5 op> + : LAInst<(outs), (ins GPR:$rj, uimm5:$imm5), + deriveInsnMnemonic.ret, "$rj, $imm5"> { + bits<5> imm5; + bits<5> rj; + + let Inst{31-0} = op; + let Inst{14-10} = imm5; + let Inst{9-5} = rj; +} + +// 1RI5I4-type (no outs) +// +class NoDstFmt1RI5I4 op> + : LAInst<(outs), (ins GPR:$rj, uimm5:$imm5, uimm4:$imm4), + deriveInsnMnemonic.ret, "$rj, $imm5, $imm4"> { + bits<5> imm5; + bits<5> rj; + bits<4> imm4; + + let Inst{31-0} = op; + let Inst{14-10} = imm5; + let Inst{9-5} = rj; + let Inst{3-0} = imm4; +} + +// 1RI5I8-type +// +class Fmt1RI5I8 op> + : LAInst<(outs GPR:$rd), (ins uimm5:$imm5, uimm8:$imm8), + deriveInsnMnemonic.ret, "$rd, $imm5, $imm8"> { + bits<8> imm8; + bits<5> imm5; + bits<5> rd; + + let Inst{31-0} = op; + let Inst{17-10} = imm8; + let Inst{9-5} = imm5; + let Inst{4-0} = rd; +} + +// 1RI6-type (no outs) +// +class NoDstFmt1RI6 op> + : LAInst<(outs), (ins GPR:$rj, uimm6:$imm6), + deriveInsnMnemonic.ret, "$rj, $imm6"> { + bits<6> imm6; + bits<5> rj; + + let Inst{31-0} = op; + let Inst{15-10} = imm6; + let Inst{9-5} = rj; +} + +// 1RI8-type +// +class Fmt1RI8 op> + : LAInst<(outs GPR:$rd), (ins uimm8:$imm8), + deriveInsnMnemonic.ret, "$rd, $imm8"> { + bits<8> imm8; + bits<5> rd; + + let Inst{31-0} = op; + let Inst{17-10} = imm8; + let Inst{4-0} = rd; +} + +// 2R-type (no outs) +// +class NoDstFmt2R op> + : LAInst<(outs), (ins GPR:$rj, GPR:$rk), + deriveInsnMnemonic.ret, "$rj, $rk"> { + bits<5> rk; + bits<5> rj; + + let Inst{31-0} = op; + let Inst{14-10} = rk; + let Inst{9-5} = rj; +} + +// 2RI4-type (no outs) +// +class NoDstFmt2RI4 op> + : LAInst<(outs), (ins GPR:$rj, GPR:$rk, uimm4:$imm4), + deriveInsnMnemonic.ret, "$rj, $rk, $imm4"> { + bits<4> imm4; + bits<5> rk; + bits<5> rj; + + let Inst{31-0} = op; + let Inst{14-10} = rk; + let Inst{9-5} = rj; + let Inst{3-0} = imm4; +} + +// 2RI3-type +// +class Fmt2RI3 op> + : LAInst<(outs GPR:$rd), (ins GPR:$rj, uimm3:$imm3), + deriveInsnMnemonic.ret, "$rd, $rj, $imm3"> { + bits<3> imm3; + bits<5> rj; + bits<5> rd; + + let Inst{31-0} = op; + let Inst{12-10} = imm3; + let Inst{9-5} = rj; + let Inst{4-0} = rd; +} + +// 2RI4-type +// +class Fmt2RI4 op> + : LAInst<(outs GPR:$rd), (ins GPR:$rj, uimm4:$imm4), + deriveInsnMnemonic.ret, "$rd, $rj, $imm4"> { + bits<4> imm4; + bits<5> rj; + bits<5> rd; + + let Inst{31-0} = op; + let Inst{13-10} = imm4; + let Inst{9-5} = rj; + let Inst{4-0} = rd; +} + +// +class FmtGR2SCR op> + : LAInst<(outs SCR:$sd), (ins GPR:$rj), deriveInsnMnemonic.ret, + "$sd, $rj"> { + bits<5> rj; + bits<2> sd; + + let Inst{31-0} = op; + let Inst{9-5} = rj; + let Inst{1-0} = sd; +} + +// +class FmtSCR2GR op> + : LAInst<(outs GPR:$rd), (ins SCR:$sj), deriveInsnMnemonic.ret, + "$rd, $sj"> { + bits<2> sj; + bits<5> rd; + + let Inst{31-0} = op; + let Inst{6-5} = sj; + let Inst{4-0} = rd; +} + +// +class FmtJISCR op> + : LAInst<(outs), (ins simm21_lsl2:$imm21), deriveInsnMnemonic.ret, + "$imm21"> { + bits<21> imm21; + bits<5> rj; + + let Inst{31-0} = op; + let Inst{25-10} = imm21{15-0}; + let Inst{4-0} = imm21{20-16}; +} + +// +class FmtMFTOP op> + : LAInst<(outs GPR:$rd), (ins), deriveInsnMnemonic.ret, + "$rd"> { + bits<5> rd; + + let Inst{31-0} = op; + let Inst{4-0} = rd; +} + +// +class FmtMTTOP op> + : LAInst<(outs), (ins uimm3:$ptr), deriveInsnMnemonic.ret, + "$ptr"> { + bits<3> ptr; + + let Inst{31-0} = op; + let Inst{7-5} = ptr; +} diff --git a/llvm/lib/Target/LoongArch/LoongArchLBTInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchLBTInstrInfo.td new file mode 100644 --- /dev/null +++ b/llvm/lib/Target/LoongArch/LoongArchLBTInstrInfo.td @@ -0,0 +1,229 @@ +//===- LoongArchLBTInstrInfo.td - LoongArch LBT instructions -*- tablegen -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file describes the LBT extension instructions. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Instructions +//===----------------------------------------------------------------------===// + +let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Predicates = [HasExtLBT] in { + +def MOVGR2SCR : FmtGR2SCR<0x00000800>; +def MOVSCR2GR : FmtSCR2GR<0x00000c00>; + +def JISCR0 : FmtJISCR<0x48000200>; +def JISCR1 : FmtJISCR<0x48000300>; + +def ADDU12I_W : ALU_2RI5<0x00290000, simm5>; + +def ADC_B : ALU_3R<0x00300000>; +def ADC_H : ALU_3R<0x00308000>; +def ADC_W : ALU_3R<0x00310000>; + +def SBC_B : ALU_3R<0x00320000>; +def SBC_H : ALU_3R<0x00328000>; +def SBC_W : ALU_3R<0x00330000>; + +def ROTR_B : ALU_3R<0x001a0000>; +def ROTR_H : ALU_3R<0x001a8000>; + +def ROTRI_B : Fmt2RI3<0x004c2000>; +def ROTRI_H : Fmt2RI4<0x004c4000>; + +def RCR_B : ALU_3R<0x00340000>; +def RCR_H : ALU_3R<0x00348000>; +def RCR_W : ALU_3R<0x00350000>; + +def RCRI_B : Fmt2RI3<0x00502000>; +def RCRI_H : Fmt2RI4<0x00504000>; +def RCRI_W : ALU_2RI5<0x00508000, uimm5>; + +def FCVT_UD_D : FP_CONV<0x0114e400>; +def FCVT_LD_D : FP_CONV<0x0114e000>; +def FCVT_D_LD : FP_ALU_3R<0x01150000>; + +def LDL_W : LOAD_2RI12<0x2e000000>; +def LDR_W : LOAD_2RI12<0x2e400000>; +def STL_W : STORE_2RI12<0x2f000000>; +def STR_W : STORE_2RI12<0x2f400000>; + +def X86ADC_B : NoDstFmt2R<0x003f000c>; +def X86ADC_H : NoDstFmt2R<0x003f000d>; +def X86ADC_W : NoDstFmt2R<0x003f000e>; +def X86ADD_B : NoDstFmt2R<0x003f0004>; +def X86ADD_H : NoDstFmt2R<0x003f0005>; +def X86ADD_W : NoDstFmt2R<0x003f0006>; + +def X86INC_B : NoDstFmt1R<0x00008000>; +def X86INC_H : NoDstFmt1R<0x00008001>; +def X86INC_W : NoDstFmt1R<0x00008002>; + +def X86SBC_B : NoDstFmt2R<0x003f0010>; +def X86SBC_H : NoDstFmt2R<0x003f0011>; +def X86SBC_W : NoDstFmt2R<0x003f0012>; +def X86SUB_B : NoDstFmt2R<0x003f0008>; +def X86SUB_H : NoDstFmt2R<0x003f0009>; +def X86SUB_W : NoDstFmt2R<0x003f000a>; + +def X86DEC_B : NoDstFmt1R<0x00008004>; +def X86DEC_H : NoDstFmt1R<0x00008005>; +def X86DEC_W : NoDstFmt1R<0x00008006>; + +def X86AND_B : NoDstFmt2R<0x003f8010>; +def X86AND_H : NoDstFmt2R<0x003f8011>; +def X86AND_W : NoDstFmt2R<0x003f8012>; + +def X86OR_B : NoDstFmt2R<0x003f8014>; +def X86OR_H : NoDstFmt2R<0x003f8015>; +def X86OR_W : NoDstFmt2R<0x003f8016>; + +def X86XOR_B : NoDstFmt2R<0x003f8018>; +def X86XOR_H : NoDstFmt2R<0x003f8019>; +def X86XOR_W : NoDstFmt2R<0x003f801a>; + +def X86MUL_B : NoDstFmt2R<0x003e8000>; +def X86MUL_H : NoDstFmt2R<0x003e8001>; +def X86MUL_W : NoDstFmt2R<0x003e8002>; +def X86MUL_BU : NoDstFmt2R<0x003e8004>; +def X86MUL_HU : NoDstFmt2R<0x003e8005>; + +def X86RCL_B : NoDstFmt2R<0x003f800c>; +def X86RCL_H : NoDstFmt2R<0x003f800d>; +def X86RCL_W : NoDstFmt2R<0x003f800e>; +def X86RCLI_B : NoDstFmt1RI3<0x00542018>; +def X86RCLI_H : NoDstFmt1RI4<0x00544019>; +def X86RCLI_W : NoDstFmt1RI5<0x0054801a>; + +def X86RCR_B : NoDstFmt2R<0x003f8008>; +def X86RCR_H : NoDstFmt2R<0x003f8009>; +def X86RCR_W : NoDstFmt2R<0x003f800a>; +def X86RCRI_B : NoDstFmt1RI3<0x00542010>; +def X86RCRI_H : NoDstFmt1RI4<0x00544011>; +def X86RCRI_W : NoDstFmt1RI5<0x00548012>; + +def X86ROTL_B : NoDstFmt2R<0x003f8004>; +def X86ROTL_H : NoDstFmt2R<0x003f8005>; +def X86ROTL_W : NoDstFmt2R<0x003f8006>; +def X86ROTLI_B : NoDstFmt1RI3<0x00542014>; +def X86ROTLI_H : NoDstFmt1RI4<0x00544015>; +def X86ROTLI_W : NoDstFmt1RI5<0x00548016>; + +def X86ROTR_B : NoDstFmt2R<0x003f8000>; +def X86ROTR_H : NoDstFmt2R<0x003f8001>; +def X86ROTR_W : NoDstFmt2R<0x003f8003>; +def X86ROTRI_B : NoDstFmt1RI3<0x0054200c>; +def X86ROTRI_H : NoDstFmt1RI4<0x0054400d>; +def X86ROTRI_W : NoDstFmt1RI5<0x0054800e>; + +def X86SLL_B : NoDstFmt2R<0x003f0014>; +def X86SLL_H : NoDstFmt2R<0x003f0015>; +def X86SLL_W : NoDstFmt2R<0x003f0016>; +def X86SLLI_B : NoDstFmt1RI3<0x00542000>; +def X86SLLI_H : NoDstFmt1RI4<0x00544001>; +def X86SLLI_W : NoDstFmt1RI5<0x00548002>; + +def X86SRL_B : NoDstFmt2R<0x003f0018>; +def X86SRL_H : NoDstFmt2R<0x003f0019>; +def X86SRL_W : NoDstFmt2R<0x003f001a>; +def X86SRLI_B : NoDstFmt1RI3<0x00542004>; +def X86SRLI_H : NoDstFmt1RI4<0x00544005>; +def X86SRLI_W : NoDstFmt1RI5<0x00548006>; + +def X86SRA_B : NoDstFmt2R<0x003f001c>; +def X86SRA_H : NoDstFmt2R<0x003f001d>; +def X86SRA_W : NoDstFmt2R<0x003f001e>; +def X86SRAI_B : NoDstFmt1RI3<0x00542008>; +def X86SRAI_H : NoDstFmt1RI4<0x00544009>; +def X86SRAI_W : NoDstFmt1RI5<0x0054800a>; + +def SETX86J : Fmt1RI4<0x00368000>; +def SETX86LOOPE : ALU_2R<0x00007800>; +def SETX86LOOPNE : ALU_2R<0x00007c00>; +def X86MFFLAG : Fmt1RI8<0x005c0000>; +def X86MTFLAG : Fmt1RI8<0x005c0020>; +def X86MFTOP : FmtMFTOP<0x00007400>; +def X86MTTOP : FmtMTTOP<0x00007000>; + +def X86INCTOP : FmtI32<0x00008009>; +def X86DECTOP : FmtI32<0x00008029>; +def X86SETTM : FmtI32<0x00008008>; +def X86CLRTM : FmtI32<0x00008028>; +def X86SETTAG : Fmt1RI5I8<0x00580000>; + +def ARMADD_W : NoDstFmt2RI4<0x00370010>; +def ARMSUB_W : NoDstFmt2RI4<0x00378010>; +def ARMADC_W : NoDstFmt2RI4<0x00380010>; +def ARMSBC_W : NoDstFmt2RI4<0x00388010>; +def ARMAND_W : NoDstFmt2RI4<0x00390010>; +def ARMOR_W : NoDstFmt2RI4<0x00398010>; +def ARMXOR_W : NoDstFmt2RI4<0x003a0010>; +def ARMNOT_W : NoDstFmt1RI4<0x003fc01c>; +def ARMSLL_W : NoDstFmt2RI4<0x003a8010>; +def ARMSRL_W : NoDstFmt2RI4<0x003b0010>; +def ARMSRA_W : NoDstFmt2RI4<0x003b8010>; +def ARMROTR_W : NoDstFmt2RI4<0x003c0010>; +def ARMSLLI_W : NoDstFmt1RI5I4<0x003c8010>; +def ARMSRLI_W : NoDstFmt1RI5I4<0x003d0010>; +def ARMSRAI_W : NoDstFmt1RI5I4<0x003d8010>; +def ARMROTRI_W : NoDstFmt1RI5I4<0x003e0010>; +def ARMRRX_W : NoDstFmt1RI4<0x003fc01f>; +def ARMMOVE : Fmt2RI4<0x00364000>; +def ARMMOV_W : NoDstFmt1RI4<0x003fc01d>; + +def ARMMFFLAG : Fmt1RI8<0x005c0040>; +def ARMMTFLAG : Fmt1RI8<0x005c0060>; +def SETARMJ : Fmt1RI4<0x0036c000>; + +let Predicates = [IsLA64] in { +def ADDU12I_D : ALU_2RI5<0x00298000, simm5>; +def ADC_D : ALU_3R<0x00318000>; +def SBC_D : ALU_3R<0x00338000>; +def RCR_D : ALU_3R<0x00358000>; +def RCRI_D : ALU_2RI6<0x00510000, uimm6>; +def LDL_D : LOAD_2RI12<0x2e800000>; +def LDR_D : LOAD_2RI12<0x2ec00000>; +def STL_D : STORE_2RI12<0x2f800000>; +def STR_D : STORE_2RI12<0x2fc00000>; + +def X86ADC_D : NoDstFmt2R<0x003f000f>; +def X86ADD_D : NoDstFmt2R<0x003f0007>; +def X86ADD_WU : NoDstFmt2R<0x003f0000>; +def X86ADD_DU : NoDstFmt2R<0x003f0001>; +def X86INC_D : NoDstFmt1R<0x00008003>; +def X86SBC_D : NoDstFmt2R<0x003f0013>; +def X86SUB_WU : NoDstFmt2R<0x003f0002>; +def X86SUB_D : NoDstFmt2R<0x003f000b>; +def X86SUB_DU : NoDstFmt2R<0x003f0003>; +def X86DEC_D : NoDstFmt1R<0x00008007>; +def X86AND_D : NoDstFmt2R<0x003f8013>; +def X86OR_D : NoDstFmt2R<0x003f8017>; +def X86XOR_D : NoDstFmt2R<0x003f801b>; +def X86MUL_D : NoDstFmt2R<0x003e8003>; +def X86MUL_WU : NoDstFmt2R<0x003e8006>; +def X86MUL_DU : NoDstFmt2R<0x003e8007>; +def X86RCL_D : NoDstFmt2R<0x003f800f>; +def X86RCLI_D : NoDstFmt1RI6<0x0055001b>; +def X86RCR_D : NoDstFmt2R<0x003f800b>; +def X86RCRI_D : NoDstFmt1RI6<0x00550013>; +def X86ROTL_D : NoDstFmt2R<0x003f8007>; +def X86ROTLI_D : NoDstFmt1RI6<0x00550017>; +def X86ROTR_D : NoDstFmt2R<0x003f8002>; +def X86ROTRI_D : NoDstFmt1RI6<0x0055000f>; +def X86SLL_D : NoDstFmt2R<0x003f0017>; +def X86SLLI_D : NoDstFmt1RI6<0x00550003>; +def X86SRL_D : NoDstFmt2R<0x003f001b>; +def X86SRLI_D : NoDstFmt1RI6<0x00550007>; +def X86SRA_D : NoDstFmt2R<0x003f001f>; +def X86SRAI_D : NoDstFmt1RI6<0x0055000b>; +def ARMMOV_D : NoDstFmt1RI4<0x003fc01e>; + +} // Predicates = [IsLA64] +} // hasSideEffects = 0, mayLoad = 0, mayStore = 0, Predicates = [HasExtLBT] diff --git a/llvm/lib/Target/LoongArch/LoongArchLVZInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchLVZInstrInfo.td new file mode 100644 --- /dev/null +++ b/llvm/lib/Target/LoongArch/LoongArchLVZInstrInfo.td @@ -0,0 +1,33 @@ +//===- LoongArchLVZInstrInfo.td - LoongArch LVZ instructions -*- tablegen -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file describes the LVZ extension instructions. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Instructions +//===----------------------------------------------------------------------===// + +let hasSideEffects = 1, mayLoad = 0, mayStore = 0, Predicates = [HasExtLVZ] in { + +def GCSRRD : FmtCSR<0x05000000, (outs GPR:$rd), (ins uimm14:$csr_num), + "$rd, $csr_num">; + +let Constraints = "$rd = $dst" in { +def GCSRWR : FmtCSR<0x05000020, (outs GPR:$dst), + (ins GPR:$rd, uimm14:$csr_num), "$rd, $csr_num">; +def GCSRXCHG : FmtCSRXCHG<0x05000000, (outs GPR:$dst), + (ins GPR:$rd, GPR:$rj, uimm14:$csr_num), + "$rd, $rj, $csr_num">; +} // Constraints = "$rd = $dst" + +def GTLBFLUSH : FmtI32<0x06482401>; +def HVCL : MISC_I15<0x002b8000>; + +} // hasSideEffects = 1, mayLoad = 0, mayStore = 0, Predicates = [HasExtLVZ] diff --git a/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.td b/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.td --- a/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.td +++ b/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.td @@ -206,3 +206,11 @@ def LASX256 : RegisterClass<"LoongArch", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64], 256, (sequence "XR%u", 0, 31)>; + +// Scratchpad registers + +foreach I = 0-3 in +def SCR#I : LoongArchReg; + +let isAllocatable = false, RegInfos = GRLenRI in +def SCR : RegisterClass<"LoongArch", [GRLenVT], 32, (sequence "SCR%u", 0, 3)>; diff --git a/llvm/test/MC/LoongArch/lbt/arm-alu.s b/llvm/test/MC/LoongArch/lbt/arm-alu.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/LoongArch/lbt/arm-alu.s @@ -0,0 +1,36 @@ +# RUN: llvm-mc --triple=loongarch64 --show-encoding %s | \ +# RUN: FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: llvm-mc --triple=loongarch64 --filetype=obj %s | \ +# RUN: llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-INST + +armadd.w $a0, $a1, 1 +# CHECK-INST: armadd.w $a0, $a1, 1 +# CHECK-ENCODING: encoding: [0x91,0x14,0x37,0x00] + +armsub.w $a0, $a1, 1 +# CHECK-INST: armsub.w $a0, $a1, 1 +# CHECK-ENCODING: encoding: [0x91,0x94,0x37,0x00] + +armadc.w $a0, $a1, 1 +# CHECK-INST: armadc.w $a0, $a1, 1 +# CHECK-ENCODING: encoding: [0x91,0x14,0x38,0x00] + +armsbc.w $a0, $a1, 1 +# CHECK-INST: armsbc.w $a0, $a1, 1 +# CHECK-ENCODING: encoding: [0x91,0x94,0x38,0x00] + +armand.w $a0, $a1, 1 +# CHECK-INST: armand.w $a0, $a1, 1 +# CHECK-ENCODING: encoding: [0x91,0x14,0x39,0x00] + +armor.w $a0, $a1, 1 +# CHECK-INST: armor.w $a0, $a1, 1 +# CHECK-ENCODING: encoding: [0x91,0x94,0x39,0x00] + +armxor.w $a0, $a1, 1 +# CHECK-INST: armxor.w $a0, $a1, 1 +# CHECK-ENCODING: encoding: [0x91,0x14,0x3a,0x00] + +armnot.w $a0, 1 +# CHECK-INST: armnot.w $a0, 1 +# CHECK-ENCODING: encoding: [0x9c,0xc4,0x3f,0x00] diff --git a/llvm/test/MC/LoongArch/lbt/arm-jump.s b/llvm/test/MC/LoongArch/lbt/arm-jump.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/LoongArch/lbt/arm-jump.s @@ -0,0 +1,8 @@ +# RUN: llvm-mc --triple=loongarch64 --show-encoding %s | \ +# RUN: FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: llvm-mc --triple=loongarch64 --filetype=obj %s | \ +# RUN: llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-INST + +setarmj $a0, 1 +# CHECK-INST: setarmj $a0, 1 +# CHECK-ENCODING: encoding: [0x04,0xc4,0x36,0x00] diff --git a/llvm/test/MC/LoongArch/lbt/arm-mov.s b/llvm/test/MC/LoongArch/lbt/arm-mov.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/LoongArch/lbt/arm-mov.s @@ -0,0 +1,24 @@ +# RUN: llvm-mc --triple=loongarch64 --show-encoding %s | \ +# RUN: FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: llvm-mc --triple=loongarch64 --filetype=obj %s | \ +# RUN: llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-INST + +armmove $a0, $a1, 1 +# CHECK-INST: armmove $a0, $a1, 1 +# CHECK-ENCODING: encoding: [0xa4,0x44,0x36,0x00] + +armmov.w $a0, 1 +# CHECK-INST: armmov.w $a0, 1 +# CHECK-ENCODING: encoding: [0x9d,0xc4,0x3f,0x00] + +armmov.d $a0, 1 +# CHECK-INST: armmov.d $a0, 1 +# CHECK-ENCODING: encoding: [0x9e,0xc4,0x3f,0x00] + +armmfflag $a0, 1 +# CHECK-INST: armmfflag $a0, 1 +# CHECK-ENCODING: encoding: [0x44,0x04,0x5c,0x00] + +armmtflag $a0, 1 +# CHECK-INST: armmtflag $a0, 1 +# CHECK-ENCODING: encoding: [0x64,0x04,0x5c,0x00] diff --git a/llvm/test/MC/LoongArch/lbt/arm-shift.s b/llvm/test/MC/LoongArch/lbt/arm-shift.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/LoongArch/lbt/arm-shift.s @@ -0,0 +1,40 @@ +# RUN: llvm-mc --triple=loongarch64 --show-encoding %s | \ +# RUN: FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: llvm-mc --triple=loongarch64 --filetype=obj %s | \ +# RUN: llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-INST + +armsll.w $a0, $a1, 1 +# CHECK-INST: armsll.w $a0, $a1, 1 +# CHECK-ENCODING: encoding: [0x91,0x94,0x3a,0x00] + +armsrl.w $a0, $a1, 1 +# CHECK-INST: armsrl.w $a0, $a1, 1 +# CHECK-ENCODING: encoding: [0x91,0x14,0x3b,0x00] + +armsra.w $a0, $a1, 1 +# CHECK-INST: armsra.w $a0, $a1, 1 +# CHECK-ENCODING: encoding: [0x91,0x94,0x3b,0x00] + +armrotr.w $a0, $a1, 1 +# CHECK-INST: armrotr.w $a0, $a1, 1 +# CHECK-ENCODING: encoding: [0x91,0x14,0x3c,0x00] + +armslli.w $a0, 1, 1 +# CHECK-INST: armslli.w $a0, 1, 1 +# CHECK-ENCODING: encoding: [0x91,0x84,0x3c,0x00] + +armsrli.w $a0, 1, 1 +# CHECK-INST: armsrli.w $a0, 1, 1 +# CHECK-ENCODING: encoding: [0x91,0x04,0x3d,0x00] + +armsrai.w $a0, 1, 1 +# CHECK-INST: armsrai.w $a0, 1, 1 +# CHECK-ENCODING: encoding: [0x91,0x84,0x3d,0x00] + +armrotri.w $a0, 1, 1 +# CHECK-INST: armrotri.w $a0, 1, 1 +# CHECK-ENCODING: encoding: [0x91,0x04,0x3e,0x00] + +armrrx.w $a0, 1 +# CHECK-INST: armrrx.w $a0, 1 +# CHECK-ENCODING: encoding: [0x9f,0xc4,0x3f,0x00] diff --git a/llvm/test/MC/LoongArch/lbt/base.s b/llvm/test/MC/LoongArch/lbt/base.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/LoongArch/lbt/base.s @@ -0,0 +1,136 @@ +# RUN: llvm-mc --triple=loongarch64 --show-encoding %s | \ +# RUN: FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: llvm-mc --triple=loongarch64 --filetype=obj %s | \ +# RUN: llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-INST + +addu12i.w $a0, $a1, 1 +# CHECK-INST: addu12i.w $a0, $a1, 1 +# CHECK-ENCODING: encoding: [0xa4,0x04,0x29,0x00] + +addu12i.d $a0, $a1, 1 +# CHECK-INST: addu12i.d $a0, $a1, 1 +# CHECK-ENCODING: encoding: [0xa4,0x84,0x29,0x00] + +adc.b $a0, $a1, $a2 +# CHECK-INST: adc.b $a0, $a1, $a2 +# CHECK-ENCODING: encoding: [0xa4,0x18,0x30,0x00] + +adc.h $a0, $a1, $a2 +# CHECK-INST: adc.h $a0, $a1, $a2 +# CHECK-ENCODING: encoding: [0xa4,0x98,0x30,0x00] + +adc.w $a0, $a1, $a2 +# CHECK-INST: adc.w $a0, $a1, $a2 +# CHECK-ENCODING: encoding: [0xa4,0x18,0x31,0x00] + +adc.d $a0, $a1, $a2 +# CHECK-INST: adc.d $a0, $a1, $a2 +# CHECK-ENCODING: encoding: [0xa4,0x98,0x31,0x00] + +sbc.b $a0, $a1, $a2 +# CHECK-INST: sbc.b $a0, $a1, $a2 +# CHECK-ENCODING: encoding: [0xa4,0x18,0x32,0x00] + +sbc.h $a0, $a1, $a2 +# CHECK-INST: sbc.h $a0, $a1, $a2 +# CHECK-ENCODING: encoding: [0xa4,0x98,0x32,0x00] + +sbc.w $a0, $a1, $a2 +# CHECK-INST: sbc.w $a0, $a1, $a2 +# CHECK-ENCODING: encoding: [0xa4,0x18,0x33,0x00] + +sbc.d $a0, $a1, $a2 +# CHECK-INST: sbc.d $a0, $a1, $a2 +# CHECK-ENCODING: encoding: [0xa4,0x98,0x33,0x00] + +rotr.b $a0, $a1, $a2 +# CHECK-INST: rotr.b $a0, $a1, $a2 +# CHECK-ENCODING: encoding: [0xa4,0x18,0x1a,0x00] + +rotr.h $a0, $a1, $a2 +# CHECK-INST: rotr.h $a0, $a1, $a2 +# CHECK-ENCODING: encoding: [0xa4,0x98,0x1a,0x00] + +rotri.b $a0, $a1, 1 +# CHECK-INST: rotri.b $a0, $a1, 1 +# CHECK-ENCODING: encoding: [0xa4,0x24,0x4c,0x00] + +rotri.h $a0, $a1, 1 +# CHECK-INST: rotri.h $a0, $a1, 1 +# CHECK-ENCODING: encoding: [0xa4,0x44,0x4c,0x00] + +rcr.b $a0, $a1, $a2 +# CHECK-INST: rcr.b $a0, $a1, $a2 +# CHECK-ENCODING: encoding: [0xa4,0x18,0x34,0x00] + +rcr.h $a0, $a1, $a2 +# CHECK-INST: rcr.h $a0, $a1, $a2 +# CHECK-ENCODING: encoding: [0xa4,0x98,0x34,0x00] + +rcr.w $a0, $a1, $a2 +# CHECK-INST: rcr.w $a0, $a1, $a2 +# CHECK-ENCODING: encoding: [0xa4,0x18,0x35,0x00] + +rcr.d $a0, $a1, $a2 +# CHECK-INST: rcr.d $a0, $a1, $a2 +# CHECK-ENCODING: encoding: [0xa4,0x98,0x35,0x00] + +rcri.b $a0, $a1, 1 +# CHECK-INST: rcri.b $a0, $a1, 1 +# CHECK-ENCODING: encoding: [0xa4,0x24,0x50,0x00] + +rcri.h $a0, $a1, 1 +# CHECK-INST: rcri.h $a0, $a1, 1 +# CHECK-ENCODING: encoding: [0xa4,0x44,0x50,0x00] + +rcri.w $a0, $a1, 1 +# CHECK-INST: rcri.w $a0, $a1, 1 +# CHECK-ENCODING: encoding: [0xa4,0x84,0x50,0x00] + +rcri.d $a0, $a1, 1 +# CHECK-INST: rcri.d $a0, $a1, 1 +# CHECK-ENCODING: encoding: [0xa4,0x04,0x51,0x00] + +fcvt.ud.d $f0, $f1 +# CHECK-INST: fcvt.ud.d $fa0, $fa1 +# CHECK-ENCODING: encoding: [0x20,0xe4,0x14,0x01] + +fcvt.ld.d $f0, $f1 +# CHECK-INST: fcvt.ld.d $fa0, $fa1 +# CHECK-ENCODING: encoding: [0x20,0xe0,0x14,0x01] + +fcvt.d.ld $f0, $f1, $f2 +# CHECK-INST: fcvt.d.ld $fa0, $fa1, $fa2 +# CHECK-ENCODING: encoding: [0x20,0x08,0x15,0x01] + +ldl.d $a0, $a1, 1 +# CHECK-INST: ldl.d $a0, $a1, 1 +# CHECK-ENCODING: encoding: [0xa4,0x04,0x80,0x2e] + +ldl.w $a0, $a1, 1 +# CHECK-INST: ldl.w $a0, $a1, 1 +# CHECK-ENCODING: encoding: [0xa4,0x04,0x00,0x2e] + +ldr.w $a0, $a1, 1 +# CHECK-INST: ldr.w $a0, $a1, 1 +# CHECK-ENCODING: encoding: [0xa4,0x04,0x40,0x2e] + +ldr.d $a0, $a1, 1 +# CHECK-INST: ldr.d $a0, $a1, 1 +# CHECK-ENCODING: encoding: [0xa4,0x04,0xc0,0x2e] + +stl.w $a0, $a1, 1 +# CHECK-INST: stl.w $a0, $a1, 1 +# CHECK-ENCODING: encoding: [0xa4,0x04,0x00,0x2f] + +stl.d $a0, $a1, 1 +# CHECK-INST: stl.d $a0, $a1, 1 +# CHECK-ENCODING: encoding: [0xa4,0x04,0x80,0x2f] + +str.w $a0, $a1, 1 +# CHECK-INST: str.w $a0, $a1, 1 +# CHECK-ENCODING: encoding: [0xa4,0x04,0x40,0x2f] + +str.d $a0, $a1, 1 +# CHECK-INST: str.d $a0, $a1, 1 +# CHECK-ENCODING: encoding: [0xa4,0x04,0xc0,0x2f] diff --git a/llvm/test/MC/LoongArch/lbt/scr.s b/llvm/test/MC/LoongArch/lbt/scr.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/LoongArch/lbt/scr.s @@ -0,0 +1,20 @@ +# RUN: llvm-mc --triple=loongarch64 --show-encoding %s | \ +# RUN: FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: llvm-mc --triple=loongarch64 --filetype=obj %s | \ +# RUN: llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-INST + +movgr2scr $scr0, $a1 +# CHECK-INST: movgr2scr $scr0, $a1 +# CHECK-ENCODING: encoding: [0xa0,0x08,0x00,0x00] + +movscr2gr $a0, $scr1 +# CHECK-INST: movscr2gr $a0, $scr1 +# CHECK-ENCODING: encoding: [0x24,0x0c,0x00,0x00] + +jiscr0 100 +# CHECK-INST: jiscr0 100 +# CHECK-ENCODING: encoding: [0x00,0x66,0x00,0x48] + +jiscr1 100 +# CHECK-INST: jiscr1 100 +# CHECK-ENCODING: encoding: [0x00,0x67,0x00,0x48] diff --git a/llvm/test/MC/LoongArch/lbt/x86-alu.s b/llvm/test/MC/LoongArch/lbt/x86-alu.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/LoongArch/lbt/x86-alu.s @@ -0,0 +1,196 @@ +# RUN: llvm-mc --triple=loongarch64 --show-encoding %s | \ +# RUN: FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: llvm-mc --triple=loongarch64 --filetype=obj %s | \ +# RUN: llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-INST + +x86adc.b $a0, $a1 +# CHECK-INST: x86adc.b $a0, $a1 +# CHECK-ENCODING: encoding: [0x8c,0x14,0x3f,0x00] + +x86adc.h $a0, $a1 +# CHECK-INST: x86adc.h $a0, $a1 +# CHECK-ENCODING: encoding: [0x8d,0x14,0x3f,0x00] + +x86adc.w $a0, $a1 +# CHECK-INST: x86adc.w $a0, $a1 +# CHECK-ENCODING: encoding: [0x8e,0x14,0x3f,0x00] + +x86adc.d $a0, $a1 +# CHECK-INST: x86adc.d $a0, $a1 +# CHECK-ENCODING: encoding: [0x8f,0x14,0x3f,0x00] + +x86add.b $a0, $a1 +# CHECK-INST: x86add.b $a0, $a1 +# CHECK-ENCODING: encoding: [0x84,0x14,0x3f,0x00] + +x86add.h $a0, $a1 +# CHECK-INST: x86add.h $a0, $a1 +# CHECK-ENCODING: encoding: [0x85,0x14,0x3f,0x00] + +x86add.w $a0, $a1 +# CHECK-INST: x86add.w $a0, $a1 +# CHECK-ENCODING: encoding: [0x86,0x14,0x3f,0x00] + +x86add.d $a0, $a1 +# CHECK-INST: x86add.d $a0, $a1 +# CHECK-ENCODING: encoding: [0x87,0x14,0x3f,0x00] + +x86add.wu $a0, $a1 +# CHECK-INST: x86add.wu $a0, $a1 +# CHECK-ENCODING: encoding: [0x80,0x14,0x3f,0x00] + +x86add.du $a0, $a1 +# CHECK-INST: x86add.du $a0, $a1 +# CHECK-ENCODING: encoding: [0x81,0x14,0x3f,0x00] + +x86inc.b $a0 +# CHECK-INST: x86inc.b $a0 +# CHECK-ENCODING: encoding: [0x80,0x80,0x00,0x00] + +x86inc.h $a0 +# CHECK-INST: x86inc.h $a0 +# CHECK-ENCODING: encoding: [0x81,0x80,0x00,0x00] + +x86inc.w $a0 +# CHECK-INST: x86inc.w $a0 +# CHECK-ENCODING: encoding: [0x82,0x80,0x00,0x00] + +x86inc.d $a0 +# CHECK-INST: x86inc.d $a0 +# CHECK-ENCODING: encoding: [0x83,0x80,0x00,0x00] + +x86sbc.b $a0, $a1 +# CHECK-INST: x86sbc.b $a0, $a1 +# CHECK-ENCODING: encoding: [0x90,0x14,0x3f,0x00] + +x86sbc.h $a0, $a1 +# CHECK-INST: x86sbc.h $a0, $a1 +# CHECK-ENCODING: encoding: [0x91,0x14,0x3f,0x00] + +x86sbc.w $a0, $a1 +# CHECK-INST: x86sbc.w $a0, $a1 +# CHECK-ENCODING: encoding: [0x92,0x14,0x3f,0x00] + +x86sbc.d $a0, $a1 +# CHECK-INST: x86sbc.d $a0, $a1 +# CHECK-ENCODING: encoding: [0x93,0x14,0x3f,0x00] + +x86sub.b $a0, $a1 +# CHECK-INST: x86sub.b $a0, $a1 +# CHECK-ENCODING: encoding: [0x88,0x14,0x3f,0x00] + +x86sub.h $a0, $a1 +# CHECK-INST: x86sub.h $a0, $a1 +# CHECK-ENCODING: encoding: [0x89,0x14,0x3f,0x00] + +x86sub.w $a0, $a1 +# CHECK-INST: x86sub.w $a0, $a1 +# CHECK-ENCODING: encoding: [0x8a,0x14,0x3f,0x00] + +x86sub.d $a0, $a1 +# CHECK-INST: x86sub.d $a0, $a1 +# CHECK-ENCODING: encoding: [0x8b,0x14,0x3f,0x00] + +x86sub.wu $a0, $a1 +# CHECK-INST: x86sub.wu $a0, $a1 +# CHECK-ENCODING: encoding: [0x82,0x14,0x3f,0x00] + +x86sub.du $a0, $a1 +# CHECK-INST: x86sub.du $a0, $a1 +# CHECK-ENCODING: encoding: [0x83,0x14,0x3f,0x00] + +x86dec.b $a0 +# CHECK-INST: x86dec.b $a0 +# CHECK-ENCODING: encoding: [0x84,0x80,0x00,0x00] + +x86dec.h $a0 +# CHECK-INST: x86dec.h $a0 +# CHECK-ENCODING: encoding: [0x85,0x80,0x00,0x00] + +x86dec.w $a0 +# CHECK-INST: x86dec.w $a0 +# CHECK-ENCODING: encoding: [0x86,0x80,0x00,0x00] + +x86dec.d $a0 +# CHECK-INST: x86dec.d $a0 +# CHECK-ENCODING: encoding: [0x87,0x80,0x00,0x00] + +x86and.b $a0, $a1 +# CHECK-INST: x86and.b $a0, $a1 +# CHECK-ENCODING: encoding: [0x90,0x94,0x3f,0x00] + +x86and.h $a0, $a1 +# CHECK-INST: x86and.h $a0, $a1 +# CHECK-ENCODING: encoding: [0x91,0x94,0x3f,0x00] + +x86and.w $a0, $a1 +# CHECK-INST: x86and.w $a0, $a1 +# CHECK-ENCODING: encoding: [0x92,0x94,0x3f,0x00] + +x86and.d $a0, $a1 +# CHECK-INST: x86and.d $a0, $a1 +# CHECK-ENCODING: encoding: [0x93,0x94,0x3f,0x00] + +x86or.b $a0, $a1 +# CHECK-INST: x86or.b $a0, $a1 +# CHECK-ENCODING: encoding: [0x94,0x94,0x3f,0x00] + +x86or.h $a0, $a1 +# CHECK-INST: x86or.h $a0, $a1 +# CHECK-ENCODING: encoding: [0x95,0x94,0x3f,0x00] + +x86or.w $a0, $a1 +# CHECK-INST: x86or.w $a0, $a1 +# CHECK-ENCODING: encoding: [0x96,0x94,0x3f,0x00] + +x86or.d $a0, $a1 +# CHECK-INST: x86or.d $a0, $a1 +# CHECK-ENCODING: encoding: [0x97,0x94,0x3f,0x00] + +x86xor.b $a0, $a1 +# CHECK-INST: x86xor.b $a0, $a1 +# CHECK-ENCODING: encoding: [0x98,0x94,0x3f,0x00] + +x86xor.h $a0, $a1 +# CHECK-INST: x86xor.h $a0, $a1 +# CHECK-ENCODING: encoding: [0x99,0x94,0x3f,0x00] + +x86xor.w $a0, $a1 +# CHECK-INST: x86xor.w $a0, $a1 +# CHECK-ENCODING: encoding: [0x9a,0x94,0x3f,0x00] + +x86xor.d $a0, $a1 +# CHECK-INST: x86xor.d $a0, $a1 +# CHECK-ENCODING: encoding: [0x9b,0x94,0x3f,0x00] + +x86mul.b $a0, $a1 +# CHECK-INST: x86mul.b $a0, $a1 +# CHECK-ENCODING: encoding: [0x80,0x94,0x3e,0x00] + +x86mul.h $a0, $a1 +# CHECK-INST: x86mul.h $a0, $a1 +# CHECK-ENCODING: encoding: [0x81,0x94,0x3e,0x00] + +x86mul.w $a0, $a1 +# CHECK-INST: x86mul.w $a0, $a1 +# CHECK-ENCODING: encoding: [0x82,0x94,0x3e,0x00] + +x86mul.d $a0, $a1 +# CHECK-INST: x86mul.d $a0, $a1 +# CHECK-ENCODING: encoding: [0x83,0x94,0x3e,0x00] + +x86mul.bu $a0, $a1 +# CHECK-INST: x86mul.bu $a0, $a1 +# CHECK-ENCODING: encoding: [0x84,0x94,0x3e,0x00] + +x86mul.hu $a0, $a1 +# CHECK-INST: x86mul.hu $a0, $a1 +# CHECK-ENCODING: encoding: [0x85,0x94,0x3e,0x00] + +x86mul.wu $a0, $a1 +# CHECK-INST: x86mul.wu $a0, $a1 +# CHECK-ENCODING: encoding: [0x86,0x94,0x3e,0x00] + +x86mul.du $a0, $a1 +# CHECK-INST: x86mul.du $a0, $a1 +# CHECK-ENCODING: encoding: [0x87,0x94,0x3e,0x00] diff --git a/llvm/test/MC/LoongArch/lbt/x86-jump.s b/llvm/test/MC/LoongArch/lbt/x86-jump.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/LoongArch/lbt/x86-jump.s @@ -0,0 +1,16 @@ +# RUN: llvm-mc --triple=loongarch64 --show-encoding %s | \ +# RUN: FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: llvm-mc --triple=loongarch64 --filetype=obj %s | \ +# RUN: llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-INST + +setx86j $a0, 1 +# CHECK-INST: setx86j $a0, 1 +# CHECK-ENCODING: encoding: [0x04,0x84,0x36,0x00] + +setx86loope $a0, $a1 +# CHECK-INST: setx86loope $a0, $a1 +# CHECK-ENCODING: encoding: [0xa4,0x78,0x00,0x00] + +setx86loopne $a0, $a1 +# CHECK-INST: setx86loopne $a0, $a1 +# CHECK-ENCODING: encoding: [0xa4,0x7c,0x00,0x00] diff --git a/llvm/test/MC/LoongArch/lbt/x86-misc.s b/llvm/test/MC/LoongArch/lbt/x86-misc.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/LoongArch/lbt/x86-misc.s @@ -0,0 +1,40 @@ +# RUN: llvm-mc --triple=loongarch64 --show-encoding %s | \ +# RUN: FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: llvm-mc --triple=loongarch64 --filetype=obj %s | \ +# RUN: llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-INST + +x86mfflag $a0, 1 +# CHECK-INST: x86mfflag $a0, 1 +# CHECK-ENCODING: encoding: [0x04,0x04,0x5c,0x00] + +x86mtflag $a0, 1 +# CHECK-INST: x86mtflag $a0, 1 +# CHECK-ENCODING: encoding: [0x24,0x04,0x5c,0x00] + +x86mftop $a0 +# CHECK-INST: x86mftop $a0 +# CHECK-ENCODING: encoding: [0x04,0x74,0x00,0x00] + +x86mttop 1 +# CHECK-INST: x86mttop 1 +# CHECK-ENCODING: encoding: [0x20,0x70,0x00,0x00] + +x86inctop +# CHECK-INST: x86inctop +# CHECK-ENCODING: encoding: [0x09,0x80,0x00,0x00] + +x86dectop +# CHECK-INST: x86dectop +# CHECK-ENCODING: encoding: [0x29,0x80,0x00,0x00] + +x86settm +# CHECK-INST: x86settm +# CHECK-ENCODING: encoding: [0x08,0x80,0x00,0x00] + +x86clrtm +# CHECK-INST: x86clrtm +# CHECK-ENCODING: encoding: [0x28,0x80,0x00,0x00] + +x86settag $a0, 1, 1 +# CHECK-INST: x86settag $a0, 1, 1 +# CHECK-ENCODING: encoding: [0x24,0x04,0x58,0x00] diff --git a/llvm/test/MC/LoongArch/lbt/x86-shift.s b/llvm/test/MC/LoongArch/lbt/x86-shift.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/LoongArch/lbt/x86-shift.s @@ -0,0 +1,228 @@ +# RUN: llvm-mc --triple=loongarch64 --show-encoding %s | \ +# RUN: FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: llvm-mc --triple=loongarch64 --filetype=obj %s | \ +# RUN: llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-INST + +x86rcl.b $a0, $a1 +# CHECK-INST: x86rcl.b $a0, $a1 +# CHECK-ENCODING: encoding: [0x8c,0x94,0x3f,0x00] + +x86rcl.h $a0, $a1 +# CHECK-INST: x86rcl.h $a0, $a1 +# CHECK-ENCODING: encoding: [0x8d,0x94,0x3f,0x00] + +x86rcl.w $a0, $a1 +# CHECK-INST: x86rcl.w $a0, $a1 +# CHECK-ENCODING: encoding: [0x8e,0x94,0x3f,0x00] + +x86rcl.d $a0, $a1 +# CHECK-INST: x86rcl.d $a0, $a1 +# CHECK-ENCODING: encoding: [0x8f,0x94,0x3f,0x00] + +x86rcli.b $a0, 1 +# CHECK-INST: x86rcli.b $a0, 1 +# CHECK-ENCODING: encoding: [0x98,0x24,0x54,0x00] + +x86rcli.h $a0, 1 +# CHECK-INST: x86rcli.h $a0, 1 +# CHECK-ENCODING: encoding: [0x99,0x44,0x54,0x00] + +x86rcli.w $a0, 1 +# CHECK-INST: x86rcli.w $a0, 1 +# CHECK-ENCODING: encoding: [0x9a,0x84,0x54,0x00] + +x86rcli.d $a0, 1 +# CHECK-INST: x86rcli.d $a0, 1 +# CHECK-ENCODING: encoding: [0x9b,0x04,0x55,0x00] + +x86rcr.b $a0, $a1 +# CHECK-INST: x86rcr.b $a0, $a1 +# CHECK-ENCODING: encoding: [0x88,0x94,0x3f,0x00] + +x86rcr.h $a0, $a1 +# CHECK-INST: x86rcr.h $a0, $a1 +# CHECK-ENCODING: encoding: [0x89,0x94,0x3f,0x00] + +x86rcr.w $a0, $a1 +# CHECK-INST: x86rcr.w $a0, $a1 +# CHECK-ENCODING: encoding: [0x8a,0x94,0x3f,0x00] + +x86rcr.d $a0, $a1 +# CHECK-INST: x86rcr.d $a0, $a1 +# CHECK-ENCODING: encoding: [0x8b,0x94,0x3f,0x00] + +x86rcri.b $a0, 1 +# CHECK-INST: x86rcri.b $a0, 1 +# CHECK-ENCODING: encoding: [0x90,0x24,0x54,0x00] + +x86rcri.h $a0, 1 +# CHECK-INST: x86rcri.h $a0, 1 +# CHECK-ENCODING: encoding: [0x91,0x44,0x54,0x00] + +x86rcri.w $a0, 1 +# CHECK-INST: x86rcri.w $a0, 1 +# CHECK-ENCODING: encoding: [0x92,0x84,0x54,0x00] + +x86rcri.d $a0, 1 +# CHECK-INST: x86rcri.d $a0, 1 +# CHECK-ENCODING: encoding: [0x93,0x04,0x55,0x00] + +x86rotl.b $a0, $a1 +# CHECK-INST: x86rotl.b $a0, $a1 +# CHECK-ENCODING: encoding: [0x84,0x94,0x3f,0x00] + +x86rotl.h $a0, $a1 +# CHECK-INST: x86rotl.h $a0, $a1 +# CHECK-ENCODING: encoding: [0x85,0x94,0x3f,0x00] + +x86rotl.w $a0, $a1 +# CHECK-INST: x86rotl.w $a0, $a1 +# CHECK-ENCODING: encoding: [0x86,0x94,0x3f,0x00] + +x86rotl.d $a0, $a1 +# CHECK-INST: x86rotl.d $a0, $a1 +# CHECK-ENCODING: encoding: [0x87,0x94,0x3f,0x00] + +x86rotli.b $a0, 1 +# CHECK-INST: x86rotli.b $a0, 1 +# CHECK-ENCODING: encoding: [0x94,0x24,0x54,0x00] + +x86rotli.h $a0, 1 +# CHECK-INST: x86rotli.h $a0, 1 +# CHECK-ENCODING: encoding: [0x95,0x44,0x54,0x00] + +x86rotli.w $a0, 1 +# CHECK-INST: x86rotli.w $a0, 1 +# CHECK-ENCODING: encoding: [0x96,0x84,0x54,0x00] + +x86rotli.d $a0, 1 +# CHECK-INST: x86rotli.d $a0, 1 +# CHECK-ENCODING: encoding: [0x97,0x04,0x55,0x00] + +x86rotr.b $a0, $a1 +# CHECK-INST: x86rotr.b $a0, $a1 +# CHECK-ENCODING: encoding: [0x80,0x94,0x3f,0x00] + +x86rotr.h $a0, $a1 +# CHECK-INST: x86rotr.h $a0, $a1 +# CHECK-ENCODING: encoding: [0x81,0x94,0x3f,0x00] + +x86rotr.d $a0, $a1 +# CHECK-INST: x86rotr.d $a0, $a1 +# CHECK-ENCODING: encoding: [0x82,0x94,0x3f,0x00] + +x86rotr.w $a0, $a1 +# CHECK-INST: x86rotr.w $a0, $a1 +# CHECK-ENCODING: encoding: [0x83,0x94,0x3f,0x00] + +x86rotri.b $a0, 1 +# CHECK-INST: x86rotri.b $a0, 1 +# CHECK-ENCODING: encoding: [0x8c,0x24,0x54,0x00] + +x86rotri.h $a0, 1 +# CHECK-INST: x86rotri.h $a0, 1 +# CHECK-ENCODING: encoding: [0x8d,0x44,0x54,0x00] + +x86rotri.w $a0, 1 +# CHECK-INST: x86rotri.w $a0, 1 +# CHECK-ENCODING: encoding: [0x8e,0x84,0x54,0x00] + +x86rotri.d $a0, 1 +# CHECK-INST: x86rotri.d $a0, 1 +# CHECK-ENCODING: encoding: [0x8f,0x04,0x55,0x00] + +x86sll.b $a0, $a1 +# CHECK-INST: x86sll.b $a0, $a1 +# CHECK-ENCODING: encoding: [0x94,0x14,0x3f,0x00] + +x86sll.h $a0, $a1 +# CHECK-INST: x86sll.h $a0, $a1 +# CHECK-ENCODING: encoding: [0x95,0x14,0x3f,0x00] + +x86sll.w $a0, $a1 +# CHECK-INST: x86sll.w $a0, $a1 +# CHECK-ENCODING: encoding: [0x96,0x14,0x3f,0x00] + +x86sll.d $a0, $a1 +# CHECK-INST: x86sll.d $a0, $a1 +# CHECK-ENCODING: encoding: [0x97,0x14,0x3f,0x00] + +x86slli.b $a0, 1 +# CHECK-INST: x86slli.b $a0, 1 +# CHECK-ENCODING: encoding: [0x80,0x24,0x54,0x00] + +x86slli.h $a0, 1 +# CHECK-INST: x86slli.h $a0, 1 +# CHECK-ENCODING: encoding: [0x81,0x44,0x54,0x00] + +x86slli.w $a0, 1 +# CHECK-INST: x86slli.w $a0, 1 +# CHECK-ENCODING: encoding: [0x82,0x84,0x54,0x00] + +x86slli.d $a0, 1 +# CHECK-INST: x86slli.d $a0, 1 +# CHECK-ENCODING: encoding: [0x83,0x04,0x55,0x00] + +x86srl.b $a0, $a1 +# CHECK-INST: x86srl.b $a0, $a1 +# CHECK-ENCODING: encoding: [0x98,0x14,0x3f,0x00] + +x86srl.h $a0, $a1 +# CHECK-INST: x86srl.h $a0, $a1 +# CHECK-ENCODING: encoding: [0x99,0x14,0x3f,0x00] + +x86srl.w $a0, $a1 +# CHECK-INST: x86srl.w $a0, $a1 +# CHECK-ENCODING: encoding: [0x9a,0x14,0x3f,0x00] + +x86srl.d $a0, $a1 +# CHECK-INST: x86srl.d $a0, $a1 +# CHECK-ENCODING: encoding: [0x9b,0x14,0x3f,0x00] + +x86srli.b $a0, 1 +# CHECK-INST: x86srli.b $a0, 1 +# CHECK-ENCODING: encoding: [0x84,0x24,0x54,0x00] + +x86srli.h $a0, 1 +# CHECK-INST: x86srli.h $a0, 1 +# CHECK-ENCODING: encoding: [0x85,0x44,0x54,0x00] + +x86srli.w $a0, 1 +# CHECK-INST: x86srli.w $a0, 1 +# CHECK-ENCODING: encoding: [0x86,0x84,0x54,0x00] + +x86srli.d $a0, 1 +# CHECK-INST: x86srli.d $a0, 1 +# CHECK-ENCODING: encoding: [0x87,0x04,0x55,0x00] + +x86sra.b $a0, $a1 +# CHECK-INST: x86sra.b $a0, $a1 +# CHECK-ENCODING: encoding: [0x9c,0x14,0x3f,0x00] + +x86sra.h $a0, $a1 +# CHECK-INST: x86sra.h $a0, $a1 +# CHECK-ENCODING: encoding: [0x9d,0x14,0x3f,0x00] + +x86sra.w $a0, $a1 +# CHECK-INST: x86sra.w $a0, $a1 +# CHECK-ENCODING: encoding: [0x9e,0x14,0x3f,0x00] + +x86sra.d $a0, $a1 +# CHECK-INST: x86sra.d $a0, $a1 +# CHECK-ENCODING: encoding: [0x9f,0x14,0x3f,0x00] + +x86srai.b $a0, 1 +# CHECK-INST: x86srai.b $a0, 1 +# CHECK-ENCODING: encoding: [0x88,0x24,0x54,0x00] + +x86srai.h $a0, 1 +# CHECK-INST: x86srai.h $a0, 1 +# CHECK-ENCODING: encoding: [0x89,0x44,0x54,0x00] + +x86srai.w $a0, 1 +# CHECK-INST: x86srai.w $a0, 1 +# CHECK-ENCODING: encoding: [0x8a,0x84,0x54,0x00] + +x86srai.d $a0, 1 +# CHECK-INST: x86srai.d $a0, 1 +# CHECK-ENCODING: encoding: [0x8b,0x04,0x55,0x00] diff --git a/llvm/test/MC/LoongArch/lvz/lvz-err.s b/llvm/test/MC/LoongArch/lvz/lvz-err.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/LoongArch/lvz/lvz-err.s @@ -0,0 +1,31 @@ +# RUN: not llvm-mc --triple=loongarch64 %s 2>&1 | FileCheck %s + +gcsrrd $a0, 16384 +# CHECK: :[[#@LINE-1]]:13: error: immediate must be an integer in the range [0, 16383] + +gcsrrd $a0, -1 +# CHECK: :[[#@LINE-1]]:13: error: immediate must be an integer in the range [0, 16383] + +gcsrwr $a0, 16384 +# CHECK: :[[#@LINE-1]]:13: error: immediate must be an integer in the range [0, 16383] + +gcsrwr $a0, -1 +# CHECK: :[[#@LINE-1]]:13: error: immediate must be an integer in the range [0, 16383] + +gcsrxchg $a0, $a1, 16384 +# CHECK: :[[#@LINE-1]]:20: error: immediate must be an integer in the range [0, 16383] + +gcsrxchg $a0, $a1, -1 +# CHECK: :[[#@LINE-1]]:20: error: immediate must be an integer in the range [0, 16383] + +gcsrxchg $a0, $ra, 1 +# CHECK: :[[#@LINE-1]]:16: error: must not be $r0 or $r1 + +gcsrxchg $a0, $zero, 1 +# CHECK: :[[#@LINE-1]]:16: error: must not be $r0 or $r1 + +hvcl 32768 +# CHECK: :[[#@LINE-1]]:6: error: immediate must be an integer in the range [0, 32767] + +hvcl -1 +# CHECK: :[[#@LINE-1]]:6: error: immediate must be an integer in the range [0, 32767] diff --git a/llvm/test/MC/LoongArch/lvz/lvz.s b/llvm/test/MC/LoongArch/lvz/lvz.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/LoongArch/lvz/lvz.s @@ -0,0 +1,24 @@ +# RUN: llvm-mc --triple=loongarch64 --show-encoding %s | \ +# RUN: FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: llvm-mc --triple=loongarch64 --filetype=obj %s | \ +# RUN: llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-INST + +gcsrrd $a0, 1 +# CHECK-INST: gcsrrd $a0, 1 +# CHECK-ENCODING: encoding: [0x04,0x04,0x00,0x05] + +gcsrwr $a0, 1 +# CHECK-INST: gcsrwr $a0, 1 +# CHECK-ENCODING: encoding: [0x24,0x04,0x00,0x05] + +gcsrxchg $a0, $a1, 1 +# CHECK-INST: gcsrxchg $a0, $a1, 1 +# CHECK-ENCODING: encoding: [0xa4,0x04,0x00,0x05] + +gtlbflush +# CHECK-INST: gtlbflush +# CHECK-ENCODING: encoding: [0x01,0x24,0x48,0x06] + +hvcl 1 +# CHECK-INST: hvcl 1 +# CHECK-ENCODING: encoding: [0x01,0x80,0x2b,0x00]