Index: clang/test/Preprocessor/riscv-target-features.c =================================================================== --- clang/test/Preprocessor/riscv-target-features.c +++ clang/test/Preprocessor/riscv-target-features.c @@ -698,28 +698,28 @@ // CHECK-SSAIA-EXT: __riscv_ssaia 1000000{{$}} // RUN: %clang -target riscv32 -menable-experimental-extensions \ -// RUN: -march=rv32izfbfmin0p6 -x c -E -dM %s \ +// RUN: -march=rv32izfbfmin0p8 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZFBFMIN-EXT %s // RUN: %clang -target riscv64 -menable-experimental-extensions \ -// RUN: -march=rv64izfbfmin0p6 -x c -E -dM %s \ +// RUN: -march=rv64izfbfmin0p8 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZFBFMIN-EXT %s -// CHECK-ZFBFMIN-EXT: __riscv_zfbfmin 6000{{$}} +// CHECK-ZFBFMIN-EXT: __riscv_zfbfmin 8000{{$}} // RUN: %clang -target riscv32 -menable-experimental-extensions \ -// RUN: -march=rv32ifzvfbfmin0p6 -x c -E -dM %s \ +// RUN: -march=rv32ifzvfbfmin0p8 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZVFBFMIN-EXT %s // RUN: %clang -target riscv64 -menable-experimental-extensions \ -// RUN: -march=rv64ifzvfbfmin0p6 -x c -E -dM %s \ +// RUN: -march=rv64ifzvfbfmin0p8 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZVFBFMIN-EXT %s -// CHECK-ZVFBFMIN-EXT: __riscv_zvfbfmin 6000{{$}} +// CHECK-ZVFBFMIN-EXT: __riscv_zvfbfmin 8000{{$}} // RUN: %clang -target riscv32 -menable-experimental-extensions \ -// RUN: -march=rv32ifzvfbfwma0p6 -x c -E -dM %s \ +// RUN: -march=rv32ifzvfbfwma0p8 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZVFBFWMA-EXT %s // RUN: %clang -target riscv64 -menable-experimental-extensions \ -// RUN: -march=rv64ifzvfbfwma0p6 -x c -E -dM %s \ +// RUN: -march=rv64ifzvfbfwma0p8 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZVFBFWMA-EXT %s -// CHECK-ZVFBFWMA-EXT: __riscv_zvfbfwma 6000{{$}} +// CHECK-ZVFBFWMA-EXT: __riscv_zvfbfwma 8000{{$}} // RUN: %clang -target riscv32 -menable-experimental-extensions \ // RUN: -march=rv32iv_zvbb1p0_zvkned1p0_zvknhb1p0_zvkt1p0 -x c -E -dM %s -o - \ Index: llvm/lib/Support/RISCVISAInfo.cpp =================================================================== --- llvm/lib/Support/RISCVISAInfo.cpp +++ llvm/lib/Support/RISCVISAInfo.cpp @@ -162,7 +162,7 @@ {"zacas", RISCVExtensionVersion{1, 0}}, {"zfa", RISCVExtensionVersion{0, 2}}, - {"zfbfmin", RISCVExtensionVersion{0, 6}}, + {"zfbfmin", RISCVExtensionVersion{0, 8}}, {"zicond", RISCVExtensionVersion{1, 0}}, @@ -173,8 +173,8 @@ {"zvbb", RISCVExtensionVersion{1, 0}}, {"zvbc", RISCVExtensionVersion{1, 0}}, - {"zvfbfmin", RISCVExtensionVersion{0, 6}}, - {"zvfbfwma", RISCVExtensionVersion{0, 6}}, + {"zvfbfmin", RISCVExtensionVersion{0, 8}}, + {"zvfbfwma", RISCVExtensionVersion{0, 8}}, // vector crypto {"zvkg", RISCVExtensionVersion{1, 0}}, @@ -981,8 +981,8 @@ static const char *ImpliedExtsZve64d[] = {"zve64f", "d"}; static const char *ImpliedExtsZve64f[] = {"zve64x", "zve32f"}; static const char *ImpliedExtsZve64x[] = {"zve32x", "zvl64b"}; -static const char *ImpliedExtsZvfbfmin[] = {"zve32f"}; -static const char *ImpliedExtsZvfbfwma[] = {"zve32f"}; +static const char *ImpliedExtsZvfbfmin[] = {"zve32f", "zfbfmin"}; +static const char *ImpliedExtsZvfbfwma[] = {"zve32f", "zvfbfmin"}; static const char *ImpliedExtsZvfh[] = {"zve32f", "zfhmin"}; static const char *ImpliedExtsZvkn[] = {"zvbb", "zvkned", "zvknhb", "zvkt"}; static const char *ImpliedExtsZvknc[] = {"zvbc", "zvkn"}; Index: llvm/lib/Target/RISCV/RISCVFeatures.td =================================================================== --- llvm/lib/Target/RISCV/RISCVFeatures.td +++ llvm/lib/Target/RISCV/RISCVFeatures.td @@ -661,8 +661,7 @@ FeatureStdExtZfbfmin, FeatureStdExtZvfbfwma), "'Zfh' (Half-Precision Floating-Point) or " "'Zfhmin' (Half-Precision Floating-Point Minimal) or " - "'Zfbfmin' (Scalar BF16 Converts) or " - "'Zvfbfwma' (Vector BF16 widening mul-add)">; + "'Zfbfmin' (Scalar BF16 Converts)">; def FeatureStdExtZacas : SubtargetFeature<"experimental-zacas", "HasStdExtZacas", "true", Index: llvm/lib/Target/RISCV/RISCVSubtarget.h =================================================================== --- llvm/lib/Target/RISCV/RISCVSubtarget.h +++ llvm/lib/Target/RISCV/RISCVSubtarget.h @@ -124,8 +124,7 @@ return hasStdExtZfhOrZfhmin() || hasStdExtZhinxOrZhinxmin(); } bool hasHalfFPLoadStoreMove() const { - return HasStdExtZfh || HasStdExtZfhmin || HasStdExtZfbfmin || - HasStdExtZvfbfwma; + return HasStdExtZfh || HasStdExtZfhmin || HasStdExtZfbfmin; } bool is64Bit() const { return IsRV64; } MVT getXLenVT() const { return XLenVT; } Index: llvm/test/CodeGen/RISCV/attributes.ll =================================================================== --- llvm/test/CodeGen/RISCV/attributes.ll +++ llvm/test/CodeGen/RISCV/attributes.ll @@ -252,9 +252,9 @@ ; RV32ZICOND: .attribute 5, "rv32i2p1_zicond1p0" ; RV32SMAIA: .attribute 5, "rv32i2p1_smaia1p0" ; RV32SSAIA: .attribute 5, "rv32i2p1_ssaia1p0" -; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p6" -; RV32ZVFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin0p6_zvl32b1p0" -; RV32ZVFBFWMA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfwma0p6_zvl32b1p0" +; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p8" +; RV32ZVFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvl32b1p0" +; RV32ZVFBFWMA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvfbfwma0p8_zvl32b1p0" ; RV32ZACAS: .attribute 5, "rv32i2p1_a2p1_zacas1p0" ; RV64M: .attribute 5, "rv64i2p1_m2p0" @@ -339,9 +339,9 @@ ; RV64ZICOND: .attribute 5, "rv64i2p1_zicond1p0" ; RV64SMAIA: .attribute 5, "rv64i2p1_smaia1p0" ; RV64SSAIA: .attribute 5, "rv64i2p1_ssaia1p0" -; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin0p6" -; RV64ZVFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin0p6_zvl32b1p0" -; RV64ZVFBFWMA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfwma0p6_zvl32b1p0" +; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin0p8" +; RV64ZVFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvl32b1p0" +; RV64ZVFBFWMA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvfbfwma0p8_zvl32b1p0" ; RV64ZACAS: .attribute 5, "rv64i2p1_a2p1_zacas1p0" define i32 @addi(i32 %a) { Index: llvm/test/MC/RISCV/attribute-arch.s =================================================================== --- llvm/test/MC/RISCV/attribute-arch.s +++ llvm/test/MC/RISCV/attribute-arch.s @@ -270,14 +270,14 @@ .attribute arch, "rv32i_ssaia1p0" # CHECK: attribute 5, "rv32i2p1_ssaia1p0" -.attribute arch, "rv32i_zfbfmin0p6" -# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p6" +.attribute arch, "rv32i_zfbfmin0p8" +# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p8" -.attribute arch, "rv32i_zvfbfmin0p6" -# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin0p6_zvl32b1p0" +.attribute arch, "rv32i_zvfbfmin0p8" +# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvl32b1p0" -.attribute arch, "rv32i_zvfbfwma0p6" -# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfwma0p6_zvl32b1p0" +.attribute arch, "rv32i_zvfbfwma0p8" +# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvfbfwma0p8_zvl32b1p0" .attribute arch, "rv64i_xsfcie" # CHECK: attribute 5, "rv64i2p1_xsfcie1p0" Index: llvm/test/MC/RISCV/rv64zhinx-invalid.s =================================================================== --- llvm/test/MC/RISCV/rv64zhinx-invalid.s +++ llvm/test/MC/RISCV/rv64zhinx-invalid.s @@ -1,7 +1,7 @@ # RUN: not llvm-mc -triple riscv64 -mattr=+zhinx %s 2>&1 | FileCheck %s # Not support float registers -flh fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts) or 'Zvfbfwma' (Vector BF16 widening mul-add){{$}} +flh fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts){{$}} # Invalid instructions fsh a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction Index: llvm/test/MC/RISCV/rv64zhinxmin-invalid.s =================================================================== --- llvm/test/MC/RISCV/rv64zhinxmin-invalid.s +++ llvm/test/MC/RISCV/rv64zhinxmin-invalid.s @@ -1,7 +1,7 @@ # RUN: not llvm-mc -triple riscv64 -mattr=+zhinxmin %s 2>&1 | FileCheck %s # Not support float registers -flh fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts) or 'Zvfbfwma' (Vector BF16 widening mul-add){{$}} +flh fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts){{$}} # Invalid instructions fsh a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction Index: llvm/test/MC/RISCV/rvv/zvfbfwma.s =================================================================== --- llvm/test/MC/RISCV/rvv/zvfbfwma.s +++ llvm/test/MC/RISCV/rvv/zvfbfwma.s @@ -45,24 +45,24 @@ # CHECK-INST: flh ft0, 12(a0) # CHECK-ENCODING: [0x07,0x10,0xc5,0x00] -# CHECK-ERROR: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts) or 'Zvfbfwma' (Vector BF16 widening mul-add){{$}} +# CHECK-ERROR: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts){{$}} # CHECK-UNKNOWN: 07 10 c5 00 flh f0, 12(a0) # CHECK-INST: fsh ft6, 2047(s4) # CHECK-ENCODING: [0xa7,0x1f,0x6a,0x7e] -# CHECK-ERROR: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts) or 'Zvfbfwma' (Vector BF16 widening mul-add){{$}} +# CHECK-ERROR: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts){{$}} # CHECK-UNKNOWN: a7 1f 6a 7e fsh f6, 2047(s4) # CHECK-INST: fmv.x.h a2, fs7 # CHECK-ENCODING: [0x53,0x86,0x0b,0xe4] -# CHECK-ERROR: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts) or 'Zvfbfwma' (Vector BF16 widening mul-add){{$}} +# CHECK-ERROR: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts){{$}} # CHECK-UNKNOWN: 53 86 0b e4 fmv.x.h a2, fs7 # CHECK-INST: fmv.h.x ft1, a6 # CHECK-ENCODING: [0xd3,0x00,0x08,0xf4] -# CHECK-ERROR: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts) or 'Zvfbfwma' (Vector BF16 widening mul-add){{$}} +# CHECK-ERROR: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts){{$}} # CHECK-UNKNOWN: d3 00 08 f4 fmv.h.x ft1, a6