diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -108,23 +108,49 @@
   ReadVLDX, ReadVMask
 ]>;
 
+class VLESchedMask<string lmul = "WorstCase"> : Sched<[
+  !cast<SchedReadWrite>("WriteVLDE_" # lmul),
+  !cast<SchedRead>("ReadVMergeOp_" # lmul), ReadVLDX, ReadVMask
+]>;
+
 class VSESched<string lmul = "WorstCase"> : Sched<[
   !cast<SchedReadWrite>("WriteVSTE_" #lmul),
   !cast<SchedReadWrite>("ReadVSTEV_" #lmul),
   ReadVSTX, ReadVMask
 ]>;
 
+class VSESchedMask<string lmul = "WorstCase"> : Sched<[
+  !cast<SchedReadWrite>("WriteVSTE_" # lmul),
+  !cast<SchedRead>("ReadVMergeOp_" # lmul),
+  !cast<SchedReadWrite>("ReadVSTEV_" # lmul), ReadVSTX, ReadVMask,
+]>;
+
 class VLSSched<int eew, string emul = "WorstCase"> : Sched<[
   !cast<SchedReadWrite>("WriteVLDS" #eew #"_" #emul),
   ReadVLDX, ReadVLDSX, ReadVMask
 ]>;
 
+class VLSSchedMask<int eew, string emul = "WorstCase"> : Sched<[
+  !cast<SchedReadWrite>("WriteVLDS" # eew #"_" #emul),
+  !cast<SchedRead>("ReadVMergeOp_" # emul # "_E" # eew), ReadVLDX, ReadVLDSX,
+  ReadVMask
+]>;
+
+
 class VSSSched<int eew, string emul = "WorstCase"> : Sched<[
   !cast<SchedReadWrite>("WriteVSTS" #eew #"_" #emul),
   !cast<SchedReadWrite>("ReadVSTS" #eew #"V_" #emul),
   ReadVSTX, ReadVSTSX, ReadVMask
 ]>;
 
+class VSSSchedMask<int eew, string emul = "WorstCase"> : Sched<[
+  !cast<SchedReadWrite>("WriteVSTS" #eew #"_" #emul),
+  !cast<SchedRead>("ReadVMergeOp_" # emul # "_E" # eew),
+  !cast<SchedReadWrite>("ReadVSTS" #eew #"V_" #emul), ReadVSTX, ReadVSTSX,
+  ReadVMask
+]>;
+
+
 class VLXSched<int dataEEW, string isOrdered,
                string dataEMUL = "WorstCase",
                string idxEMUL = "WorstCase"> : Sched<[
@@ -133,6 +159,15 @@
   !cast<SchedReadWrite>("ReadVLD" #isOrdered #"XV_" #idxEMUL), ReadVMask
 ]>;
 
+class VLXSchedMask<int dataEEW, string isOrdered,
+               string dataEMUL = "WorstCase",
+               string idxEMUL = "WorstCase"> : Sched<[
+  !cast<SchedReadWrite>("WriteVLD" #isOrdered #"X" #dataEEW #"_" #dataEMUL),
+  !cast<SchedRead>("ReadVMergeOp_" # dataEMUL # "_E" # dataEEW), ReadVLDX,
+  !cast<SchedReadWrite>("ReadVLD" #isOrdered #"XV_" #idxEMUL), ReadVMask,
+]>;
+
+
 class VSXSched<int dataEEW, string isOrdered,
                string dataEMUL = "WorstCase",
                string idxEMUL = "WorstCase"> : Sched<[
@@ -141,45 +176,101 @@
   ReadVSTX, !cast<SchedReadWrite>("ReadVST" #isOrdered #"XV_" #idxEMUL), ReadVMask
 ]>;
 
+class VSXSchedMask<int dataEEW, string isOrdered,
+               string dataEMUL = "WorstCase",
+               string idxEMUL = "WorstCase"> : Sched<[
+  !cast<SchedReadWrite>("WriteVST" #isOrdered #"X" #dataEEW #"_" #dataEMUL),
+  !cast<SchedRead>("ReadVMergeOp_" # dataEMUL # "_E" # dataEEW),
+  !cast<SchedReadWrite>("ReadVST" #isOrdered #"X" #dataEEW #"_" #dataEMUL),
+  ReadVSTX, !cast<SchedReadWrite>("ReadVST" #isOrdered #"XV_" #idxEMUL),
+  ReadVMask
+]>;
+
+
 class VLFSched<string lmul = "WorstCase"> : Sched<[
   !cast<SchedReadWrite>("WriteVLDFF_" #lmul),
   ReadVLDX, ReadVMask
 ]>;
 
+class VLFSchedMask<string lmul = "WorstCase"> : Sched<[
+  !cast<SchedReadWrite>("WriteVLDFF_" # lmul),
+  !cast<SchedRead>("ReadVMergeOp_" # lmul), ReadVLDX, ReadVMask,
+]>;
+
 // Unit-Stride Segment Loads and Stores
 class VLSEGSched<int nf, int eew, string emul = "WorstCase"> : Sched<[
   !cast<SchedReadWrite>("WriteVLSEG" #nf #"e" #eew #"_" #emul),
   ReadVLDX, ReadVMask
 ]>;
+class VLSEGSchedMask<int nf, int eew, string emul = "WorstCase"> : Sched<[
+  !cast<SchedReadWrite>("WriteVLSEG" #nf #"e" #eew #"_" #emul),
+  !cast<SchedRead>("ReadVMergeOp_" # emul # "_E" # eew), ReadVLDX, ReadVMask
+]>;
+
 class VSSEGSched<int nf, int eew, string emul = "WorstCase"> : Sched<[
   !cast<SchedReadWrite>("WriteVSSEG" #nf #"e" #eew #"_" #emul),
   !cast<SchedReadWrite>("ReadVSTEV_" #emul),
   ReadVSTX, ReadVMask
 ]>;
+class VSSEGSchedMask<int nf, int eew, string emul = "WorstCase"> : Sched<[
+  !cast<SchedReadWrite>("WriteVSSEG" #nf #"e" #eew #"_" #emul),
+  !cast<SchedRead>("ReadVMergeOp_" # emul # "_E" # eew),
+  !cast<SchedReadWrite>("ReadVSTEV_" #emul), ReadVSTX, ReadVMask
+]>;
+
 class VLSEGFFSched<int nf, int eew, string emul = "WorstCase"> : Sched<[
   !cast<SchedReadWrite>("WriteVLSEGFF" #nf #"e" #eew #"_" #emul),
   ReadVLDX, ReadVMask
 ]>;
+class VLSEGFFSchedMask<int nf, int eew, string emul = "WorstCase"> : Sched<[
+  !cast<SchedReadWrite>("WriteVLSEGFF" #nf #"e" #eew #"_" #emul),
+  !cast<SchedRead>("ReadVMergeOp_" # emul # "_E" # eew), ReadVLDX, ReadVMask
+]>;
+
 // Strided Segment Loads and Stores
 class VLSSEGSched<int nf, int eew, string emul = "WorstCase"> : Sched<[
   !cast<SchedReadWrite>("WriteVLSSEG" #nf #"e" #eew #"_" #emul),
   ReadVLDX, ReadVLDSX, ReadVMask
 ]>;
+class VLSSEGSchedMask<int nf, int eew, string emul = "WorstCase"> : Sched<[
+  !cast<SchedReadWrite>("WriteVLSSEG" #nf #"e" #eew #"_" #emul),
+  !cast<SchedRead>("ReadVMergeOp_" # emul # "_E" # eew), ReadVLDX, ReadVLDSX,
+  ReadVMask
+]>;
+
 class VSSSEGSched<int nf, int eew, string emul = "WorstCase"> : Sched<[
   !cast<SchedReadWrite>("WriteVSSSEG" #nf #"e" #eew #"_" #emul),
   !cast<SchedReadWrite>("ReadVSTS" #eew #"V_" #emul),
   ReadVSTX, ReadVSTSX, ReadVMask
 ]>;
+class VSSSEGSchedMask<int nf, int eew, string emul = "WorstCase"> : Sched<[
+  !cast<SchedReadWrite>("WriteVSSSEG" #nf #"e" #eew #"_" #emul),
+  !cast<SchedRead>("ReadVMergeOp_" # emul # "_E" # eew),
+  !cast<SchedReadWrite>("ReadVSTS" #eew #"V_" #emul), ReadVSTX, ReadVSTSX,
+  ReadVMask
+]>;
+
 // Indexed Segment Loads and Stores
 class VLXSEGSched<int nf, int eew, string isOrdered, string emul = "WorstCase"> : Sched<[
   !cast<SchedReadWrite>("WriteVL" #isOrdered #"XSEG" #nf #"e" #eew #"_" #emul),
   ReadVLDX, !cast<SchedReadWrite>("ReadVLD" #isOrdered #"XV_" #emul), ReadVMask
 ]>;
+class VLXSEGSchedMask<int nf, int eew, string isOrdered, string emul = "WorstCase"> : Sched<[
+  !cast<SchedReadWrite>("WriteVL" #isOrdered #"XSEG" #nf #"e" #eew #"_" #emul),
+  !cast<SchedRead>("ReadVMergeOp_" # emul # "_E" # eew), ReadVLDX,
+  !cast<SchedReadWrite>("ReadVLD" #isOrdered #"XV_" #emul), ReadVMask
+]>;
 class VSXSEGSched<int nf, int eew, string isOrdered, string emul = "WorstCase"> : Sched<[
   !cast<SchedReadWrite>("WriteVS" #isOrdered #"XSEG" #nf #"e" #eew #"_" #emul),
   !cast<SchedReadWrite>("ReadVST" #isOrdered #"X" #eew #"_" #emul),
   ReadVSTX, !cast<SchedReadWrite>("ReadVST" #isOrdered #"XV_" #emul), ReadVMask
 ]>;
+class VSXSEGSchedMask<int nf, int eew, string isOrdered, string emul = "WorstCase"> : Sched<[
+  !cast<SchedReadWrite>("WriteVS" #isOrdered #"XSEG" #nf #"e" #eew #"_" #emul),
+  !cast<SchedRead>("ReadVMergeOp_" # emul),
+  !cast<SchedReadWrite>("ReadVST" #isOrdered #"X" #eew #"_" #emul), ReadVSTX,
+  !cast<SchedReadWrite>("ReadVST" #isOrdered #"XV_" #emul), ReadVMask
+]>;
 
 //===----------------------------------------------------------------------===//
 // Instruction class templates
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -253,6 +253,11 @@
                                            true: m.MX));
 }
 
+// Helper subroutine used to insert ToInsert at index 1 of Lst.
+class InsertAtIdx1<list<SchedReadWrite> Lst, SchedReadWrite ToInsert> {
+  list <SchedReadWrite> l = !listconcat([!head(Lst)], [ToInsert], !tail(Lst));
+}
+
 //===----------------------------------------------------------------------===//
 // Vector register and vector group type information.
 //===----------------------------------------------------------------------===//
@@ -1715,7 +1720,7 @@
         def "E" # eew # "_V_" # LInfo # "_MASK" :
           VPseudoUSLoadMask<vreg, eew>,
           RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
-          VLESched<LInfo>;
+          VLESchedMask<LInfo>;
       }
     }
   }
@@ -1733,7 +1738,7 @@
         def "E" # eew # "FF_V_" # LInfo # "_MASK":
           VPseudoUSLoadFFMask<vreg, eew>,
           RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
-          VLFSched<LInfo>;
+          VLFSchedMask<LInfo>;
       }
     }
   }
@@ -1761,7 +1766,7 @@
         def "E" # eew # "_V_" # LInfo # "_MASK" :
           VPseudoSLoadMask<vreg, eew>,
           RISCVMaskedPseudo</*MaskOpIdx*/ 3>,
-          VLSSched<eew, LInfo>;
+          VLSSchedMask<eew, LInfo>;
       }
     }
   }
@@ -1790,7 +1795,7 @@
             def "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo # "_MASK" :
               VPseudoILoadMask<Vreg, IdxVreg, idxEEW, idxEMUL.value, Ordered, HasConstraint>,
               RISCVMaskedPseudo</*MaskOpIdx*/ 3>,
-              VLXSched<dataEEW, Order, DataLInfo, IdxLInfo>;
+              VLXSchedMask<dataEEW, Order, DataLInfo, IdxLInfo>;
           }
         }
       }
@@ -1807,7 +1812,7 @@
         def "E" # eew # "_V_" # LInfo : VPseudoUSStoreNoMask<vreg, eew>,
                                         VSESched<LInfo>;
         def "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoUSStoreMask<vreg, eew>,
-                                                  VSESched<LInfo>;
+                                                  VSESchedMask<LInfo>;
       }
     }
   }
@@ -1833,7 +1838,7 @@
         def "E" # eew # "_V_" # LInfo : VPseudoSStoreNoMask<vreg, eew>,
                                         VSSSched<eew, LInfo>;
         def "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoSStoreMask<vreg, eew>,
-                                                  VSSSched<eew, LInfo>;
+                                                  VSSSchedMask<eew, LInfo>;
       }
     }
   }
@@ -1860,7 +1865,7 @@
               VSXSched<dataEEW, Order, DataLInfo, IdxLInfo>;
             def "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo # "_MASK" :
               VPseudoIStoreMask<Vreg, IdxVreg, idxEEW, idxEMUL.value, Ordered>,
-              VSXSched<dataEEW, Order, DataLInfo, IdxLInfo>;
+              VSXSchedMask<dataEEW, Order, DataLInfo, IdxLInfo>;
           }
         }
       }
@@ -1873,11 +1878,15 @@
     defvar mx = mti.LMul.MX;
     defvar WriteVMPopV_MX = !cast<SchedWrite>("WriteVMPopV_" # mx);
     defvar ReadVMPopV_MX = !cast<SchedRead>("ReadVMPopV_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
+
     let VLMul = mti.LMul.value in {
       def "_M_" # mti.BX : VPseudoUnaryNoMaskGPROut,
-                           Sched<[WriteVMPopV_MX, ReadVMPopV_MX, ReadVMPopV_MX]>;
+                           Sched<[WriteVMPopV_MX, ReadVMPopV_MX,
+                                  ReadVMPopV_MX]>;
       def "_M_" # mti.BX # "_MASK" : VPseudoUnaryMaskGPROut,
-                                     Sched<[WriteVMPopV_MX, ReadVMPopV_MX, ReadVMPopV_MX]>;
+                                     Sched<[WriteVMPopV_MX, ReadVMergeOp_MX,
+                                            ReadVMPopV_MX, ReadVMPopV_MX]>;
     }
   }
 }
@@ -1887,11 +1896,15 @@
     defvar mx = mti.LMul.MX;
     defvar WriteVMFFSV_MX = !cast<SchedWrite>("WriteVMFFSV_" # mx);
     defvar ReadVMFFSV_MX = !cast<SchedRead>("ReadVMFFSV_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
+
     let VLMul = mti.LMul.value in {
       def "_M_" # mti.BX : VPseudoUnaryNoMaskGPROut,
-                           Sched<[WriteVMFFSV_MX, ReadVMFFSV_MX, ReadVMFFSV_MX]>;
+                           Sched<[WriteVMFFSV_MX, ReadVMFFSV_MX,
+                                  ReadVMFFSV_MX]>;
       def "_M_" # mti.BX # "_MASK" : VPseudoUnaryMaskGPROut,
-                                     Sched<[WriteVMFFSV_MX, ReadVMFFSV_MX, ReadVMFFSV_MX]>;
+                                     Sched<[WriteVMFFSV_MX, ReadVMergeOp_MX,
+                                            ReadVMFFSV_MX, ReadVMFFSV_MX]>;
     }
   }
 }
@@ -1902,11 +1915,14 @@
     defvar mx = mti.LMul.MX;
     defvar WriteVMSFSV_MX = !cast<SchedWrite>("WriteVMSFSV_" # mx);
     defvar ReadVMSFSV_MX = !cast<SchedRead>("ReadVMSFSV_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
+
     let VLMul = mti.LMul.value in {
       def "_M_" # mti.BX : VPseudoUnaryNoMask<VR, VR, constraint>,
                            Sched<[WriteVMSFSV_MX, ReadVMSFSV_MX, ReadVMask]>;
       def "_M_" # mti.BX # "_MASK" : VPseudoUnaryMask<VR, VR, constraint>,
-                                     Sched<[WriteVMSFSV_MX, ReadVMSFSV_MX, ReadVMask]>;
+                                     Sched<[WriteVMSFSV_MX, ReadVMergeOp_MX,
+                                            ReadVMSFSV_MX, ReadVMask]>;
     }
   }
 }
@@ -1916,13 +1932,15 @@
     defvar mx = m.MX;
     defvar WriteVMIdxV_MX = !cast<SchedWrite>("WriteVMIdxV_" # mx);
     defvar ReadVMIdxV_MX = !cast<SchedRead>("ReadVMIdxV_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
     let VLMul = m.value in {
       def "_V_" # m.MX : VPseudoNullaryNoMask<m.vrclass>,
                          Sched<[WriteVMIdxV_MX, ReadVMask]>;
       def "_V_" # m.MX # "_MASK" : VPseudoNullaryMask<m.vrclass>,
                                    RISCVMaskedPseudo</*MaskOpIdx*/ 1>,
-                                   Sched<[WriteVMIdxV_MX, ReadVMask]>;
+                                   Sched<[WriteVMIdxV_MX, ReadVMergeOp_MX,
+                                          ReadVMask]>;
     }
   }
 }
@@ -1946,12 +1964,15 @@
     defvar mx = m.MX;
     defvar WriteVMIotV_MX = !cast<SchedWrite>("WriteVMIotV_" # mx);
     defvar ReadVMIotV_MX = !cast<SchedRead>("ReadVMIotV_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
+
     let VLMul = m.value in {
       def "_" # m.MX : VPseudoUnaryNoMask<m.vrclass, VR, constraint>,
                        Sched<[WriteVMIotV_MX, ReadVMIotV_MX, ReadVMask]>;
       def "_" # m.MX # "_MASK" : VPseudoUnaryMask<m.vrclass, VR, constraint>,
                                  RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
-                                 Sched<[WriteVMIotV_MX, ReadVMIotV_MX, ReadVMask]>;
+                                 Sched<[WriteVMIotV_MX, ReadVMergeOp_MX,
+                                        ReadVMIotV_MX, ReadVMask]>;
     }
   }
 }
@@ -1963,12 +1984,15 @@
     let VLMul = m.value in
       foreach e = sews in {
         defvar suffix = "_" # m.MX # "_E" # e;
-        defvar WriteVCompressV_MX_E = !cast<SchedWrite>("WriteVCompressV" # suffix);
-        defvar ReadVCompressV_MX_E = !cast<SchedRead>("ReadVCompressV" # suffix);
+        defvar WriteVCompressV_MX_E =
+          !cast<SchedWrite>("WriteVCompressV" # suffix);
+        defvar ReadVCompressV_MX_E =
+          !cast<SchedRead>("ReadVCompressV" # suffix);
 
         let SEW = e in
         def _VM # suffix : VPseudoUnaryAnyMask<m.vrclass, m.vrclass>,
-                           Sched<[WriteVCompressV_MX_E, ReadVCompressV_MX_E, ReadVCompressV_MX_E]>;
+                           Sched<[WriteVCompressV_MX_E, ReadVCompressV_MX_E,
+                                  ReadVCompressV_MX_E]>;
       }
   }
 }
@@ -1977,15 +2001,19 @@
                          VReg Op1Class,
                          DAGOperand Op2Class,
                          LMULInfo MInfo,
+                         list<SchedReadWrite> ReadWrites,
+                         list<SchedReadWrite> ReadWritesMask,
                          string Constraint = "",
                          int sew = 0> {
   let VLMul = MInfo.value, SEW=sew in {
     defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX);
     def suffix : VPseudoBinaryNoMaskTU<RetClass, Op1Class, Op2Class,
-                                       Constraint>;
+                                       Constraint>,
+                 Sched<ReadWrites>;
     def suffix # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class,
                                                    Constraint>,
-                           RISCVMaskedPseudo</*MaskOpIdx*/ 3>;
+                           RISCVMaskedPseudo</*MaskOpIdx*/ 3>,
+                           Sched<ReadWritesMask>;
   }
 }
 
@@ -1993,19 +2021,23 @@
                                      VReg Op1Class,
                                      DAGOperand Op2Class,
                                      LMULInfo MInfo,
+                                     list<SchedReadWrite> ReadWrites,
+                                     list<SchedReadWrite> ReadWritesMask,
                                      string Constraint = "",
                                      int sew = 0,
                                      int UsesVXRM = 1> {
   let VLMul = MInfo.value, SEW=sew in {
     defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX);
     def suffix : VPseudoBinaryNoMaskRoundingMode<RetClass, Op1Class, Op2Class,
-                                                 Constraint, UsesVXRM>;
+                                                 Constraint, UsesVXRM>,
+                 Sched<ReadWrites>;
     def suffix # "_MASK" : VPseudoBinaryMaskPolicyRoundingMode<RetClass,
                                                                Op1Class,
                                                                Op2Class,
                                                                Constraint,
                                                                UsesVXRM>,
-                           RISCVMaskedPseudo</*MaskOpIdx*/ 3>;
+                           RISCVMaskedPseudo</*MaskOpIdx*/ 3>,
+                           Sched<ReadWritesMask>;
   }
 }
 
@@ -2014,14 +2046,18 @@
                           VReg Op1Class,
                           DAGOperand Op2Class,
                           LMULInfo MInfo,
+                          list<SchedReadWrite> ReadWrites,
+                          list<SchedReadWrite> ReadWritesMask,
                           string Constraint = ""> {
   let VLMul = MInfo.value in {
     def "_" # MInfo.MX : VPseudoBinaryMOutNoMask<RetClass, Op1Class, Op2Class,
-                                                 Constraint>;
+                                                 Constraint>,
+                         Sched<ReadWrites>;
     let ForceTailAgnostic = true in
     def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMOutMask<RetClass, Op1Class,
                                                          Op2Class, Constraint>,
-                                   RISCVMaskedPseudo</*MaskOpIdx*/ 3>;
+                                   RISCVMaskedPseudo</*MaskOpIdx*/ 3>,
+                                   Sched<ReadWritesMask>;
   }
 }
 
@@ -2030,60 +2066,83 @@
                              DAGOperand Op2Class,
                              LMULInfo lmul,
                              LMULInfo emul,
+                             list<SchedReadWrite> ReadWrites,
+                             list<SchedReadWrite> ReadWritesMask,
                              string Constraint = "",
                              int sew = 0> {
   let VLMul = lmul.value, SEW=sew in {
     defvar suffix = !if(sew, "_" # lmul.MX # "_E" # sew, "_" # lmul.MX);
-    def suffix # "_" # emul.MX : VPseudoBinaryNoMaskTU<RetClass, Op1Class, Op2Class,
-                                                       Constraint>;
-    def suffix # "_" # emul.MX # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class,
-                                                                          Constraint>,
-                                                  RISCVMaskedPseudo</*MaskOpIdx*/ 3>;
+    def suffix # "_" # emul.MX :
+      VPseudoBinaryNoMaskTU<RetClass, Op1Class, Op2Class, Constraint>,
+      Sched<ReadWrites>;
+    def suffix # "_" # emul.MX # "_MASK" :
+      VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class, Constraint>,
+                              RISCVMaskedPseudo</*MaskOpIdx*/ 3>,
+      Sched<ReadWritesMask>;
   }
 }
 
 multiclass VPseudoTiedBinary<VReg RetClass,
                              DAGOperand Op2Class,
                              LMULInfo MInfo,
+                             list<SchedReadWrite> ReadWrites,
+                             list<SchedReadWrite> ReadWritesMask,
                              string Constraint = ""> {
   let VLMul = MInfo.value in {
     def "_" # MInfo.MX # "_TIED": VPseudoTiedBinaryNoMask<RetClass, Op2Class,
-                                                          Constraint>;
+                                                          Constraint>,
+                                  Sched<ReadWrites>;
     def "_" # MInfo.MX # "_MASK_TIED" : VPseudoTiedBinaryMask<RetClass, Op2Class,
-                                                         Constraint>;
+                                                              Constraint>,
+                                        Sched<ReadWritesMask>;
   }
 }
 
 multiclass VPseudoTiedBinaryRoundingMode<VReg RetClass,
                                          DAGOperand Op2Class,
                                          LMULInfo MInfo,
+                                         list<SchedReadWrite> ReadWrites,
+                                         list<SchedReadWrite> ReadWritesMask,
                                          string Constraint = ""> {
     let VLMul = MInfo.value in {
     def "_" # MInfo.MX # "_TIED":
-      VPseudoTiedBinaryNoMaskRoundingMode<RetClass, Op2Class, Constraint>;
+      VPseudoTiedBinaryNoMaskRoundingMode<RetClass, Op2Class, Constraint>,
+      Sched<ReadWrites>;
     def "_" # MInfo.MX # "_MASK_TIED" :
-      VPseudoTiedBinaryMaskRoundingMode<RetClass, Op2Class, Constraint>;
+      VPseudoTiedBinaryMaskRoundingMode<RetClass, Op2Class, Constraint>,
+      Sched<ReadWritesMask>;
   }
 }
 
 
-multiclass VPseudoBinaryV_VV<LMULInfo m, string Constraint = "", int sew = 0> {
-  defm _VV : VPseudoBinary<m.vrclass, m.vrclass, m.vrclass, m, Constraint, sew>;
+multiclass VPseudoBinaryV_VV<LMULInfo m, list<SchedReadWrite> ReadWrites,
+                             list<SchedReadWrite> ReadWritesMask,
+                             string Constraint = "", int sew = 0> {
+  defm _VV : VPseudoBinary<m.vrclass, m.vrclass, m.vrclass, m, ReadWrites,
+                           ReadWritesMask, Constraint, sew>;
 }
 
-multiclass VPseudoBinaryV_VV_RM<LMULInfo m, string Constraint = ""> {
-  defm _VV : VPseudoBinaryRoundingMode<m.vrclass, m.vrclass, m.vrclass, m, Constraint>;
+multiclass VPseudoBinaryV_VV_RM<LMULInfo m, list<SchedReadWrite> ReadWrites,
+                             list<SchedReadWrite> ReadWritesMask,
+                             string Constraint = ""> {
+  defm _VV : VPseudoBinaryRoundingMode<m.vrclass, m.vrclass, m.vrclass, m,
+                                       ReadWrites, ReadWritesMask, Constraint>;
 }
 
 // Similar to VPseudoBinaryV_VV, but uses MxListF.
-multiclass VPseudoBinaryFV_VV<LMULInfo m, string Constraint = "", int sew = 0> {
-  defm _VV : VPseudoBinary<m.vrclass, m.vrclass, m.vrclass, m, Constraint, sew>;
+multiclass VPseudoBinaryFV_VV<LMULInfo m, list<SchedReadWrite> ReadWrites,
+                             list<SchedReadWrite> ReadWritesMask,
+                             string Constraint = "", int sew = 0> {
+  defm _VV : VPseudoBinary<m.vrclass, m.vrclass, m.vrclass, m, ReadWrites,
+                           ReadWritesMask, Constraint, sew>;
 }
 
-multiclass VPseudoBinaryFV_VV_RM<LMULInfo m, string Constraint = "", int sew = 0> {
+multiclass VPseudoBinaryFV_VV_RM<LMULInfo m, list<SchedReadWrite> ReadWrites,
+                             list<SchedReadWrite> ReadWritesMask,
+                             string Constraint = "", int sew = 0> {
   defm _VV : VPseudoBinaryRoundingMode<m.vrclass, m.vrclass, m.vrclass, m,
-                                       Constraint, sew,
-                                       /* UsesVXRM = */ 0>;
+                                       ReadWrites, ReadWritesMask, Constraint,
+                                       sew, /* UsesVXRM = */ 0>;
 }
 
 multiclass VPseudoVGTR_VV_EEW<int eew, string Constraint = ""> {
@@ -2098,23 +2157,40 @@
         defvar emul = !cast<LMULInfo>("V_" # emulMX);
         defvar sews = SchedSEWSet<mx>.val;
         foreach e = sews in {
-          defvar WriteVRGatherVV_MX_E = !cast<SchedWrite>("WriteVRGatherVV_" # mx # "_E" # e);
-          defvar ReadVRGatherVV_data_MX_E = !cast<SchedRead>("ReadVRGatherVV_data_" # mx # "_E" # e);
-          defvar ReadVRGatherVV_index_MX_E = !cast<SchedRead>("ReadVRGatherVV_index_" # mx # "_E" # e);
-          defm _VV : VPseudoBinaryEmul<m.vrclass, m.vrclass, emul.vrclass, m, emul, Constraint, e>,
-                     Sched<[WriteVRGatherVV_MX_E, ReadVRGatherVV_data_MX_E, ReadVRGatherVV_index_MX_E]>;
+          defvar WriteVRGatherVV_MX_E =
+            !cast<SchedWrite>("WriteVRGatherVV_" # mx # "_E" # e);
+          defvar ReadVRGatherVV_data_MX_E =
+            !cast<SchedRead>("ReadVRGatherVV_data_" # mx # "_E" # e);
+          defvar ReadVRGatherVV_index_MX_E =
+            !cast<SchedRead>("ReadVRGatherVV_index_" # mx # "_E" # e);
+          defvar ReadVMergeOp_MX_E =
+            !cast<SchedRead>("ReadVMergeOp_" # mx # "_E" # e);
+
+          defvar ReadWrites = [WriteVRGatherVV_MX_E, ReadVRGatherVV_data_MX_E,
+                               ReadVRGatherVV_index_MX_E];
+          defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX_E>.l;
+          defm _VV : VPseudoBinaryEmul<m.vrclass, m.vrclass, emul.vrclass, m,
+                                       emul, ReadWrites, ReadWritesMask,
+                                       Constraint, e>;
         }
       }
     }
   }
 }
 
-multiclass VPseudoBinaryV_VX<LMULInfo m, string Constraint = "", int sew = 0> {
-  defm "_VX" : VPseudoBinary<m.vrclass, m.vrclass, GPR, m, Constraint, sew>;
+multiclass VPseudoBinaryV_VX<LMULInfo m, list<SchedReadWrite> ReadWrites,
+                             list<SchedReadWrite> ReadWritesMask,
+                             string Constraint = "", int sew = 0> {
+  defm "_VX" : VPseudoBinary<m.vrclass, m.vrclass, GPR, m, ReadWrites,
+                             ReadWritesMask, Constraint, sew>;
 }
 
-multiclass VPseudoBinaryV_VX_RM<LMULInfo m, string Constraint = ""> {
-  defm "_VX" : VPseudoBinaryRoundingMode<m.vrclass, m.vrclass, GPR, m, Constraint>;
+multiclass VPseudoBinaryV_VX_RM<LMULInfo m, list<SchedReadWrite> ReadWrites,
+                             list<SchedReadWrite> ReadWritesMask,
+                             string Constraint = ""> {
+  defm "_VX" : VPseudoBinaryRoundingMode<m.vrclass, m.vrclass, GPR, m,
+                                         ReadWrites, ReadWritesMask,
+                                         Constraint>;
 }
 
 multiclass VPseudoVSLD1_VX<string Constraint = ""> {
@@ -2123,23 +2199,36 @@
     defvar WriteVISlide1X_MX = !cast<SchedWrite>("WriteVISlide1X_" # mx);
     defvar ReadVISlideV_MX = !cast<SchedRead>("ReadVISlideV_" # mx);
     defvar ReadVISlideX_MX = !cast<SchedRead>("ReadVISlideX_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-    defm "_VX" : VPseudoBinary<m.vrclass, m.vrclass, GPR, m, Constraint>,
-                 Sched<[WriteVISlide1X_MX, ReadVISlideV_MX, ReadVISlideX_MX, ReadVMask]>;
+    defvar ReadWrites = [WriteVISlide1X_MX, ReadVISlideV_MX, ReadVISlideX_MX,
+                         ReadVMask];
+    defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX>.l;
+    defm "_VX" : VPseudoBinary<m.vrclass, m.vrclass, GPR, m,
+                               ReadWrites, ReadWritesMask, Constraint>;
   }
 }
 
-multiclass VPseudoBinaryV_VF<LMULInfo m, FPR_Info f, string Constraint = "", int sew = 0> {
+multiclass VPseudoBinaryV_VF<LMULInfo m, FPR_Info f,
+                             list<SchedReadWrite> ReadWrites,
+                             list<SchedReadWrite> ReadWritesMask,
+                             string Constraint = "", int sew = 0> {
   defm "_V" # f.FX : VPseudoBinary<m.vrclass, m.vrclass,
-                                   f.fprclass, m, Constraint, sew>;
+                                   f.fprclass, m, ReadWrites, ReadWritesMask,
+                                   Constraint, sew>;
 }
 
-multiclass VPseudoBinaryV_VF_RM<LMULInfo m, FPR_Info f, string Constraint = "", int sew = 0> {
+multiclass VPseudoBinaryV_VF_RM<LMULInfo m, FPR_Info f,
+                             list<SchedReadWrite> ReadWrites,
+                             list<SchedReadWrite> ReadWritesMask,
+                             string Constraint = "", int sew = 0> {
   defm "_V" # f.FX : VPseudoBinaryRoundingMode<m.vrclass, m.vrclass,
-                                               f.fprclass, m, Constraint, sew,
+                                               f.fprclass, m, ReadWrites,
+                                               ReadWritesMask, Constraint, sew,
                                                /* UsesVXRM = */ 0>;
 }
 
+
 multiclass VPseudoVSLD1_VF<string Constraint = ""> {
   foreach f = FPList in {
     foreach m = f.MxList in {
@@ -2147,20 +2236,32 @@
       defvar WriteVFSlide1F_MX = !cast<SchedWrite>("WriteVFSlide1F_" # mx);
       defvar ReadVFSlideV_MX = !cast<SchedRead>("ReadVFSlideV_" # mx);
       defvar ReadVFSlideF_MX = !cast<SchedRead>("ReadVFSlideF_" # mx);
+      defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
+      defvar ReadWrites = [WriteVFSlide1F_MX, ReadVFSlideV_MX, ReadVFSlideF_MX,
+                           ReadVMask];
+      defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX>.l;
       defm "_V" # f.FX :
-        VPseudoBinary<m.vrclass, m.vrclass, f.fprclass, m, Constraint>,
-        Sched<[WriteVFSlide1F_MX, ReadVFSlideV_MX, ReadVFSlideF_MX, ReadVMask]>;
+        VPseudoBinary<m.vrclass, m.vrclass, f.fprclass, m, ReadWrites,
+                      ReadWritesMask, Constraint>;
     }
   }
 }
 
-multiclass VPseudoBinaryV_VI<Operand ImmType = simm5, LMULInfo m, string Constraint = ""> {
-  defm _VI : VPseudoBinary<m.vrclass, m.vrclass, ImmType, m, Constraint>;
+multiclass VPseudoBinaryV_VI<Operand ImmType = simm5, LMULInfo m,
+                             list<SchedReadWrite> ReadWrites,
+                             list<SchedReadWrite> ReadWritesMask,
+                             string Constraint = ""> {
+  defm _VI : VPseudoBinary<m.vrclass, m.vrclass, ImmType, m, ReadWrites,
+                           ReadWritesMask, Constraint>;
 }
 
-multiclass VPseudoBinaryV_VI_RM<Operand ImmType = simm5, LMULInfo m, string Constraint = ""> {
-  defm _VI : VPseudoBinaryRoundingMode<m.vrclass, m.vrclass, ImmType, m, Constraint>;
+multiclass VPseudoBinaryV_VI_RM<Operand ImmType = simm5, LMULInfo m,
+                                list<SchedReadWrite> ReadWrites,
+                                list<SchedReadWrite> ReadWritesMask,
+                                string Constraint = ""> {
+  defm _VI : VPseudoBinaryRoundingMode<m.vrclass, m.vrclass, ImmType, m,
+                                       ReadWrites, ReadWritesMask, Constraint>;
 }
 
 multiclass VPseudoVALU_MM {
@@ -2183,63 +2284,83 @@
 // * The destination EEW is greater than the source EEW, the source EMUL is
 //   at least 1, and the overlap is in the highest-numbered part of the
 //   destination register group is legal. Otherwise, it is illegal.
-multiclass VPseudoBinaryW_VV<LMULInfo m> {
-  defm _VV : VPseudoBinary<m.wvrclass, m.vrclass, m.vrclass, m,
-                           "@earlyclobber $rd">;
+multiclass VPseudoBinaryW_VV<LMULInfo m, list<SchedReadWrite> ReadWrites,
+                             list<SchedReadWrite> ReadWritesMask> {
+  defm _VV : VPseudoBinary<m.wvrclass, m.vrclass, m.vrclass, m, ReadWrites,
+                           ReadWritesMask, "@earlyclobber $rd">;
 }
 
-multiclass VPseudoBinaryW_VV_RM<LMULInfo m> {
+multiclass VPseudoBinaryW_VV_RM<LMULInfo m,
+                                list<SchedReadWrite> ReadWrites,
+                                list<SchedReadWrite> ReadWritesMask> {
   defm _VV : VPseudoBinaryRoundingMode<m.wvrclass, m.vrclass, m.vrclass, m,
+                                       ReadWrites, ReadWritesMask,
                                       "@earlyclobber $rd", /* sew = */ 0,
                                       /* UsesVXRM = */ 0>;
 }
 
-multiclass VPseudoBinaryW_VX<LMULInfo m> {
-  defm "_VX" : VPseudoBinary<m.wvrclass, m.vrclass, GPR, m,
-                             "@earlyclobber $rd">;
+multiclass VPseudoBinaryW_VX<LMULInfo m, list<SchedReadWrite> ReadWrites,
+                             list<SchedReadWrite> ReadWritesMask> {
+  defm "_VX" : VPseudoBinary<m.wvrclass, m.vrclass, GPR, m, ReadWrites,
+                             ReadWritesMask, "@earlyclobber $rd">;
 }
 
-multiclass VPseudoBinaryW_VF<LMULInfo m, FPR_Info f> {
+multiclass VPseudoBinaryW_VF<LMULInfo m, FPR_Info f,
+                             list<SchedReadWrite> ReadWrites,
+                             list<SchedReadWrite> ReadWritesMask> {
   defm "_V" # f.FX : VPseudoBinary<m.wvrclass, m.vrclass,
-                                   f.fprclass, m,
+                                   f.fprclass, m, ReadWrites, ReadWritesMask,
                                    "@earlyclobber $rd">;
 }
 
-multiclass VPseudoBinaryW_VF_RM<LMULInfo m, FPR_Info f> {
+multiclass VPseudoBinaryW_VF_RM<LMULInfo m, FPR_Info f,
+                             list<SchedReadWrite> ReadWrites,
+                             list<SchedReadWrite> ReadWritesMask> {
   defm "_V" # f.FX : VPseudoBinaryRoundingMode<m.wvrclass, m.vrclass,
-                                               f.fprclass, m,
+                                               f.fprclass, m, ReadWrites,
+                                               ReadWritesMask,
                                                "@earlyclobber $rd",
                                                /* sew = */ 0,
                                                /* UsesVXRM = */ 0>;
 }
 
-multiclass VPseudoBinaryW_WV<LMULInfo m> {
-  defm _WV : VPseudoBinary<m.wvrclass, m.wvrclass, m.vrclass, m,
-                           "@earlyclobber $rd">;
-  defm _WV : VPseudoTiedBinary<m.wvrclass, m.vrclass, m,
-                               "@earlyclobber $rd">;
+multiclass VPseudoBinaryW_WV<LMULInfo m, list<SchedReadWrite> ReadWrites,
+                             list<SchedReadWrite> ReadWritesMask> {
+  defm _WV : VPseudoBinary<m.wvrclass, m.wvrclass, m.vrclass, m, ReadWrites,
+                           ReadWritesMask, "@earlyclobber $rd">;
+  defm _WV : VPseudoTiedBinary<m.wvrclass, m.vrclass, m, ReadWrites,
+                               ReadWritesMask, "@earlyclobber $rd">;
 }
 
-multiclass VPseudoBinaryW_WV_RM<LMULInfo m> {
+multiclass VPseudoBinaryW_WV_RM<LMULInfo m, list<SchedReadWrite> ReadWrites,
+                             list<SchedReadWrite> ReadWritesMask> {
   defm _WV : VPseudoBinaryRoundingMode<m.wvrclass, m.wvrclass, m.vrclass, m,
+                                       ReadWrites, ReadWritesMask,
                                        "@earlyclobber $rd", /* sew = */ 0,
                                        /* UsesVXRM = */ 0>;
-  defm _WV : VPseudoTiedBinaryRoundingMode<m.wvrclass, m.vrclass, m,
-                                           "@earlyclobber $rd">;
+  defm _WV : VPseudoTiedBinaryRoundingMode<m.wvrclass, m.vrclass, m, ReadWrites,
+                                           ReadWritesMask, "@earlyclobber $rd">;
 }
 
-multiclass VPseudoBinaryW_WX<LMULInfo m> {
-  defm "_WX" : VPseudoBinary<m.wvrclass, m.wvrclass, GPR, m>;
+multiclass VPseudoBinaryW_WX<LMULInfo m, list<SchedReadWrite> ReadWrites,
+                             list<SchedReadWrite> ReadWritesMask> {
+  defm "_WX" : VPseudoBinary<m.wvrclass, m.wvrclass, GPR, m, ReadWrites,
+                             ReadWritesMask>;
 }
 
-multiclass VPseudoBinaryW_WF<LMULInfo m, FPR_Info f> {
+multiclass VPseudoBinaryW_WF<LMULInfo m, FPR_Info f,
+                             list<SchedReadWrite> ReadWrites,
+                             list<SchedReadWrite> ReadWritesMask> {
   defm "_W" # f.FX : VPseudoBinary<m.wvrclass, m.wvrclass,
-                                   f.fprclass, m>;
+                                   f.fprclass, m, ReadWrites, ReadWritesMask>;
 }
 
-multiclass VPseudoBinaryW_WF_RM<LMULInfo m, FPR_Info f> {
+multiclass VPseudoBinaryW_WF_RM<LMULInfo m, FPR_Info f,
+                                list<SchedReadWrite> ReadWrites,
+                                list<SchedReadWrite> ReadWritesMask> {
   defm "_W" # f.FX : VPseudoBinaryRoundingMode<m.wvrclass, m.wvrclass,
-                                               f.fprclass, m,
+                                               f.fprclass, m, ReadWrites,
+                                               ReadWritesMask,
                                                /* Constraint = */ "",
                                                /* sew = */ 0,
                                                /* UsesVXRM = */ 0>;
@@ -2250,35 +2371,47 @@
 // exception from the spec.
 // "The destination EEW is smaller than the source EEW and the overlap is in the
 //  lowest-numbered part of the source register group."
-multiclass VPseudoBinaryV_WV<LMULInfo m> {
-  defm _WV : VPseudoBinary<m.vrclass, m.wvrclass, m.vrclass, m,
+multiclass VPseudoBinaryV_WV<LMULInfo m, list<SchedReadWrite> ReadWrites,
+                             list<SchedReadWrite> ReadWritesMask> {
+  defm _WV : VPseudoBinary<m.vrclass, m.wvrclass, m.vrclass, m, ReadWrites,
+                           ReadWritesMask,
                            !if(!ge(m.octuple, 8), "@earlyclobber $rd", "")>;
 }
 
-multiclass VPseudoBinaryV_WV_RM<LMULInfo m> {
+multiclass VPseudoBinaryV_WV_RM<LMULInfo m, list<SchedReadWrite> ReadWrites,
+                             list<SchedReadWrite> ReadWritesMask> {
   defm _WV : VPseudoBinaryRoundingMode<m.vrclass, m.wvrclass, m.vrclass, m,
+                                       ReadWrites, ReadWritesMask,
                                        !if(!ge(m.octuple, 8),
                                        "@earlyclobber $rd", "")>;
 }
 
-multiclass VPseudoBinaryV_WX<LMULInfo m> {
-  defm _WX : VPseudoBinary<m.vrclass, m.wvrclass, GPR, m,
+multiclass VPseudoBinaryV_WX<LMULInfo m, list<SchedReadWrite> ReadWrites,
+                             list<SchedReadWrite> ReadWritesMask> {
+  defm _WX : VPseudoBinary<m.vrclass, m.wvrclass, GPR, m, ReadWrites,
+                           ReadWritesMask,
                            !if(!ge(m.octuple, 8), "@earlyclobber $rd", "")>;
 }
 
-multiclass VPseudoBinaryV_WX_RM<LMULInfo m> {
+multiclass VPseudoBinaryV_WX_RM<LMULInfo m, list<SchedReadWrite> ReadWrites,
+                                list<SchedReadWrite> ReadWritesMask> {
   defm _WX : VPseudoBinaryRoundingMode<m.vrclass, m.wvrclass, GPR, m,
+                                       ReadWrites, ReadWritesMask,
                                        !if(!ge(m.octuple, 8),
                                        "@earlyclobber $rd", "")>;
 }
 
-multiclass VPseudoBinaryV_WI<LMULInfo m> {
-  defm _WI : VPseudoBinary<m.vrclass, m.wvrclass, uimm5, m,
+multiclass VPseudoBinaryV_WI<LMULInfo m, list<SchedReadWrite> ReadWrites,
+                             list<SchedReadWrite> ReadWritesMask> {
+  defm _WI : VPseudoBinary<m.vrclass, m.wvrclass, uimm5, m, ReadWrites,
+                           ReadWritesMask,
                            !if(!ge(m.octuple, 8), "@earlyclobber $rd", "")>;
 }
 
-multiclass VPseudoBinaryV_WI_RM<LMULInfo m> {
+multiclass VPseudoBinaryV_WI_RM<LMULInfo m, list<SchedReadWrite> ReadWrites,
+                                list<SchedReadWrite> ReadWritesMask> {
   defm _WI : VPseudoBinaryRoundingMode<m.vrclass, m.wvrclass, uimm5, m,
+                                       ReadWrites, ReadWritesMask,
                                        !if(!ge(m.octuple, 8),
                                        "@earlyclobber $rd", "")>;
 }
@@ -2390,13 +2523,15 @@
     defvar mx = m.MX;
     defvar WriteVFClassV_MX = !cast<SchedWrite>("WriteVFClassV_" # mx);
     defvar ReadVFClassV_MX = !cast<SchedRead>("ReadVFClassV_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
     let VLMul = m.value in {
       def "_V_" # mx : VPseudoUnaryNoMask<m.vrclass, m.vrclass>,
                        Sched<[WriteVFClassV_MX, ReadVFClassV_MX, ReadVMask]>;
       def "_V_" # mx # "_MASK" : VPseudoUnaryMask<m.vrclass, m.vrclass>,
                                  RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
-                                 Sched<[WriteVFClassV_MX, ReadVFClassV_MX, ReadVMask]>;
+                                 Sched<[WriteVFClassV_MX, ReadVFClassV_MX,
+                                        ReadVMask, ReadVMergeOp_MX]>;
     }
   }
 }
@@ -2411,15 +2546,18 @@
         defvar suffix = "_" # mx # "_E" # e;
         defvar WriteVFSqrtV_MX_E = !cast<SchedWrite>("WriteVFSqrtV" # suffix);
         defvar ReadVFSqrtV_MX_E = !cast<SchedRead>("ReadVFSqrtV" # suffix);
+        defvar ReadVMergeOp_MX_E = !cast<SchedRead>("ReadVMergeOp" # suffix);
 
         let SEW = e in {
-          def "_V" # suffix : VPseudoUnaryNoMaskRoundingMode<m.vrclass, m.vrclass>,
-                              Sched<[WriteVFSqrtV_MX_E, ReadVFSqrtV_MX_E,
-                                     ReadVMask]>;
-          def "_V" # suffix # "_MASK" : VPseudoUnaryMaskRoundingMode<m.vrclass, m.vrclass>,
-                                        RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
-                                        Sched<[WriteVFSqrtV_MX_E, ReadVFSqrtV_MX_E,
-                                               ReadVMask]>;
+          def "_V" # suffix :
+            VPseudoUnaryNoMaskRoundingMode<m.vrclass, m.vrclass>,
+            Sched<[WriteVFSqrtV_MX_E, ReadVFSqrtV_MX_E,
+                   ReadVMask]>;
+          def "_V" # suffix # "_MASK" :
+            VPseudoUnaryMaskRoundingMode<m.vrclass, m.vrclass>,
+            RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
+            Sched<[WriteVFSqrtV_MX_E, ReadVFSqrtV_MX_E,
+                   ReadVMask, ReadVMergeOp_MX_E]>;
         }
       }
   }
@@ -2430,13 +2568,15 @@
     defvar mx = m.MX;
     defvar WriteVFRecpV_MX = !cast<SchedWrite>("WriteVFRecpV_" # mx);
     defvar ReadVFRecpV_MX = !cast<SchedRead>("ReadVFRecpV_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
     let VLMul = m.value in {
       def "_V_" # mx : VPseudoUnaryNoMask<m.vrclass, m.vrclass>,
                          Sched<[WriteVFRecpV_MX, ReadVFRecpV_MX, ReadVMask]>;
       def "_V_" # mx # "_MASK" : VPseudoUnaryMask<m.vrclass, m.vrclass>,
                                  RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
-                                 Sched<[WriteVFRecpV_MX, ReadVFRecpV_MX, ReadVMask]>;
+                                 Sched<[WriteVFRecpV_MX, ReadVFRecpV_MX,
+                                        ReadVMask, ReadVMergeOp_MX]>;
     }
   }
 }
@@ -2446,13 +2586,15 @@
     defvar mx = m.MX;
     defvar WriteVFRecpV_MX = !cast<SchedWrite>("WriteVFRecpV_" # mx);
     defvar ReadVFRecpV_MX = !cast<SchedRead>("ReadVFRecpV_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
     let VLMul = m.value in {
       def "_V_" # mx : VPseudoUnaryNoMaskRoundingMode<m.vrclass, m.vrclass>,
                          Sched<[WriteVFRecpV_MX, ReadVFRecpV_MX, ReadVMask]>;
-      def "_V_" # mx # "_MASK" : VPseudoUnaryMaskRoundingMode<m.vrclass, m.vrclass>,
-                                 RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
-                                 Sched<[WriteVFRecpV_MX, ReadVFRecpV_MX, ReadVMask]>;
+      def "_V_" # mx # "_MASK" :
+        VPseudoUnaryMaskRoundingMode<m.vrclass, m.vrclass>,
+        RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
+        Sched<[WriteVFRecpV_MX, ReadVFRecpV_MX, ReadVMask, ReadVMergeOp_MX]>;
     }
   }
 }
@@ -2463,6 +2605,7 @@
     defvar mx = m.MX;
     defvar WriteVExtV_MX = !cast<SchedWrite>("WriteVExtV_" # mx);
     defvar ReadVExtV_MX = !cast<SchedRead>("ReadVExtV_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
     let VLMul = m.value in {
       def "_" # mx : VPseudoUnaryNoMask<m.vrclass, m.f2vrclass, constraints>,
@@ -2470,7 +2613,7 @@
       def "_" # mx # "_MASK" :
         VPseudoUnaryMask<m.vrclass, m.f2vrclass, constraints>,
         RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
-        Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>;
+        Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask, ReadVMergeOp_MX]>;
     }
   }
 }
@@ -2481,6 +2624,7 @@
     defvar mx = m.MX;
     defvar WriteVExtV_MX = !cast<SchedWrite>("WriteVExtV_" # mx);
     defvar ReadVExtV_MX = !cast<SchedRead>("ReadVExtV_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
     let VLMul = m.value in {
       def "_" # mx : VPseudoUnaryNoMask<m.vrclass, m.f4vrclass, constraints>,
@@ -2488,7 +2632,7 @@
       def "_" # mx # "_MASK" :
         VPseudoUnaryMask<m.vrclass, m.f4vrclass, constraints>,
         RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
-        Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>;
+        Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask, ReadVMergeOp_MX]>;
     }
   }
 }
@@ -2499,6 +2643,7 @@
     defvar mx = m.MX;
     defvar WriteVExtV_MX = !cast<SchedWrite>("WriteVExtV_" # mx);
     defvar ReadVExtV_MX = !cast<SchedRead>("ReadVExtV_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
     let VLMul = m.value in {
       def "_" # mx : VPseudoUnaryNoMask<m.vrclass, m.f8vrclass, constraints>,
@@ -2506,7 +2651,7 @@
       def "_" # mx # "_MASK" :
         VPseudoUnaryMask<m.vrclass, m.f8vrclass, constraints>,
         RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
-        Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>;
+        Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask, ReadVMergeOp_MX]>;
     }
   }
 }
@@ -2522,25 +2667,31 @@
 //  lowest-numbered part of the source register group".
 // With LMUL<=1 the source and dest occupy a single register so any overlap
 // is in the lowest-numbered part.
-multiclass VPseudoBinaryM_VV<LMULInfo m> {
-  defm _VV : VPseudoBinaryM<VR, m.vrclass, m.vrclass, m,
+multiclass VPseudoBinaryM_VV<LMULInfo m, list<SchedReadWrite> ReadWrites,
+                          list<SchedReadWrite> ReadWritesMask> {
+  defm _VV : VPseudoBinaryM<VR, m.vrclass, m.vrclass, m, ReadWrites,
+                            ReadWritesMask,
                             !if(!ge(m.octuple, 16), "@earlyclobber $rd", "")>;
 }
 
-multiclass VPseudoBinaryM_VX<LMULInfo m> {
+multiclass VPseudoBinaryM_VX<LMULInfo m, list<SchedReadWrite> ReadWrites,
+                          list<SchedReadWrite> ReadWritesMask> {
   defm "_VX" :
-    VPseudoBinaryM<VR, m.vrclass, GPR, m,
+    VPseudoBinaryM<VR, m.vrclass, GPR, m, ReadWrites, ReadWritesMask,
                    !if(!ge(m.octuple, 16), "@earlyclobber $rd", "")>;
 }
 
-multiclass VPseudoBinaryM_VF<LMULInfo m, FPR_Info f> {
+multiclass VPseudoBinaryM_VF<LMULInfo m, FPR_Info f,
+                             list<SchedReadWrite> ReadWrites,
+                             list<SchedReadWrite> ReadWritesMask> {
   defm "_V" # f.FX :
-    VPseudoBinaryM<VR, m.vrclass, f.fprclass, m,
+    VPseudoBinaryM<VR, m.vrclass, f.fprclass, m, ReadWrites, ReadWritesMask,
                    !if(!ge(m.octuple, 16), "@earlyclobber $rd", "")>;
 }
 
-multiclass VPseudoBinaryM_VI<LMULInfo m> {
-  defm _VI : VPseudoBinaryM<VR, m.vrclass, simm5, m,
+multiclass VPseudoBinaryM_VI<LMULInfo m, list<SchedReadWrite> ReadWrites,
+                             list<SchedReadWrite> ReadWritesMask> {
+  defm _VI : VPseudoBinaryM<VR, m.vrclass, simm5, m, ReadWrites, ReadWritesMask,
                             !if(!ge(m.octuple, 16), "@earlyclobber $rd", "")>;
 }
 
@@ -2552,21 +2703,33 @@
     defvar ReadVRGatherVX_data_MX = !cast<SchedRead>("ReadVRGatherVX_data_" # mx);
     defvar ReadVRGatherVX_index_MX = !cast<SchedRead>("ReadVRGatherVX_index_" # mx);
     defvar ReadVRGatherVI_data_MX = !cast<SchedRead>("ReadVRGatherVI_data_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
+
+    defvar ReadWritesVX = [WriteVRGatherVX_MX, ReadVRGatherVX_data_MX,
+                           ReadVRGatherVX_index_MX, ReadVMask];
+    defvar ReadWritesVXMask = InsertAtIdx1<ReadWritesVX, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryV_VX<m, ReadWritesVX, ReadWritesVXMask, Constraint>;
 
-    defm "" : VPseudoBinaryV_VX<m, Constraint>,
-              Sched<[WriteVRGatherVX_MX, ReadVRGatherVX_data_MX,
-                     ReadVRGatherVX_index_MX, ReadVMask]>;
-    defm "" : VPseudoBinaryV_VI<ImmType, m, Constraint>,
-              Sched<[WriteVRGatherVI_MX, ReadVRGatherVI_data_MX, ReadVMask]>;
+    defvar ReadWritesVI = [WriteVRGatherVI_MX, ReadVRGatherVI_data_MX,
+                           ReadVMask];
+    defvar ReadWritesVIMask = InsertAtIdx1<ReadWritesVI, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryV_VI<ImmType, m, ReadWritesVI, ReadWritesVIMask,
+                                Constraint>;
 
     defvar sews = SchedSEWSet<mx>.val;
     foreach e = sews in {
-      defvar WriteVRGatherVV_MX_E = !cast<SchedWrite>("WriteVRGatherVV_" # mx # "_E" # e);
-      defvar ReadVRGatherVV_data_MX_E = !cast<SchedRead>("ReadVRGatherVV_data_" # mx # "_E" # e);
-      defvar ReadVRGatherVV_index_MX_E = !cast<SchedRead>("ReadVRGatherVV_index_" # mx # "_E" # e);
-      defm "" : VPseudoBinaryV_VV<m, Constraint, e>,
-                Sched<[WriteVRGatherVV_MX_E, ReadVRGatherVV_data_MX_E,
-                       ReadVRGatherVV_index_MX_E, ReadVMask]>;
+      defvar WriteVRGatherVV_MX_E =
+         !cast<SchedWrite>("WriteVRGatherVV_" # mx # "_E" # e);
+      defvar ReadVRGatherVV_data_MX_E =
+         !cast<SchedRead>("ReadVRGatherVV_data_" # mx # "_E" # e);
+      defvar ReadVRGatherVV_index_MX_E =
+         !cast<SchedRead>("ReadVRGatherVV_index_" # mx # "_E" # e);
+      defvar ReadVMergeOp_MX_E = !cast<SchedRead>("ReadVMergeOp_" # mx # "_E" # e);
+
+      defvar ReadWrites = [WriteVRGatherVV_MX_E, ReadVRGatherVV_data_MX_E,
+                           ReadVRGatherVV_index_MX_E, ReadVMask];
+      defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX_E>.l;
+      defm "" : VPseudoBinaryV_VV<m, ReadWrites, ReadWritesMask, Constraint, e>;
     }
   }
 }
@@ -2579,17 +2742,25 @@
     defvar WriteVSALUI_MX = !cast<SchedWrite>("WriteVSALUI_" # mx);
     defvar ReadVSALUV_MX = !cast<SchedRead>("ReadVSALUV_" # mx);
     defvar ReadVSALUX_MX = !cast<SchedRead>("ReadVSALUX_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-    defm "" : VPseudoBinaryV_VV<m, Constraint>,
-              Sched<[WriteVSALUV_MX, ReadVSALUV_MX, ReadVSALUV_MX, ReadVMask]>;
-    defm "" : VPseudoBinaryV_VX<m, Constraint>,
-              Sched<[WriteVSALUX_MX, ReadVSALUV_MX, ReadVSALUX_MX, ReadVMask]>;
-    defm "" : VPseudoBinaryV_VI<ImmType, m, Constraint>,
-              Sched<[WriteVSALUI_MX, ReadVSALUV_MX, ReadVMask]>;
+    defvar ReadWritesVV = [WriteVSALUV_MX, ReadVSALUV_MX, ReadVSALUV_MX,
+                           ReadVMask];
+    defvar ReadWritesVVMask = InsertAtIdx1<ReadWritesVV, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryV_VV<m, ReadWritesVV, ReadWritesVVMask, Constraint>;
+
+    defvar ReadWritesVX = [WriteVSALUX_MX, ReadVSALUV_MX, ReadVSALUX_MX,
+                           ReadVMask];
+    defvar ReadWritesVXMask = InsertAtIdx1<ReadWritesVX, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryV_VX<m, ReadWritesVX, ReadWritesVXMask, Constraint>;
+
+    defvar ReadWritesVI = [WriteVSALUI_MX, ReadVSALUV_MX, ReadVMask];
+    defvar ReadWritesVIMask = InsertAtIdx1<ReadWritesVI, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryV_VI<ImmType, m, ReadWritesVI, ReadWritesVIMask,
+                                Constraint>;
   }
 }
 
-
 multiclass VPseudoVSHT_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
   foreach m = MxList in {
     defvar mx = m.MX;
@@ -2598,13 +2769,22 @@
     defvar WriteVShiftI_MX = !cast<SchedWrite>("WriteVShiftI_" # mx);
     defvar ReadVShiftV_MX = !cast<SchedRead>("ReadVShiftV_" # mx);
     defvar ReadVShiftX_MX = !cast<SchedRead>("ReadVShiftX_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
+
+    defvar ReadWritesVV = [WriteVShiftV_MX, ReadVShiftV_MX, ReadVShiftV_MX,
+                           ReadVMask];
+    defvar ReadWritesVVMask = InsertAtIdx1<ReadWritesVV, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryV_VV<m, ReadWritesVV, ReadWritesVVMask, Constraint>;
 
-    defm "" : VPseudoBinaryV_VV<m, Constraint>,
-              Sched<[WriteVShiftV_MX, ReadVShiftV_MX, ReadVShiftV_MX, ReadVMask]>;
-    defm "" : VPseudoBinaryV_VX<m, Constraint>,
-              Sched<[WriteVShiftX_MX, ReadVShiftV_MX, ReadVShiftX_MX, ReadVMask]>;
-    defm "" : VPseudoBinaryV_VI<ImmType, m, Constraint>,
-              Sched<[WriteVShiftI_MX, ReadVShiftV_MX, ReadVMask]>;
+    defvar ReadWritesVX = [WriteVShiftX_MX, ReadVShiftV_MX, ReadVShiftX_MX,
+                           ReadVMask];
+    defvar ReadWritesVXMask = InsertAtIdx1<ReadWritesVX, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryV_VX<m, ReadWritesVX, ReadWritesVXMask, Constraint>;
+
+    defvar ReadWritesVI = [WriteVShiftI_MX, ReadVShiftV_MX, ReadVMask];
+    defvar ReadWritesVIMask = InsertAtIdx1<ReadWritesVI, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryV_VI<ImmType, m, ReadWritesVI, ReadWritesVIMask,
+                                Constraint>;
   }
 }
 
@@ -2616,13 +2796,24 @@
     defvar WriteVSShiftI_MX = !cast<SchedWrite>("WriteVSShiftI_" # mx);
     defvar ReadVSShiftV_MX = !cast<SchedRead>("ReadVSShiftV_" # mx);
     defvar ReadVSShiftX_MX = !cast<SchedRead>("ReadVSShiftX_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
+
+    defvar ReadWritesVV = [WriteVSShiftV_MX, ReadVSShiftV_MX, ReadVSShiftV_MX,
+                           ReadVMask];
+    defvar ReadWritesVVMask = InsertAtIdx1<ReadWritesVV, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryV_VV_RM<m, ReadWritesVV, ReadWritesVVMask,
+                                   Constraint>;
 
-    defm "" : VPseudoBinaryV_VV_RM<m, Constraint>,
-              Sched<[WriteVSShiftV_MX, ReadVSShiftV_MX, ReadVSShiftV_MX, ReadVMask]>;
-    defm "" : VPseudoBinaryV_VX_RM<m, Constraint>,
-              Sched<[WriteVSShiftX_MX, ReadVSShiftV_MX, ReadVSShiftX_MX, ReadVMask]>;
-    defm "" : VPseudoBinaryV_VI_RM<ImmType, m, Constraint>,
-              Sched<[WriteVSShiftI_MX, ReadVSShiftV_MX, ReadVMask]>;
+    defvar ReadWritesVX = [WriteVSShiftX_MX, ReadVSShiftV_MX, ReadVSShiftX_MX,
+                           ReadVMask];
+    defvar ReadWritesVXMask = InsertAtIdx1<ReadWritesVX, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryV_VX_RM<m, ReadWritesVX, ReadWritesVXMask,
+                                   Constraint>;
+
+    defvar ReadWritesVI = [WriteVSShiftI_MX, ReadVSShiftV_MX, ReadVMask];
+    defvar ReadWritesVIMask = InsertAtIdx1<ReadWritesVI, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryV_VI_RM<ImmType, m, ReadWritesVI, ReadWritesVIMask,
+                                   Constraint>;
   }
 }
 
@@ -2634,13 +2825,22 @@
     defvar WriteVIALUI_MX = !cast<SchedWrite>("WriteVIALUI_" # mx);
     defvar ReadVIALUV_MX = !cast<SchedRead>("ReadVIALUV_" # mx);
     defvar ReadVIALUX_MX = !cast<SchedRead>("ReadVIALUX_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
+
+    defvar ReadWritesVV = [WriteVIALUV_MX, ReadVIALUV_MX, ReadVIALUV_MX,
+                           ReadVMask];
+    defvar ReadWritesVVMask = InsertAtIdx1<ReadWritesVV, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryV_VV<m, ReadWritesVV, ReadWritesVVMask, Constraint>;
 
-    defm "" : VPseudoBinaryV_VV<m, Constraint>,
-            Sched<[WriteVIALUV_MX, ReadVIALUV_MX, ReadVIALUV_MX, ReadVMask]>;
-    defm "" : VPseudoBinaryV_VX<m, Constraint>,
-            Sched<[WriteVIALUX_MX, ReadVIALUV_MX, ReadVIALUX_MX, ReadVMask]>;
-    defm "" : VPseudoBinaryV_VI<ImmType, m, Constraint>,
-            Sched<[WriteVIALUI_MX, ReadVIALUV_MX, ReadVMask]>;
+    defvar ReadWritesVX = [WriteVIALUX_MX, ReadVIALUV_MX, ReadVIALUX_MX,
+                           ReadVMask];
+    defvar ReadWritesVXMask = InsertAtIdx1<ReadWritesVX, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryV_VX<m, ReadWritesVX, ReadWritesVXMask, Constraint>;
+
+    defvar ReadWritesVI = [WriteVIALUI_MX, ReadVIALUV_MX, ReadVMask];
+    defvar ReadWritesVIMask = InsertAtIdx1<ReadWritesVI, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryV_VI<ImmType, m, ReadWritesVI, ReadWritesVIMask,
+                                Constraint>;
   }
 }
 
@@ -2651,11 +2851,17 @@
     defvar WriteVSALUX_MX = !cast<SchedWrite>("WriteVSALUX_" # mx);
     defvar ReadVSALUV_MX = !cast<SchedRead>("ReadVSALUV_" # mx);
     defvar ReadVSALUX_MX = !cast<SchedRead>("ReadVSALUX_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
+
+    defvar ReadWritesVV = [WriteVSALUV_MX, ReadVSALUV_MX, ReadVSALUV_MX,
+                           ReadVMask];
+    defvar ReadWritesVVMask = InsertAtIdx1<ReadWritesVV, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryV_VV<m, ReadWritesVV, ReadWritesVVMask>;
 
-    defm "" : VPseudoBinaryV_VV<m>,
-              Sched<[WriteVSALUV_MX, ReadVSALUV_MX, ReadVSALUV_MX, ReadVMask]>;
-    defm "" : VPseudoBinaryV_VX<m>,
-              Sched<[WriteVSALUX_MX, ReadVSALUV_MX, ReadVSALUX_MX, ReadVMask]>;
+    defvar ReadWritesVX = [WriteVSALUX_MX, ReadVSALUV_MX, ReadVSALUX_MX,
+                           ReadVMask];
+    defvar ReadWritesVXMask = InsertAtIdx1<ReadWritesVX, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryV_VX<m, ReadWritesVX, ReadWritesVXMask>;
   }
 }
 
@@ -2666,11 +2872,17 @@
     defvar WriteVSMulX_MX = !cast<SchedWrite>("WriteVSMulX_" # mx);
     defvar ReadVSMulV_MX = !cast<SchedRead>("ReadVSMulV_" # mx);
     defvar ReadVSMulX_MX = !cast<SchedRead>("ReadVSMulX_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
+
+    defvar ReadWritesVV = [WriteVSMulV_MX, ReadVSMulV_MX, ReadVSMulV_MX,
+                           ReadVMask];
+    defvar ReadWritesVVMask = InsertAtIdx1<ReadWritesVV, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryV_VV_RM<m, ReadWritesVV, ReadWritesVVMask>;
 
-    defm "" : VPseudoBinaryV_VV_RM<m>,
-              Sched<[WriteVSMulV_MX, ReadVSMulV_MX, ReadVSMulV_MX, ReadVMask]>;
-    defm "" : VPseudoBinaryV_VX_RM<m>,
-              Sched<[WriteVSMulX_MX, ReadVSMulV_MX, ReadVSMulX_MX, ReadVMask]>;
+    defvar ReadWritesVX = [WriteVSMulX_MX, ReadVSMulV_MX, ReadVSMulX_MX,
+                           ReadVMask];
+    defvar ReadWritesVXMask = InsertAtIdx1<ReadWritesVX, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryV_VX_RM<m, ReadWritesVX, ReadWritesVXMask>;
   }
 }
 
@@ -2681,11 +2893,16 @@
     defvar WriteVAALUX_MX = !cast<SchedWrite>("WriteVAALUX_" # mx);
     defvar ReadVAALUV_MX = !cast<SchedRead>("ReadVAALUV_" # mx);
     defvar ReadVAALUX_MX = !cast<SchedRead>("ReadVAALUX_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-    defm "" : VPseudoBinaryV_VV_RM<m>,
-              Sched<[WriteVAALUV_MX, ReadVAALUV_MX, ReadVAALUV_MX, ReadVMask]>;
-    defm "" : VPseudoBinaryV_VX_RM<m>,
-              Sched<[WriteVAALUX_MX, ReadVAALUV_MX, ReadVAALUX_MX, ReadVMask]>;
+    defvar ReadWritesVV = [WriteVAALUV_MX, ReadVAALUV_MX, ReadVAALUV_MX,
+                           ReadVMask];
+    defvar ReadWritesVVMask = InsertAtIdx1<ReadWritesVV, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryV_VV_RM<m, ReadWritesVV, ReadWritesVVMask>;
+
+    defvar ReadWritesVX = [WriteVAALUX_MX, ReadVAALUV_MX, ReadVAALUX_MX, ReadVMask];
+    defvar ReadWritesVXMask = InsertAtIdx1<ReadWritesVX, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryV_VX_RM<m, ReadWritesVX, ReadWritesVXMask>;
   }
 }
 
@@ -2696,11 +2913,17 @@
     defvar WriteVIMinMaxX_MX = !cast<SchedWrite>("WriteVIMinMaxX_" # mx);
     defvar ReadVIMinMaxV_MX = !cast<SchedRead>("ReadVIMinMaxV_" # mx);
     defvar ReadVIMinMaxX_MX = !cast<SchedRead>("ReadVIMinMaxX_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
+
+    defvar ReadWritesVV = [WriteVIMinMaxV_MX, ReadVIMinMaxV_MX,
+                           ReadVIMinMaxV_MX, ReadVMask];
+    defvar ReadWritesVVMask = InsertAtIdx1<ReadWritesVV, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryV_VV<m, ReadWritesVV, ReadWritesVVMask>;
 
-    defm "" : VPseudoBinaryV_VV<m>,
-              Sched<[WriteVIMinMaxV_MX, ReadVIMinMaxV_MX, ReadVIMinMaxV_MX, ReadVMask]>;
-    defm "" : VPseudoBinaryV_VX<m>,
-              Sched<[WriteVIMinMaxX_MX, ReadVIMinMaxV_MX, ReadVIMinMaxX_MX, ReadVMask]>;
+    defvar ReadWritesVX = [WriteVIMinMaxX_MX, ReadVIMinMaxV_MX,
+                           ReadVIMinMaxX_MX, ReadVMask];
+    defvar ReadWritesVXMask = InsertAtIdx1<ReadWritesVX, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryV_VX<m, ReadWritesVX, ReadWritesVXMask>;
   }
 }
 
@@ -2711,11 +2934,17 @@
     defvar WriteVIMulX_MX = !cast<SchedWrite>("WriteVIMulX_" # mx);
     defvar ReadVIMulV_MX = !cast<SchedRead>("ReadVIMulV_" # mx);
     defvar ReadVIMulX_MX = !cast<SchedRead>("ReadVIMulX_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-    defm "" : VPseudoBinaryV_VV<m>,
-              Sched<[WriteVIMulV_MX, ReadVIMulV_MX, ReadVIMulV_MX, ReadVMask]>;
-    defm "" : VPseudoBinaryV_VX<m>,
-              Sched<[WriteVIMulX_MX, ReadVIMulV_MX, ReadVIMulX_MX, ReadVMask]>;
+    defvar ReadWritesVV = [WriteVIMulV_MX, ReadVIMulV_MX, ReadVIMulV_MX,
+                           ReadVMask];
+    defvar ReadWritesVVMask = InsertAtIdx1<ReadWritesVV, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryV_VV<m, ReadWritesVV, ReadWritesVVMask>;
+
+    defvar ReadWritesVX = [WriteVIMulX_MX, ReadVIMulV_MX, ReadVIMulX_MX,
+                           ReadVMask];
+    defvar ReadWritesVXMask = InsertAtIdx1<ReadWritesVX, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryV_VX<m, ReadWritesVX, ReadWritesVXMask>;
   }
 }
 
@@ -2724,15 +2953,23 @@
     defvar mx = m.MX;
     defvar sews = SchedSEWSet<mx>.val;
     foreach e = sews in {
-      defvar WriteVIDivV_MX_E = !cast<SchedWrite>("WriteVIDivV_" # mx # "_E" # e);
-      defvar WriteVIDivX_MX_E = !cast<SchedWrite>("WriteVIDivX_" # mx # "_E" # e);
+      defvar WriteVIDivV_MX_E =
+        !cast<SchedWrite>("WriteVIDivV_" # mx # "_E" # e);
+      defvar WriteVIDivX_MX_E =
+        !cast<SchedWrite>("WriteVIDivX_" # mx # "_E" # e);
       defvar ReadVIDivV_MX_E = !cast<SchedRead>("ReadVIDivV_" # mx # "_E" # e);
       defvar ReadVIDivX_MX_E = !cast<SchedRead>("ReadVIDivX_" # mx # "_E" # e);
+      defvar ReadVMergeOp_MX_E = !cast<SchedRead>("ReadVMergeOp_" # mx # "_E" # e);
+
+      defvar ReadWritesVV = [WriteVIDivV_MX_E, ReadVIDivV_MX_E, ReadVIDivV_MX_E,
+                             ReadVMask];
+      defvar ReadWritesVVMask = InsertAtIdx1<ReadWritesVV, ReadVMergeOp_MX_E>.l;
+      defm "" : VPseudoBinaryV_VV<m, ReadWritesVV, ReadWritesVVMask, "", e>;
 
-      defm "" : VPseudoBinaryV_VV<m, "", e>,
-                Sched<[WriteVIDivV_MX_E, ReadVIDivV_MX_E, ReadVIDivV_MX_E, ReadVMask]>;
-      defm "" : VPseudoBinaryV_VX<m, "", e>,
-                Sched<[WriteVIDivX_MX_E, ReadVIDivV_MX_E, ReadVIDivX_MX_E, ReadVMask]>;
+      defvar ReadWritesVX = [WriteVIDivX_MX_E, ReadVIDivV_MX_E, ReadVIDivX_MX_E,
+                             ReadVMask];
+      defvar ReadWritesVXMask = InsertAtIdx1<ReadWritesVX, ReadVMergeOp_MX_E>.l;
+      defm "" : VPseudoBinaryV_VX<m, ReadWritesVX, ReadWritesVXMask, "", e>;
     }
   }
 }
@@ -2742,9 +2979,12 @@
     defvar mx = m.MX;
     defvar WriteVFMulV_MX = !cast<SchedWrite>("WriteVFMulV_" # mx);
     defvar ReadVFMulV_MX = !cast<SchedRead>("ReadVFMulV_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-    defm "" : VPseudoBinaryFV_VV_RM<m>,
-              Sched<[WriteVFMulV_MX, ReadVFMulV_MX, ReadVFMulV_MX, ReadVMask]>;
+    defvar ReadWrites = [WriteVFMulV_MX, ReadVFMulV_MX, ReadVFMulV_MX,
+                         ReadVMask];
+    defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryFV_VV_RM<m, ReadWrites, ReadWritesMask>;
   }
 
   foreach f = FPList in {
@@ -2753,9 +2993,12 @@
       defvar WriteVFMulF_MX = !cast<SchedWrite>("WriteVFMulF_" # mx);
       defvar ReadVFMulV_MX = !cast<SchedRead>("ReadVFMulV_" # mx);
       defvar ReadVFMulF_MX = !cast<SchedRead>("ReadVFMulF_" # mx);
+      defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-      defm "" : VPseudoBinaryV_VF_RM<m, f>,
-                Sched<[WriteVFMulF_MX, ReadVFMulV_MX, ReadVFMulF_MX, ReadVMask]>;
+      defvar ReadWrites = [WriteVFMulF_MX, ReadVFMulV_MX, ReadVFMulF_MX,
+                           ReadVMask];
+      defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX>.l;
+      defm "" : VPseudoBinaryV_VF_RM<m, f, ReadWrites, ReadWritesMask>;
     }
   }
 }
@@ -2767,21 +3010,32 @@
     foreach e = sews in {
       defvar WriteVFDivV_MX_E = !cast<SchedWrite>("WriteVFDivV_" # mx # "_E" # e);
       defvar ReadVFDivV_MX_E = !cast<SchedRead>("ReadVFDivV_" # mx # "_E" # e);
+      defvar ReadVMergeOp_MX_E = !cast<SchedRead>("ReadVMergeOp_" # mx # "_E" # e);
 
-      defm "" : VPseudoBinaryFV_VV_RM<m, "", e>,
-                Sched<[WriteVFDivV_MX_E, ReadVFDivV_MX_E, ReadVFDivV_MX_E, ReadVMask]>;
+      defvar ReadWrites = [WriteVFDivV_MX_E, ReadVFDivV_MX_E, ReadVFDivV_MX_E,
+                           ReadVMask];
+      defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX_E>.l;
+      defm "" : VPseudoBinaryFV_VV_RM<m, ReadWrites, ReadWritesMask, "", e>;
     }
   }
 
   foreach f = FPList in {
     foreach m = f.MxList in {
       defvar mx = m.MX;
-      defvar WriteVFDivF_MX_E = !cast<SchedWrite>("WriteVFDivF_" # mx # "_E" # f.SEW);
-      defvar ReadVFDivV_MX_E = !cast<SchedRead>("ReadVFDivV_" # mx # "_E" # f.SEW);
-      defvar ReadVFDivF_MX_E = !cast<SchedRead>("ReadVFDivF_" # mx # "_E" # f.SEW);
-
-      defm "" : VPseudoBinaryV_VF_RM<m, f, "", f.SEW>,
-                Sched<[WriteVFDivF_MX_E, ReadVFDivV_MX_E, ReadVFDivF_MX_E, ReadVMask]>;
+      defvar WriteVFDivF_MX_E =
+        !cast<SchedWrite>("WriteVFDivF_" # mx # "_E" # f.SEW);
+      defvar ReadVFDivV_MX_E =
+        !cast<SchedRead>("ReadVFDivV_" # mx # "_E" # f.SEW);
+      defvar ReadVFDivF_MX_E =
+        !cast<SchedRead>("ReadVFDivF_" # mx # "_E" # f.SEW);
+      defvar ReadVMergeOp_MX_E =
+        !cast<SchedRead>("ReadVMergeOp_" # mx # "_E" # f.SEW);
+
+      defvar ReadWrites = [WriteVFDivF_MX_E, ReadVFDivV_MX_E, ReadVFDivF_MX_E,
+                           ReadVMask];
+      defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX_E>.l;
+      defm "" : VPseudoBinaryV_VF_RM<m, f, ReadWrites, ReadWritesMask, "",
+                                     f.SEW>;
     }
   }
 }
@@ -2790,12 +3044,20 @@
   foreach f = FPList in {
     foreach m = f.MxList in {
       defvar mx = m.MX;
-      defvar WriteVFDivF_MX_E = !cast<SchedWrite>("WriteVFDivF_" # mx # "_E" # f.SEW);
-      defvar ReadVFDivV_MX_E = !cast<SchedRead>("ReadVFDivV_" # mx # "_E" # f.SEW);
-      defvar ReadVFDivF_MX_E = !cast<SchedRead>("ReadVFDivF_" # mx # "_E" # f.SEW);
-
-      defm "" : VPseudoBinaryV_VF_RM<m, f, "", f.SEW>,
-                Sched<[WriteVFDivF_MX_E, ReadVFDivV_MX_E, ReadVFDivF_MX_E, ReadVMask]>;
+      defvar WriteVFDivF_MX_E =
+        !cast<SchedWrite>("WriteVFDivF_" # mx # "_E" # f.SEW);
+      defvar ReadVFDivV_MX_E =
+        !cast<SchedRead>("ReadVFDivV_" # mx # "_E" # f.SEW);
+      defvar ReadVFDivF_MX_E =
+        !cast<SchedRead>("ReadVFDivF_" # mx # "_E" # f.SEW);
+      defvar ReadVMergeOp_MX_E =
+        !cast<SchedRead>("ReadVMergeOp_" # mx # "_E" # f.SEW);
+
+      defvar ReadWrites = [WriteVFDivF_MX_E, ReadVFDivV_MX_E, ReadVFDivF_MX_E,
+                           ReadVMask];
+      defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX_E>.l;
+      defm "" : VPseudoBinaryV_VF_RM<m, f, ReadWrites, ReadWritesMask, "",
+                                     f.SEW>;
     }
   }
 }
@@ -2807,11 +3069,17 @@
     defvar WriteVIALUX_MX = !cast<SchedWrite>("WriteVIALUV_" # mx);
     defvar ReadVIALUV_MX = !cast<SchedRead>("ReadVIALUV_" # mx);
     defvar ReadVIALUX_MX = !cast<SchedRead>("ReadVIALUX_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-    defm "" : VPseudoBinaryV_VV<m>,
-            Sched<[WriteVIALUV_MX, ReadVIALUV_MX, ReadVIALUV_MX, ReadVMask]>;
-    defm "" : VPseudoBinaryV_VX<m>,
-            Sched<[WriteVIALUX_MX, ReadVIALUV_MX, ReadVIALUX_MX, ReadVMask]>;
+    defvar ReadWritesVV = [WriteVIALUV_MX, ReadVIALUV_MX, ReadVIALUV_MX,
+                           ReadVMask];
+    defvar ReadWritesVVMask = InsertAtIdx1<ReadWritesVV, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryV_VV<m, ReadWritesVV, ReadWritesVVMask>;
+
+    defvar ReadWritesVX = [WriteVIALUX_MX, ReadVIALUV_MX, ReadVIALUX_MX,
+                           ReadVMask];
+    defvar ReadWritesVXMask = InsertAtIdx1<ReadWritesVX, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryV_VX<m, ReadWritesVX, ReadWritesVXMask>;
   }
 }
 
@@ -2820,9 +3088,12 @@
     defvar mx = m.MX;
     defvar WriteVFSgnjV_MX = !cast<SchedWrite>("WriteVFSgnjV_" # mx);
     defvar ReadVFSgnjV_MX = !cast<SchedRead>("ReadVFSgnjV_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-    defm "" : VPseudoBinaryFV_VV<m>,
-              Sched<[WriteVFSgnjV_MX, ReadVFSgnjV_MX, ReadVFSgnjV_MX, ReadVMask]>;
+    defvar ReadWrites = [WriteVFSgnjV_MX, ReadVFSgnjV_MX, ReadVFSgnjV_MX,
+                         ReadVMask];
+    defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryFV_VV<m, ReadWrites, ReadWritesMask>;
   }
 
   foreach f = FPList in {
@@ -2831,9 +3102,12 @@
       defvar WriteVFSgnjF_MX = !cast<SchedWrite>("WriteVFSgnjF_" # mx);
       defvar ReadVFSgnjV_MX = !cast<SchedRead>("ReadVFSgnjV_" # mx);
       defvar ReadVFSgnjF_MX = !cast<SchedRead>("ReadVFSgnjF_" # mx);
+      defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-      defm "" : VPseudoBinaryV_VF<m, f>,
-                Sched<[WriteVFSgnjF_MX, ReadVFSgnjV_MX, ReadVFSgnjF_MX, ReadVMask]>;
+      defvar ReadWrites = [WriteVFSgnjF_MX, ReadVFSgnjV_MX, ReadVFSgnjF_MX,
+                           ReadVMask];
+      defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX>.l;
+      defm "" : VPseudoBinaryV_VF<m, f, ReadWrites, ReadWritesMask>;
     }
   }
 }
@@ -2843,9 +3117,12 @@
     defvar mx = m.MX;
     defvar WriteVFMinMaxV_MX = !cast<SchedWrite>("WriteVFMinMaxV_" # mx);
     defvar ReadVFMinMaxV_MX = !cast<SchedRead>("ReadVFMinMaxV_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-    defm "" : VPseudoBinaryFV_VV<m>,
-              Sched<[WriteVFMinMaxV_MX, ReadVFMinMaxV_MX, ReadVFMinMaxV_MX, ReadVMask]>;
+    defvar ReadWrites = [WriteVFMinMaxV_MX, ReadVFMinMaxV_MX, ReadVFMinMaxV_MX,
+                         ReadVMask];
+    defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryFV_VV<m, ReadWrites, ReadWritesMask>;
   }
 
   foreach f = FPList in {
@@ -2854,9 +3131,12 @@
       defvar WriteVFMinMaxF_MX = !cast<SchedWrite>("WriteVFMinMaxF_" # mx);
       defvar ReadVFMinMaxV_MX = !cast<SchedRead>("ReadVFMinMaxV_" # mx);
       defvar ReadVFMinMaxF_MX = !cast<SchedRead>("ReadVFMinMaxF_" # mx);
+      defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-      defm "" : VPseudoBinaryV_VF<m, f>,
-                Sched<[WriteVFMinMaxF_MX, ReadVFMinMaxV_MX, ReadVFMinMaxF_MX, ReadVMask]>;
+      defvar ReadWrites = [WriteVFMinMaxF_MX, ReadVFMinMaxV_MX,
+                           ReadVFMinMaxF_MX, ReadVMask];
+      defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX>.l;
+      defm "" : VPseudoBinaryV_VF<m, f, ReadWrites, ReadWritesMask>;
     }
   }
 }
@@ -2866,9 +3146,12 @@
     defvar mx = m.MX;
     defvar WriteVFALUV_MX = !cast<SchedWrite>("WriteVFALUV_" # mx);
     defvar ReadVFALUV_MX = !cast<SchedRead>("ReadVFALUV_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-    defm "" : VPseudoBinaryFV_VV<m>,
-              Sched<[WriteVFALUV_MX, ReadVFALUV_MX, ReadVFALUV_MX, ReadVMask]>;
+    defvar ReadWrites = [WriteVFALUV_MX, ReadVFALUV_MX, ReadVFALUV_MX,
+                         ReadVMask];
+    defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryFV_VV<m, ReadWrites, ReadWritesMask>;
   }
 
   foreach f = FPList in {
@@ -2877,8 +3160,12 @@
       defvar WriteVFALUF_MX = !cast<SchedWrite>("WriteVFALUF_" # mx);
       defvar ReadVFALUV_MX = !cast<SchedRead>("ReadVFALUV_" # mx);
       defvar ReadVFALUF_MX = !cast<SchedRead>("ReadVFALUF_" # mx);
-      defm "" : VPseudoBinaryV_VF<m, f>,
-                Sched<[WriteVFALUF_MX, ReadVFALUV_MX, ReadVFALUF_MX, ReadVMask]>;
+      defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
+
+      defvar ReadWrites = [WriteVFALUF_MX, ReadVFALUV_MX, ReadVFALUF_MX,
+                           ReadVMask];
+      defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX>.l;
+      defm "" : VPseudoBinaryV_VF<m, f, ReadWrites, ReadWritesMask>;
     }
   }
 }
@@ -2888,9 +3175,12 @@
     defvar mx = m.MX;
     defvar WriteVFALUV_MX = !cast<SchedWrite>("WriteVFALUV_" # mx);
     defvar ReadVFALUV_MX = !cast<SchedRead>("ReadVFALUV_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-    defm "" : VPseudoBinaryFV_VV_RM<m>,
-              Sched<[WriteVFALUV_MX, ReadVFALUV_MX, ReadVFALUV_MX, ReadVMask]>;
+    defvar ReadWrites = [WriteVFALUV_MX, ReadVFALUV_MX, ReadVFALUV_MX,
+                         ReadVMask];
+    defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryFV_VV_RM<m, ReadWrites, ReadWritesMask>;
   }
 
   foreach f = FPList in {
@@ -2899,8 +3189,12 @@
       defvar WriteVFALUF_MX = !cast<SchedWrite>("WriteVFALUF_" # mx);
       defvar ReadVFALUV_MX = !cast<SchedRead>("ReadVFALUV_" # mx);
       defvar ReadVFALUF_MX = !cast<SchedRead>("ReadVFALUF_" # mx);
-      defm "" : VPseudoBinaryV_VF_RM<m, f>,
-                Sched<[WriteVFALUF_MX, ReadVFALUV_MX, ReadVFALUF_MX, ReadVMask]>;
+      defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
+
+      defvar ReadWrites = [WriteVFALUF_MX, ReadVFALUV_MX, ReadVFALUF_MX,
+                           ReadVMask];
+      defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX>.l;
+      defm "" : VPseudoBinaryV_VF_RM<m, f, ReadWrites, ReadWritesMask>;
     }
   }
 }
@@ -2912,9 +3206,12 @@
       defvar WriteVFALUF_MX = !cast<SchedWrite>("WriteVFALUF_" # mx);
       defvar ReadVFALUV_MX = !cast<SchedRead>("ReadVFALUV_" # mx);
       defvar ReadVFALUF_MX = !cast<SchedRead>("ReadVFALUF_" # mx);
+      defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-      defm "" : VPseudoBinaryV_VF<m, f>,
-                Sched<[WriteVFALUF_MX, ReadVFALUV_MX, ReadVFALUF_MX, ReadVMask]>;
+      defvar ReadWrites = [WriteVFALUF_MX, ReadVFALUV_MX, ReadVFALUF_MX,
+                           ReadVMask];
+      defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX>.l;
+      defm "" : VPseudoBinaryV_VF<m, f, ReadWrites, ReadWritesMask>;
     }
   }
 }
@@ -2926,9 +3223,12 @@
       defvar WriteVFALUF_MX = !cast<SchedWrite>("WriteVFALUF_" # mx);
       defvar ReadVFALUV_MX = !cast<SchedRead>("ReadVFALUV_" # mx);
       defvar ReadVFALUF_MX = !cast<SchedRead>("ReadVFALUF_" # mx);
+      defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-      defm "" : VPseudoBinaryV_VF_RM<m, f>,
-                Sched<[WriteVFALUF_MX, ReadVFALUV_MX, ReadVFALUF_MX, ReadVMask]>;
+      defvar ReadWrites = [WriteVFALUF_MX, ReadVFALUV_MX, ReadVFALUF_MX,
+                           ReadVMask];
+      defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX>.l;
+      defm "" : VPseudoBinaryV_VF_RM<m, f, ReadWrites, ReadWritesMask>;
     }
   }
 }
@@ -2940,11 +3240,16 @@
     defvar WriteVIALUI_MX = !cast<SchedWrite>("WriteVIALUI_" # mx);
     defvar ReadVIALUV_MX = !cast<SchedRead>("ReadVIALUV_" # mx);
     defvar ReadVIALUX_MX = !cast<SchedRead>("ReadVIALUX_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
+
+    defvar ReadWritesVX = [WriteVIALUX_MX, ReadVIALUV_MX, ReadVIALUX_MX,
+                           ReadVMask];
+    defvar ReadWritesVXMask = InsertAtIdx1<ReadWritesVX, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryV_VX<m, ReadWritesVX, ReadWritesVXMask>;
 
-    defm "" : VPseudoBinaryV_VX<m>,
-            Sched<[WriteVIALUX_MX, ReadVIALUV_MX, ReadVIALUX_MX, ReadVMask]>;
-    defm "" : VPseudoBinaryV_VI<ImmType, m>,
-            Sched<[WriteVIALUI_MX, ReadVIALUV_MX, ReadVMask]>;
+    defvar ReadWritesVI = [WriteVIALUI_MX, ReadVIALUV_MX, ReadVMask];
+    defvar ReadWritesVIMask = InsertAtIdx1<ReadWritesVI, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryV_VI<ImmType, m, ReadWritesVI, ReadWritesVIMask>;
   }
 }
 
@@ -2955,11 +3260,17 @@
     defvar WriteVIWALUX_MX = !cast<SchedWrite>("WriteVIWALUX_" # mx);
     defvar ReadVIWALUV_MX = !cast<SchedRead>("ReadVIWALUV_" # mx);
     defvar ReadVIWALUX_MX = !cast<SchedRead>("ReadVIWALUX_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-    defm "" : VPseudoBinaryW_VV<m>,
-            Sched<[WriteVIWALUV_MX, ReadVIWALUV_MX, ReadVIWALUV_MX, ReadVMask]>;
-    defm "" : VPseudoBinaryW_VX<m>,
-            Sched<[WriteVIWALUX_MX, ReadVIWALUV_MX, ReadVIWALUX_MX, ReadVMask]>;
+    defvar ReadWritesVV = [WriteVIWALUV_MX, ReadVIWALUV_MX, ReadVIWALUV_MX,
+                           ReadVMask];
+    defvar ReadWritesVVMask = InsertAtIdx1<ReadWritesVV, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryW_VV<m, ReadWritesVV, ReadWritesVVMask>;
+
+    defvar ReadWritesVX = [WriteVIWALUX_MX, ReadVIWALUV_MX, ReadVIWALUX_MX,
+                           ReadVMask];
+    defvar ReadWritesVXMask = InsertAtIdx1<ReadWritesVX, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryW_VX<m, ReadWritesVX, ReadWritesVXMask>;
   }
 }
 
@@ -2970,11 +3281,17 @@
     defvar WriteVIWMulX_MX = !cast<SchedWrite>("WriteVIWMulX_" # mx);
     defvar ReadVIWMulV_MX = !cast<SchedRead>("ReadVIWMulV_" # mx);
     defvar ReadVIWMulX_MX = !cast<SchedRead>("ReadVIWMulX_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
+
+    defvar ReadWritesVV = [WriteVIWMulV_MX, ReadVIWMulV_MX, ReadVIWMulV_MX,
+                           ReadVMask];
+    defvar ReadWritesVVMask = InsertAtIdx1<ReadWritesVV, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryW_VV<m, ReadWritesVV, ReadWritesVVMask>;
 
-    defm "" : VPseudoBinaryW_VV<m>,
-              Sched<[WriteVIWMulV_MX, ReadVIWMulV_MX, ReadVIWMulV_MX, ReadVMask]>;
-    defm "" : VPseudoBinaryW_VX<m>,
-              Sched<[WriteVIWMulX_MX, ReadVIWMulV_MX, ReadVIWMulX_MX, ReadVMask]>;
+    defvar ReadWritesVX = [WriteVIWMulX_MX, ReadVIWMulV_MX, ReadVIWMulX_MX,
+                           ReadVMask];
+    defvar ReadWritesVXMask = InsertAtIdx1<ReadWritesVX, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryW_VX<m, ReadWritesVX, ReadWritesVXMask>;
   }
 }
 
@@ -2983,9 +3300,12 @@
     defvar mx = m.MX;
     defvar WriteVFWMulV_MX = !cast<SchedWrite>("WriteVFWMulV_" # mx);
     defvar ReadVFWMulV_MX = !cast<SchedRead>("ReadVFWMulV_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-    defm "" : VPseudoBinaryW_VV_RM<m>,
-              Sched<[WriteVFWMulV_MX, ReadVFWMulV_MX, ReadVFWMulV_MX, ReadVMask]>;
+    defvar ReadWrites = [WriteVFWMulV_MX, ReadVFWMulV_MX, ReadVFWMulV_MX,
+                         ReadVMask];
+    defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryW_VV_RM<m, ReadWrites, ReadWritesMask>;
   }
 
   foreach f = FPListW in {
@@ -2994,9 +3314,12 @@
       defvar WriteVFWMulF_MX = !cast<SchedWrite>("WriteVFWMulF_" # mx);
       defvar ReadVFWMulV_MX = !cast<SchedRead>("ReadVFWMulV_" # mx);
       defvar ReadVFWMulF_MX = !cast<SchedRead>("ReadVFWMulF_" # mx);
+      defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-      defm "" : VPseudoBinaryW_VF_RM<m, f>,
-                Sched<[WriteVFWMulF_MX, ReadVFWMulV_MX, ReadVFWMulF_MX, ReadVMask]>;
+      defvar ReadWrites = [WriteVFWMulF_MX, ReadVFWMulV_MX, ReadVFWMulF_MX,
+                           ReadVMask];
+      defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX>.l;
+      defm "" : VPseudoBinaryW_VF_RM<m, f, ReadWrites, ReadWritesMask>;
     }
   }
 }
@@ -3008,11 +3331,17 @@
     defvar WriteVIWALUX_MX = !cast<SchedWrite>("WriteVIWALUX_" # mx);
     defvar ReadVIWALUV_MX = !cast<SchedRead>("ReadVIWALUV_" # mx);
     defvar ReadVIWALUX_MX = !cast<SchedRead>("ReadVIWALUX_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-    defm "" : VPseudoBinaryW_WV<m>,
-              Sched<[WriteVIWALUV_MX, ReadVIWALUV_MX, ReadVIWALUV_MX, ReadVMask]>;
-    defm "" : VPseudoBinaryW_WX<m>,
-              Sched<[WriteVIWALUX_MX, ReadVIWALUV_MX, ReadVIWALUX_MX, ReadVMask]>;
+    defvar ReadWritesWV = [WriteVIWALUV_MX, ReadVIWALUV_MX, ReadVIWALUV_MX,
+                           ReadVMask];
+    defvar ReadWritesWVMask = InsertAtIdx1<ReadWritesWV, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryW_WV<m, ReadWritesWV, ReadWritesWVMask>;
+
+    defvar ReadWritesWX = [WriteVIWALUX_MX, ReadVIWALUV_MX, ReadVIWALUX_MX,
+                           ReadVMask];
+    defvar ReadWritesWXMask = InsertAtIdx1<ReadWritesWX, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryW_WX<m, ReadWritesWX, ReadWritesWXMask>;
   }
 }
 
@@ -3021,9 +3350,12 @@
     defvar mx = m.MX;
     defvar WriteVFWALUV_MX = !cast<SchedWrite>("WriteVFWALUV_" # mx);
     defvar ReadVFWALUV_MX = !cast<SchedRead>("ReadVFWALUV_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-    defm "" : VPseudoBinaryW_VV_RM<m>,
-              Sched<[WriteVFWALUV_MX, ReadVFWALUV_MX, ReadVFWALUV_MX, ReadVMask]>;
+    defvar ReadWrites = [WriteVFWALUV_MX, ReadVFWALUV_MX, ReadVFWALUV_MX,
+                         ReadVMask];
+    defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryW_VV_RM<m, ReadWrites, ReadWritesMask>;
   }
 
   foreach f = FPListW in {
@@ -3032,9 +3364,12 @@
       defvar WriteVFWALUF_MX = !cast<SchedWrite>("WriteVFWALUF_" # mx);
       defvar ReadVFWALUV_MX = !cast<SchedRead>("ReadVFWALUV_" # mx);
       defvar ReadVFWALUF_MX = !cast<SchedRead>("ReadVFWALUF_" # mx);
+      defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-      defm "" : VPseudoBinaryW_VF_RM<m, f>,
-                Sched<[WriteVFWALUF_MX, ReadVFWALUV_MX, ReadVFWALUF_MX, ReadVMask]>;
+      defvar ReadWrites = [WriteVFWALUF_MX, ReadVFWALUV_MX, ReadVFWALUF_MX,
+                           ReadVMask];
+      defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX>.l;
+      defm "" : VPseudoBinaryW_VF_RM<m, f, ReadWrites, ReadWritesMask>;
     }
   }
 }
@@ -3044,9 +3379,12 @@
     defvar mx = m.MX;
     defvar WriteVFWALUV_MX = !cast<SchedWrite>("WriteVFWALUV_" # mx);
     defvar ReadVFWALUV_MX = !cast<SchedRead>("ReadVFWALUV_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-    defm "" : VPseudoBinaryW_WV_RM<m>,
-              Sched<[WriteVFWALUV_MX, ReadVFWALUV_MX, ReadVFWALUV_MX, ReadVMask]>;
+    defvar ReadWrites = [WriteVFWALUV_MX, ReadVFWALUV_MX, ReadVFWALUV_MX,
+                         ReadVMask];
+    defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryW_WV_RM<m, ReadWrites, ReadWritesMask>;
   }
   foreach f = FPListW in {
     foreach m = f.MxListFW in {
@@ -3054,9 +3392,12 @@
       defvar WriteVFWALUF_MX = !cast<SchedWrite>("WriteVFWALUF_" # mx);
       defvar ReadVFWALUV_MX = !cast<SchedRead>("ReadVFWALUV_" # mx);
       defvar ReadVFWALUF_MX = !cast<SchedRead>("ReadVFWALUF_" # mx);
+      defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-      defm "" : VPseudoBinaryW_WF_RM<m, f>,
-                Sched<[WriteVFWALUF_MX, ReadVFWALUV_MX, ReadVFWALUF_MX, ReadVMask]>;
+      defvar ReadWrites = [WriteVFWALUF_MX, ReadVFWALUV_MX, ReadVFWALUF_MX,
+                           ReadVMask];
+      defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX>.l;
+      defm "" : VPseudoBinaryW_WF_RM<m, f, ReadWrites, ReadWritesMask>;
     }
   }
 }
@@ -3192,13 +3533,22 @@
     defvar WriteVNClipI_MX = !cast<SchedWrite>("WriteVNClipI_" # mx);
     defvar ReadVNClipV_MX = !cast<SchedRead>("ReadVNClipV_" # mx);
     defvar ReadVNClipX_MX = !cast<SchedRead>("ReadVNClipX_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
+
+    defvar ReadWritesWV = [WriteVNClipV_MX, ReadVNClipV_MX, ReadVNClipV_MX,
+                           ReadVMask];
+    defvar ReadWritesWVMask = InsertAtIdx1<ReadWritesWV, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryV_WV_RM<m, ReadWritesWV, ReadWritesWVMask>;
+
+    defvar ReadWritesWX = [WriteVNClipX_MX, ReadVNClipV_MX, ReadVNClipX_MX,
+                           ReadVMask];
+    defvar ReadWritesWXMask = InsertAtIdx1<ReadWritesWX, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryV_WX_RM<m, ReadWritesWX, ReadWritesWXMask>;
 
-    defm "" : VPseudoBinaryV_WV_RM<m>,
-              Sched<[WriteVNClipV_MX, ReadVNClipV_MX, ReadVNClipV_MX, ReadVMask]>;
-    defm "" : VPseudoBinaryV_WX_RM<m>,
-              Sched<[WriteVNClipX_MX, ReadVNClipV_MX, ReadVNClipX_MX, ReadVMask]>;
-    defm "" : VPseudoBinaryV_WI_RM<m>,
-              Sched<[WriteVNClipI_MX, ReadVNClipV_MX, ReadVMask]>;
+    defvar ReadWritesWI = [WriteVNClipI_MX, ReadVNClipV_MX,
+                           ReadVMask];
+    defvar ReadWritesWIMask = InsertAtIdx1<ReadWritesWI, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryV_WI_RM<m, ReadWritesWI, ReadWritesWIMask>;
   }
 }
 
@@ -3210,13 +3560,22 @@
     defvar WriteVNShiftI_MX = !cast<SchedWrite>("WriteVNShiftI_" # mx);
     defvar ReadVNShiftV_MX = !cast<SchedRead>("ReadVNShiftV_" # mx);
     defvar ReadVNShiftX_MX = !cast<SchedRead>("ReadVNShiftX_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-    defm "" : VPseudoBinaryV_WV<m>,
-              Sched<[WriteVNShiftV_MX, ReadVNShiftV_MX, ReadVNShiftV_MX, ReadVMask]>;
-    defm "" : VPseudoBinaryV_WX<m>,
-              Sched<[WriteVNShiftX_MX, ReadVNShiftV_MX, ReadVNShiftX_MX, ReadVMask]>;
-    defm "" : VPseudoBinaryV_WI<m>,
-              Sched<[WriteVNShiftI_MX, ReadVNShiftV_MX, ReadVMask]>;
+    defvar ReadWritesWV = [WriteVNShiftV_MX, ReadVNShiftV_MX, ReadVNShiftV_MX,
+                           ReadVMask];
+    defvar ReadWritesWVMask = InsertAtIdx1<ReadWritesWV, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryV_WV<m, ReadWritesWV, ReadWritesWVMask>;
+
+    defvar ReadWritesWX = [WriteVNShiftX_MX, ReadVNShiftV_MX, ReadVNShiftX_MX,
+                           ReadVMask];
+    defvar ReadWritesWXMask = InsertAtIdx1<ReadWritesWX, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryV_WX<m, ReadWritesWX, ReadWritesWXMask>;
+
+    defvar ReadWritesWI = [WriteVNShiftI_MX, ReadVNShiftV_MX,
+                           ReadVMask];
+    defvar ReadWritesWIMask = InsertAtIdx1<ReadWritesWI, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryV_WI<m, ReadWritesWI, ReadWritesWIMask>;
   }
 }
 
@@ -3225,13 +3584,20 @@
                                           DAGOperand Op2Class,
                                           LMULInfo MInfo,
                                           int sew,
+                                          list<SchedReadWrite> ReadWrites,
+                                          list<SchedReadWrite> ReadWritesMask,
                                           string Constraint = "",
                                           bit Commutable = 0> {
   let VLMul = MInfo.value in {
     defvar mx = MInfo.MX;
     let isCommutable = Commutable in
-    def "_" # mx # "_E" # sew : VPseudoTernaryNoMaskWithPolicy<RetClass, Op1Class, Op2Class, Constraint>;
-    def "_" # mx # "_E" # sew # "_MASK" : VPseudoTernaryMaskPolicy<RetClass, Op1Class, Op2Class, Constraint>;
+    def "_" # mx # "_E" # sew
+      : VPseudoTernaryNoMaskWithPolicy<RetClass, Op1Class, Op2Class,
+                                       Constraint>,
+        Sched<ReadWrites>;
+    def "_" # mx # "_E" # sew # "_MASK"
+      : VPseudoTernaryMaskPolicy<RetClass, Op1Class, Op2Class, Constraint>,
+        Sched<ReadWritesMask>;
   }
 }
 
@@ -3240,6 +3606,8 @@
                                           DAGOperand Op2Class,
                                           LMULInfo MInfo,
                                           int sew,
+                                          list<SchedReadWrite> ReadWrites,
+                                          list<SchedReadWrite> ReadWritesMask,
                                           string Constraint = "",
                                           bit Commutable = 0> {
   let VLMul = MInfo.value in {
@@ -3247,10 +3615,12 @@
     let isCommutable = Commutable in
     def "_" # mx # "_E" # sew
         : VPseudoTernaryNoMaskWithPolicyRoundingMode<RetClass, Op1Class, 
-                                                     Op2Class, Constraint>;
+                                                     Op2Class, Constraint>,
+          Sched<ReadWrites>;
     def "_" # mx # "_E" # sew # "_MASK"
         : VPseudoTernaryMaskPolicyRoundingMode<RetClass, Op1Class,
-                                               Op2Class, Constraint>;
+                                               Op2Class, Constraint>,
+          Sched<ReadWritesMask>;
   }
 }
 
@@ -3258,110 +3628,161 @@
                                     RegisterClass Op1Class,
                                     DAGOperand Op2Class,
                                     LMULInfo MInfo,
+                                    list<SchedReadWrite> ReadWrites,
+                                    list<SchedReadWrite> ReadWritesMask,
                                     string Constraint = "",
                                     bit Commutable = 0> {
   let VLMul = MInfo.value in {
     let isCommutable = Commutable in
-    def "_" # MInfo.MX : VPseudoTernaryNoMaskWithPolicy<RetClass, Op1Class, Op2Class, Constraint>;
-    def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class, Constraint>,
-                                   RISCVMaskedPseudo</*MaskOpIdx*/ 3>;
+    def "_" # MInfo.MX
+      : VPseudoTernaryNoMaskWithPolicy<RetClass, Op1Class, Op2Class,
+                                       Constraint>,
+        Sched<ReadWrites>;
+    def "_" # MInfo.MX # "_MASK"
+      : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class, Constraint>,
+        RISCVMaskedPseudo</*MaskOpIdx*/ 3>,
+        Sched<ReadWritesMask>;
   }
 }
 
-multiclass VPseudoTernaryWithPolicyRoundingMode<VReg RetClass,
-                                                RegisterClass Op1Class,
-                                                DAGOperand Op2Class,
-                                                LMULInfo MInfo,
-                                                string Constraint = "",
-                                                bit Commutable = 0> {
+multiclass VPseudoTernaryWithPolicyRoundingMode<
+    VReg RetClass, RegisterClass Op1Class, DAGOperand Op2Class, LMULInfo MInfo,
+    list<SchedReadWrite> ReadWrites, list<SchedReadWrite> ReadWritesMask,
+    string Constraint = "", bit Commutable = 0> {
   let VLMul = MInfo.value in {
     let isCommutable = Commutable in
     def "_" # MInfo.MX :
         VPseudoTernaryNoMaskWithPolicyRoundingMode<RetClass, Op1Class,
-                                                   Op2Class, Constraint>;
+                                                   Op2Class, Constraint>,
+        Sched<ReadWrites>;
     def "_" # MInfo.MX # "_MASK" :
         VPseudoBinaryMaskPolicyRoundingMode<RetClass, Op1Class,
                                             Op2Class, Constraint,
                                             /* UsesVXRM = */ 0>,
-                                   RISCVMaskedPseudo</*MaskOpIdx*/ 3>;
+        RISCVMaskedPseudo</*MaskOpIdx*/ 3>,
+        Sched<ReadWritesMask>;
   }
 }
 
-multiclass VPseudoTernaryV_VV_AAXA<LMULInfo m, string Constraint = ""> {
+multiclass VPseudoTernaryV_VV_AAXA<LMULInfo m, list<SchedReadWrite> ReadWrites,
+                                   list<SchedReadWrite> ReadWritesMask,
+                                   string Constraint = ""> {
   defm _VV : VPseudoTernaryWithPolicy<m.vrclass, m.vrclass, m.vrclass, m,
+                                      ReadWrites, ReadWritesMask,
                                       Constraint, /*Commutable*/1>;
 }
 
-multiclass VPseudoTernaryV_VV_AAXA_RM<LMULInfo m, string Constraint = ""> {
-  defm _VV : VPseudoTernaryWithPolicyRoundingMode<m.vrclass, m.vrclass, m.vrclass, m,
-                                                  Constraint, /*Commutable*/1>;
+multiclass VPseudoTernaryV_VV_AAXA_RM<
+    LMULInfo m, list<SchedReadWrite> ReadWrites,
+    list<SchedReadWrite> ReadWritesMask, string Constraint = ""> {
+  defm _VV : VPseudoTernaryWithPolicyRoundingMode<m.vrclass, m.vrclass,
+                                                  m.vrclass, m, ReadWrites,
+                                                  ReadWritesMask, Constraint,
+                                                  /*Commutable*/1>;
 }
 
-multiclass VPseudoTernaryV_VX_AAXA<LMULInfo m, string Constraint = ""> {
+multiclass VPseudoTernaryV_VX_AAXA<LMULInfo m, list<SchedReadWrite> ReadWrites,
+                                   list<SchedReadWrite> ReadWritesMask,
+                                   string Constraint = ""> {
   defm "_VX" : VPseudoTernaryWithPolicy<m.vrclass, GPR, m.vrclass, m,
-                                        Constraint, /*Commutable*/1>;
+                                        ReadWrites, ReadWritesMask, Constraint,
+                                        /*Commutable*/1>;
 }
 
-multiclass VPseudoTernaryV_VF_AAXA<LMULInfo m, FPR_Info f, string Constraint = ""> {
+multiclass VPseudoTernaryV_VF_AAXA<
+    LMULInfo m, FPR_Info f, list<SchedReadWrite> ReadWrites,
+    list<SchedReadWrite> ReadWritesMask, string Constraint = ""> {
   defm "_V" # f.FX : VPseudoTernaryWithPolicy<m.vrclass, f.fprclass,
-                                              m.vrclass, m, Constraint,
+                                              m.vrclass, m, ReadWrites,
+                                              ReadWritesMask, Constraint,
                                               /*Commutable*/1>;
 }
 
-multiclass VPseudoTernaryV_VF_AAXA_RM<LMULInfo m, FPR_Info f, string Constraint = ""> {
+multiclass VPseudoTernaryV_VF_AAXA_RM<
+    LMULInfo m, FPR_Info f, list<SchedReadWrite> ReadWrites,
+    list<SchedReadWrite> ReadWritesMask, string Constraint = ""> {
   defm "_V" # f.FX : VPseudoTernaryWithPolicyRoundingMode<m.vrclass, f.fprclass,
-                                                          m.vrclass, m, Constraint,
+                                                          m.vrclass, m,
+                                                          ReadWrites,
+                                                          ReadWritesMask,
+                                                          Constraint,
                                                           /*Commutable*/1>;
 }
 
-multiclass VPseudoTernaryW_VV<LMULInfo m> {
+multiclass VPseudoTernaryW_VV<LMULInfo m, list<SchedReadWrite> ReadWrites,
+                              list<SchedReadWrite> ReadWritesMask> {
   defvar constraint = "@earlyclobber $rd";
   defm _VV : VPseudoTernaryWithPolicy<m.wvrclass, m.vrclass, m.vrclass, m,
-                                      constraint>;
+                                      ReadWrites, ReadWritesMask, constraint>;
 }
 
-multiclass VPseudoTernaryW_VV_RM<LMULInfo m> {
+multiclass VPseudoTernaryW_VV_RM<LMULInfo m, list<SchedReadWrite> ReadWrites,
+                              list<SchedReadWrite> ReadWritesMask> {
   defvar constraint = "@earlyclobber $rd";
-  defm _VV : VPseudoTernaryWithPolicyRoundingMode<m.wvrclass, m.vrclass, m.vrclass, m,
+  defm _VV : VPseudoTernaryWithPolicyRoundingMode<m.wvrclass, m.vrclass,
+                                                  m.vrclass, m, ReadWrites,
+                                                  ReadWritesMask,
                                                   constraint>;
 }
 
-multiclass VPseudoTernaryW_VX<LMULInfo m> {
+multiclass VPseudoTernaryW_VX<LMULInfo m, list<SchedReadWrite> ReadWrites,
+                              list<SchedReadWrite> ReadWritesMask> {
   defvar constraint = "@earlyclobber $rd";
   defm "_VX" : VPseudoTernaryWithPolicy<m.wvrclass, GPR, m.vrclass, m,
-                                        constraint>;
+                                        ReadWrites, ReadWritesMask, constraint>;
 }
 
-multiclass VPseudoTernaryW_VF<LMULInfo m, FPR_Info f> {
+multiclass VPseudoTernaryW_VF<LMULInfo m, FPR_Info f,
+                              list<SchedReadWrite> ReadWrites,
+                              list<SchedReadWrite> ReadWritesMask> {
   defvar constraint = "@earlyclobber $rd";
   defm "_V" # f.FX : VPseudoTernaryWithPolicy<m.wvrclass, f.fprclass,
-                                              m.vrclass, m, constraint>;
+                                              m.vrclass, m, ReadWrites,
+                                              ReadWritesMask, constraint>;
 }
 
-multiclass VPseudoTernaryW_VF_RM<LMULInfo m, FPR_Info f> {
+multiclass VPseudoTernaryW_VF_RM<LMULInfo m, FPR_Info f,
+                                 list<SchedReadWrite> ReadWrites,
+                                 list<SchedReadWrite> ReadWritesMask> {
   defvar constraint = "@earlyclobber $rd";
-  defm "_V" # f.FX : VPseudoTernaryWithPolicyRoundingMode<m.wvrclass, f.fprclass,
-                                                          m.vrclass, m, constraint>;
+  defm "_V" # f.FX
+  : VPseudoTernaryWithPolicyRoundingMode<m.wvrclass, f.fprclass, m.vrclass, m,
+                                         ReadWrites, ReadWritesMask,
+                                         constraint>;
 }
 
 multiclass VPseudoVSLDVWithPolicy<VReg RetClass,
                                   RegisterClass Op1Class,
                                   DAGOperand Op2Class,
                                   LMULInfo MInfo,
+                                  list<SchedReadWrite> ReadWrites,
+                                  list<SchedReadWrite> ReadWritesMask,
                                   string Constraint = ""> {
   let VLMul = MInfo.value in {
-    def "_" # MInfo.MX : VPseudoTernaryNoMaskWithPolicy<RetClass, Op1Class, Op2Class, Constraint>;
-    def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class, Constraint>,
-                                   RISCVMaskedPseudo</*MaskOpIdx*/ 3>;
+    def "_" # MInfo.MX
+      : VPseudoTernaryNoMaskWithPolicy<RetClass, Op1Class, Op2Class,
+                                       Constraint>,
+        Sched<ReadWrites>;
+    def "_" # MInfo.MX # "_MASK"
+      : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class, Constraint>,
+        RISCVMaskedPseudo</*MaskOpIdx*/ 3>,
+        Sched<ReadWritesMask>;
   }
 }
 
-multiclass VPseudoVSLDV_VX<LMULInfo m, string Constraint = ""> {
-  defm _VX : VPseudoVSLDVWithPolicy<m.vrclass, m.vrclass, GPR, m, Constraint>;
+multiclass VPseudoVSLDV_VX<LMULInfo m, list<SchedReadWrite> ReadWrites,
+                           list<SchedReadWrite> ReadWritesMask,
+                           string Constraint = ""> {
+  defm _VX : VPseudoVSLDVWithPolicy<m.vrclass, m.vrclass, GPR, m,
+                                    ReadWrites, ReadWritesMask, Constraint>;
 }
 
-multiclass VPseudoVSLDV_VI<Operand ImmType = simm5, LMULInfo m, string Constraint = ""> {
-  defm _VI : VPseudoVSLDVWithPolicy<m.vrclass, m.vrclass, ImmType, m, Constraint>;
+multiclass VPseudoVSLDV_VI<Operand ImmType = simm5, LMULInfo m,
+                           list<SchedReadWrite> ReadWrites,
+                           list<SchedReadWrite> ReadWritesMask,
+                           string Constraint = ""> {
+  defm _VI : VPseudoVSLDVWithPolicy<m.vrclass, m.vrclass, ImmType, m,
+                                    ReadWrites, ReadWritesMask, Constraint>;
 }
 
 multiclass VPseudoVMAC_VV_VX_AAXA<string Constraint = ""> {
@@ -3371,13 +3792,19 @@
     defvar WriteVIMulAddX_MX = !cast<SchedWrite>("WriteVIMulAddX_" # mx);
     defvar ReadVIMulAddV_MX = !cast<SchedRead>("ReadVIMulAddV_" # mx);
     defvar ReadVIMulAddX_MX = !cast<SchedRead>("ReadVIMulAddX_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-    defm "" : VPseudoTernaryV_VV_AAXA<m, Constraint>,
-              Sched<[WriteVIMulAddV_MX, ReadVIMulAddV_MX, ReadVIMulAddV_MX,
-                     ReadVIMulAddV_MX, ReadVMask]>;
-    defm "" : VPseudoTernaryV_VX_AAXA<m, Constraint>,
-              Sched<[WriteVIMulAddX_MX, ReadVIMulAddV_MX, ReadVIMulAddV_MX,
-                     ReadVIMulAddX_MX, ReadVMask]>;
+    defvar ReadWritesVV = [WriteVIMulAddV_MX, ReadVIMulAddV_MX,
+                           ReadVIMulAddV_MX, ReadVIMulAddV_MX, ReadVMask];
+    defvar ReadWritesVVMask = InsertAtIdx1<ReadWritesVV, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoTernaryV_VV_AAXA<m, ReadWritesVV, ReadWritesVVMask,
+                                      Constraint>;
+
+    defvar ReadWritesVX = [WriteVIMulAddX_MX, ReadVIMulAddV_MX,
+                           ReadVIMulAddV_MX, ReadVIMulAddX_MX, ReadVMask];
+    defvar ReadWritesVXMask = InsertAtIdx1<ReadWritesVX, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoTernaryV_VX_AAXA<m, ReadWritesVX, ReadWritesVXMask,
+                                      Constraint>;
   }
 }
 
@@ -3386,9 +3813,13 @@
     defvar mx = m.MX;
     defvar WriteVFMulAddV_MX = !cast<SchedWrite>("WriteVFMulAddV_" # mx);
     defvar ReadVFMulAddV_MX = !cast<SchedRead>("ReadVFMulAddV_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-    defm "" : VPseudoTernaryV_VV_AAXA<m, Constraint>,
-              Sched<[WriteVFMulAddV_MX, ReadVFMulAddV_MX, ReadVFMulAddV_MX, ReadVFMulAddV_MX, ReadVMask]>;
+    defvar ReadWrites = [WriteVFMulAddV_MX, ReadVFMulAddV_MX, ReadVFMulAddV_MX,
+                         ReadVFMulAddV_MX, ReadVMask];
+    defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoTernaryV_VV_AAXA<m, ReadWrites, ReadWritesMask,
+                                      Constraint>;
   }
 
   foreach f = FPList in {
@@ -3397,9 +3828,13 @@
       defvar WriteVFMulAddF_MX = !cast<SchedWrite>("WriteVFMulAddF_" # mx);
       defvar ReadVFMulAddV_MX = !cast<SchedRead>("ReadVFMulAddV_" # mx);
       defvar ReadVFMulAddF_MX = !cast<SchedRead>("ReadVFMulAddF_" # mx);
+      defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-      defm "" : VPseudoTernaryV_VF_AAXA<m, f, Constraint>,
-                Sched<[WriteVFMulAddF_MX, ReadVFMulAddV_MX, ReadVFMulAddV_MX, ReadVFMulAddF_MX, ReadVMask]>;
+      defvar ReadWrites = [WriteVFMulAddF_MX, ReadVFMulAddV_MX,
+                           ReadVFMulAddV_MX, ReadVFMulAddF_MX, ReadVMask];
+      defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX>.l;
+      defm "" : VPseudoTernaryV_VF_AAXA<m, f, ReadWrites, ReadWritesMask,
+                                        Constraint>;
     }
   }
 }
@@ -3409,9 +3844,13 @@
     defvar mx = m.MX;
     defvar WriteVFMulAddV_MX = !cast<SchedWrite>("WriteVFMulAddV_" # mx);
     defvar ReadVFMulAddV_MX = !cast<SchedRead>("ReadVFMulAddV_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-    defm "" : VPseudoTernaryV_VV_AAXA_RM<m, Constraint>,
-              Sched<[WriteVFMulAddV_MX, ReadVFMulAddV_MX, ReadVFMulAddV_MX, ReadVFMulAddV_MX, ReadVMask]>;
+    defvar ReadWrites = [WriteVFMulAddV_MX, ReadVFMulAddV_MX, ReadVFMulAddV_MX,
+                         ReadVFMulAddV_MX, ReadVMask];
+    defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoTernaryV_VV_AAXA_RM<m, ReadWrites, ReadWritesMask,
+                                         Constraint>;
   }
 
   foreach f = FPList in {
@@ -3420,9 +3859,13 @@
       defvar WriteVFMulAddF_MX = !cast<SchedWrite>("WriteVFMulAddF_" # mx);
       defvar ReadVFMulAddV_MX = !cast<SchedRead>("ReadVFMulAddV_" # mx);
       defvar ReadVFMulAddF_MX = !cast<SchedRead>("ReadVFMulAddF_" # mx);
+      defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-      defm "" : VPseudoTernaryV_VF_AAXA_RM<m, f, Constraint>,
-                Sched<[WriteVFMulAddF_MX, ReadVFMulAddV_MX, ReadVFMulAddV_MX, ReadVFMulAddF_MX, ReadVMask]>;
+      defvar ReadWrites = [WriteVFMulAddF_MX, ReadVFMulAddV_MX,
+                           ReadVFMulAddV_MX, ReadVFMulAddF_MX, ReadVMask];
+      defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX>.l;
+      defm "" : VPseudoTernaryV_VF_AAXA_RM<m, f, ReadWrites, ReadWritesMask,
+                                           Constraint>;
     }
   }
 }
@@ -3434,12 +3877,18 @@
     defvar WriteVISlideI_MX = !cast<SchedWrite>("WriteVISlideI_" # mx);
     defvar ReadVISlideV_MX = !cast<SchedRead>("ReadVISlideV_" # mx);
     defvar ReadVISlideX_MX = !cast<SchedRead>("ReadVISlideX_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
+
+    defvar ReadWritesVX = [WriteVISlideX_MX, ReadVISlideV_MX, ReadVISlideV_MX,
+                           ReadVISlideX_MX, ReadVMask];
+    defvar ReadWritesVXMask = InsertAtIdx1<ReadWritesVX, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoVSLDV_VX<m, ReadWritesVX, ReadWritesVXMask, Constraint>;
 
-    defm "" : VPseudoVSLDV_VX<m, Constraint>,
-              Sched<[WriteVISlideX_MX, ReadVISlideV_MX, ReadVISlideV_MX,
-                     ReadVISlideX_MX, ReadVMask]>;
-    defm "" : VPseudoVSLDV_VI<ImmType, m, Constraint>,
-              Sched<[WriteVISlideI_MX, ReadVISlideV_MX, ReadVISlideV_MX, ReadVMask]>;
+    defvar ReadWritesVI = [WriteVISlideI_MX, ReadVISlideV_MX, ReadVISlideV_MX,
+                           ReadVMask];
+    defvar ReadWritesVIMask = InsertAtIdx1<ReadWritesVI, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoVSLDV_VI<ImmType, m, ReadWritesVI, ReadWritesVIMask,
+                              Constraint>;
   }
 }
 
@@ -3450,13 +3899,17 @@
     defvar WriteVIWMulAddX_MX = !cast<SchedWrite>("WriteVIWMulAddX_" # mx);
     defvar ReadVIWMulAddV_MX = !cast<SchedRead>("ReadVIWMulAddV_" # mx);
     defvar ReadVIWMulAddX_MX = !cast<SchedRead>("ReadVIWMulAddX_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-    defm "" : VPseudoTernaryW_VV<m>,
-              Sched<[WriteVIWMulAddV_MX, ReadVIWMulAddV_MX, ReadVIWMulAddV_MX,
-                     ReadVIWMulAddV_MX, ReadVMask]>;
-    defm "" : VPseudoTernaryW_VX<m>,
-              Sched<[WriteVIWMulAddX_MX, ReadVIWMulAddV_MX, ReadVIWMulAddV_MX,
-                     ReadVIWMulAddX_MX, ReadVMask]>;
+    defvar ReadWritesVV = [WriteVIWMulAddV_MX, ReadVIWMulAddV_MX,
+                           ReadVIWMulAddV_MX, ReadVIWMulAddV_MX, ReadVMask];
+    defvar ReadWritesVVMask = InsertAtIdx1<ReadWritesVV, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoTernaryW_VV<m, ReadWritesVV, ReadWritesVVMask>;
+
+    defvar ReadWritesVX = [WriteVIWMulAddX_MX, ReadVIWMulAddV_MX,
+                           ReadVIWMulAddV_MX, ReadVIWMulAddX_MX, ReadVMask];
+    defvar ReadWritesVXMask = InsertAtIdx1<ReadWritesVX, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoTernaryW_VX<m, ReadWritesVX, ReadWritesVXMask>;
   }
 }
 
@@ -3466,10 +3919,12 @@
     defvar WriteVIWMulAddX_MX = !cast<SchedWrite>("WriteVIWMulAddX_" # mx);
     defvar ReadVIWMulAddV_MX= !cast<SchedRead>("ReadVIWMulAddV_" # mx);
     defvar ReadVIWMulAddX_MX = !cast<SchedRead>("ReadVIWMulAddX_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-    defm "" : VPseudoTernaryW_VX<m>,
-              Sched<[WriteVIWMulAddX_MX, ReadVIWMulAddV_MX, ReadVIWMulAddV_MX,
-                     ReadVIWMulAddX_MX, ReadVMask]>;
+    defvar ReadWrites = [WriteVIWMulAddX_MX, ReadVIWMulAddV_MX,
+                         ReadVIWMulAddV_MX, ReadVIWMulAddX_MX, ReadVMask];
+    defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoTernaryW_VX<m, ReadWrites, ReadWritesMask>;
   }
 }
 
@@ -3478,10 +3933,12 @@
     defvar mx = m.MX;
     defvar WriteVFWMulAddV_MX = !cast<SchedWrite>("WriteVFWMulAddV_" # mx);
     defvar ReadVFWMulAddV_MX = !cast<SchedRead>("ReadVFWMulAddV_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-    defm "" : VPseudoTernaryW_VV_RM<m>,
-              Sched<[WriteVFWMulAddV_MX, ReadVFWMulAddV_MX,
-                     ReadVFWMulAddV_MX, ReadVFWMulAddV_MX, ReadVMask]>;
+    defvar ReadWrites = [WriteVFWMulAddV_MX, ReadVFWMulAddV_MX,
+                         ReadVFWMulAddV_MX, ReadVFWMulAddV_MX, ReadVMask];
+    defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoTernaryW_VV_RM<m, ReadWrites, ReadWritesMask>;
   }
 
   foreach f = FPListW in {
@@ -3490,10 +3947,12 @@
       defvar WriteVFWMulAddF_MX = !cast<SchedWrite>("WriteVFWMulAddF_" # mx);
       defvar ReadVFWMulAddV_MX = !cast<SchedRead>("ReadVFWMulAddV_" # mx);
       defvar ReadVFWMulAddF_MX = !cast<SchedRead>("ReadVFWMulAddF_" # mx);
+      defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-      defm "" : VPseudoTernaryW_VF_RM<m, f>,
-                Sched<[WriteVFWMulAddF_MX, ReadVFWMulAddV_MX,
-                       ReadVFWMulAddV_MX, ReadVFWMulAddF_MX, ReadVMask]>;
+      defvar ReadWrites = [WriteVFWMulAddF_MX, ReadVFWMulAddV_MX,
+                           ReadVFWMulAddV_MX, ReadVFWMulAddF_MX, ReadVMask];
+      defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX>.l;
+      defm "" : VPseudoTernaryW_VF_RM<m, f, ReadWrites, ReadWritesMask>;
     }
   }
 }
@@ -3506,13 +3965,21 @@
     defvar WriteVICmpI_MX = !cast<SchedWrite>("WriteVICmpI_" # mx);
     defvar ReadVICmpV_MX = !cast<SchedRead>("ReadVICmpV_" # mx);
     defvar ReadVICmpX_MX = !cast<SchedRead>("ReadVICmpX_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
+
+    defvar ReadWritesVV = [WriteVICmpV_MX, ReadVICmpV_MX, ReadVICmpV_MX,
+                           ReadVMask];
+    defvar ReadWritesVVMask = InsertAtIdx1<ReadWritesVV, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryM_VV<m, ReadWritesVV, ReadWritesVVMask>;
 
-    defm "" : VPseudoBinaryM_VV<m>,
-              Sched<[WriteVICmpV_MX, ReadVICmpV_MX, ReadVICmpV_MX, ReadVMask]>;
-    defm "" : VPseudoBinaryM_VX<m>,
-              Sched<[WriteVICmpX_MX, ReadVICmpV_MX, ReadVICmpX_MX, ReadVMask]>;
-    defm "" : VPseudoBinaryM_VI<m>,
-              Sched<[WriteVICmpI_MX, ReadVICmpV_MX, ReadVMask]>;
+    defvar ReadWritesVX = [WriteVICmpX_MX, ReadVICmpV_MX, ReadVICmpX_MX,
+                           ReadVMask];
+    defvar ReadWritesVXMask = InsertAtIdx1<ReadWritesVX, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryM_VX<m, ReadWritesVX, ReadWritesVXMask>;
+
+    defvar ReadWritesVI = [WriteVICmpI_MX, ReadVICmpV_MX, ReadVMask];
+    defvar ReadWritesVIMask = InsertAtIdx1<ReadWritesVI, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryM_VI<m, ReadWritesVI, ReadWritesVIMask>;
   }
 }
 
@@ -3523,11 +3990,17 @@
     defvar WriteVICmpX_MX = !cast<SchedWrite>("WriteVICmpX_" # mx);
     defvar ReadVICmpV_MX = !cast<SchedRead>("ReadVICmpV_" # mx);
     defvar ReadVICmpX_MX = !cast<SchedRead>("ReadVICmpX_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
+
+    defvar ReadWritesVV = [WriteVICmpV_MX, ReadVICmpV_MX, ReadVICmpV_MX,
+                           ReadVMask];
+    defvar ReadWritesVVMask = InsertAtIdx1<ReadWritesVV, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryM_VV<m, ReadWritesVV, ReadWritesVVMask>;
 
-    defm "" : VPseudoBinaryM_VV<m>,
-              Sched<[WriteVICmpV_MX, ReadVICmpV_MX, ReadVICmpV_MX, ReadVMask]>;
-    defm "" : VPseudoBinaryM_VX<m>,
-              Sched<[WriteVICmpX_MX, ReadVICmpV_MX, ReadVICmpX_MX, ReadVMask]>;
+    defvar ReadWritesVX = [WriteVICmpX_MX, ReadVICmpV_MX, ReadVICmpX_MX,
+                           ReadVMask];
+    defvar ReadWritesVXMask = InsertAtIdx1<ReadWritesVX, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryM_VX<m, ReadWritesVV, ReadWritesVX>;
   }
 }
 
@@ -3536,9 +4009,12 @@
     defvar mx = m.MX;
     defvar WriteVFCmpV_MX = !cast<SchedWrite>("WriteVFCmpV_" # mx);
     defvar ReadVFCmpV_MX = !cast<SchedRead>("ReadVFCmpV_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-    defm "" : VPseudoBinaryM_VV<m>,
-              Sched<[WriteVFCmpV_MX, ReadVFCmpV_MX, ReadVFCmpV_MX, ReadVMask]>;
+    defvar ReadWrites = [WriteVFCmpV_MX, ReadVFCmpV_MX, ReadVFCmpV_MX,
+                         ReadVMask];
+    defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryM_VV<m, ReadWrites, ReadWritesMask>;
   }
 
   foreach f = FPList in {
@@ -3547,9 +4023,12 @@
       defvar WriteVFCmpF_MX = !cast<SchedWrite>("WriteVFCmpF_" # mx);
       defvar ReadVFCmpV_MX = !cast<SchedRead>("ReadVFCmpV_" # mx);
       defvar ReadVFCmpF_MX = !cast<SchedRead>("ReadVFCmpF_" # mx);
+      defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-      defm "" : VPseudoBinaryM_VF<m, f>,
-                Sched<[WriteVFCmpF_MX, ReadVFCmpV_MX, ReadVFCmpF_MX, ReadVMask]>;
+      defvar ReadWrites = [WriteVFCmpF_MX, ReadVFCmpV_MX, ReadVFCmpF_MX,
+                           ReadVMask];
+      defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX>.l;
+      defm "" : VPseudoBinaryM_VF<m, f, ReadWrites, ReadWritesMask>;
     }
   }
 }
@@ -3561,9 +4040,12 @@
       defvar WriteVFCmpF_MX = !cast<SchedWrite>("WriteVFCmpF_" # mx);
       defvar ReadVFCmpV_MX = !cast<SchedRead>("ReadVFCmpV_" # mx);
       defvar ReadVFCmpF_MX = !cast<SchedRead>("ReadVFCmpF_" # mx);
+      defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-      defm "" : VPseudoBinaryM_VF<m, f>,
-                Sched<[WriteVFCmpF_MX, ReadVFCmpV_MX, ReadVFCmpF_MX, ReadVMask]>;
+      defvar ReadWrites = [WriteVFCmpF_MX, ReadVFCmpV_MX, ReadVFCmpF_MX,
+                           ReadVMask];
+      defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX>.l;
+      defm "" : VPseudoBinaryM_VF<m, f, ReadWrites, ReadWritesMask>;
     }
   }
 }
@@ -3575,11 +4057,16 @@
     defvar WriteVICmpI_MX = !cast<SchedWrite>("WriteVICmpI_" # mx);
     defvar ReadVICmpV_MX = !cast<SchedRead>("ReadVICmpV_" # mx);
     defvar ReadVICmpX_MX = !cast<SchedRead>("ReadVICmpX_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-    defm "" : VPseudoBinaryM_VX<m>,
-              Sched<[WriteVICmpX_MX, ReadVICmpV_MX, ReadVICmpX_MX, ReadVMask]>;
-    defm "" : VPseudoBinaryM_VI<m>,
-              Sched<[WriteVICmpI_MX, ReadVICmpV_MX, ReadVMask]>;
+    defvar ReadWritesVX = [WriteVICmpX_MX, ReadVICmpV_MX, ReadVICmpX_MX,
+                           ReadVMask];
+    defvar ReadWritesVXMask = InsertAtIdx1<ReadWritesVX, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryM_VX<m, ReadWritesVX, ReadWritesVXMask>;
+
+    defvar ReadWritesVI = [WriteVICmpI_MX, ReadVICmpV_MX, ReadVMask];
+    defvar ReadWritesVIMask = InsertAtIdx1<ReadWritesVI, ReadVMergeOp_MX>.l;
+    defm "" : VPseudoBinaryM_VI<m, ReadWritesVI, ReadWritesVIMask>;
   }
 }
 
@@ -3587,10 +4074,18 @@
   foreach m = MxList in {
     defvar mx = m.MX;
     foreach e = SchedSEWSet<mx>.val in {
-      defvar WriteVIRedV_From_MX_E = !cast<SchedWrite>("WriteVIRedV_From_" # mx # "_E" # e);
-      defm _VS : VPseudoTernaryWithTailPolicy<V_M1.vrclass, m.vrclass, V_M1.vrclass, m, e>,
-                 Sched<[WriteVIRedV_From_MX_E, ReadVIRedV, ReadVIRedV, ReadVIRedV,
-                        ReadVMask]>;
+      defvar WriteVIRedV_From_MX_E =
+        !cast<SchedWrite>("WriteVIRedV_From_" # mx # "_E" # e);
+      // TODO: ReadVMergeOp should be MX of destination
+      defvar ReadVMergeOp_MX_E =
+        !cast<SchedRead>("ReadVMergeOp_" # mx # "_E" # e);
+
+      defvar ReadWrites = [WriteVIRedV_From_MX_E, ReadVIRedV, ReadVIRedV,
+                           ReadVIRedV, ReadVMask];
+      defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX_E>.l;
+      defm _VS : VPseudoTernaryWithTailPolicy<V_M1.vrclass, m.vrclass,
+                                              V_M1.vrclass, m, e, ReadWrites,
+                                              ReadWritesMask>;
     }
   }
 }
@@ -3599,10 +4094,18 @@
   foreach m = MxList in {
     defvar mx = m.MX;
     foreach e = SchedSEWSet<mx>.val in {
-      defvar WriteVIRedMinMaxV_From_MX_E = !cast<SchedWrite>("WriteVIRedMinMaxV_From_" # mx # "_E" # e);
-      defm _VS : VPseudoTernaryWithTailPolicy<V_M1.vrclass, m.vrclass, V_M1.vrclass, m, e>,
-                 Sched<[WriteVIRedMinMaxV_From_MX_E, ReadVIRedV, ReadVIRedV,
-                        ReadVIRedV, ReadVMask]>;
+      defvar WriteVIRedMinMaxV_From_MX_E =
+        !cast<SchedWrite>("WriteVIRedMinMaxV_From_" # mx # "_E" # e);
+      // TODO: ReadVMergeOp should be MX of destination
+      defvar ReadVMergeOp_MX_E =
+        !cast<SchedRead>("ReadVMergeOp_" # mx # "_E" # e);
+
+      defvar ReadWrites = [WriteVIRedMinMaxV_From_MX_E, ReadVIRedV, ReadVIRedV,
+                           ReadVIRedV, ReadVMask];
+      defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX_E>.l;
+      defm _VS : VPseudoTernaryWithTailPolicy<V_M1.vrclass, m.vrclass,
+                                              V_M1.vrclass, m, e, ReadWrites,
+                                              ReadWritesMask>;
     }
   }
 }
@@ -3611,10 +4114,18 @@
   foreach m = MxListWRed in {
     defvar mx = m.MX;
     foreach e = SchedSEWSet<mx, /*isF*/ 0, /*isWidening*/ 1>.val in {
-      defvar WriteVIWRedV_From_MX_E = !cast<SchedWrite>("WriteVIWRedV_From_" # mx # "_E" # e);
-      defm _VS : VPseudoTernaryWithTailPolicy<V_M1.vrclass, m.vrclass, V_M1.vrclass, m, e>,
-                 Sched<[WriteVIWRedV_From_MX_E, ReadVIWRedV, ReadVIWRedV,
-                        ReadVIWRedV, ReadVMask]>;
+      defvar WriteVIWRedV_From_MX_E =
+        !cast<SchedWrite>("WriteVIWRedV_From_" # mx # "_E" # e);
+      // TODO: ReadVMergeOp should be MX of destination
+      defvar ReadVMergeOp_MX_E =
+        !cast<SchedRead>("ReadVMergeOp_" # mx # "_E" # e);
+
+      defvar ReadWrites = [WriteVIWRedV_From_MX_E, ReadVIWRedV, ReadVIWRedV,
+                           ReadVIWRedV, ReadVMask];
+      defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX_E>.l;
+      defm _VS : VPseudoTernaryWithTailPolicy<V_M1.vrclass, m.vrclass,
+                                              V_M1.vrclass, m, e, ReadWrites,
+                                              ReadWritesMask>;
     }
   }
 }
@@ -3623,12 +4134,20 @@
   foreach m = MxListF in {
     defvar mx = m.MX;
     foreach e = SchedSEWSet<mx, /*isF*/ 1>.val in {
-      defvar WriteVFRedV_From_MX_E = !cast<SchedWrite>("WriteVFRedV_From_" # mx # "_E" # e);
+      defvar WriteVFRedV_From_MX_E =
+        !cast<SchedWrite>("WriteVFRedV_From_" # mx # "_E" # e);
+      // TODO: ReadVMergeOp should be MX of destination
+      defvar ReadVMergeOp_MX_E =
+        !cast<SchedRead>("ReadVMergeOp_" # mx # "_E" # e);
+
+      defvar ReadWrites = [WriteVFRedV_From_MX_E, ReadVFRedV, ReadVFRedV,
+                           ReadVFRedV, ReadVMask];
+      defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX_E>.l;
       defm _VS
           : VPseudoTernaryWithTailPolicyRoundingMode<V_M1.vrclass, m.vrclass, 
-                                                     V_M1.vrclass, m, e>,
-                 Sched<[WriteVFRedV_From_MX_E, ReadVFRedV, ReadVFRedV, ReadVFRedV,
-                        ReadVMask]>;
+                                                     V_M1.vrclass, m, e,
+                                                     ReadWrites,
+                                                     ReadWritesMask>;
     }
   }
 }
@@ -3637,10 +4156,18 @@
   foreach m = MxListF in {
     defvar mx = m.MX;
     foreach e = SchedSEWSet<mx, /*isF*/ 1>.val in {
-      defvar WriteVFRedMinMaxV_From_MX_E = !cast<SchedWrite>("WriteVFRedMinMaxV_From_" # mx # "_E" # e);
-      defm _VS : VPseudoTernaryWithTailPolicy<V_M1.vrclass, m.vrclass, V_M1.vrclass, m, e>,
-                 Sched<[WriteVFRedMinMaxV_From_MX_E, ReadVFRedV, ReadVFRedV, ReadVFRedV,
-                        ReadVMask]>;
+      defvar WriteVFRedMinMaxV_From_MX_E =
+        !cast<SchedWrite>("WriteVFRedMinMaxV_From_" # mx # "_E" # e);
+      // TODO: ReadVMergeOp should be MX of destination
+      defvar ReadVMergeOp_MX_E =
+        !cast<SchedRead>("ReadVMergeOp_" # mx # "_E" # e);
+
+      defvar ReadWrites = [WriteVFRedMinMaxV_From_MX_E, ReadVFRedV, ReadVFRedV,
+                           ReadVFRedV, ReadVMask];
+      defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX_E>.l;
+      defm _VS : VPseudoTernaryWithTailPolicy<V_M1.vrclass, m.vrclass,
+                                              V_M1.vrclass, m, e, ReadWrites,
+                                              ReadWritesMask>;
     }
   }
 }
@@ -3649,11 +4176,19 @@
   foreach m = MxListF in {
     defvar mx = m.MX;
     foreach e = SchedSEWSet<mx, /*isF*/ 1>.val in {
-      defvar WriteVFRedOV_From_MX_E = !cast<SchedWrite>("WriteVFRedOV_From_" # mx # "_E" # e);
-      defm _VS : VPseudoTernaryWithTailPolicyRoundingMode<V_M1.vrclass, m.vrclass,
-                                                          V_M1.vrclass, m, e>,
-                 Sched<[WriteVFRedOV_From_MX_E, ReadVFRedOV, ReadVFRedOV,
-                        ReadVFRedOV, ReadVMask]>;
+      defvar WriteVFRedOV_From_MX_E =
+        !cast<SchedWrite>("WriteVFRedOV_From_" # mx # "_E" # e);
+      defvar ReadVMergeOp_MX_E =
+        !cast<SchedRead>("ReadVMergeOp_" # mx # "_E" # e);
+
+      defvar ReadWrites = [WriteVFRedOV_From_MX_E, ReadVFRedOV, ReadVFRedOV,
+                           ReadVFRedOV, ReadVMask];
+      defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX_E>.l;
+      defm _VS : VPseudoTernaryWithTailPolicyRoundingMode<V_M1.vrclass,
+                                                          m.vrclass,
+                                                          V_M1.vrclass, m, e,
+                                                          ReadWrites,
+                                                          ReadWritesMask>;
     }
   }
 }
@@ -3662,12 +4197,19 @@
   foreach m = MxListFWRed in {
     defvar mx = m.MX;
     foreach e = SchedSEWSet<mx, /*isF*/ 1, /*isWidening*/ 1>.val in {
-      defvar WriteVFWRedV_From_MX_E = !cast<SchedWrite>("WriteVFWRedV_From_" # mx # "_E" # e);
+      defvar WriteVFWRedV_From_MX_E =
+        !cast<SchedWrite>("WriteVFWRedV_From_" # mx # "_E" # e);
+      defvar ReadVMergeOp_MX_E =
+        !cast<SchedRead>("ReadVMergeOp_" # mx # "_E" # e);
+
+      defvar ReadWrites = [WriteVFWRedV_From_MX_E, ReadVFWRedV, ReadVFWRedV,
+                           ReadVFWRedV, ReadVMask];
+      defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX_E>.l;
       defm _VS
           : VPseudoTernaryWithTailPolicyRoundingMode<V_M1.vrclass, m.vrclass,
-                                                     V_M1.vrclass, m, e>,
-                 Sched<[WriteVFWRedV_From_MX_E, ReadVFWRedV, ReadVFWRedV,
-                        ReadVFWRedV, ReadVMask]>;
+                                                     V_M1.vrclass, m, e,
+                                                     ReadWrites,
+                                                     ReadWritesMask>;
     }
   }
 }
@@ -3675,24 +4217,33 @@
 multiclass VPseudoConversion<VReg RetClass,
                              VReg Op1Class,
                              LMULInfo MInfo,
+                             list<SchedReadWrite> ReadWrites,
+                             list<SchedReadWrite> ReadWritesMask,
                              string Constraint = ""> {
   let VLMul = MInfo.value in {
-    def "_" # MInfo.MX : VPseudoUnaryNoMask<RetClass, Op1Class, Constraint>;
+    def "_" # MInfo.MX : VPseudoUnaryNoMask<RetClass, Op1Class, Constraint>,
+                         Sched<ReadWrites>;
     def "_" # MInfo.MX # "_MASK" : VPseudoUnaryMask<RetClass, Op1Class,
                                                     Constraint>,
-                                   RISCVMaskedPseudo</*MaskOpIdx*/ 2>;
+                                   RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
+                                   Sched<ReadWritesMask>;
   }
 }
 
 multiclass VPseudoConversionRoundingMode<VReg RetClass,
                              VReg Op1Class,
                              LMULInfo MInfo,
+                             list<SchedReadWrite> ReadWrites,
+                             list<SchedReadWrite> ReadWritesMask,
                              string Constraint = ""> {
   let VLMul = MInfo.value in {
-    def "_" # MInfo.MX : VPseudoUnaryNoMaskRoundingMode<RetClass, Op1Class, Constraint>;
+    def "_" # MInfo.MX
+      : VPseudoUnaryNoMaskRoundingMode<RetClass, Op1Class, Constraint>,
+        Sched<ReadWrites>;
     def "_" # MInfo.MX # "_MASK" : VPseudoUnaryMaskRoundingMode<RetClass, Op1Class,
                                                                 Constraint>,
-                                   RISCVMaskedPseudo</*MaskOpIdx*/ 2>;
+                                   RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
+                                   Sched<ReadWritesMask>;
   }
 }
 
@@ -3700,22 +4251,30 @@
 multiclass VPseudoConversionRM<VReg RetClass,
                                VReg Op1Class,
                                LMULInfo MInfo,
+                               list<SchedReadWrite> ReadWrites,
+                               list<SchedReadWrite> ReadWritesMask,
                                string Constraint = ""> {
   let VLMul = MInfo.value in {
     def "_" # MInfo.MX : VPseudoUnaryNoMask_FRM<RetClass, Op1Class,
-                                                        Constraint>;
+                                                        Constraint>,
+                         Sched<ReadWrites>;
+
     def "_" # MInfo.MX # "_MASK" : VPseudoUnaryMask_FRM<RetClass, Op1Class,
                                                         Constraint>,
-                                   RISCVMaskedPseudo</*MaskOpIdx*/ 2>;
+                                   RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
+                                   Sched<ReadWritesMask>;
   }
 }
 
 multiclass VPseudoConversionNoExcept<VReg RetClass,
                                      VReg Op1Class,
                                      LMULInfo MInfo,
+                                     list<SchedReadWrite> ReadWritesMask,
                                      string Constraint = ""> {
   let VLMul = MInfo.value in {
-    def "_" # MInfo.MX # "_MASK" : VPseudoUnaryMask_NoExcept<RetClass, Op1Class, Constraint>;
+    def "_" # MInfo.MX # "_MASK"
+      : VPseudoUnaryMask_NoExcept<RetClass, Op1Class, Constraint>,
+        Sched<ReadWritesMask>;
   }
 }
 
@@ -3724,9 +4283,12 @@
     defvar mx = m.MX;
     defvar WriteVFCvtFToIV_MX = !cast<SchedWrite>("WriteVFCvtFToIV_" # mx);
     defvar ReadVFCvtFToIV_MX = !cast<SchedRead>("ReadVFCvtFToIV_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-    defm _V : VPseudoConversion<m.vrclass, m.vrclass, m>,
-              Sched<[WriteVFCvtFToIV_MX, ReadVFCvtFToIV_MX, ReadVMask]>;
+    defvar ReadWrites = [WriteVFCvtFToIV_MX, ReadVFCvtFToIV_MX, ReadVMask];
+    defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX>.l;
+    defm _V : VPseudoConversion<m.vrclass, m.vrclass, m, ReadWrites,
+                                ReadWritesMask>;
   }
 }
 
@@ -3735,9 +4297,12 @@
     defvar mx = m.MX;
     defvar WriteVFCvtFToIV_MX = !cast<SchedWrite>("WriteVFCvtFToIV_" # mx);
     defvar ReadVFCvtFToIV_MX = !cast<SchedRead>("ReadVFCvtFToIV_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-    defm _V : VPseudoConversionRoundingMode<m.vrclass, m.vrclass, m>,
-              Sched<[WriteVFCvtFToIV_MX, ReadVFCvtFToIV_MX, ReadVMask]>;
+    defvar ReadWrites = [WriteVFCvtFToIV_MX, ReadVFCvtFToIV_MX, ReadVMask];
+    defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX>.l;
+    defm _V : VPseudoConversionRoundingMode<m.vrclass, m.vrclass, m,
+                                            ReadWrites, ReadWritesMask>;
   }
 }
 
@@ -3746,9 +4311,12 @@
     defvar mx = m.MX;
     defvar WriteVFCvtFToIV_MX = !cast<SchedWrite>("WriteVFCvtFToIV_" # mx);
     defvar ReadVFCvtFToIV_MX = !cast<SchedRead>("ReadVFCvtFToIV_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-    defm _V : VPseudoConversionRM<m.vrclass, m.vrclass, m>,
-              Sched<[WriteVFCvtFToIV_MX, ReadVFCvtFToIV_MX, ReadVMask]>;
+    defvar ReadWrites = [WriteVFCvtFToIV_MX, ReadVFCvtFToIV_MX, ReadVMask];
+    defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX>.l;
+    defm _V : VPseudoConversionRM<m.vrclass, m.vrclass, m, ReadWrites,
+                                  ReadWritesMask>;
   }
 }
 
@@ -3757,9 +4325,12 @@
     defvar mx = m.MX;
     defvar WriteVFCvtFToIV_MX = !cast<SchedWrite>("WriteVFCvtFToIV_" # mx);
     defvar ReadVFCvtFToIV_MX = !cast<SchedRead>("ReadVFCvtFToIV_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-    defm _V : VPseudoConversionNoExcept<m.vrclass, m.vrclass, m>,
-              Sched<[WriteVFCvtFToIV_MX, ReadVFCvtFToIV_MX, ReadVMask]>;
+    defvar ReadWritesMask = [WriteVFCvtFToIV_MX, ReadVFCvtFToIV_MX, ReadVMask,
+                             ReadVMergeOp_MX];
+    defm _V : VPseudoConversionNoExcept<m.vrclass, m.vrclass, m,
+                                        ReadWritesMask>;
   }
 }
 
@@ -3768,9 +4339,12 @@
     defvar mx = m.MX;
     defvar WriteVFCvtIToFV_MX = !cast<SchedWrite>("WriteVFCvtIToFV_" # mx);
     defvar ReadVFCvtIToFV_MX = !cast<SchedRead>("ReadVFCvtIToFV_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-    defm _V : VPseudoConversionRoundingMode<m.vrclass, m.vrclass, m>,
-              Sched<[WriteVFCvtIToFV_MX, ReadVFCvtIToFV_MX, ReadVMask]>;
+    defvar ReadWrites = [WriteVFCvtIToFV_MX, ReadVFCvtIToFV_MX, ReadVMask];
+    defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX>.l;
+    defm _V : VPseudoConversionRoundingMode<m.vrclass, m.vrclass, m,
+                                            ReadWrites, ReadWritesMask>;
   }
 }
 
@@ -3779,9 +4353,12 @@
     defvar mx = m.MX;
     defvar WriteVFCvtIToFV_MX = !cast<SchedWrite>("WriteVFCvtIToFV_" # mx);
     defvar ReadVFCvtIToFV_MX = !cast<SchedRead>("ReadVFCvtIToFV_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-    defm _V : VPseudoConversionRM<m.vrclass, m.vrclass, m>,
-              Sched<[WriteVFCvtIToFV_MX, ReadVFCvtIToFV_MX, ReadVMask]>;
+    defvar ReadWrites = [WriteVFCvtIToFV_MX, ReadVFCvtIToFV_MX, ReadVMask];
+    defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX>.l;
+    defm _V : VPseudoConversionRM<m.vrclass, m.vrclass, m, ReadWrites,
+                                  ReadWritesMask>;
   }
 }
 
@@ -3791,9 +4368,12 @@
     defvar mx = m.MX;
     defvar WriteVFWCvtFToIV_MX = !cast<SchedWrite>("WriteVFWCvtFToIV_" # mx);
     defvar ReadVFWCvtFToIV_MX = !cast<SchedRead>("ReadVFWCvtFToIV_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-    defm _V : VPseudoConversion<m.wvrclass, m.vrclass, m, constraint>,
-              Sched<[WriteVFWCvtFToIV_MX, ReadVFWCvtFToIV_MX, ReadVMask]>;
+    defvar ReadWrites = [WriteVFWCvtFToIV_MX, ReadVFWCvtFToIV_MX, ReadVMask];
+    defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX>.l;
+    defm _V : VPseudoConversion<m.wvrclass, m.vrclass, m, ReadWrites,
+                                ReadWritesMask, constraint>;
   }
 }
 
@@ -3803,9 +4383,13 @@
     defvar mx = m.MX;
     defvar WriteVFWCvtFToIV_MX = !cast<SchedWrite>("WriteVFWCvtFToIV_" # mx);
     defvar ReadVFWCvtFToIV_MX = !cast<SchedRead>("ReadVFWCvtFToIV_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-    defm _V : VPseudoConversionRoundingMode<m.wvrclass, m.vrclass, m, constraint>,
-              Sched<[WriteVFWCvtFToIV_MX, ReadVFWCvtFToIV_MX, ReadVMask]>;
+    defvar ReadWrites = [WriteVFWCvtFToIV_MX, ReadVFWCvtFToIV_MX, ReadVMask];
+    defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX>.l;
+    defm _V : VPseudoConversionRoundingMode<m.wvrclass, m.vrclass, m,
+                                            ReadWrites, ReadWritesMask,
+                                            constraint>;
   }
 }
 
@@ -3815,9 +4399,12 @@
     defvar mx = m.MX;
     defvar WriteVFWCvtFToIV_MX = !cast<SchedWrite>("WriteVFWCvtFToIV_" # mx);
     defvar ReadVFWCvtFToIV_MX = !cast<SchedRead>("ReadVFWCvtFToIV_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-    defm _V : VPseudoConversionRM<m.wvrclass, m.vrclass, m, constraint>,
-              Sched<[WriteVFWCvtFToIV_MX, ReadVFWCvtFToIV_MX, ReadVMask]>;
+    defvar ReadWrites = [WriteVFWCvtFToIV_MX, ReadVFWCvtFToIV_MX, ReadVMask];
+    defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX>.l;
+    defm _V : VPseudoConversionRM<m.wvrclass, m.vrclass, m,
+                                  ReadWrites, ReadWritesMask, constraint>;
   }
 }
 
@@ -3827,9 +4414,12 @@
     defvar mx = m.MX;
     defvar WriteVFWCvtIToFV_MX = !cast<SchedWrite>("WriteVFWCvtIToFV_" # mx);
     defvar ReadVFWCvtIToFV_MX = !cast<SchedRead>("ReadVFWCvtIToFV_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-    defm _V : VPseudoConversion<m.wvrclass, m.vrclass, m, constraint>,
-              Sched<[WriteVFWCvtIToFV_MX, ReadVFWCvtIToFV_MX, ReadVMask]>;
+    defvar ReadWrites = [WriteVFWCvtIToFV_MX, ReadVFWCvtIToFV_MX, ReadVMask];
+    defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX>.l;
+    defm _V : VPseudoConversion<m.wvrclass, m.vrclass, m, ReadWrites,
+                                ReadWritesMask, constraint>;
   }
 }
 
@@ -3839,9 +4429,12 @@
     defvar mx = m.MX;
     defvar WriteVFWCvtFToFV_MX = !cast<SchedWrite>("WriteVFWCvtFToFV_" # mx);
     defvar ReadVFWCvtFToFV_MX = !cast<SchedRead>("ReadVFWCvtFToFV_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-    defm _V : VPseudoConversion<m.wvrclass, m.vrclass, m, constraint>,
-              Sched<[WriteVFWCvtFToFV_MX, ReadVFWCvtFToFV_MX, ReadVMask]>;
+    defvar ReadWrites = [WriteVFWCvtFToFV_MX, ReadVFWCvtFToFV_MX, ReadVMask];
+    defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX>.l;
+    defm _V : VPseudoConversion<m.wvrclass, m.vrclass, m, ReadWrites,
+                                ReadWritesMask, constraint>;
   }
 }
 
@@ -3851,9 +4444,12 @@
     defvar mx = m.MX;
     defvar WriteVFNCvtFToIV_MX = !cast<SchedWrite>("WriteVFNCvtFToIV_" # mx);
     defvar ReadVFNCvtFToIV_MX = !cast<SchedRead>("ReadVFNCvtFToIV_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-    defm _W : VPseudoConversion<m.vrclass, m.wvrclass, m, constraint>,
-              Sched<[WriteVFNCvtFToIV_MX, ReadVFNCvtFToIV_MX, ReadVMask]>;
+    defvar ReadWrites = [WriteVFNCvtFToIV_MX, ReadVFNCvtFToIV_MX, ReadVMask];
+    defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX>.l;
+    defm _W : VPseudoConversion<m.vrclass, m.wvrclass, m, ReadWrites,
+                                ReadWritesMask, constraint>;
   }
 }
 
@@ -3863,9 +4459,13 @@
     defvar mx = m.MX;
     defvar WriteVFNCvtFToIV_MX = !cast<SchedWrite>("WriteVFNCvtFToIV_" # mx);
     defvar ReadVFNCvtFToIV_MX = !cast<SchedRead>("ReadVFNCvtFToIV_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-    defm _W : VPseudoConversionRoundingMode<m.vrclass, m.wvrclass, m, constraint>,
-              Sched<[WriteVFNCvtFToIV_MX, ReadVFNCvtFToIV_MX, ReadVMask]>;
+    defvar ReadWrites = [WriteVFNCvtFToIV_MX, ReadVFNCvtFToIV_MX, ReadVMask];
+    defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX>.l;
+    defm _W : VPseudoConversionRoundingMode<m.vrclass, m.wvrclass, m,
+                                            ReadWrites, ReadWritesMask,
+                                            constraint>;
   }
 }
 
@@ -3875,9 +4475,12 @@
     defvar mx = m.MX;
     defvar WriteVFNCvtFToIV_MX = !cast<SchedWrite>("WriteVFNCvtFToIV_" # mx);
     defvar ReadVFNCvtFToIV_MX = !cast<SchedRead>("ReadVFNCvtFToIV_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-    defm _W : VPseudoConversionRM<m.vrclass, m.wvrclass, m, constraint>,
-              Sched<[WriteVFNCvtFToIV_MX, ReadVFNCvtFToIV_MX, ReadVMask]>;
+    defvar ReadWrites = [WriteVFNCvtFToIV_MX, ReadVFNCvtFToIV_MX, ReadVMask];
+    defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX>.l;
+    defm _W : VPseudoConversionRM<m.vrclass, m.wvrclass, m, ReadWrites,
+                                  ReadWritesMask, constraint>;
   }
 }
 
@@ -3887,9 +4490,13 @@
     defvar mx = m.MX;
     defvar WriteVFNCvtIToFV_MX = !cast<SchedWrite>("WriteVFNCvtIToFV_" # mx);
     defvar ReadVFNCvtIToFV_MX = !cast<SchedRead>("ReadVFNCvtIToFV_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-    defm _W : VPseudoConversionRoundingMode<m.vrclass, m.wvrclass, m, constraint>,
-              Sched<[WriteVFNCvtIToFV_MX, ReadVFNCvtIToFV_MX, ReadVMask]>;
+    defvar ReadWrites = [WriteVFNCvtIToFV_MX, ReadVFNCvtIToFV_MX, ReadVMask];
+    defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX>.l;
+    defm _W : VPseudoConversionRoundingMode<m.vrclass, m.wvrclass, m,
+                                            ReadWrites, ReadWritesMask,
+                                            constraint>;
   }
 }
 
@@ -3899,9 +4506,12 @@
     defvar mx = m.MX;
     defvar WriteVFNCvtIToFV_MX = !cast<SchedWrite>("WriteVFNCvtIToFV_" # mx);
     defvar ReadVFNCvtIToFV_MX = !cast<SchedRead>("ReadVFNCvtIToFV_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-    defm _W : VPseudoConversionRM<m.vrclass, m.wvrclass, m, constraint>,
-              Sched<[WriteVFNCvtIToFV_MX, ReadVFNCvtIToFV_MX, ReadVMask]>;
+    defvar ReadWrites = [WriteVFNCvtIToFV_MX, ReadVFNCvtIToFV_MX, ReadVMask];
+    defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX>.l;
+    defm _W : VPseudoConversionRM<m.vrclass, m.wvrclass, m, ReadWrites,
+                                  ReadWritesMask, constraint>;
   }
 }
 
@@ -3911,9 +4521,12 @@
     defvar mx = m.MX;
     defvar WriteVFNCvtFToFV_MX = !cast<SchedWrite>("WriteVFNCvtFToFV_" # mx);
     defvar ReadVFNCvtFToFV_MX = !cast<SchedRead>("ReadVFNCvtFToFV_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-    defm _W : VPseudoConversion<m.vrclass, m.wvrclass, m, constraint>,
-              Sched<[WriteVFNCvtFToFV_MX, ReadVFNCvtFToFV_MX, ReadVMask]>;
+    defvar ReadWrites = [WriteVFNCvtFToFV_MX, ReadVFNCvtFToFV_MX, ReadVMask];
+    defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX>.l;
+    defm _W : VPseudoConversion<m.vrclass, m.wvrclass, m, ReadWrites,
+                                ReadWritesMask, constraint>;
   }
 }
 
@@ -3923,9 +4536,13 @@
     defvar mx = m.MX;
     defvar WriteVFNCvtFToFV_MX = !cast<SchedWrite>("WriteVFNCvtFToFV_" # mx);
     defvar ReadVFNCvtFToFV_MX = !cast<SchedRead>("ReadVFNCvtFToFV_" # mx);
+    defvar ReadVMergeOp_MX = !cast<SchedRead>("ReadVMergeOp_" # mx);
 
-    defm _W : VPseudoConversionRoundingMode<m.vrclass, m.wvrclass, m, constraint>,
-              Sched<[WriteVFNCvtFToFV_MX, ReadVFNCvtFToFV_MX, ReadVMask]>;
+    defvar ReadWrites = [WriteVFNCvtFToFV_MX, ReadVFNCvtFToFV_MX, ReadVMask];
+    defvar ReadWritesMask = InsertAtIdx1<ReadWrites, ReadVMergeOp_MX>.l;
+    defm _W : VPseudoConversionRoundingMode<m.vrclass, m.wvrclass, m,
+                                            ReadWrites, ReadWritesMask,
+                                            constraint>;
   }
 }
 
@@ -3939,7 +4556,7 @@
           def nf # "E" # eew # "_V_" # LInfo :
             VPseudoUSSegLoadNoMask<vreg, eew, nf>, VLSEGSched<nf, eew, LInfo>;
           def nf # "E" # eew # "_V_" # LInfo # "_MASK" :
-            VPseudoUSSegLoadMask<vreg, eew, nf>, VLSEGSched<nf, eew, LInfo>;
+            VPseudoUSSegLoadMask<vreg, eew, nf>, VLSEGSchedMask<nf, eew, LInfo>;
         }
       }
     }
@@ -3954,9 +4571,11 @@
         foreach nf = NFSet<lmul>.L in {
           defvar vreg = SegRegClass<lmul, nf>.RC;
           def nf # "E" # eew # "FF_V_" # LInfo :
-            VPseudoUSSegLoadFFNoMask<vreg, eew, nf>, VLSEGFFSched<nf, eew, LInfo>;
+            VPseudoUSSegLoadFFNoMask<vreg, eew, nf>,
+            VLSEGFFSched<nf, eew, LInfo>;
           def nf # "E" # eew # "FF_V_" # LInfo # "_MASK" :
-            VPseudoUSSegLoadFFMask<vreg, eew, nf>, VLSEGFFSched<nf, eew, LInfo>;
+            VPseudoUSSegLoadFFMask<vreg, eew, nf>,
+            VLSEGFFSchedMask<nf, eew, LInfo>;
         }
       }
     }
@@ -3970,10 +4589,12 @@
       let VLMul = lmul.value, SEW=eew in {
         foreach nf = NFSet<lmul>.L in {
           defvar vreg = SegRegClass<lmul, nf>.RC;
-          def nf # "E" # eew # "_V_" # LInfo : VPseudoSSegLoadNoMask<vreg, eew, nf>,
-                                               VLSSEGSched<nf, eew, LInfo>;
-          def nf # "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoSSegLoadMask<vreg, eew, nf>,
-                                                         VLSSEGSched<nf, eew, LInfo>;
+          def nf # "E" # eew # "_V_" # LInfo
+            : VPseudoSSegLoadNoMask<vreg, eew, nf>,
+              VLSSEGSched<nf, eew, LInfo>;
+          def nf # "E" # eew # "_V_" # LInfo # "_MASK"
+            : VPseudoSSegLoadMask<vreg, eew, nf>,
+              VLSSEGSchedMask<nf, eew, LInfo>;
         }
       }
     }
@@ -4004,7 +4625,7 @@
               def nf # "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo # "_MASK" :
                 VPseudoISegLoadMask<Vreg, IdxVreg, idxEEW, idxEMUL.value,
                                     nf, Ordered>,
-                VLXSEGSched<nf, dataEEW, Order, DataLInfo>;
+                VLXSEGSchedMask<nf, dataEEW, Order, DataLInfo>;
             }
           }
         }
@@ -4020,10 +4641,12 @@
       let VLMul = lmul.value, SEW=eew in {
         foreach nf = NFSet<lmul>.L in {
           defvar vreg = SegRegClass<lmul, nf>.RC;
-          def nf # "E" # eew # "_V_" # LInfo : VPseudoUSSegStoreNoMask<vreg, eew, nf>,
-                                               VSSEGSched<nf, eew, LInfo>;
-          def nf # "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoUSSegStoreMask<vreg, eew, nf>,
-                                                         VSSEGSched<nf, eew, LInfo>;
+          def nf # "E" # eew # "_V_" # LInfo
+            : VPseudoUSSegStoreNoMask<vreg, eew, nf>,
+              VSSEGSched<nf, eew, LInfo>;
+          def nf # "E" # eew # "_V_" # LInfo # "_MASK"
+            : VPseudoUSSegStoreMask<vreg, eew, nf>,
+              VSSEGSchedMask<nf, eew, LInfo>;
         }
       }
     }
@@ -4037,10 +4660,12 @@
       let VLMul = lmul.value, SEW=eew in {
         foreach nf = NFSet<lmul>.L in {
           defvar vreg = SegRegClass<lmul, nf>.RC;
-          def nf # "E" # eew # "_V_" # LInfo : VPseudoSSegStoreNoMask<vreg, eew, nf>,
-                                               VSSSEGSched<nf, eew, LInfo>;
-          def nf # "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoSSegStoreMask<vreg, eew, nf>,
-                                                         VSSSEGSched<nf, eew, LInfo>;
+          def nf # "E" # eew # "_V_" # LInfo
+            : VPseudoSSegStoreNoMask<vreg, eew, nf>,
+              VSSSEGSched<nf, eew, LInfo>;
+          def nf # "E" # eew # "_V_" # LInfo # "_MASK"
+            : VPseudoSSegStoreMask<vreg, eew, nf>,
+              VSSSEGSchedMask<nf, eew, LInfo>;
         }
       }
     }
@@ -4071,7 +4696,7 @@
               def nf # "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo # "_MASK" :
                 VPseudoISegStoreMask<Vreg, IdxVreg, idxEEW, idxEMUL.value,
                                      nf, Ordered>,
-                VSXSEGSched<nf, idxEEW, Order, DataLInfo>;
+                VSXSEGSchedMask<nf, idxEEW, Order, DataLInfo>;
             }
           }
         }
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
@@ -474,14 +474,16 @@
 //===----------------------------------------------------------------------===//
 multiclass VPseudoVMAQA_VV_VX {
   foreach m = MxListTHVdot in {
-    defm "" : VPseudoTernaryW_VV<m>;
-    defm "" : VPseudoTernaryW_VX<m>;
+    // TODO: Add SchedReadWrites
+    defm "" : VPseudoTernaryW_VV<m, [], []>;
+    defm "" : VPseudoTernaryW_VX<m, [], []>;
   }
 }
 
 multiclass VPseudoVMAQA_VX {
   foreach m = MxListTHVdot in {
-    defm "" : VPseudoTernaryW_VX<m>;
+    // TODO: Add SchedReadWrites
+    defm "" : VPseudoTernaryW_VX<m, [], []>;
   }
 }
 
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -1154,6 +1154,11 @@
 
 // Others
 def : ReadAdvance<ReadVMask, 0>;
+foreach mx = SchedMxList in {
+  def : ReadAdvance<!cast<SchedRead>("ReadVMergeOp_" # mx), 0>;
+  foreach sew = SchedSEWSet<mx>.val in
+    def : ReadAdvance<!cast<SchedRead>("ReadVMergeOp_" # mx  # "_E" # sew), 0>;
+}
 
 //===----------------------------------------------------------------------===//
 // Unsupported extensions
diff --git a/llvm/lib/Target/RISCV/RISCVScheduleV.td b/llvm/lib/Target/RISCV/RISCVScheduleV.td
--- a/llvm/lib/Target/RISCV/RISCVScheduleV.td
+++ b/llvm/lib/Target/RISCV/RISCVScheduleV.td
@@ -687,6 +687,11 @@
 
 // Others
 def ReadVMask         : SchedRead;
+foreach mx = SchedMxList in {
+  def ReadVMergeOp_ # mx : SchedRead;
+  foreach sew = SchedSEWSet<mx>.val in
+    def ReadVMergeOp_ # mx  # "_E" # sew : SchedRead;
+}
 
 //===----------------------------------------------------------------------===//
 /// Define default scheduler resources for V.
@@ -1050,6 +1055,11 @@
 
 // Others
 def : ReadAdvance<ReadVMask, 0>;
+foreach mx = SchedMxList in {
+  def : ReadAdvance<!cast<SchedRead>("ReadVMergeOp_" # mx), 0>;
+  foreach sew = SchedSEWSet<mx>.val in
+    def : ReadAdvance<!cast<SchedRead>("ReadVMergeOp_" # mx  # "_E" # sew), 0>;
+}
 
 } // Unsupported
 } // UnsupportedSchedV