Index: llvm/test/CodeGen/RISCV/condbinops.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/RISCV/condbinops.ll
@@ -0,0 +1,827 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -mtriple=riscv32 < %s | FileCheck %s -check-prefix=RV32I
+; RUN: llc -mtriple=riscv64 < %s | FileCheck %s -check-prefix=RV64I
+; RUN: llc -mtriple=riscv64 -mattr=+xventanacondops < %s | FileCheck %s -check-prefix=RV64XVENTANACONDOPS
+; RUN: llc -mtriple=riscv64 -mattr=+xtheadcondmov < %s | FileCheck %s -check-prefix=RV64XTHEADCONDMOV
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicond < %s | FileCheck %s -check-prefix=RV32ZICOND
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicond < %s | FileCheck %s -check-prefix=RV64ZICOND
+
+define i64 @shl(i64 %x, i64 %y, i1 %c) {
+; RV32I-LABEL: shl:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    andi a4, a4, 1
+; RV32I-NEXT:    addi a5, a2, -32
+; RV32I-NEXT:    sll a3, a0, a2
+; RV32I-NEXT:    bltz a5, .LBB0_3
+; RV32I-NEXT:  # %bb.1:
+; RV32I-NEXT:    mv a2, a3
+; RV32I-NEXT:    beqz a4, .LBB0_4
+; RV32I-NEXT:  .LBB0_2:
+; RV32I-NEXT:    srai a0, a5, 31
+; RV32I-NEXT:    and a0, a0, a3
+; RV32I-NEXT:    mv a1, a2
+; RV32I-NEXT:    ret
+; RV32I-NEXT:  .LBB0_3:
+; RV32I-NEXT:    sll a6, a1, a2
+; RV32I-NEXT:    not a2, a2
+; RV32I-NEXT:    srli a7, a0, 1
+; RV32I-NEXT:    srl a2, a7, a2
+; RV32I-NEXT:    or a2, a6, a2
+; RV32I-NEXT:    bnez a4, .LBB0_2
+; RV32I-NEXT:  .LBB0_4:
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: shl:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    andi a2, a2, 1
+; RV64I-NEXT:    beqz a2, .LBB0_2
+; RV64I-NEXT:  # %bb.1:
+; RV64I-NEXT:    sll a0, a0, a1
+; RV64I-NEXT:  .LBB0_2:
+; RV64I-NEXT:    ret
+;
+; RV64XVENTANACONDOPS-LABEL: shl:
+; RV64XVENTANACONDOPS:       # %bb.0:
+; RV64XVENTANACONDOPS-NEXT:    andi a2, a2, 1
+; RV64XVENTANACONDOPS-NEXT:    sll a1, a0, a1
+; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a0, a0, a2
+; RV64XVENTANACONDOPS-NEXT:    vt.maskc a1, a1, a2
+; RV64XVENTANACONDOPS-NEXT:    or a0, a1, a0
+; RV64XVENTANACONDOPS-NEXT:    ret
+;
+; RV64XTHEADCONDMOV-LABEL: shl:
+; RV64XTHEADCONDMOV:       # %bb.0:
+; RV64XTHEADCONDMOV-NEXT:    andi a2, a2, 1
+; RV64XTHEADCONDMOV-NEXT:    sll a1, a0, a1
+; RV64XTHEADCONDMOV-NEXT:    th.mvnez a0, a1, a2
+; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: shl:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    andi a4, a4, 1
+; RV32ZICOND-NEXT:    sll a3, a1, a2
+; RV32ZICOND-NEXT:    not a5, a2
+; RV32ZICOND-NEXT:    srli a6, a0, 1
+; RV32ZICOND-NEXT:    srl a5, a6, a5
+; RV32ZICOND-NEXT:    or a3, a3, a5
+; RV32ZICOND-NEXT:    addi a5, a2, -32
+; RV32ZICOND-NEXT:    slti a5, a5, 0
+; RV32ZICOND-NEXT:    czero.eqz a3, a3, a5
+; RV32ZICOND-NEXT:    sll a2, a0, a2
+; RV32ZICOND-NEXT:    czero.nez a6, a2, a5
+; RV32ZICOND-NEXT:    or a3, a3, a6
+; RV32ZICOND-NEXT:    czero.eqz a2, a2, a5
+; RV32ZICOND-NEXT:    czero.nez a0, a0, a4
+; RV32ZICOND-NEXT:    czero.eqz a2, a2, a4
+; RV32ZICOND-NEXT:    or a0, a2, a0
+; RV32ZICOND-NEXT:    czero.eqz a2, a3, a4
+; RV32ZICOND-NEXT:    czero.nez a1, a1, a4
+; RV32ZICOND-NEXT:    or a1, a2, a1
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: shl:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    andi a2, a2, 1
+; RV64ZICOND-NEXT:    sll a1, a0, a1
+; RV64ZICOND-NEXT:    czero.nez a0, a0, a2
+; RV64ZICOND-NEXT:    czero.eqz a1, a1, a2
+; RV64ZICOND-NEXT:    or a0, a1, a0
+; RV64ZICOND-NEXT:    ret
+  %binop = shl i64 %x, %y
+  %select_ = select i1 %c, i64 %binop, i64 %x
+  ret i64 %select_
+}
+
+define i64 @ashr(i64 %x, i64 %y, i1 %c) {
+; RV32I-LABEL: ashr:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    andi a5, a4, 1
+; RV32I-NEXT:    addi a3, a2, -32
+; RV32I-NEXT:    sra a4, a1, a2
+; RV32I-NEXT:    bltz a3, .LBB1_2
+; RV32I-NEXT:  # %bb.1:
+; RV32I-NEXT:    srai a2, a1, 31
+; RV32I-NEXT:    mv a3, a4
+; RV32I-NEXT:    mv a4, a2
+; RV32I-NEXT:    beqz a5, .LBB1_3
+; RV32I-NEXT:    j .LBB1_4
+; RV32I-NEXT:  .LBB1_2:
+; RV32I-NEXT:    srl a3, a0, a2
+; RV32I-NEXT:    not a2, a2
+; RV32I-NEXT:    slli a6, a1, 1
+; RV32I-NEXT:    sll a2, a6, a2
+; RV32I-NEXT:    or a3, a3, a2
+; RV32I-NEXT:    bnez a5, .LBB1_4
+; RV32I-NEXT:  .LBB1_3:
+; RV32I-NEXT:    mv a3, a0
+; RV32I-NEXT:    mv a4, a1
+; RV32I-NEXT:  .LBB1_4:
+; RV32I-NEXT:    mv a0, a3
+; RV32I-NEXT:    mv a1, a4
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: ashr:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    andi a2, a2, 1
+; RV64I-NEXT:    beqz a2, .LBB1_2
+; RV64I-NEXT:  # %bb.1:
+; RV64I-NEXT:    sra a0, a0, a1
+; RV64I-NEXT:  .LBB1_2:
+; RV64I-NEXT:    ret
+;
+; RV64XVENTANACONDOPS-LABEL: ashr:
+; RV64XVENTANACONDOPS:       # %bb.0:
+; RV64XVENTANACONDOPS-NEXT:    andi a2, a2, 1
+; RV64XVENTANACONDOPS-NEXT:    sra a1, a0, a1
+; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a0, a0, a2
+; RV64XVENTANACONDOPS-NEXT:    vt.maskc a1, a1, a2
+; RV64XVENTANACONDOPS-NEXT:    or a0, a1, a0
+; RV64XVENTANACONDOPS-NEXT:    ret
+;
+; RV64XTHEADCONDMOV-LABEL: ashr:
+; RV64XTHEADCONDMOV:       # %bb.0:
+; RV64XTHEADCONDMOV-NEXT:    andi a2, a2, 1
+; RV64XTHEADCONDMOV-NEXT:    sra a1, a0, a1
+; RV64XTHEADCONDMOV-NEXT:    th.mvnez a0, a1, a2
+; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: ashr:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    andi a4, a4, 1
+; RV32ZICOND-NEXT:    srl a3, a0, a2
+; RV32ZICOND-NEXT:    not a5, a2
+; RV32ZICOND-NEXT:    slli a6, a1, 1
+; RV32ZICOND-NEXT:    sll a5, a6, a5
+; RV32ZICOND-NEXT:    or a3, a3, a5
+; RV32ZICOND-NEXT:    addi a5, a2, -32
+; RV32ZICOND-NEXT:    slti a5, a5, 0
+; RV32ZICOND-NEXT:    czero.eqz a3, a3, a5
+; RV32ZICOND-NEXT:    sra a2, a1, a2
+; RV32ZICOND-NEXT:    czero.nez a6, a2, a5
+; RV32ZICOND-NEXT:    or a3, a3, a6
+; RV32ZICOND-NEXT:    srai a6, a1, 31
+; RV32ZICOND-NEXT:    czero.nez a6, a6, a5
+; RV32ZICOND-NEXT:    czero.eqz a2, a2, a5
+; RV32ZICOND-NEXT:    or a2, a2, a6
+; RV32ZICOND-NEXT:    czero.eqz a2, a2, a4
+; RV32ZICOND-NEXT:    czero.nez a1, a1, a4
+; RV32ZICOND-NEXT:    or a1, a2, a1
+; RV32ZICOND-NEXT:    czero.eqz a2, a3, a4
+; RV32ZICOND-NEXT:    czero.nez a0, a0, a4
+; RV32ZICOND-NEXT:    or a0, a2, a0
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: ashr:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    andi a2, a2, 1
+; RV64ZICOND-NEXT:    sra a1, a0, a1
+; RV64ZICOND-NEXT:    czero.nez a0, a0, a2
+; RV64ZICOND-NEXT:    czero.eqz a1, a1, a2
+; RV64ZICOND-NEXT:    or a0, a1, a0
+; RV64ZICOND-NEXT:    ret
+  %binop = ashr i64 %x, %y
+  %select_ = select i1 %c, i64 %binop, i64 %x
+  ret i64 %select_
+}
+
+define i64 @lshr(i64 %x, i64 %y, i1 %c) {
+; RV32I-LABEL: lshr:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    andi a4, a4, 1
+; RV32I-NEXT:    addi a5, a2, -32
+; RV32I-NEXT:    srl a3, a1, a2
+; RV32I-NEXT:    bltz a5, .LBB2_3
+; RV32I-NEXT:  # %bb.1:
+; RV32I-NEXT:    mv a2, a3
+; RV32I-NEXT:    beqz a4, .LBB2_4
+; RV32I-NEXT:  .LBB2_2:
+; RV32I-NEXT:    srai a1, a5, 31
+; RV32I-NEXT:    and a1, a1, a3
+; RV32I-NEXT:    mv a0, a2
+; RV32I-NEXT:    ret
+; RV32I-NEXT:  .LBB2_3:
+; RV32I-NEXT:    srl a6, a0, a2
+; RV32I-NEXT:    not a2, a2
+; RV32I-NEXT:    slli a7, a1, 1
+; RV32I-NEXT:    sll a2, a7, a2
+; RV32I-NEXT:    or a2, a6, a2
+; RV32I-NEXT:    bnez a4, .LBB2_2
+; RV32I-NEXT:  .LBB2_4:
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: lshr:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    andi a2, a2, 1
+; RV64I-NEXT:    beqz a2, .LBB2_2
+; RV64I-NEXT:  # %bb.1:
+; RV64I-NEXT:    srl a0, a0, a1
+; RV64I-NEXT:  .LBB2_2:
+; RV64I-NEXT:    ret
+;
+; RV64XVENTANACONDOPS-LABEL: lshr:
+; RV64XVENTANACONDOPS:       # %bb.0:
+; RV64XVENTANACONDOPS-NEXT:    andi a2, a2, 1
+; RV64XVENTANACONDOPS-NEXT:    srl a1, a0, a1
+; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a0, a0, a2
+; RV64XVENTANACONDOPS-NEXT:    vt.maskc a1, a1, a2
+; RV64XVENTANACONDOPS-NEXT:    or a0, a1, a0
+; RV64XVENTANACONDOPS-NEXT:    ret
+;
+; RV64XTHEADCONDMOV-LABEL: lshr:
+; RV64XTHEADCONDMOV:       # %bb.0:
+; RV64XTHEADCONDMOV-NEXT:    andi a2, a2, 1
+; RV64XTHEADCONDMOV-NEXT:    srl a1, a0, a1
+; RV64XTHEADCONDMOV-NEXT:    th.mvnez a0, a1, a2
+; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: lshr:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    andi a4, a4, 1
+; RV32ZICOND-NEXT:    srl a3, a0, a2
+; RV32ZICOND-NEXT:    not a5, a2
+; RV32ZICOND-NEXT:    slli a6, a1, 1
+; RV32ZICOND-NEXT:    sll a5, a6, a5
+; RV32ZICOND-NEXT:    or a3, a3, a5
+; RV32ZICOND-NEXT:    addi a5, a2, -32
+; RV32ZICOND-NEXT:    slti a5, a5, 0
+; RV32ZICOND-NEXT:    czero.eqz a3, a3, a5
+; RV32ZICOND-NEXT:    srl a2, a1, a2
+; RV32ZICOND-NEXT:    czero.nez a6, a2, a5
+; RV32ZICOND-NEXT:    or a3, a3, a6
+; RV32ZICOND-NEXT:    czero.eqz a2, a2, a5
+; RV32ZICOND-NEXT:    czero.nez a1, a1, a4
+; RV32ZICOND-NEXT:    czero.eqz a2, a2, a4
+; RV32ZICOND-NEXT:    or a1, a2, a1
+; RV32ZICOND-NEXT:    czero.eqz a2, a3, a4
+; RV32ZICOND-NEXT:    czero.nez a0, a0, a4
+; RV32ZICOND-NEXT:    or a0, a2, a0
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: lshr:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    andi a2, a2, 1
+; RV64ZICOND-NEXT:    srl a1, a0, a1
+; RV64ZICOND-NEXT:    czero.nez a0, a0, a2
+; RV64ZICOND-NEXT:    czero.eqz a1, a1, a2
+; RV64ZICOND-NEXT:    or a0, a1, a0
+; RV64ZICOND-NEXT:    ret
+  %binop = lshr i64 %x, %y
+  %select_ = select i1 %c, i64 %binop, i64 %x
+  ret i64 %select_
+}
+
+define i64 @sub(i64 %x, i64 %y, i1 %c) {
+; RV32I-LABEL: sub:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    slli a4, a4, 31
+; RV32I-NEXT:    srai a4, a4, 31
+; RV32I-NEXT:    and a2, a4, a2
+; RV32I-NEXT:    sltu a5, a0, a2
+; RV32I-NEXT:    and a3, a4, a3
+; RV32I-NEXT:    sub a1, a1, a3
+; RV32I-NEXT:    sub a1, a1, a5
+; RV32I-NEXT:    sub a0, a0, a2
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: sub:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    slli a2, a2, 63
+; RV64I-NEXT:    srai a2, a2, 63
+; RV64I-NEXT:    and a1, a2, a1
+; RV64I-NEXT:    sub a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64XVENTANACONDOPS-LABEL: sub:
+; RV64XVENTANACONDOPS:       # %bb.0:
+; RV64XVENTANACONDOPS-NEXT:    andi a2, a2, 1
+; RV64XVENTANACONDOPS-NEXT:    vt.maskc a1, a1, a2
+; RV64XVENTANACONDOPS-NEXT:    sub a0, a0, a1
+; RV64XVENTANACONDOPS-NEXT:    ret
+;
+; RV64XTHEADCONDMOV-LABEL: sub:
+; RV64XTHEADCONDMOV:       # %bb.0:
+; RV64XTHEADCONDMOV-NEXT:    andi a2, a2, 1
+; RV64XTHEADCONDMOV-NEXT:    th.mveqz a1, zero, a2
+; RV64XTHEADCONDMOV-NEXT:    sub a0, a0, a1
+; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: sub:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    andi a4, a4, 1
+; RV32ZICOND-NEXT:    czero.eqz a2, a2, a4
+; RV32ZICOND-NEXT:    sltu a5, a0, a2
+; RV32ZICOND-NEXT:    czero.eqz a3, a3, a4
+; RV32ZICOND-NEXT:    sub a1, a1, a3
+; RV32ZICOND-NEXT:    sub a1, a1, a5
+; RV32ZICOND-NEXT:    sub a0, a0, a2
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: sub:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    andi a2, a2, 1
+; RV64ZICOND-NEXT:    czero.eqz a1, a1, a2
+; RV64ZICOND-NEXT:    sub a0, a0, a1
+; RV64ZICOND-NEXT:    ret
+  %binop = sub i64 %x, %y
+  %select_ = select i1 %c, i64 %binop, i64 %x
+  ret i64 %select_
+}
+
+define i64 @and(i64 %x, i64 %y, i1 %c) {
+; RV32I-LABEL: and:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    andi a4, a4, 1
+; RV32I-NEXT:    beqz a4, .LBB4_2
+; RV32I-NEXT:  # %bb.1:
+; RV32I-NEXT:    and a1, a1, a3
+; RV32I-NEXT:    and a0, a0, a2
+; RV32I-NEXT:  .LBB4_2:
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: and:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    andi a2, a2, 1
+; RV64I-NEXT:    beqz a2, .LBB4_2
+; RV64I-NEXT:  # %bb.1:
+; RV64I-NEXT:    and a0, a0, a1
+; RV64I-NEXT:  .LBB4_2:
+; RV64I-NEXT:    ret
+;
+; RV64XVENTANACONDOPS-LABEL: and:
+; RV64XVENTANACONDOPS:       # %bb.0:
+; RV64XVENTANACONDOPS-NEXT:    andi a2, a2, 1
+; RV64XVENTANACONDOPS-NEXT:    and a1, a0, a1
+; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a0, a0, a2
+; RV64XVENTANACONDOPS-NEXT:    or a0, a1, a0
+; RV64XVENTANACONDOPS-NEXT:    ret
+;
+; RV64XTHEADCONDMOV-LABEL: and:
+; RV64XTHEADCONDMOV:       # %bb.0:
+; RV64XTHEADCONDMOV-NEXT:    andi a2, a2, 1
+; RV64XTHEADCONDMOV-NEXT:    and a1, a0, a1
+; RV64XTHEADCONDMOV-NEXT:    th.mvnez a0, a1, a2
+; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: and:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    andi a4, a4, 1
+; RV32ZICOND-NEXT:    and a3, a1, a3
+; RV32ZICOND-NEXT:    and a2, a0, a2
+; RV32ZICOND-NEXT:    czero.nez a0, a0, a4
+; RV32ZICOND-NEXT:    or a0, a2, a0
+; RV32ZICOND-NEXT:    czero.nez a1, a1, a4
+; RV32ZICOND-NEXT:    or a1, a3, a1
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: and:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    andi a2, a2, 1
+; RV64ZICOND-NEXT:    and a1, a0, a1
+; RV64ZICOND-NEXT:    czero.nez a0, a0, a2
+; RV64ZICOND-NEXT:    or a0, a1, a0
+; RV64ZICOND-NEXT:    ret
+  %binop = and i64 %x, %y
+  %select_ = select i1 %c, i64 %binop, i64 %x
+  ret i64 %select_
+}
+
+
+define i64 @add(i64 %x, i64 %y, i1 %c) {
+; RV32I-LABEL: add:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    slli a4, a4, 31
+; RV32I-NEXT:    srai a4, a4, 31
+; RV32I-NEXT:    and a3, a4, a3
+; RV32I-NEXT:    add a1, a1, a3
+; RV32I-NEXT:    and a2, a4, a2
+; RV32I-NEXT:    add a2, a0, a2
+; RV32I-NEXT:    sltu a0, a2, a0
+; RV32I-NEXT:    add a1, a1, a0
+; RV32I-NEXT:    mv a0, a2
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: add:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    slli a2, a2, 63
+; RV64I-NEXT:    srai a2, a2, 63
+; RV64I-NEXT:    and a1, a2, a1
+; RV64I-NEXT:    add a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64XVENTANACONDOPS-LABEL: add:
+; RV64XVENTANACONDOPS:       # %bb.0:
+; RV64XVENTANACONDOPS-NEXT:    andi a2, a2, 1
+; RV64XVENTANACONDOPS-NEXT:    vt.maskc a1, a1, a2
+; RV64XVENTANACONDOPS-NEXT:    add a0, a0, a1
+; RV64XVENTANACONDOPS-NEXT:    ret
+;
+; RV64XTHEADCONDMOV-LABEL: add:
+; RV64XTHEADCONDMOV:       # %bb.0:
+; RV64XTHEADCONDMOV-NEXT:    andi a2, a2, 1
+; RV64XTHEADCONDMOV-NEXT:    th.mveqz a1, zero, a2
+; RV64XTHEADCONDMOV-NEXT:    add a0, a0, a1
+; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: add:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    andi a4, a4, 1
+; RV32ZICOND-NEXT:    czero.eqz a3, a3, a4
+; RV32ZICOND-NEXT:    add a1, a1, a3
+; RV32ZICOND-NEXT:    czero.eqz a2, a2, a4
+; RV32ZICOND-NEXT:    add a2, a0, a2
+; RV32ZICOND-NEXT:    sltu a0, a2, a0
+; RV32ZICOND-NEXT:    add a1, a1, a0
+; RV32ZICOND-NEXT:    mv a0, a2
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: add:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    andi a2, a2, 1
+; RV64ZICOND-NEXT:    czero.eqz a1, a1, a2
+; RV64ZICOND-NEXT:    add a0, a0, a1
+; RV64ZICOND-NEXT:    ret
+  %binop = add i64 %x, %y
+  %select_ = select i1 %c, i64 %binop, i64 %x
+  ret i64 %select_
+}
+
+
+define i64 @or(i64 %x, i64 %y, i1 %c) {
+; RV32I-LABEL: or:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    slli a4, a4, 31
+; RV32I-NEXT:    srai a4, a4, 31
+; RV32I-NEXT:    and a2, a4, a2
+; RV32I-NEXT:    or a0, a0, a2
+; RV32I-NEXT:    and a3, a4, a3
+; RV32I-NEXT:    or a1, a1, a3
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: or:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    slli a2, a2, 63
+; RV64I-NEXT:    srai a2, a2, 63
+; RV64I-NEXT:    and a1, a2, a1
+; RV64I-NEXT:    or a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64XVENTANACONDOPS-LABEL: or:
+; RV64XVENTANACONDOPS:       # %bb.0:
+; RV64XVENTANACONDOPS-NEXT:    andi a2, a2, 1
+; RV64XVENTANACONDOPS-NEXT:    vt.maskc a1, a1, a2
+; RV64XVENTANACONDOPS-NEXT:    or a0, a0, a1
+; RV64XVENTANACONDOPS-NEXT:    ret
+;
+; RV64XTHEADCONDMOV-LABEL: or:
+; RV64XTHEADCONDMOV:       # %bb.0:
+; RV64XTHEADCONDMOV-NEXT:    andi a2, a2, 1
+; RV64XTHEADCONDMOV-NEXT:    th.mveqz a1, zero, a2
+; RV64XTHEADCONDMOV-NEXT:    or a0, a0, a1
+; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: or:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    andi a4, a4, 1
+; RV32ZICOND-NEXT:    czero.eqz a2, a2, a4
+; RV32ZICOND-NEXT:    or a0, a0, a2
+; RV32ZICOND-NEXT:    czero.eqz a2, a3, a4
+; RV32ZICOND-NEXT:    or a1, a1, a2
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: or:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    andi a2, a2, 1
+; RV64ZICOND-NEXT:    czero.eqz a1, a1, a2
+; RV64ZICOND-NEXT:    or a0, a0, a1
+; RV64ZICOND-NEXT:    ret
+  %binop = or i64 %x, %y
+  %select_ = select i1 %c, i64 %binop, i64 %x
+  ret i64 %select_
+}
+
+define i64 @xor(i64 %x, i64 %y, i1 %c) {
+; RV32I-LABEL: xor:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    slli a4, a4, 31
+; RV32I-NEXT:    srai a4, a4, 31
+; RV32I-NEXT:    and a2, a4, a2
+; RV32I-NEXT:    xor a0, a0, a2
+; RV32I-NEXT:    and a3, a4, a3
+; RV32I-NEXT:    xor a1, a1, a3
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: xor:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    slli a2, a2, 63
+; RV64I-NEXT:    srai a2, a2, 63
+; RV64I-NEXT:    and a1, a2, a1
+; RV64I-NEXT:    xor a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64XVENTANACONDOPS-LABEL: xor:
+; RV64XVENTANACONDOPS:       # %bb.0:
+; RV64XVENTANACONDOPS-NEXT:    andi a2, a2, 1
+; RV64XVENTANACONDOPS-NEXT:    vt.maskc a1, a1, a2
+; RV64XVENTANACONDOPS-NEXT:    xor a0, a0, a1
+; RV64XVENTANACONDOPS-NEXT:    ret
+;
+; RV64XTHEADCONDMOV-LABEL: xor:
+; RV64XTHEADCONDMOV:       # %bb.0:
+; RV64XTHEADCONDMOV-NEXT:    andi a2, a2, 1
+; RV64XTHEADCONDMOV-NEXT:    th.mveqz a1, zero, a2
+; RV64XTHEADCONDMOV-NEXT:    xor a0, a0, a1
+; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: xor:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    andi a4, a4, 1
+; RV32ZICOND-NEXT:    czero.eqz a2, a2, a4
+; RV32ZICOND-NEXT:    xor a0, a0, a2
+; RV32ZICOND-NEXT:    czero.eqz a2, a3, a4
+; RV32ZICOND-NEXT:    xor a1, a1, a2
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: xor:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    andi a2, a2, 1
+; RV64ZICOND-NEXT:    czero.eqz a1, a1, a2
+; RV64ZICOND-NEXT:    xor a0, a0, a1
+; RV64ZICOND-NEXT:    ret
+  %binop = xor i64 %x, %y
+  %select_ = select i1 %c, i64 %binop, i64 %x
+  ret i64 %select_
+}
+
+define float @fadd(float %x, float %y, i1 %c) {
+; RV32I-LABEL: fadd:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi sp, sp, -16
+; RV32I-NEXT:    .cfi_def_cfa_offset 16
+; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT:    .cfi_offset ra, -4
+; RV32I-NEXT:    .cfi_offset s0, -8
+; RV32I-NEXT:    .cfi_offset s1, -12
+; RV32I-NEXT:    mv s0, a0
+; RV32I-NEXT:    andi s1, a2, 1
+; RV32I-NEXT:    call __addsf3@plt
+; RV32I-NEXT:    bnez s1, .LBB8_2
+; RV32I-NEXT:  # %bb.1:
+; RV32I-NEXT:    mv a0, s0
+; RV32I-NEXT:  .LBB8_2:
+; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT:    addi sp, sp, 16
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: fadd:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -32
+; RV64I-NEXT:    .cfi_def_cfa_offset 32
+; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT:    .cfi_offset ra, -8
+; RV64I-NEXT:    .cfi_offset s0, -16
+; RV64I-NEXT:    .cfi_offset s1, -24
+; RV64I-NEXT:    mv s0, a0
+; RV64I-NEXT:    andi s1, a2, 1
+; RV64I-NEXT:    call __addsf3@plt
+; RV64I-NEXT:    bnez s1, .LBB8_2
+; RV64I-NEXT:  # %bb.1:
+; RV64I-NEXT:    mv a0, s0
+; RV64I-NEXT:  .LBB8_2:
+; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT:    addi sp, sp, 32
+; RV64I-NEXT:    ret
+;
+; RV64XVENTANACONDOPS-LABEL: fadd:
+; RV64XVENTANACONDOPS:       # %bb.0:
+; RV64XVENTANACONDOPS-NEXT:    addi sp, sp, -32
+; RV64XVENTANACONDOPS-NEXT:    .cfi_def_cfa_offset 32
+; RV64XVENTANACONDOPS-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+; RV64XVENTANACONDOPS-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
+; RV64XVENTANACONDOPS-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
+; RV64XVENTANACONDOPS-NEXT:    .cfi_offset ra, -8
+; RV64XVENTANACONDOPS-NEXT:    .cfi_offset s0, -16
+; RV64XVENTANACONDOPS-NEXT:    .cfi_offset s1, -24
+; RV64XVENTANACONDOPS-NEXT:    mv s0, a0
+; RV64XVENTANACONDOPS-NEXT:    andi s1, a2, 1
+; RV64XVENTANACONDOPS-NEXT:    call __addsf3@plt
+; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a1, s0, s1
+; RV64XVENTANACONDOPS-NEXT:    vt.maskc a0, a0, s1
+; RV64XVENTANACONDOPS-NEXT:    or a0, a0, a1
+; RV64XVENTANACONDOPS-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
+; RV64XVENTANACONDOPS-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
+; RV64XVENTANACONDOPS-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
+; RV64XVENTANACONDOPS-NEXT:    addi sp, sp, 32
+; RV64XVENTANACONDOPS-NEXT:    ret
+;
+; RV64XTHEADCONDMOV-LABEL: fadd:
+; RV64XTHEADCONDMOV:       # %bb.0:
+; RV64XTHEADCONDMOV-NEXT:    addi sp, sp, -32
+; RV64XTHEADCONDMOV-NEXT:    .cfi_def_cfa_offset 32
+; RV64XTHEADCONDMOV-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+; RV64XTHEADCONDMOV-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
+; RV64XTHEADCONDMOV-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
+; RV64XTHEADCONDMOV-NEXT:    .cfi_offset ra, -8
+; RV64XTHEADCONDMOV-NEXT:    .cfi_offset s0, -16
+; RV64XTHEADCONDMOV-NEXT:    .cfi_offset s1, -24
+; RV64XTHEADCONDMOV-NEXT:    mv s0, a0
+; RV64XTHEADCONDMOV-NEXT:    andi s1, a2, 1
+; RV64XTHEADCONDMOV-NEXT:    call __addsf3@plt
+; RV64XTHEADCONDMOV-NEXT:    th.mveqz a0, s0, s1
+; RV64XTHEADCONDMOV-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
+; RV64XTHEADCONDMOV-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
+; RV64XTHEADCONDMOV-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
+; RV64XTHEADCONDMOV-NEXT:    addi sp, sp, 32
+; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: fadd:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    addi sp, sp, -16
+; RV32ZICOND-NEXT:    .cfi_def_cfa_offset 16
+; RV32ZICOND-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32ZICOND-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32ZICOND-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; RV32ZICOND-NEXT:    .cfi_offset ra, -4
+; RV32ZICOND-NEXT:    .cfi_offset s0, -8
+; RV32ZICOND-NEXT:    .cfi_offset s1, -12
+; RV32ZICOND-NEXT:    mv s0, a0
+; RV32ZICOND-NEXT:    andi s1, a2, 1
+; RV32ZICOND-NEXT:    call __addsf3@plt
+; RV32ZICOND-NEXT:    czero.nez a1, s0, s1
+; RV32ZICOND-NEXT:    czero.eqz a0, a0, s1
+; RV32ZICOND-NEXT:    or a0, a0, a1
+; RV32ZICOND-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32ZICOND-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32ZICOND-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; RV32ZICOND-NEXT:    addi sp, sp, 16
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: fadd:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    addi sp, sp, -32
+; RV64ZICOND-NEXT:    .cfi_def_cfa_offset 32
+; RV64ZICOND-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+; RV64ZICOND-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
+; RV64ZICOND-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
+; RV64ZICOND-NEXT:    .cfi_offset ra, -8
+; RV64ZICOND-NEXT:    .cfi_offset s0, -16
+; RV64ZICOND-NEXT:    .cfi_offset s1, -24
+; RV64ZICOND-NEXT:    mv s0, a0
+; RV64ZICOND-NEXT:    andi s1, a2, 1
+; RV64ZICOND-NEXT:    call __addsf3@plt
+; RV64ZICOND-NEXT:    czero.nez a1, s0, s1
+; RV64ZICOND-NEXT:    czero.eqz a0, a0, s1
+; RV64ZICOND-NEXT:    or a0, a0, a1
+; RV64ZICOND-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
+; RV64ZICOND-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
+; RV64ZICOND-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
+; RV64ZICOND-NEXT:    addi sp, sp, 32
+; RV64ZICOND-NEXT:    ret
+  %binop = fadd float %x, %y
+  %select_ = select i1 %c, float %binop, float %x
+  ret float %select_
+}
+
+define float @fsub(float %x, float %y, i1 %c) {
+; RV32I-LABEL: fsub:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi sp, sp, -16
+; RV32I-NEXT:    .cfi_def_cfa_offset 16
+; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT:    .cfi_offset ra, -4
+; RV32I-NEXT:    .cfi_offset s0, -8
+; RV32I-NEXT:    .cfi_offset s1, -12
+; RV32I-NEXT:    mv s0, a0
+; RV32I-NEXT:    andi s1, a2, 1
+; RV32I-NEXT:    call __subsf3@plt
+; RV32I-NEXT:    bnez s1, .LBB9_2
+; RV32I-NEXT:  # %bb.1:
+; RV32I-NEXT:    mv a0, s0
+; RV32I-NEXT:  .LBB9_2:
+; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT:    addi sp, sp, 16
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: fsub:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -32
+; RV64I-NEXT:    .cfi_def_cfa_offset 32
+; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT:    .cfi_offset ra, -8
+; RV64I-NEXT:    .cfi_offset s0, -16
+; RV64I-NEXT:    .cfi_offset s1, -24
+; RV64I-NEXT:    mv s0, a0
+; RV64I-NEXT:    andi s1, a2, 1
+; RV64I-NEXT:    call __subsf3@plt
+; RV64I-NEXT:    bnez s1, .LBB9_2
+; RV64I-NEXT:  # %bb.1:
+; RV64I-NEXT:    mv a0, s0
+; RV64I-NEXT:  .LBB9_2:
+; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT:    addi sp, sp, 32
+; RV64I-NEXT:    ret
+;
+; RV64XVENTANACONDOPS-LABEL: fsub:
+; RV64XVENTANACONDOPS:       # %bb.0:
+; RV64XVENTANACONDOPS-NEXT:    addi sp, sp, -32
+; RV64XVENTANACONDOPS-NEXT:    .cfi_def_cfa_offset 32
+; RV64XVENTANACONDOPS-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+; RV64XVENTANACONDOPS-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
+; RV64XVENTANACONDOPS-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
+; RV64XVENTANACONDOPS-NEXT:    .cfi_offset ra, -8
+; RV64XVENTANACONDOPS-NEXT:    .cfi_offset s0, -16
+; RV64XVENTANACONDOPS-NEXT:    .cfi_offset s1, -24
+; RV64XVENTANACONDOPS-NEXT:    mv s0, a0
+; RV64XVENTANACONDOPS-NEXT:    andi s1, a2, 1
+; RV64XVENTANACONDOPS-NEXT:    call __subsf3@plt
+; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a1, s0, s1
+; RV64XVENTANACONDOPS-NEXT:    vt.maskc a0, a0, s1
+; RV64XVENTANACONDOPS-NEXT:    or a0, a0, a1
+; RV64XVENTANACONDOPS-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
+; RV64XVENTANACONDOPS-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
+; RV64XVENTANACONDOPS-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
+; RV64XVENTANACONDOPS-NEXT:    addi sp, sp, 32
+; RV64XVENTANACONDOPS-NEXT:    ret
+;
+; RV64XTHEADCONDMOV-LABEL: fsub:
+; RV64XTHEADCONDMOV:       # %bb.0:
+; RV64XTHEADCONDMOV-NEXT:    addi sp, sp, -32
+; RV64XTHEADCONDMOV-NEXT:    .cfi_def_cfa_offset 32
+; RV64XTHEADCONDMOV-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+; RV64XTHEADCONDMOV-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
+; RV64XTHEADCONDMOV-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
+; RV64XTHEADCONDMOV-NEXT:    .cfi_offset ra, -8
+; RV64XTHEADCONDMOV-NEXT:    .cfi_offset s0, -16
+; RV64XTHEADCONDMOV-NEXT:    .cfi_offset s1, -24
+; RV64XTHEADCONDMOV-NEXT:    mv s0, a0
+; RV64XTHEADCONDMOV-NEXT:    andi s1, a2, 1
+; RV64XTHEADCONDMOV-NEXT:    call __subsf3@plt
+; RV64XTHEADCONDMOV-NEXT:    th.mveqz a0, s0, s1
+; RV64XTHEADCONDMOV-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
+; RV64XTHEADCONDMOV-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
+; RV64XTHEADCONDMOV-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
+; RV64XTHEADCONDMOV-NEXT:    addi sp, sp, 32
+; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: fsub:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    addi sp, sp, -16
+; RV32ZICOND-NEXT:    .cfi_def_cfa_offset 16
+; RV32ZICOND-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32ZICOND-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32ZICOND-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; RV32ZICOND-NEXT:    .cfi_offset ra, -4
+; RV32ZICOND-NEXT:    .cfi_offset s0, -8
+; RV32ZICOND-NEXT:    .cfi_offset s1, -12
+; RV32ZICOND-NEXT:    mv s0, a0
+; RV32ZICOND-NEXT:    andi s1, a2, 1
+; RV32ZICOND-NEXT:    call __subsf3@plt
+; RV32ZICOND-NEXT:    czero.nez a1, s0, s1
+; RV32ZICOND-NEXT:    czero.eqz a0, a0, s1
+; RV32ZICOND-NEXT:    or a0, a0, a1
+; RV32ZICOND-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32ZICOND-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32ZICOND-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; RV32ZICOND-NEXT:    addi sp, sp, 16
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: fsub:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    addi sp, sp, -32
+; RV64ZICOND-NEXT:    .cfi_def_cfa_offset 32
+; RV64ZICOND-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+; RV64ZICOND-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
+; RV64ZICOND-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
+; RV64ZICOND-NEXT:    .cfi_offset ra, -8
+; RV64ZICOND-NEXT:    .cfi_offset s0, -16
+; RV64ZICOND-NEXT:    .cfi_offset s1, -24
+; RV64ZICOND-NEXT:    mv s0, a0
+; RV64ZICOND-NEXT:    andi s1, a2, 1
+; RV64ZICOND-NEXT:    call __subsf3@plt
+; RV64ZICOND-NEXT:    czero.nez a1, s0, s1
+; RV64ZICOND-NEXT:    czero.eqz a0, a0, s1
+; RV64ZICOND-NEXT:    or a0, a0, a1
+; RV64ZICOND-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
+; RV64ZICOND-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
+; RV64ZICOND-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
+; RV64ZICOND-NEXT:    addi sp, sp, 32
+; RV64ZICOND-NEXT:    ret
+  %binop = fsub float %x, %y
+  %select_ = select i1 %c, float %binop, float %x
+  ret float %select_
+}