diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td @@ -351,7 +351,7 @@ Sched<[WriteSingleBit, ReadSingleBit, ReadSingleBit]>; let IsSignExtendingOpW = 1 in def BEXT : ALU_rr<0b0100100, 0b101, "bext">, - Sched<[WriteSingleBit, ReadSingleBit, ReadSingleBit]>; + Sched<[WriteBEXT, ReadSingleBit, ReadSingleBit]>; def BCLRI : RVBShift_ri<0b01001, 0b001, OPC_OP_IMM, "bclri">, Sched<[WriteSingleBitImm, ReadSingleBitImm]>; @@ -361,7 +361,7 @@ Sched<[WriteSingleBitImm, ReadSingleBitImm]>; let IsSignExtendingOpW = 1 in def BEXTI : RVBShift_ri<0b01001, 0b101, OPC_OP_IMM, "bexti">, - Sched<[WriteSingleBitImm, ReadSingleBitImm]>; + Sched<[WriteBEXTI, ReadSingleBitImm]>; } // Predicates = [HasStdExtZbs] // These instructions were named xperm.n and xperm.b in the last version of diff --git a/llvm/lib/Target/RISCV/RISCVScheduleZb.td b/llvm/lib/Target/RISCV/RISCVScheduleZb.td --- a/llvm/lib/Target/RISCV/RISCVScheduleZb.td +++ b/llvm/lib/Target/RISCV/RISCVScheduleZb.td @@ -30,8 +30,10 @@ def WriteCLMUL : SchedWrite; // CLMUL/CLMULR/CLMULH // Zbs extension -def WriteSingleBit : SchedWrite; // BCLR/BSET/BINV/BEXT -def WriteSingleBitImm: SchedWrite; // BCLRI/BSETI/BINVI/BEXTI +def WriteSingleBit : SchedWrite; // BCLR/BSET/BINV +def WriteSingleBitImm: SchedWrite; // BCLRI/BSETI/BINVI +def WriteBEXT : SchedWrite; // BEXT +def WriteBEXTI : SchedWrite; // BEXTI // Zbkb extension def WriteBREV8 : SchedWrite; // brev8 @@ -132,6 +134,8 @@ let Unsupported = true in { def : WriteRes; def : WriteRes; +def : WriteRes; +def : WriteRes; def : ReadAdvance; def : ReadAdvance;