diff --git a/llvm/lib/Target/CSKY/CSKYInstrInfoF1.td b/llvm/lib/Target/CSKY/CSKYInstrInfoF1.td
--- a/llvm/lib/Target/CSKY/CSKYInstrInfoF1.td
+++ b/llvm/lib/Target/CSKY/CSKYInstrInfoF1.td
@@ -298,13 +298,19 @@
 def : Pat<(f64(CSKY_BITCAST_FROM_LOHI GPR:$rs1, GPR:$rs2)), (FMTVRH_D(FMTVRL_D GPR:$rs1), GPR:$rs2)>,
         Requires<[HasFPUv2_DF]>;
 
-multiclass BRCond_Bin<CondCode CC, string Instr, Instruction Br, Instruction MV> {
+multiclass BRCond_Bin<CondCode CC, string Instr, Instruction Br0, Instruction Br1, Instruction MV> {
   let Predicates = [HasFPUv2_SF] in
   def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, sFPR32Op:$rs2, CC)), bb:$imm16),
-            (Br (!cast<Instruction>(Instr#_S) sFPR32Op:$rs1, sFPR32Op:$rs2), bb:$imm16)>;
+            (Br0 (!cast<Instruction>(Instr#_S) sFPR32Op:$rs1, sFPR32Op:$rs2), bb:$imm16)>;
+  let Predicates = [HasFPUv2_SF] in
+  def : Pat<(brcond (xor (i32 (setcc sFPR32Op:$rs1, sFPR32Op:$rs2, CC)), 1), bb:$imm16),
+            (Br1 (!cast<Instruction>(Instr#_S) sFPR32Op:$rs1, sFPR32Op:$rs2), bb:$imm16)>;
   let Predicates = [HasFPUv2_DF] in
   def : Pat<(brcond (i32 (setcc sFPR64Op:$rs1, sFPR64Op:$rs2, CC)), bb:$imm16),
-            (Br (!cast<Instruction>(Instr#_D) sFPR64Op:$rs1, sFPR64Op:$rs2), bb:$imm16)>;
+            (Br0 (!cast<Instruction>(Instr#_D) sFPR64Op:$rs1, sFPR64Op:$rs2), bb:$imm16)>;
+  let Predicates = [HasFPUv2_DF] in
+  def : Pat<(brcond (xor (i32 (setcc sFPR64Op:$rs1, sFPR64Op:$rs2, CC)), 1), bb:$imm16),
+            (Br1 (!cast<Instruction>(Instr#_D) sFPR64Op:$rs1, sFPR64Op:$rs2), bb:$imm16)>;
 
   let Predicates = [HasFPUv2_SF] in
   def : Pat<(i32 (setcc sFPR32Op:$rs1, sFPR32Op:$rs2, CC)),
@@ -314,13 +320,19 @@
             (MV (!cast<Instruction>(Instr#_D) sFPR64Op:$rs1, sFPR64Op:$rs2))>;
 }
 
-multiclass BRCond_Bin_SWAP<CondCode CC, string Instr, Instruction Br, Instruction MV> {
+multiclass BRCond_Bin_SWAP<CondCode CC, string Instr, Instruction Br0, Instruction Br1, Instruction MV> {
   let Predicates = [HasFPUv2_SF] in
   def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, sFPR32Op:$rs2, CC)), bb:$imm16),
-            (Br (!cast<Instruction>(Instr#_S) sFPR32Op:$rs2, sFPR32Op:$rs1), bb:$imm16)>;
+            (Br0 (!cast<Instruction>(Instr#_S) sFPR32Op:$rs2, sFPR32Op:$rs1), bb:$imm16)>;
+  let Predicates = [HasFPUv2_SF] in
+  def : Pat<(brcond (xor (i32 (setcc sFPR32Op:$rs1, sFPR32Op:$rs2, CC)), 1), bb:$imm16),
+            (Br1 (!cast<Instruction>(Instr#_S) sFPR32Op:$rs2, sFPR32Op:$rs1), bb:$imm16)>;
   let Predicates = [HasFPUv2_DF] in
   def : Pat<(brcond (i32 (setcc sFPR64Op:$rs1, sFPR64Op:$rs2, CC)), bb:$imm16),
-            (Br (!cast<Instruction>(Instr#_D) sFPR64Op:$rs2, sFPR64Op:$rs1), bb:$imm16)>;
+            (Br0 (!cast<Instruction>(Instr#_D) sFPR64Op:$rs2, sFPR64Op:$rs1), bb:$imm16)>;
+  let Predicates = [HasFPUv2_DF] in
+  def : Pat<(brcond (xor (i32 (setcc sFPR64Op:$rs1, sFPR64Op:$rs2, CC)), 1), bb:$imm16),
+            (Br1 (!cast<Instruction>(Instr#_D) sFPR64Op:$rs2, sFPR64Op:$rs1), bb:$imm16)>;
 
   let Predicates = [HasFPUv2_SF] in
   def : Pat<(i32 (setcc sFPR32Op:$rs1, sFPR32Op:$rs2, CC)),
@@ -332,21 +344,21 @@
 
 // inverse (order && compare) to (unorder || inverse(compare))
 
-defm : BRCond_Bin<SETUNE, "FCMPNE", BT32, MVC32>;
-defm : BRCond_Bin<SETOEQ, "FCMPNE", BF32, MVCV32>;
-defm : BRCond_Bin<SETOGE, "FCMPHS", BT32, MVC32>;
-defm : BRCond_Bin<SETOLT, "FCMPLT", BT32, MVC32>;
-defm : BRCond_Bin<SETUO, "FCMPUO", BT32, MVC32>;
-defm : BRCond_Bin<SETO, "FCMPUO", BF32, MVCV32>;
-defm : BRCond_Bin_SWAP<SETOGT, "FCMPLT", BT32, MVC32>;
-defm : BRCond_Bin_SWAP<SETOLE, "FCMPHS", BT32, MVC32>;
-
-defm : BRCond_Bin<SETNE, "FCMPNE", BT32, MVC32>;
-defm : BRCond_Bin<SETEQ, "FCMPNE", BF32, MVCV32>;
-defm : BRCond_Bin<SETGE, "FCMPHS", BT32, MVC32>;
-defm : BRCond_Bin<SETLT, "FCMPLT", BT32, MVC32>;
-defm : BRCond_Bin_SWAP<SETGT, "FCMPLT", BT32, MVC32>;
-defm : BRCond_Bin_SWAP<SETLE, "FCMPHS", BT32, MVC32>;
+defm : BRCond_Bin<SETUNE, "FCMPNE", BT32, BF32, MVC32>;
+defm : BRCond_Bin<SETOEQ, "FCMPNE", BF32, BT32, MVCV32>;
+defm : BRCond_Bin<SETOGE, "FCMPHS", BT32, BF32, MVC32>;
+defm : BRCond_Bin<SETOLT, "FCMPLT", BT32, BF32, MVC32>;
+defm : BRCond_Bin<SETUO, "FCMPUO", BT32, BF32, MVC32>;
+defm : BRCond_Bin<SETO, "FCMPUO", BF32, BT32, MVCV32>;
+defm : BRCond_Bin_SWAP<SETOGT, "FCMPLT", BT32, BF32, MVC32>;
+defm : BRCond_Bin_SWAP<SETOLE, "FCMPHS", BT32, BF32, MVC32>;
+
+defm : BRCond_Bin<SETNE, "FCMPNE", BT32, BF32, MVC32>;
+defm : BRCond_Bin<SETEQ, "FCMPNE", BF32, BT32, MVCV32>;
+defm : BRCond_Bin<SETGE, "FCMPHS", BT32, BF32, MVC32>;
+defm : BRCond_Bin<SETLT, "FCMPLT", BT32, BF32, MVC32>;
+defm : BRCond_Bin_SWAP<SETGT, "FCMPLT", BT32, BF32, MVC32>;
+defm : BRCond_Bin_SWAP<SETLE, "FCMPHS", BT32, BF32, MVC32>;
 
 // -----------
 
@@ -417,4 +429,4 @@
   let Predicates = [HasFPUv2_DF] in
   def FSELD : CSKYPseudo<(outs sFPR64Op:$dst), (ins CARRY:$cond, sFPR64Op:$src1, sFPR64Op:$src2),
     "!fseld\t$dst, $src1, src2", [(set sFPR64Op:$dst, (select CARRY:$cond, sFPR64Op:$src1, sFPR64Op:$src2))]>;
-}
\ No newline at end of file
+}
diff --git a/llvm/lib/Target/CSKY/CSKYInstrInfoF2.td b/llvm/lib/Target/CSKY/CSKYInstrInfoF2.td
--- a/llvm/lib/Target/CSKY/CSKYInstrInfoF2.td
+++ b/llvm/lib/Target/CSKY/CSKYInstrInfoF2.td
@@ -284,13 +284,19 @@
         Requires<[HasFPUv3_SF]>;
 
 
-multiclass BRCond_Bin_F2<CondCode CC, string Instr, Instruction Br, Instruction MV, bit IsSelectSwap = 0> {
+multiclass BRCond_Bin_F2<CondCode CC, string Instr, Instruction Br0, Instruction Br1, Instruction MV, bit IsSelectSwap = 0> {
   let Predicates = [HasFPUv3_SF] in
   def : Pat<(brcond (i32 (setcc FPR32Op:$rs1, FPR32Op:$rs2, CC)), bb:$imm16),
-            (Br (!cast<Instruction>(Instr#_S) FPR32Op:$rs1, FPR32Op:$rs2), bb:$imm16)>;
+            (Br0 (!cast<Instruction>(Instr#_S) FPR32Op:$rs1, FPR32Op:$rs2), bb:$imm16)>;
+  let Predicates = [HasFPUv3_SF] in
+  def : Pat<(brcond (xor (i32 (setcc FPR32Op:$rs1, FPR32Op:$rs2, CC)), 1), bb:$imm16),
+            (Br1 (!cast<Instruction>(Instr#_S) FPR32Op:$rs1, FPR32Op:$rs2), bb:$imm16)>;
   let Predicates = [HasFPUv3_DF] in
   def : Pat<(brcond (i32 (setcc FPR64Op:$rs1, FPR64Op:$rs2, CC)), bb:$imm16),
-            (Br (!cast<Instruction>(Instr#_D) FPR64Op:$rs1, FPR64Op:$rs2), bb:$imm16)>;
+            (Br0 (!cast<Instruction>(Instr#_D) FPR64Op:$rs1, FPR64Op:$rs2), bb:$imm16)>;
+  let Predicates = [HasFPUv3_DF] in
+  def : Pat<(brcond (xor (i32 (setcc FPR64Op:$rs1, FPR64Op:$rs2, CC)), 1), bb:$imm16),
+            (Br1 (!cast<Instruction>(Instr#_D) FPR64Op:$rs1, FPR64Op:$rs2), bb:$imm16)>;
 
   let Predicates = [HasFPUv3_SF] in
   def : Pat<(i32 (setcc FPR32Op:$rs1, FPR32Op:$rs2, CC)),
@@ -317,13 +323,19 @@
   }
 }
 
-multiclass BRCond_Bin_SWAP_F2<CondCode CC, string Instr, Instruction Br, Instruction MV, bit IsSelectSwap = 0> {
+multiclass BRCond_Bin_SWAP_F2<CondCode CC, string Instr, Instruction Br0, Instruction Br1, Instruction MV, bit IsSelectSwap = 0> {
   let Predicates = [HasFPUv3_SF] in
   def : Pat<(brcond (i32 (setcc FPR32Op:$rs1, FPR32Op:$rs2, CC)), bb:$imm16),
-            (Br (!cast<Instruction>(Instr#_S) FPR32Op:$rs2, FPR32Op:$rs1), bb:$imm16)>;
+            (Br0 (!cast<Instruction>(Instr#_S) FPR32Op:$rs2, FPR32Op:$rs1), bb:$imm16)>;
+  let Predicates = [HasFPUv3_SF] in
+  def : Pat<(brcond (xor (i32 (setcc FPR32Op:$rs1, FPR32Op:$rs2, CC)), 1), bb:$imm16),
+            (Br1 (!cast<Instruction>(Instr#_S) FPR32Op:$rs2, FPR32Op:$rs1), bb:$imm16)>;
   let Predicates = [HasFPUv3_DF] in
   def : Pat<(brcond (i32 (setcc FPR64Op:$rs1, FPR64Op:$rs2, CC)), bb:$imm16),
-            (Br (!cast<Instruction>(Instr#_D) FPR64Op:$rs2, FPR64Op:$rs1), bb:$imm16)>;
+            (Br0 (!cast<Instruction>(Instr#_D) FPR64Op:$rs2, FPR64Op:$rs1), bb:$imm16)>;
+  let Predicates = [HasFPUv3_DF] in
+  def : Pat<(brcond (xor (i32 (setcc FPR64Op:$rs1, FPR64Op:$rs2, CC)), 1), bb:$imm16),
+            (Br1 (!cast<Instruction>(Instr#_D) FPR64Op:$rs2, FPR64Op:$rs1), bb:$imm16)>;
 
   let Predicates = [HasFPUv3_SF] in
   def : Pat<(i32 (setcc FPR32Op:$rs1, FPR32Op:$rs2, CC)),
@@ -352,21 +364,21 @@
 
 // inverse (order && compare) to (unorder || inverse(compare))
 
-defm : BRCond_Bin_F2<SETUNE, "f2FCMPNE", BT32, MVC32>;
-defm : BRCond_Bin_F2<SETOEQ, "f2FCMPNE", BF32, MVCV32, 1>;
-defm : BRCond_Bin_F2<SETOGE, "f2FCMPHS", BT32, MVC32>;
-defm : BRCond_Bin_F2<SETOLT, "f2FCMPLT", BT32, MVC32>;
-defm : BRCond_Bin_F2<SETUO, "f2FCMPUO", BT32, MVC32>;
-defm : BRCond_Bin_F2<SETO, "f2FCMPUO", BF32, MVCV32, 1>;
-defm : BRCond_Bin_SWAP_F2<SETOGT, "f2FCMPLT", BT32, MVC32>;
-defm : BRCond_Bin_SWAP_F2<SETOLE, "f2FCMPHS", BT32, MVC32>;
-
-defm : BRCond_Bin_F2<SETNE, "f2FCMPNE", BT32, MVC32>;
-defm : BRCond_Bin_F2<SETEQ, "f2FCMPNE", BF32, MVCV32, 1>;
-defm : BRCond_Bin_F2<SETGE, "f2FCMPHS", BT32, MVC32>;
-defm : BRCond_Bin_F2<SETLT, "f2FCMPLT", BT32, MVC32>;
-defm : BRCond_Bin_SWAP_F2<SETGT, "f2FCMPLT", BT32, MVC32>;
-defm : BRCond_Bin_SWAP_F2<SETLE, "f2FCMPHS", BT32, MVC32>;
+defm : BRCond_Bin_F2<SETUNE, "f2FCMPNE", BT32, BF32, MVC32>;
+defm : BRCond_Bin_F2<SETOEQ, "f2FCMPNE", BF32, BT32, MVCV32, 1>;
+defm : BRCond_Bin_F2<SETOGE, "f2FCMPHS", BT32, BF32, MVC32>;
+defm : BRCond_Bin_F2<SETOLT, "f2FCMPLT", BT32, BF32, MVC32>;
+defm : BRCond_Bin_F2<SETUO, "f2FCMPUO", BT32, BF32, MVC32>;
+defm : BRCond_Bin_F2<SETO, "f2FCMPUO", BF32, BT32, MVCV32, 1>;
+defm : BRCond_Bin_SWAP_F2<SETOGT, "f2FCMPLT", BT32, BF32, MVC32>;
+defm : BRCond_Bin_SWAP_F2<SETOLE, "f2FCMPHS", BT32, BF32, MVC32>;
+
+defm : BRCond_Bin_F2<SETNE, "f2FCMPNE", BT32, BF32, MVC32>;
+defm : BRCond_Bin_F2<SETEQ, "f2FCMPNE", BF32, BT32, MVCV32, 1>;
+defm : BRCond_Bin_F2<SETGE, "f2FCMPHS", BT32, BF32, MVC32>;
+defm : BRCond_Bin_F2<SETLT, "f2FCMPLT", BT32, BF32, MVC32>;
+defm : BRCond_Bin_SWAP_F2<SETGT, "f2FCMPLT", BT32, BF32, MVC32>;
+defm : BRCond_Bin_SWAP_F2<SETLE, "f2FCMPHS", BT32, BF32, MVC32>;
 
 // ------
 
@@ -459,4 +471,4 @@
           (f2FSEL_S CARRY:$ca, FPR32Op:$rx, FPR32Op:$false)>;
 let Predicates = [HasFPUv3_DF] in
 def : Pat<(select CARRY:$ca, FPR64Op:$rx, FPR64Op:$false),
-          (f2FSEL_D CARRY:$ca, FPR64Op:$rx, FPR64Op:$false)>;
\ No newline at end of file
+          (f2FSEL_D CARRY:$ca, FPR64Op:$rx, FPR64Op:$false)>;
diff --git a/llvm/test/CodeGen/CSKY/fpu/br-d.ll b/llvm/test/CodeGen/CSKY/fpu/br-d.ll
--- a/llvm/test/CodeGen/CSKY/fpu/br-d.ll
+++ b/llvm/test/CodeGen/CSKY/fpu/br-d.ll
@@ -795,10 +795,7 @@
 ; CHECK-DF-LABEL: brRR_ogt:
 ; CHECK-DF:       # %bb.0: # %entry
 ; CHECK-DF-NEXT:    fcmpltd vr0, vr1
-; CHECK-DF-NEXT:    mvc32 a0
-; CHECK-DF-NEXT:    xori32 a0, a0, 1
-; CHECK-DF-NEXT:    btsti16 a0, 0
-; CHECK-DF-NEXT:    bt32 .LBB18_2
+; CHECK-DF-NEXT:    bf32 .LBB18_2
 ; CHECK-DF-NEXT:  # %bb.1: # %label1
 ; CHECK-DF-NEXT:    movi16 a0, 1
 ; CHECK-DF-NEXT:    rts16
@@ -809,10 +806,7 @@
 ; CHECK-DF2-LABEL: brRR_ogt:
 ; CHECK-DF2:       # %bb.0: # %entry
 ; CHECK-DF2-NEXT:    fcmplt.64 vr0, vr1
-; CHECK-DF2-NEXT:    mvc32 a0
-; CHECK-DF2-NEXT:    xori32 a0, a0, 1
-; CHECK-DF2-NEXT:    btsti16 a0, 0
-; CHECK-DF2-NEXT:    bt32 .LBB18_2
+; CHECK-DF2-NEXT:    bf32 .LBB18_2
 ; CHECK-DF2-NEXT:  # %bb.1: # %label1
 ; CHECK-DF2-NEXT:    movi16 a0, 1
 ; CHECK-DF2-NEXT:    rts16
@@ -836,10 +830,7 @@
 ; CHECK-DF-NEXT:    grs32 a0, .LCPI19_0
 ; CHECK-DF-NEXT:    fldd vr1, (a0, 0)
 ; CHECK-DF-NEXT:    fcmpltd vr1, vr0
-; CHECK-DF-NEXT:    mvc32 a0
-; CHECK-DF-NEXT:    xori32 a0, a0, 1
-; CHECK-DF-NEXT:    btsti16 a0, 0
-; CHECK-DF-NEXT:    bt32 .LBB19_2
+; CHECK-DF-NEXT:    bf32 .LBB19_2
 ; CHECK-DF-NEXT:  # %bb.1: # %label1
 ; CHECK-DF-NEXT:    movi16 a0, 1
 ; CHECK-DF-NEXT:    rts16
@@ -856,10 +847,7 @@
 ; CHECK-DF2:       # %bb.0: # %entry
 ; CHECK-DF2-NEXT:    flrw.64 vr1, [.LCPI19_0]
 ; CHECK-DF2-NEXT:    fcmplt.64 vr1, vr0
-; CHECK-DF2-NEXT:    mvc32 a0
-; CHECK-DF2-NEXT:    xori32 a0, a0, 1
-; CHECK-DF2-NEXT:    btsti16 a0, 0
-; CHECK-DF2-NEXT:    bt32 .LBB19_2
+; CHECK-DF2-NEXT:    bf32 .LBB19_2
 ; CHECK-DF2-NEXT:  # %bb.1: # %label1
 ; CHECK-DF2-NEXT:    movi16 a0, 1
 ; CHECK-DF2-NEXT:    rts16
@@ -888,10 +876,7 @@
 ; CHECK-DF-NEXT:    grs32 a0, .LCPI20_0
 ; CHECK-DF-NEXT:    fldd vr1, (a0, 0)
 ; CHECK-DF-NEXT:    fcmpltd vr1, vr0
-; CHECK-DF-NEXT:    mvc32 a0
-; CHECK-DF-NEXT:    xori32 a0, a0, 1
-; CHECK-DF-NEXT:    btsti16 a0, 0
-; CHECK-DF-NEXT:    bt32 .LBB20_2
+; CHECK-DF-NEXT:    bf32 .LBB20_2
 ; CHECK-DF-NEXT:  # %bb.1: # %label1
 ; CHECK-DF-NEXT:    movi16 a0, 1
 ; CHECK-DF-NEXT:    rts16
@@ -908,10 +893,7 @@
 ; CHECK-DF2:       # %bb.0: # %entry
 ; CHECK-DF2-NEXT:    flrw.64 vr1, [.LCPI20_0]
 ; CHECK-DF2-NEXT:    fcmplt.64 vr1, vr0
-; CHECK-DF2-NEXT:    mvc32 a0
-; CHECK-DF2-NEXT:    xori32 a0, a0, 1
-; CHECK-DF2-NEXT:    btsti16 a0, 0
-; CHECK-DF2-NEXT:    bt32 .LBB20_2
+; CHECK-DF2-NEXT:    bf32 .LBB20_2
 ; CHECK-DF2-NEXT:  # %bb.1: # %label1
 ; CHECK-DF2-NEXT:    movi16 a0, 1
 ; CHECK-DF2-NEXT:    rts16
@@ -939,10 +921,7 @@
 ; CHECK-DF-LABEL: brRR_oge:
 ; CHECK-DF:       # %bb.0: # %entry
 ; CHECK-DF-NEXT:    fcmphsd vr1, vr0
-; CHECK-DF-NEXT:    mvc32 a0
-; CHECK-DF-NEXT:    xori32 a0, a0, 1
-; CHECK-DF-NEXT:    btsti16 a0, 0
-; CHECK-DF-NEXT:    bt32 .LBB21_2
+; CHECK-DF-NEXT:    bf32 .LBB21_2
 ; CHECK-DF-NEXT:  # %bb.1: # %label1
 ; CHECK-DF-NEXT:    movi16 a0, 1
 ; CHECK-DF-NEXT:    rts16
@@ -953,10 +932,7 @@
 ; CHECK-DF2-LABEL: brRR_oge:
 ; CHECK-DF2:       # %bb.0: # %entry
 ; CHECK-DF2-NEXT:    fcmphs.64 vr1, vr0
-; CHECK-DF2-NEXT:    mvc32 a0
-; CHECK-DF2-NEXT:    xori32 a0, a0, 1
-; CHECK-DF2-NEXT:    btsti16 a0, 0
-; CHECK-DF2-NEXT:    bt32 .LBB21_2
+; CHECK-DF2-NEXT:    bf32 .LBB21_2
 ; CHECK-DF2-NEXT:  # %bb.1: # %label1
 ; CHECK-DF2-NEXT:    movi16 a0, 1
 ; CHECK-DF2-NEXT:    rts16
@@ -980,10 +956,7 @@
 ; CHECK-DF-NEXT:    grs32 a0, .LCPI22_0
 ; CHECK-DF-NEXT:    fldd vr1, (a0, 0)
 ; CHECK-DF-NEXT:    fcmphsd vr0, vr1
-; CHECK-DF-NEXT:    mvc32 a0
-; CHECK-DF-NEXT:    xori32 a0, a0, 1
-; CHECK-DF-NEXT:    btsti16 a0, 0
-; CHECK-DF-NEXT:    bt32 .LBB22_2
+; CHECK-DF-NEXT:    bf32 .LBB22_2
 ; CHECK-DF-NEXT:  # %bb.1: # %label1
 ; CHECK-DF-NEXT:    movi16 a0, 1
 ; CHECK-DF-NEXT:    rts16
@@ -1000,10 +973,7 @@
 ; CHECK-DF2:       # %bb.0: # %entry
 ; CHECK-DF2-NEXT:    flrw.64 vr1, [.LCPI22_0]
 ; CHECK-DF2-NEXT:    fcmphs.64 vr0, vr1
-; CHECK-DF2-NEXT:    mvc32 a0
-; CHECK-DF2-NEXT:    xori32 a0, a0, 1
-; CHECK-DF2-NEXT:    btsti16 a0, 0
-; CHECK-DF2-NEXT:    bt32 .LBB22_2
+; CHECK-DF2-NEXT:    bf32 .LBB22_2
 ; CHECK-DF2-NEXT:  # %bb.1: # %label1
 ; CHECK-DF2-NEXT:    movi16 a0, 1
 ; CHECK-DF2-NEXT:    rts16
@@ -1032,10 +1002,7 @@
 ; CHECK-DF-NEXT:    grs32 a0, .LCPI23_0
 ; CHECK-DF-NEXT:    fldd vr1, (a0, 0)
 ; CHECK-DF-NEXT:    fcmphsd vr0, vr1
-; CHECK-DF-NEXT:    mvc32 a0
-; CHECK-DF-NEXT:    xori32 a0, a0, 1
-; CHECK-DF-NEXT:    btsti16 a0, 0
-; CHECK-DF-NEXT:    bt32 .LBB23_2
+; CHECK-DF-NEXT:    bf32 .LBB23_2
 ; CHECK-DF-NEXT:  # %bb.1: # %label1
 ; CHECK-DF-NEXT:    movi16 a0, 1
 ; CHECK-DF-NEXT:    rts16
@@ -1052,10 +1019,7 @@
 ; CHECK-DF2:       # %bb.0: # %entry
 ; CHECK-DF2-NEXT:    flrw.64 vr1, [.LCPI23_0]
 ; CHECK-DF2-NEXT:    fcmphs.64 vr0, vr1
-; CHECK-DF2-NEXT:    mvc32 a0
-; CHECK-DF2-NEXT:    xori32 a0, a0, 1
-; CHECK-DF2-NEXT:    btsti16 a0, 0
-; CHECK-DF2-NEXT:    bt32 .LBB23_2
+; CHECK-DF2-NEXT:    bf32 .LBB23_2
 ; CHECK-DF2-NEXT:  # %bb.1: # %label1
 ; CHECK-DF2-NEXT:    movi16 a0, 1
 ; CHECK-DF2-NEXT:    rts16
@@ -1083,10 +1047,7 @@
 ; CHECK-DF-LABEL: brRR_olt:
 ; CHECK-DF:       # %bb.0: # %entry
 ; CHECK-DF-NEXT:    fcmpltd vr1, vr0
-; CHECK-DF-NEXT:    mvc32 a0
-; CHECK-DF-NEXT:    xori32 a0, a0, 1
-; CHECK-DF-NEXT:    btsti16 a0, 0
-; CHECK-DF-NEXT:    bt32 .LBB24_2
+; CHECK-DF-NEXT:    bf32 .LBB24_2
 ; CHECK-DF-NEXT:  # %bb.1: # %label1
 ; CHECK-DF-NEXT:    movi16 a0, 1
 ; CHECK-DF-NEXT:    rts16
@@ -1097,10 +1058,7 @@
 ; CHECK-DF2-LABEL: brRR_olt:
 ; CHECK-DF2:       # %bb.0: # %entry
 ; CHECK-DF2-NEXT:    fcmplt.64 vr1, vr0
-; CHECK-DF2-NEXT:    mvc32 a0
-; CHECK-DF2-NEXT:    xori32 a0, a0, 1
-; CHECK-DF2-NEXT:    btsti16 a0, 0
-; CHECK-DF2-NEXT:    bt32 .LBB24_2
+; CHECK-DF2-NEXT:    bf32 .LBB24_2
 ; CHECK-DF2-NEXT:  # %bb.1: # %label1
 ; CHECK-DF2-NEXT:    movi16 a0, 1
 ; CHECK-DF2-NEXT:    rts16
@@ -1124,10 +1082,7 @@
 ; CHECK-DF-NEXT:    grs32 a0, .LCPI25_0
 ; CHECK-DF-NEXT:    fldd vr1, (a0, 0)
 ; CHECK-DF-NEXT:    fcmpltd vr0, vr1
-; CHECK-DF-NEXT:    mvc32 a0
-; CHECK-DF-NEXT:    xori32 a0, a0, 1
-; CHECK-DF-NEXT:    btsti16 a0, 0
-; CHECK-DF-NEXT:    bt32 .LBB25_2
+; CHECK-DF-NEXT:    bf32 .LBB25_2
 ; CHECK-DF-NEXT:  # %bb.1: # %label1
 ; CHECK-DF-NEXT:    movi16 a0, 1
 ; CHECK-DF-NEXT:    rts16
@@ -1144,10 +1099,7 @@
 ; CHECK-DF2:       # %bb.0: # %entry
 ; CHECK-DF2-NEXT:    flrw.64 vr1, [.LCPI25_0]
 ; CHECK-DF2-NEXT:    fcmplt.64 vr0, vr1
-; CHECK-DF2-NEXT:    mvc32 a0
-; CHECK-DF2-NEXT:    xori32 a0, a0, 1
-; CHECK-DF2-NEXT:    btsti16 a0, 0
-; CHECK-DF2-NEXT:    bt32 .LBB25_2
+; CHECK-DF2-NEXT:    bf32 .LBB25_2
 ; CHECK-DF2-NEXT:  # %bb.1: # %label1
 ; CHECK-DF2-NEXT:    movi16 a0, 1
 ; CHECK-DF2-NEXT:    rts16
@@ -1176,10 +1128,7 @@
 ; CHECK-DF-NEXT:    grs32 a0, .LCPI26_0
 ; CHECK-DF-NEXT:    fldd vr1, (a0, 0)
 ; CHECK-DF-NEXT:    fcmpltd vr0, vr1
-; CHECK-DF-NEXT:    mvc32 a0
-; CHECK-DF-NEXT:    xori32 a0, a0, 1
-; CHECK-DF-NEXT:    btsti16 a0, 0
-; CHECK-DF-NEXT:    bt32 .LBB26_2
+; CHECK-DF-NEXT:    bf32 .LBB26_2
 ; CHECK-DF-NEXT:  # %bb.1: # %label1
 ; CHECK-DF-NEXT:    movi16 a0, 1
 ; CHECK-DF-NEXT:    rts16
@@ -1196,10 +1145,7 @@
 ; CHECK-DF2:       # %bb.0: # %entry
 ; CHECK-DF2-NEXT:    flrw.64 vr1, [.LCPI26_0]
 ; CHECK-DF2-NEXT:    fcmplt.64 vr0, vr1
-; CHECK-DF2-NEXT:    mvc32 a0
-; CHECK-DF2-NEXT:    xori32 a0, a0, 1
-; CHECK-DF2-NEXT:    btsti16 a0, 0
-; CHECK-DF2-NEXT:    bt32 .LBB26_2
+; CHECK-DF2-NEXT:    bf32 .LBB26_2
 ; CHECK-DF2-NEXT:  # %bb.1: # %label1
 ; CHECK-DF2-NEXT:    movi16 a0, 1
 ; CHECK-DF2-NEXT:    rts16
@@ -1227,10 +1173,7 @@
 ; CHECK-DF-LABEL: brRR_ole:
 ; CHECK-DF:       # %bb.0: # %entry
 ; CHECK-DF-NEXT:    fcmphsd vr0, vr1
-; CHECK-DF-NEXT:    mvc32 a0
-; CHECK-DF-NEXT:    xori32 a0, a0, 1
-; CHECK-DF-NEXT:    btsti16 a0, 0
-; CHECK-DF-NEXT:    bt32 .LBB27_2
+; CHECK-DF-NEXT:    bf32 .LBB27_2
 ; CHECK-DF-NEXT:  # %bb.1: # %label1
 ; CHECK-DF-NEXT:    movi16 a0, 1
 ; CHECK-DF-NEXT:    rts16
@@ -1241,10 +1184,7 @@
 ; CHECK-DF2-LABEL: brRR_ole:
 ; CHECK-DF2:       # %bb.0: # %entry
 ; CHECK-DF2-NEXT:    fcmphs.64 vr0, vr1
-; CHECK-DF2-NEXT:    mvc32 a0
-; CHECK-DF2-NEXT:    xori32 a0, a0, 1
-; CHECK-DF2-NEXT:    btsti16 a0, 0
-; CHECK-DF2-NEXT:    bt32 .LBB27_2
+; CHECK-DF2-NEXT:    bf32 .LBB27_2
 ; CHECK-DF2-NEXT:  # %bb.1: # %label1
 ; CHECK-DF2-NEXT:    movi16 a0, 1
 ; CHECK-DF2-NEXT:    rts16
@@ -1268,10 +1208,7 @@
 ; CHECK-DF-NEXT:    grs32 a0, .LCPI28_0
 ; CHECK-DF-NEXT:    fldd vr1, (a0, 0)
 ; CHECK-DF-NEXT:    fcmphsd vr1, vr0
-; CHECK-DF-NEXT:    mvc32 a0
-; CHECK-DF-NEXT:    xori32 a0, a0, 1
-; CHECK-DF-NEXT:    btsti16 a0, 0
-; CHECK-DF-NEXT:    bt32 .LBB28_2
+; CHECK-DF-NEXT:    bf32 .LBB28_2
 ; CHECK-DF-NEXT:  # %bb.1: # %label1
 ; CHECK-DF-NEXT:    movi16 a0, 1
 ; CHECK-DF-NEXT:    rts16
@@ -1288,10 +1225,7 @@
 ; CHECK-DF2:       # %bb.0: # %entry
 ; CHECK-DF2-NEXT:    flrw.64 vr1, [.LCPI28_0]
 ; CHECK-DF2-NEXT:    fcmphs.64 vr1, vr0
-; CHECK-DF2-NEXT:    mvc32 a0
-; CHECK-DF2-NEXT:    xori32 a0, a0, 1
-; CHECK-DF2-NEXT:    btsti16 a0, 0
-; CHECK-DF2-NEXT:    bt32 .LBB28_2
+; CHECK-DF2-NEXT:    bf32 .LBB28_2
 ; CHECK-DF2-NEXT:  # %bb.1: # %label1
 ; CHECK-DF2-NEXT:    movi16 a0, 1
 ; CHECK-DF2-NEXT:    rts16
@@ -1320,10 +1254,7 @@
 ; CHECK-DF-NEXT:    grs32 a0, .LCPI29_0
 ; CHECK-DF-NEXT:    fldd vr1, (a0, 0)
 ; CHECK-DF-NEXT:    fcmphsd vr1, vr0
-; CHECK-DF-NEXT:    mvc32 a0
-; CHECK-DF-NEXT:    xori32 a0, a0, 1
-; CHECK-DF-NEXT:    btsti16 a0, 0
-; CHECK-DF-NEXT:    bt32 .LBB29_2
+; CHECK-DF-NEXT:    bf32 .LBB29_2
 ; CHECK-DF-NEXT:  # %bb.1: # %label1
 ; CHECK-DF-NEXT:    movi16 a0, 1
 ; CHECK-DF-NEXT:    rts16
@@ -1340,10 +1271,7 @@
 ; CHECK-DF2:       # %bb.0: # %entry
 ; CHECK-DF2-NEXT:    flrw.64 vr1, [.LCPI29_0]
 ; CHECK-DF2-NEXT:    fcmphs.64 vr1, vr0
-; CHECK-DF2-NEXT:    mvc32 a0
-; CHECK-DF2-NEXT:    xori32 a0, a0, 1
-; CHECK-DF2-NEXT:    btsti16 a0, 0
-; CHECK-DF2-NEXT:    bt32 .LBB29_2
+; CHECK-DF2-NEXT:    bf32 .LBB29_2
 ; CHECK-DF2-NEXT:  # %bb.1: # %label1
 ; CHECK-DF2-NEXT:    movi16 a0, 1
 ; CHECK-DF2-NEXT:    rts16
diff --git a/llvm/test/CodeGen/CSKY/fpu/br-f.ll b/llvm/test/CodeGen/CSKY/fpu/br-f.ll
--- a/llvm/test/CodeGen/CSKY/fpu/br-f.ll
+++ b/llvm/test/CodeGen/CSKY/fpu/br-f.ll
@@ -644,10 +644,7 @@
 ; CHECK-SF-LABEL: brRR_ogt:
 ; CHECK-SF:       # %bb.0: # %entry
 ; CHECK-SF-NEXT:    fcmplts vr0, vr1
-; CHECK-SF-NEXT:    mvc32 a0
-; CHECK-SF-NEXT:    xori32 a0, a0, 1
-; CHECK-SF-NEXT:    btsti16 a0, 0
-; CHECK-SF-NEXT:    bt32 .LBB18_2
+; CHECK-SF-NEXT:    bf32 .LBB18_2
 ; CHECK-SF-NEXT:  # %bb.1: # %label1
 ; CHECK-SF-NEXT:    movi16 a0, 1
 ; CHECK-SF-NEXT:    rts16
@@ -658,10 +655,7 @@
 ; CHECK-SF2-LABEL: brRR_ogt:
 ; CHECK-SF2:       # %bb.0: # %entry
 ; CHECK-SF2-NEXT:    fcmplt.32 vr0, vr1
-; CHECK-SF2-NEXT:    mvc32 a0
-; CHECK-SF2-NEXT:    xori32 a0, a0, 1
-; CHECK-SF2-NEXT:    btsti16 a0, 0
-; CHECK-SF2-NEXT:    bt32 .LBB18_2
+; CHECK-SF2-NEXT:    bf32 .LBB18_2
 ; CHECK-SF2-NEXT:  # %bb.1: # %label1
 ; CHECK-SF2-NEXT:    movi16 a0, 1
 ; CHECK-SF2-NEXT:    rts16
@@ -684,10 +678,7 @@
 ; CHECK-SF-NEXT:    movih32 a0, 16672
 ; CHECK-SF-NEXT:    fmtvrl vr1, a0
 ; CHECK-SF-NEXT:    fcmplts vr1, vr0
-; CHECK-SF-NEXT:    mvc32 a0
-; CHECK-SF-NEXT:    xori32 a0, a0, 1
-; CHECK-SF-NEXT:    btsti16 a0, 0
-; CHECK-SF-NEXT:    bt32 .LBB19_2
+; CHECK-SF-NEXT:    bf32 .LBB19_2
 ; CHECK-SF-NEXT:  # %bb.1: # %label1
 ; CHECK-SF-NEXT:    movi16 a0, 1
 ; CHECK-SF-NEXT:    rts16
@@ -700,10 +691,7 @@
 ; CHECK-SF2-NEXT:    movih32 a0, 16672
 ; CHECK-SF2-NEXT:    fmtvr.32.1 vr1, a0
 ; CHECK-SF2-NEXT:    fcmplt.32 vr1, vr0
-; CHECK-SF2-NEXT:    mvc32 a0
-; CHECK-SF2-NEXT:    xori32 a0, a0, 1
-; CHECK-SF2-NEXT:    btsti16 a0, 0
-; CHECK-SF2-NEXT:    bt32 .LBB19_2
+; CHECK-SF2-NEXT:    bf32 .LBB19_2
 ; CHECK-SF2-NEXT:  # %bb.1: # %label1
 ; CHECK-SF2-NEXT:    movi16 a0, 1
 ; CHECK-SF2-NEXT:    rts16
@@ -723,30 +711,24 @@
 ;
 ; CHECK-SF-LABEL: brR0_ogt:
 ; CHECK-SF:       # %bb.0: # %entry
-; CHECK-SF-NEXT:    fcmpzlss vr0
-; CHECK-SF-NEXT:    mvcv16 a0
-; CHECK-SF-NEXT:    xori32 a0, a0, 1
-; CHECK-SF-NEXT:    btsti16 a0, 0
-; CHECK-SF-NEXT:    bt32 .LBB20_2
+; CHECK-SF-NEXT:    movi16 a0, 0
+; CHECK-SF-NEXT:    fmtvrl vr1, a0
+; CHECK-SF-NEXT:    fcmplts vr1, vr0
+; CHECK-SF-NEXT:    bf32 .LBB20_2
 ; CHECK-SF-NEXT:  # %bb.1: # %label1
 ; CHECK-SF-NEXT:    movi16 a0, 1
-; CHECK-SF-NEXT:    rts16
 ; CHECK-SF-NEXT:  .LBB20_2: # %label2
-; CHECK-SF-NEXT:    movi16 a0, 0
 ; CHECK-SF-NEXT:    rts16
 ;
 ; CHECK-SF2-LABEL: brR0_ogt:
 ; CHECK-SF2:       # %bb.0: # %entry
-; CHECK-SF2-NEXT:    fcmphz.32 vr0
-; CHECK-SF2-NEXT:    mvc32 a0
-; CHECK-SF2-NEXT:    xori32 a0, a0, 1
-; CHECK-SF2-NEXT:    btsti16 a0, 0
-; CHECK-SF2-NEXT:    bt32 .LBB20_2
+; CHECK-SF2-NEXT:    movi16 a0, 0
+; CHECK-SF2-NEXT:    fmtvr.32.1 vr1, a0
+; CHECK-SF2-NEXT:    fcmplt.32 vr1, vr0
+; CHECK-SF2-NEXT:    bf32 .LBB20_2
 ; CHECK-SF2-NEXT:  # %bb.1: # %label1
 ; CHECK-SF2-NEXT:    movi16 a0, 1
-; CHECK-SF2-NEXT:    rts16
 ; CHECK-SF2-NEXT:  .LBB20_2: # %label2
-; CHECK-SF2-NEXT:    movi16 a0, 0
 ; CHECK-SF2-NEXT:    rts16
 entry:
   %fcmp = fcmp ogt float %x, 0.0
@@ -763,10 +745,7 @@
 ; CHECK-SF-LABEL: brRR_oge:
 ; CHECK-SF:       # %bb.0: # %entry
 ; CHECK-SF-NEXT:    fcmphss vr1, vr0
-; CHECK-SF-NEXT:    mvc32 a0
-; CHECK-SF-NEXT:    xori32 a0, a0, 1
-; CHECK-SF-NEXT:    btsti16 a0, 0
-; CHECK-SF-NEXT:    bt32 .LBB21_2
+; CHECK-SF-NEXT:    bf32 .LBB21_2
 ; CHECK-SF-NEXT:  # %bb.1: # %label1
 ; CHECK-SF-NEXT:    movi16 a0, 1
 ; CHECK-SF-NEXT:    rts16
@@ -777,10 +756,7 @@
 ; CHECK-SF2-LABEL: brRR_oge:
 ; CHECK-SF2:       # %bb.0: # %entry
 ; CHECK-SF2-NEXT:    fcmphs.32 vr1, vr0
-; CHECK-SF2-NEXT:    mvc32 a0
-; CHECK-SF2-NEXT:    xori32 a0, a0, 1
-; CHECK-SF2-NEXT:    btsti16 a0, 0
-; CHECK-SF2-NEXT:    bt32 .LBB21_2
+; CHECK-SF2-NEXT:    bf32 .LBB21_2
 ; CHECK-SF2-NEXT:  # %bb.1: # %label1
 ; CHECK-SF2-NEXT:    movi16 a0, 1
 ; CHECK-SF2-NEXT:    rts16
@@ -803,10 +779,7 @@
 ; CHECK-SF-NEXT:    movih32 a0, 16672
 ; CHECK-SF-NEXT:    fmtvrl vr1, a0
 ; CHECK-SF-NEXT:    fcmphss vr0, vr1
-; CHECK-SF-NEXT:    mvc32 a0
-; CHECK-SF-NEXT:    xori32 a0, a0, 1
-; CHECK-SF-NEXT:    btsti16 a0, 0
-; CHECK-SF-NEXT:    bt32 .LBB22_2
+; CHECK-SF-NEXT:    bf32 .LBB22_2
 ; CHECK-SF-NEXT:  # %bb.1: # %label1
 ; CHECK-SF-NEXT:    movi16 a0, 1
 ; CHECK-SF-NEXT:    rts16
@@ -819,10 +792,7 @@
 ; CHECK-SF2-NEXT:    movih32 a0, 16672
 ; CHECK-SF2-NEXT:    fmtvr.32.1 vr1, a0
 ; CHECK-SF2-NEXT:    fcmphs.32 vr0, vr1
-; CHECK-SF2-NEXT:    mvc32 a0
-; CHECK-SF2-NEXT:    xori32 a0, a0, 1
-; CHECK-SF2-NEXT:    btsti16 a0, 0
-; CHECK-SF2-NEXT:    bt32 .LBB22_2
+; CHECK-SF2-NEXT:    bf32 .LBB22_2
 ; CHECK-SF2-NEXT:  # %bb.1: # %label1
 ; CHECK-SF2-NEXT:    movi16 a0, 1
 ; CHECK-SF2-NEXT:    rts16
@@ -842,30 +812,24 @@
 ;
 ; CHECK-SF-LABEL: brR0_oge:
 ; CHECK-SF:       # %bb.0: # %entry
-; CHECK-SF-NEXT:    fcmpzhss vr0
-; CHECK-SF-NEXT:    mvc32 a0
-; CHECK-SF-NEXT:    xori32 a0, a0, 1
-; CHECK-SF-NEXT:    btsti16 a0, 0
-; CHECK-SF-NEXT:    bt32 .LBB23_2
+; CHECK-SF-NEXT:    movi16 a0, 0
+; CHECK-SF-NEXT:    fmtvrl vr1, a0
+; CHECK-SF-NEXT:    fcmphss vr0, vr1
+; CHECK-SF-NEXT:    bf32 .LBB23_2
 ; CHECK-SF-NEXT:  # %bb.1: # %label1
 ; CHECK-SF-NEXT:    movi16 a0, 1
-; CHECK-SF-NEXT:    rts16
 ; CHECK-SF-NEXT:  .LBB23_2: # %label2
-; CHECK-SF-NEXT:    movi16 a0, 0
 ; CHECK-SF-NEXT:    rts16
 ;
 ; CHECK-SF2-LABEL: brR0_oge:
 ; CHECK-SF2:       # %bb.0: # %entry
-; CHECK-SF2-NEXT:    fcmphsz.32 vr0
-; CHECK-SF2-NEXT:    mvc32 a0
-; CHECK-SF2-NEXT:    xori32 a0, a0, 1
-; CHECK-SF2-NEXT:    btsti16 a0, 0
-; CHECK-SF2-NEXT:    bt32 .LBB23_2
+; CHECK-SF2-NEXT:    movi16 a0, 0
+; CHECK-SF2-NEXT:    fmtvr.32.1 vr1, a0
+; CHECK-SF2-NEXT:    fcmphs.32 vr0, vr1
+; CHECK-SF2-NEXT:    bf32 .LBB23_2
 ; CHECK-SF2-NEXT:  # %bb.1: # %label1
 ; CHECK-SF2-NEXT:    movi16 a0, 1
-; CHECK-SF2-NEXT:    rts16
 ; CHECK-SF2-NEXT:  .LBB23_2: # %label2
-; CHECK-SF2-NEXT:    movi16 a0, 0
 ; CHECK-SF2-NEXT:    rts16
 entry:
   %fcmp = fcmp oge float %x, 0.0
@@ -882,10 +846,7 @@
 ; CHECK-SF-LABEL: brRR_olt:
 ; CHECK-SF:       # %bb.0: # %entry
 ; CHECK-SF-NEXT:    fcmplts vr1, vr0
-; CHECK-SF-NEXT:    mvc32 a0
-; CHECK-SF-NEXT:    xori32 a0, a0, 1
-; CHECK-SF-NEXT:    btsti16 a0, 0
-; CHECK-SF-NEXT:    bt32 .LBB24_2
+; CHECK-SF-NEXT:    bf32 .LBB24_2
 ; CHECK-SF-NEXT:  # %bb.1: # %label1
 ; CHECK-SF-NEXT:    movi16 a0, 1
 ; CHECK-SF-NEXT:    rts16
@@ -896,10 +857,7 @@
 ; CHECK-SF2-LABEL: brRR_olt:
 ; CHECK-SF2:       # %bb.0: # %entry
 ; CHECK-SF2-NEXT:    fcmplt.32 vr1, vr0
-; CHECK-SF2-NEXT:    mvc32 a0
-; CHECK-SF2-NEXT:    xori32 a0, a0, 1
-; CHECK-SF2-NEXT:    btsti16 a0, 0
-; CHECK-SF2-NEXT:    bt32 .LBB24_2
+; CHECK-SF2-NEXT:    bf32 .LBB24_2
 ; CHECK-SF2-NEXT:  # %bb.1: # %label1
 ; CHECK-SF2-NEXT:    movi16 a0, 1
 ; CHECK-SF2-NEXT:    rts16
@@ -922,10 +880,7 @@
 ; CHECK-SF-NEXT:    movih32 a0, 16672
 ; CHECK-SF-NEXT:    fmtvrl vr1, a0
 ; CHECK-SF-NEXT:    fcmplts vr0, vr1
-; CHECK-SF-NEXT:    mvc32 a0
-; CHECK-SF-NEXT:    xori32 a0, a0, 1
-; CHECK-SF-NEXT:    btsti16 a0, 0
-; CHECK-SF-NEXT:    bt32 .LBB25_2
+; CHECK-SF-NEXT:    bf32 .LBB25_2
 ; CHECK-SF-NEXT:  # %bb.1: # %label1
 ; CHECK-SF-NEXT:    movi16 a0, 1
 ; CHECK-SF-NEXT:    rts16
@@ -938,10 +893,7 @@
 ; CHECK-SF2-NEXT:    movih32 a0, 16672
 ; CHECK-SF2-NEXT:    fmtvr.32.1 vr1, a0
 ; CHECK-SF2-NEXT:    fcmplt.32 vr0, vr1
-; CHECK-SF2-NEXT:    mvc32 a0
-; CHECK-SF2-NEXT:    xori32 a0, a0, 1
-; CHECK-SF2-NEXT:    btsti16 a0, 0
-; CHECK-SF2-NEXT:    bt32 .LBB25_2
+; CHECK-SF2-NEXT:    bf32 .LBB25_2
 ; CHECK-SF2-NEXT:  # %bb.1: # %label1
 ; CHECK-SF2-NEXT:    movi16 a0, 1
 ; CHECK-SF2-NEXT:    rts16
@@ -961,30 +913,24 @@
 ;
 ; CHECK-SF-LABEL: brR0_olt:
 ; CHECK-SF:       # %bb.0: # %entry
-; CHECK-SF-NEXT:    fcmpzhss vr0
-; CHECK-SF-NEXT:    mvcv16 a0
-; CHECK-SF-NEXT:    xori32 a0, a0, 1
-; CHECK-SF-NEXT:    btsti16 a0, 0
-; CHECK-SF-NEXT:    bt32 .LBB26_2
+; CHECK-SF-NEXT:    movi16 a0, 0
+; CHECK-SF-NEXT:    fmtvrl vr1, a0
+; CHECK-SF-NEXT:    fcmplts vr0, vr1
+; CHECK-SF-NEXT:    bf32 .LBB26_2
 ; CHECK-SF-NEXT:  # %bb.1: # %label1
 ; CHECK-SF-NEXT:    movi16 a0, 1
-; CHECK-SF-NEXT:    rts16
 ; CHECK-SF-NEXT:  .LBB26_2: # %label2
-; CHECK-SF-NEXT:    movi16 a0, 0
 ; CHECK-SF-NEXT:    rts16
 ;
 ; CHECK-SF2-LABEL: brR0_olt:
 ; CHECK-SF2:       # %bb.0: # %entry
-; CHECK-SF2-NEXT:    fcmpltz.32 vr0
-; CHECK-SF2-NEXT:    mvc32 a0
-; CHECK-SF2-NEXT:    xori32 a0, a0, 1
-; CHECK-SF2-NEXT:    btsti16 a0, 0
-; CHECK-SF2-NEXT:    bt32 .LBB26_2
+; CHECK-SF2-NEXT:    movi16 a0, 0
+; CHECK-SF2-NEXT:    fmtvr.32.1 vr1, a0
+; CHECK-SF2-NEXT:    fcmplt.32 vr0, vr1
+; CHECK-SF2-NEXT:    bf32 .LBB26_2
 ; CHECK-SF2-NEXT:  # %bb.1: # %label1
 ; CHECK-SF2-NEXT:    movi16 a0, 1
-; CHECK-SF2-NEXT:    rts16
 ; CHECK-SF2-NEXT:  .LBB26_2: # %label2
-; CHECK-SF2-NEXT:    movi16 a0, 0
 ; CHECK-SF2-NEXT:    rts16
 entry:
   %fcmp = fcmp olt float %x, 0.0
@@ -1001,10 +947,7 @@
 ; CHECK-SF-LABEL: brRR_ole:
 ; CHECK-SF:       # %bb.0: # %entry
 ; CHECK-SF-NEXT:    fcmphss vr0, vr1
-; CHECK-SF-NEXT:    mvc32 a0
-; CHECK-SF-NEXT:    xori32 a0, a0, 1
-; CHECK-SF-NEXT:    btsti16 a0, 0
-; CHECK-SF-NEXT:    bt32 .LBB27_2
+; CHECK-SF-NEXT:    bf32 .LBB27_2
 ; CHECK-SF-NEXT:  # %bb.1: # %label1
 ; CHECK-SF-NEXT:    movi16 a0, 1
 ; CHECK-SF-NEXT:    rts16
@@ -1015,10 +958,7 @@
 ; CHECK-SF2-LABEL: brRR_ole:
 ; CHECK-SF2:       # %bb.0: # %entry
 ; CHECK-SF2-NEXT:    fcmphs.32 vr0, vr1
-; CHECK-SF2-NEXT:    mvc32 a0
-; CHECK-SF2-NEXT:    xori32 a0, a0, 1
-; CHECK-SF2-NEXT:    btsti16 a0, 0
-; CHECK-SF2-NEXT:    bt32 .LBB27_2
+; CHECK-SF2-NEXT:    bf32 .LBB27_2
 ; CHECK-SF2-NEXT:  # %bb.1: # %label1
 ; CHECK-SF2-NEXT:    movi16 a0, 1
 ; CHECK-SF2-NEXT:    rts16
@@ -1041,10 +981,7 @@
 ; CHECK-SF-NEXT:    movih32 a0, 16672
 ; CHECK-SF-NEXT:    fmtvrl vr1, a0
 ; CHECK-SF-NEXT:    fcmphss vr1, vr0
-; CHECK-SF-NEXT:    mvc32 a0
-; CHECK-SF-NEXT:    xori32 a0, a0, 1
-; CHECK-SF-NEXT:    btsti16 a0, 0
-; CHECK-SF-NEXT:    bt32 .LBB28_2
+; CHECK-SF-NEXT:    bf32 .LBB28_2
 ; CHECK-SF-NEXT:  # %bb.1: # %label1
 ; CHECK-SF-NEXT:    movi16 a0, 1
 ; CHECK-SF-NEXT:    rts16
@@ -1057,10 +994,7 @@
 ; CHECK-SF2-NEXT:    movih32 a0, 16672
 ; CHECK-SF2-NEXT:    fmtvr.32.1 vr1, a0
 ; CHECK-SF2-NEXT:    fcmphs.32 vr1, vr0
-; CHECK-SF2-NEXT:    mvc32 a0
-; CHECK-SF2-NEXT:    xori32 a0, a0, 1
-; CHECK-SF2-NEXT:    btsti16 a0, 0
-; CHECK-SF2-NEXT:    bt32 .LBB28_2
+; CHECK-SF2-NEXT:    bf32 .LBB28_2
 ; CHECK-SF2-NEXT:  # %bb.1: # %label1
 ; CHECK-SF2-NEXT:    movi16 a0, 1
 ; CHECK-SF2-NEXT:    rts16
@@ -1080,30 +1014,24 @@
 ;
 ; CHECK-SF-LABEL: brR0_ole:
 ; CHECK-SF:       # %bb.0: # %entry
-; CHECK-SF-NEXT:    fcmpzlss vr0
-; CHECK-SF-NEXT:    mvc32 a0
-; CHECK-SF-NEXT:    xori32 a0, a0, 1
-; CHECK-SF-NEXT:    btsti16 a0, 0
-; CHECK-SF-NEXT:    bt32 .LBB29_2
+; CHECK-SF-NEXT:    movi16 a0, 0
+; CHECK-SF-NEXT:    fmtvrl vr1, a0
+; CHECK-SF-NEXT:    fcmphss vr1, vr0
+; CHECK-SF-NEXT:    bf32 .LBB29_2
 ; CHECK-SF-NEXT:  # %bb.1: # %label1
 ; CHECK-SF-NEXT:    movi16 a0, 1
-; CHECK-SF-NEXT:    rts16
 ; CHECK-SF-NEXT:  .LBB29_2: # %label2
-; CHECK-SF-NEXT:    movi16 a0, 0
 ; CHECK-SF-NEXT:    rts16
 ;
 ; CHECK-SF2-LABEL: brR0_ole:
 ; CHECK-SF2:       # %bb.0: # %entry
-; CHECK-SF2-NEXT:    fcmplsz.32 vr0
-; CHECK-SF2-NEXT:    mvc32 a0
-; CHECK-SF2-NEXT:    xori32 a0, a0, 1
-; CHECK-SF2-NEXT:    btsti16 a0, 0
-; CHECK-SF2-NEXT:    bt32 .LBB29_2
+; CHECK-SF2-NEXT:    movi16 a0, 0
+; CHECK-SF2-NEXT:    fmtvr.32.1 vr1, a0
+; CHECK-SF2-NEXT:    fcmphs.32 vr1, vr0
+; CHECK-SF2-NEXT:    bf32 .LBB29_2
 ; CHECK-SF2-NEXT:  # %bb.1: # %label1
 ; CHECK-SF2-NEXT:    movi16 a0, 1
-; CHECK-SF2-NEXT:    rts16
 ; CHECK-SF2-NEXT:  .LBB29_2: # %label2
-; CHECK-SF2-NEXT:    movi16 a0, 0
 ; CHECK-SF2-NEXT:    rts16
 entry:
   %fcmp = fcmp ole float %x, 0.0