diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -12406,9 +12406,13 @@ SDValue TrueVal, SDValue FalseVal, bool Swapped) { bool Commutative = true; - switch (TrueVal.getOpcode()) { + unsigned Opc = TrueVal.getOpcode(); + switch (Opc) { default: return SDValue(); + case ISD::SHL: + case ISD::SRA: + case ISD::SRL: case ISD::SUB: Commutative = false; break; @@ -12431,12 +12435,18 @@ EVT VT = N->getValueType(0); SDLoc DL(N); - SDValue Zero = DAG.getConstant(0, DL, VT); SDValue OtherOp = TrueVal.getOperand(1 - OpToFold); + EVT OtherOpVT = OtherOp->getValueType(0); + SDValue IdentityOperand = + DAG.getNeutralElement(Opc, DL, OtherOpVT, N->getFlags()); + if (!Commutative) + IdentityOperand = DAG.getConstant(0, DL, OtherOpVT); + assert(IdentityOperand && "No identity operand!"); if (Swapped) - std::swap(OtherOp, Zero); - SDValue NewSel = DAG.getSelect(DL, VT, N->getOperand(0), OtherOp, Zero); + std::swap(OtherOp, IdentityOperand); + SDValue NewSel = + DAG.getSelect(DL, OtherOpVT, N->getOperand(0), OtherOp, IdentityOperand); return DAG.getNode(TrueVal.getOpcode(), DL, VT, FalseVal, NewSel); } diff --git a/llvm/test/CodeGen/RISCV/condbinops.ll b/llvm/test/CodeGen/RISCV/condbinops.ll --- a/llvm/test/CodeGen/RISCV/condbinops.ll +++ b/llvm/test/CodeGen/RISCV/condbinops.ll @@ -9,54 +9,46 @@ define i32 @shl32(i32 %x, i32 %y, i1 %c) { ; RV32I-LABEL: shl32: ; RV32I: # %bb.0: -; RV32I-NEXT: andi a2, a2, 1 -; RV32I-NEXT: beqz a2, .LBB0_2 -; RV32I-NEXT: # %bb.1: +; RV32I-NEXT: slli a2, a2, 31 +; RV32I-NEXT: srai a2, a2, 31 +; RV32I-NEXT: and a1, a2, a1 ; RV32I-NEXT: sll a0, a0, a1 -; RV32I-NEXT: .LBB0_2: ; RV32I-NEXT: ret ; ; RV64I-LABEL: shl32: ; RV64I: # %bb.0: -; RV64I-NEXT: andi a2, a2, 1 -; RV64I-NEXT: beqz a2, .LBB0_2 -; RV64I-NEXT: # %bb.1: +; RV64I-NEXT: slli a2, a2, 63 +; RV64I-NEXT: srai a2, a2, 63 +; RV64I-NEXT: and a1, a2, a1 ; RV64I-NEXT: sllw a0, a0, a1 -; RV64I-NEXT: .LBB0_2: ; RV64I-NEXT: ret ; ; RV64XVENTANACONDOPS-LABEL: shl32: ; RV64XVENTANACONDOPS: # %bb.0: ; RV64XVENTANACONDOPS-NEXT: andi a2, a2, 1 -; RV64XVENTANACONDOPS-NEXT: sllw a1, a0, a1 -; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, a2 ; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a2 -; RV64XVENTANACONDOPS-NEXT: or a0, a1, a0 +; RV64XVENTANACONDOPS-NEXT: sllw a0, a0, a1 ; RV64XVENTANACONDOPS-NEXT: ret ; ; RV64XTHEADCONDMOV-LABEL: shl32: ; RV64XTHEADCONDMOV: # %bb.0: ; RV64XTHEADCONDMOV-NEXT: andi a2, a2, 1 -; RV64XTHEADCONDMOV-NEXT: sllw a1, a0, a1 -; RV64XTHEADCONDMOV-NEXT: th.mvnez a0, a1, a2 +; RV64XTHEADCONDMOV-NEXT: th.mveqz a1, zero, a2 +; RV64XTHEADCONDMOV-NEXT: sllw a0, a0, a1 ; RV64XTHEADCONDMOV-NEXT: ret ; ; RV32ZICOND-LABEL: shl32: ; RV32ZICOND: # %bb.0: ; RV32ZICOND-NEXT: andi a2, a2, 1 -; RV32ZICOND-NEXT: sll a1, a0, a1 -; RV32ZICOND-NEXT: czero.nez a0, a0, a2 ; RV32ZICOND-NEXT: czero.eqz a1, a1, a2 -; RV32ZICOND-NEXT: or a0, a1, a0 +; RV32ZICOND-NEXT: sll a0, a0, a1 ; RV32ZICOND-NEXT: ret ; ; RV64ZICOND-LABEL: shl32: ; RV64ZICOND: # %bb.0: ; RV64ZICOND-NEXT: andi a2, a2, 1 -; RV64ZICOND-NEXT: sllw a1, a0, a1 -; RV64ZICOND-NEXT: czero.nez a0, a0, a2 ; RV64ZICOND-NEXT: czero.eqz a1, a1, a2 -; RV64ZICOND-NEXT: or a0, a1, a0 +; RV64ZICOND-NEXT: sllw a0, a0, a1 ; RV64ZICOND-NEXT: ret %binop = shl i32 %x, %y %select_ = select i1 %c, i32 %binop, i32 %x @@ -66,54 +58,46 @@ define i32 @ashr32(i32 %x, i32 %y, i1 %c) { ; RV32I-LABEL: ashr32: ; RV32I: # %bb.0: -; RV32I-NEXT: andi a2, a2, 1 -; RV32I-NEXT: beqz a2, .LBB1_2 -; RV32I-NEXT: # %bb.1: +; RV32I-NEXT: slli a2, a2, 31 +; RV32I-NEXT: srai a2, a2, 31 +; RV32I-NEXT: and a1, a2, a1 ; RV32I-NEXT: sra a0, a0, a1 -; RV32I-NEXT: .LBB1_2: ; RV32I-NEXT: ret ; ; RV64I-LABEL: ashr32: ; RV64I: # %bb.0: -; RV64I-NEXT: andi a2, a2, 1 -; RV64I-NEXT: beqz a2, .LBB1_2 -; RV64I-NEXT: # %bb.1: +; RV64I-NEXT: slli a2, a2, 63 +; RV64I-NEXT: srai a2, a2, 63 +; RV64I-NEXT: and a1, a2, a1 ; RV64I-NEXT: sraw a0, a0, a1 -; RV64I-NEXT: .LBB1_2: ; RV64I-NEXT: ret ; ; RV64XVENTANACONDOPS-LABEL: ashr32: ; RV64XVENTANACONDOPS: # %bb.0: ; RV64XVENTANACONDOPS-NEXT: andi a2, a2, 1 -; RV64XVENTANACONDOPS-NEXT: sraw a1, a0, a1 -; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, a2 ; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a2 -; RV64XVENTANACONDOPS-NEXT: or a0, a1, a0 +; RV64XVENTANACONDOPS-NEXT: sraw a0, a0, a1 ; RV64XVENTANACONDOPS-NEXT: ret ; ; RV64XTHEADCONDMOV-LABEL: ashr32: ; RV64XTHEADCONDMOV: # %bb.0: ; RV64XTHEADCONDMOV-NEXT: andi a2, a2, 1 -; RV64XTHEADCONDMOV-NEXT: sraw a1, a0, a1 -; RV64XTHEADCONDMOV-NEXT: th.mvnez a0, a1, a2 +; RV64XTHEADCONDMOV-NEXT: th.mveqz a1, zero, a2 +; RV64XTHEADCONDMOV-NEXT: sraw a0, a0, a1 ; RV64XTHEADCONDMOV-NEXT: ret ; ; RV32ZICOND-LABEL: ashr32: ; RV32ZICOND: # %bb.0: ; RV32ZICOND-NEXT: andi a2, a2, 1 -; RV32ZICOND-NEXT: sra a1, a0, a1 -; RV32ZICOND-NEXT: czero.nez a0, a0, a2 ; RV32ZICOND-NEXT: czero.eqz a1, a1, a2 -; RV32ZICOND-NEXT: or a0, a1, a0 +; RV32ZICOND-NEXT: sra a0, a0, a1 ; RV32ZICOND-NEXT: ret ; ; RV64ZICOND-LABEL: ashr32: ; RV64ZICOND: # %bb.0: ; RV64ZICOND-NEXT: andi a2, a2, 1 -; RV64ZICOND-NEXT: sraw a1, a0, a1 -; RV64ZICOND-NEXT: czero.nez a0, a0, a2 ; RV64ZICOND-NEXT: czero.eqz a1, a1, a2 -; RV64ZICOND-NEXT: or a0, a1, a0 +; RV64ZICOND-NEXT: sraw a0, a0, a1 ; RV64ZICOND-NEXT: ret %binop = ashr i32 %x, %y %select_ = select i1 %c, i32 %binop, i32 %x @@ -123,54 +107,46 @@ define i32 @lshr32(i32 %x, i32 %y, i1 %c) { ; RV32I-LABEL: lshr32: ; RV32I: # %bb.0: -; RV32I-NEXT: andi a2, a2, 1 -; RV32I-NEXT: beqz a2, .LBB2_2 -; RV32I-NEXT: # %bb.1: +; RV32I-NEXT: slli a2, a2, 31 +; RV32I-NEXT: srai a2, a2, 31 +; RV32I-NEXT: and a1, a2, a1 ; RV32I-NEXT: srl a0, a0, a1 -; RV32I-NEXT: .LBB2_2: ; RV32I-NEXT: ret ; ; RV64I-LABEL: lshr32: ; RV64I: # %bb.0: -; RV64I-NEXT: andi a2, a2, 1 -; RV64I-NEXT: beqz a2, .LBB2_2 -; RV64I-NEXT: # %bb.1: +; RV64I-NEXT: slli a2, a2, 63 +; RV64I-NEXT: srai a2, a2, 63 +; RV64I-NEXT: and a1, a2, a1 ; RV64I-NEXT: srlw a0, a0, a1 -; RV64I-NEXT: .LBB2_2: ; RV64I-NEXT: ret ; ; RV64XVENTANACONDOPS-LABEL: lshr32: ; RV64XVENTANACONDOPS: # %bb.0: ; RV64XVENTANACONDOPS-NEXT: andi a2, a2, 1 -; RV64XVENTANACONDOPS-NEXT: srlw a1, a0, a1 -; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, a2 ; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a2 -; RV64XVENTANACONDOPS-NEXT: or a0, a1, a0 +; RV64XVENTANACONDOPS-NEXT: srlw a0, a0, a1 ; RV64XVENTANACONDOPS-NEXT: ret ; ; RV64XTHEADCONDMOV-LABEL: lshr32: ; RV64XTHEADCONDMOV: # %bb.0: ; RV64XTHEADCONDMOV-NEXT: andi a2, a2, 1 -; RV64XTHEADCONDMOV-NEXT: srlw a1, a0, a1 -; RV64XTHEADCONDMOV-NEXT: th.mvnez a0, a1, a2 +; RV64XTHEADCONDMOV-NEXT: th.mveqz a1, zero, a2 +; RV64XTHEADCONDMOV-NEXT: srlw a0, a0, a1 ; RV64XTHEADCONDMOV-NEXT: ret ; ; RV32ZICOND-LABEL: lshr32: ; RV32ZICOND: # %bb.0: ; RV32ZICOND-NEXT: andi a2, a2, 1 -; RV32ZICOND-NEXT: srl a1, a0, a1 -; RV32ZICOND-NEXT: czero.nez a0, a0, a2 ; RV32ZICOND-NEXT: czero.eqz a1, a1, a2 -; RV32ZICOND-NEXT: or a0, a1, a0 +; RV32ZICOND-NEXT: srl a0, a0, a1 ; RV32ZICOND-NEXT: ret ; ; RV64ZICOND-LABEL: lshr32: ; RV64ZICOND: # %bb.0: ; RV64ZICOND-NEXT: andi a2, a2, 1 -; RV64ZICOND-NEXT: srlw a1, a0, a1 -; RV64ZICOND-NEXT: czero.nez a0, a0, a2 ; RV64ZICOND-NEXT: czero.eqz a1, a1, a2 -; RV64ZICOND-NEXT: or a0, a1, a0 +; RV64ZICOND-NEXT: srlw a0, a0, a1 ; RV64ZICOND-NEXT: ret %binop = lshr i32 %x, %y %select_ = select i1 %c, i32 %binop, i32 %x @@ -432,83 +408,71 @@ define i64 @shl64(i64 %x, i64 %y, i1 %c) { ; RV32I-LABEL: shl64: ; RV32I: # %bb.0: -; RV32I-NEXT: andi a4, a4, 1 -; RV32I-NEXT: addi a5, a2, -32 -; RV32I-NEXT: sll a3, a0, a2 -; RV32I-NEXT: bltz a5, .LBB8_3 +; RV32I-NEXT: slli a4, a4, 31 +; RV32I-NEXT: srai a4, a4, 31 +; RV32I-NEXT: and a4, a4, a2 +; RV32I-NEXT: addi a3, a4, -32 +; RV32I-NEXT: sll a2, a0, a4 +; RV32I-NEXT: bltz a3, .LBB8_2 ; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: beqz a4, .LBB8_4 -; RV32I-NEXT: .LBB8_2: -; RV32I-NEXT: srai a0, a5, 31 -; RV32I-NEXT: and a0, a0, a3 ; RV32I-NEXT: mv a1, a2 -; RV32I-NEXT: ret +; RV32I-NEXT: j .LBB8_3 +; RV32I-NEXT: .LBB8_2: +; RV32I-NEXT: sll a1, a1, a4 +; RV32I-NEXT: not a4, a4 +; RV32I-NEXT: srli a0, a0, 1 +; RV32I-NEXT: srl a0, a0, a4 +; RV32I-NEXT: or a1, a1, a0 ; RV32I-NEXT: .LBB8_3: -; RV32I-NEXT: sll a6, a1, a2 -; RV32I-NEXT: not a2, a2 -; RV32I-NEXT: srli a7, a0, 1 -; RV32I-NEXT: srl a2, a7, a2 -; RV32I-NEXT: or a2, a6, a2 -; RV32I-NEXT: bnez a4, .LBB8_2 -; RV32I-NEXT: .LBB8_4: +; RV32I-NEXT: srai a0, a3, 31 +; RV32I-NEXT: and a0, a0, a2 ; RV32I-NEXT: ret ; ; RV64I-LABEL: shl64: ; RV64I: # %bb.0: -; RV64I-NEXT: andi a2, a2, 1 -; RV64I-NEXT: beqz a2, .LBB8_2 -; RV64I-NEXT: # %bb.1: +; RV64I-NEXT: slli a2, a2, 63 +; RV64I-NEXT: srai a2, a2, 63 +; RV64I-NEXT: and a1, a2, a1 ; RV64I-NEXT: sll a0, a0, a1 -; RV64I-NEXT: .LBB8_2: ; RV64I-NEXT: ret ; ; RV64XVENTANACONDOPS-LABEL: shl64: ; RV64XVENTANACONDOPS: # %bb.0: ; RV64XVENTANACONDOPS-NEXT: andi a2, a2, 1 -; RV64XVENTANACONDOPS-NEXT: sll a1, a0, a1 -; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, a2 ; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a2 -; RV64XVENTANACONDOPS-NEXT: or a0, a1, a0 +; RV64XVENTANACONDOPS-NEXT: sll a0, a0, a1 ; RV64XVENTANACONDOPS-NEXT: ret ; ; RV64XTHEADCONDMOV-LABEL: shl64: ; RV64XTHEADCONDMOV: # %bb.0: ; RV64XTHEADCONDMOV-NEXT: andi a2, a2, 1 -; RV64XTHEADCONDMOV-NEXT: sll a1, a0, a1 -; RV64XTHEADCONDMOV-NEXT: th.mvnez a0, a1, a2 +; RV64XTHEADCONDMOV-NEXT: th.mveqz a1, zero, a2 +; RV64XTHEADCONDMOV-NEXT: sll a0, a0, a1 ; RV64XTHEADCONDMOV-NEXT: ret ; ; RV32ZICOND-LABEL: shl64: ; RV32ZICOND: # %bb.0: ; RV32ZICOND-NEXT: andi a4, a4, 1 -; RV32ZICOND-NEXT: sll a3, a1, a2 -; RV32ZICOND-NEXT: not a5, a2 -; RV32ZICOND-NEXT: srli a6, a0, 1 -; RV32ZICOND-NEXT: srl a5, a6, a5 -; RV32ZICOND-NEXT: or a3, a3, a5 -; RV32ZICOND-NEXT: addi a5, a2, -32 -; RV32ZICOND-NEXT: slti a5, a5, 0 -; RV32ZICOND-NEXT: czero.eqz a3, a3, a5 -; RV32ZICOND-NEXT: sll a2, a0, a2 -; RV32ZICOND-NEXT: czero.nez a6, a2, a5 -; RV32ZICOND-NEXT: or a3, a3, a6 -; RV32ZICOND-NEXT: czero.eqz a2, a2, a5 -; RV32ZICOND-NEXT: czero.nez a0, a0, a4 ; RV32ZICOND-NEXT: czero.eqz a2, a2, a4 -; RV32ZICOND-NEXT: or a0, a2, a0 -; RV32ZICOND-NEXT: czero.eqz a2, a3, a4 -; RV32ZICOND-NEXT: czero.nez a1, a1, a4 -; RV32ZICOND-NEXT: or a1, a2, a1 +; RV32ZICOND-NEXT: sll a3, a0, a2 +; RV32ZICOND-NEXT: addi a4, a2, -32 +; RV32ZICOND-NEXT: slti a4, a4, 0 +; RV32ZICOND-NEXT: czero.nez a5, a3, a4 +; RV32ZICOND-NEXT: sll a1, a1, a2 +; RV32ZICOND-NEXT: not a2, a2 +; RV32ZICOND-NEXT: srli a0, a0, 1 +; RV32ZICOND-NEXT: srl a0, a0, a2 +; RV32ZICOND-NEXT: or a0, a1, a0 +; RV32ZICOND-NEXT: czero.eqz a1, a0, a4 +; RV32ZICOND-NEXT: or a1, a1, a5 +; RV32ZICOND-NEXT: czero.eqz a0, a3, a4 ; RV32ZICOND-NEXT: ret ; ; RV64ZICOND-LABEL: shl64: ; RV64ZICOND: # %bb.0: ; RV64ZICOND-NEXT: andi a2, a2, 1 -; RV64ZICOND-NEXT: sll a1, a0, a1 -; RV64ZICOND-NEXT: czero.nez a0, a0, a2 ; RV64ZICOND-NEXT: czero.eqz a1, a1, a2 -; RV64ZICOND-NEXT: or a0, a1, a0 +; RV64ZICOND-NEXT: sll a0, a0, a1 ; RV64ZICOND-NEXT: ret %binop = shl i64 %x, %y %select_ = select i1 %c, i64 %binop, i64 %x @@ -518,89 +482,74 @@ define i64 @ashr64(i64 %x, i64 %y, i1 %c) { ; RV32I-LABEL: ashr64: ; RV32I: # %bb.0: -; RV32I-NEXT: andi a5, a4, 1 -; RV32I-NEXT: addi a3, a2, -32 -; RV32I-NEXT: sra a4, a1, a2 -; RV32I-NEXT: bltz a3, .LBB9_2 +; RV32I-NEXT: mv a3, a0 +; RV32I-NEXT: slli a4, a4, 31 +; RV32I-NEXT: srai a4, a4, 31 +; RV32I-NEXT: and a2, a4, a2 +; RV32I-NEXT: addi a4, a2, -32 +; RV32I-NEXT: sra a0, a1, a2 +; RV32I-NEXT: bltz a4, .LBB9_2 ; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: srai a2, a1, 31 -; RV32I-NEXT: mv a3, a4 -; RV32I-NEXT: mv a4, a2 -; RV32I-NEXT: beqz a5, .LBB9_3 -; RV32I-NEXT: j .LBB9_4 +; RV32I-NEXT: srai a1, a1, 31 +; RV32I-NEXT: ret ; RV32I-NEXT: .LBB9_2: -; RV32I-NEXT: srl a3, a0, a2 +; RV32I-NEXT: srl a3, a3, a2 ; RV32I-NEXT: not a2, a2 -; RV32I-NEXT: slli a6, a1, 1 -; RV32I-NEXT: sll a2, a6, a2 -; RV32I-NEXT: or a3, a3, a2 -; RV32I-NEXT: bnez a5, .LBB9_4 -; RV32I-NEXT: .LBB9_3: -; RV32I-NEXT: mv a3, a0 -; RV32I-NEXT: mv a4, a1 -; RV32I-NEXT: .LBB9_4: +; RV32I-NEXT: slli a1, a1, 1 +; RV32I-NEXT: sll a1, a1, a2 +; RV32I-NEXT: or a3, a3, a1 +; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a0, a3 -; RV32I-NEXT: mv a1, a4 ; RV32I-NEXT: ret ; ; RV64I-LABEL: ashr64: ; RV64I: # %bb.0: -; RV64I-NEXT: andi a2, a2, 1 -; RV64I-NEXT: beqz a2, .LBB9_2 -; RV64I-NEXT: # %bb.1: +; RV64I-NEXT: slli a2, a2, 63 +; RV64I-NEXT: srai a2, a2, 63 +; RV64I-NEXT: and a1, a2, a1 ; RV64I-NEXT: sra a0, a0, a1 -; RV64I-NEXT: .LBB9_2: ; RV64I-NEXT: ret ; ; RV64XVENTANACONDOPS-LABEL: ashr64: ; RV64XVENTANACONDOPS: # %bb.0: ; RV64XVENTANACONDOPS-NEXT: andi a2, a2, 1 -; RV64XVENTANACONDOPS-NEXT: sra a1, a0, a1 -; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, a2 ; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a2 -; RV64XVENTANACONDOPS-NEXT: or a0, a1, a0 +; RV64XVENTANACONDOPS-NEXT: sra a0, a0, a1 ; RV64XVENTANACONDOPS-NEXT: ret ; ; RV64XTHEADCONDMOV-LABEL: ashr64: ; RV64XTHEADCONDMOV: # %bb.0: ; RV64XTHEADCONDMOV-NEXT: andi a2, a2, 1 -; RV64XTHEADCONDMOV-NEXT: sra a1, a0, a1 -; RV64XTHEADCONDMOV-NEXT: th.mvnez a0, a1, a2 +; RV64XTHEADCONDMOV-NEXT: th.mveqz a1, zero, a2 +; RV64XTHEADCONDMOV-NEXT: sra a0, a0, a1 ; RV64XTHEADCONDMOV-NEXT: ret ; ; RV32ZICOND-LABEL: ashr64: ; RV32ZICOND: # %bb.0: ; RV32ZICOND-NEXT: andi a4, a4, 1 -; RV32ZICOND-NEXT: srl a3, a0, a2 -; RV32ZICOND-NEXT: not a5, a2 -; RV32ZICOND-NEXT: slli a6, a1, 1 -; RV32ZICOND-NEXT: sll a5, a6, a5 -; RV32ZICOND-NEXT: or a3, a3, a5 -; RV32ZICOND-NEXT: addi a5, a2, -32 -; RV32ZICOND-NEXT: slti a5, a5, 0 -; RV32ZICOND-NEXT: czero.eqz a3, a3, a5 -; RV32ZICOND-NEXT: sra a2, a1, a2 -; RV32ZICOND-NEXT: czero.nez a6, a2, a5 -; RV32ZICOND-NEXT: or a3, a3, a6 -; RV32ZICOND-NEXT: srai a6, a1, 31 -; RV32ZICOND-NEXT: czero.nez a6, a6, a5 -; RV32ZICOND-NEXT: czero.eqz a2, a2, a5 -; RV32ZICOND-NEXT: or a2, a2, a6 ; RV32ZICOND-NEXT: czero.eqz a2, a2, a4 +; RV32ZICOND-NEXT: sra a3, a1, a2 +; RV32ZICOND-NEXT: addi a4, a2, -32 +; RV32ZICOND-NEXT: slti a4, a4, 0 +; RV32ZICOND-NEXT: czero.nez a5, a3, a4 +; RV32ZICOND-NEXT: srl a0, a0, a2 +; RV32ZICOND-NEXT: not a2, a2 +; RV32ZICOND-NEXT: slli a6, a1, 1 +; RV32ZICOND-NEXT: sll a2, a6, a2 +; RV32ZICOND-NEXT: or a0, a0, a2 +; RV32ZICOND-NEXT: czero.eqz a0, a0, a4 +; RV32ZICOND-NEXT: or a0, a0, a5 +; RV32ZICOND-NEXT: czero.eqz a2, a3, a4 +; RV32ZICOND-NEXT: srai a1, a1, 31 ; RV32ZICOND-NEXT: czero.nez a1, a1, a4 ; RV32ZICOND-NEXT: or a1, a2, a1 -; RV32ZICOND-NEXT: czero.eqz a2, a3, a4 -; RV32ZICOND-NEXT: czero.nez a0, a0, a4 -; RV32ZICOND-NEXT: or a0, a2, a0 ; RV32ZICOND-NEXT: ret ; ; RV64ZICOND-LABEL: ashr64: ; RV64ZICOND: # %bb.0: ; RV64ZICOND-NEXT: andi a2, a2, 1 -; RV64ZICOND-NEXT: sra a1, a0, a1 -; RV64ZICOND-NEXT: czero.nez a0, a0, a2 ; RV64ZICOND-NEXT: czero.eqz a1, a1, a2 -; RV64ZICOND-NEXT: or a0, a1, a0 +; RV64ZICOND-NEXT: sra a0, a0, a1 ; RV64ZICOND-NEXT: ret %binop = ashr i64 %x, %y %select_ = select i1 %c, i64 %binop, i64 %x @@ -610,83 +559,71 @@ define i64 @lshr64(i64 %x, i64 %y, i1 %c) { ; RV32I-LABEL: lshr64: ; RV32I: # %bb.0: -; RV32I-NEXT: andi a4, a4, 1 -; RV32I-NEXT: addi a5, a2, -32 -; RV32I-NEXT: srl a3, a1, a2 -; RV32I-NEXT: bltz a5, .LBB10_3 +; RV32I-NEXT: slli a4, a4, 31 +; RV32I-NEXT: srai a4, a4, 31 +; RV32I-NEXT: and a4, a4, a2 +; RV32I-NEXT: addi a3, a4, -32 +; RV32I-NEXT: srl a2, a1, a4 +; RV32I-NEXT: bltz a3, .LBB10_2 ; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: beqz a4, .LBB10_4 -; RV32I-NEXT: .LBB10_2: -; RV32I-NEXT: srai a1, a5, 31 -; RV32I-NEXT: and a1, a1, a3 ; RV32I-NEXT: mv a0, a2 -; RV32I-NEXT: ret +; RV32I-NEXT: j .LBB10_3 +; RV32I-NEXT: .LBB10_2: +; RV32I-NEXT: srl a0, a0, a4 +; RV32I-NEXT: not a4, a4 +; RV32I-NEXT: slli a1, a1, 1 +; RV32I-NEXT: sll a1, a1, a4 +; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: .LBB10_3: -; RV32I-NEXT: srl a6, a0, a2 -; RV32I-NEXT: not a2, a2 -; RV32I-NEXT: slli a7, a1, 1 -; RV32I-NEXT: sll a2, a7, a2 -; RV32I-NEXT: or a2, a6, a2 -; RV32I-NEXT: bnez a4, .LBB10_2 -; RV32I-NEXT: .LBB10_4: +; RV32I-NEXT: srai a1, a3, 31 +; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: ret ; ; RV64I-LABEL: lshr64: ; RV64I: # %bb.0: -; RV64I-NEXT: andi a2, a2, 1 -; RV64I-NEXT: beqz a2, .LBB10_2 -; RV64I-NEXT: # %bb.1: +; RV64I-NEXT: slli a2, a2, 63 +; RV64I-NEXT: srai a2, a2, 63 +; RV64I-NEXT: and a1, a2, a1 ; RV64I-NEXT: srl a0, a0, a1 -; RV64I-NEXT: .LBB10_2: ; RV64I-NEXT: ret ; ; RV64XVENTANACONDOPS-LABEL: lshr64: ; RV64XVENTANACONDOPS: # %bb.0: ; RV64XVENTANACONDOPS-NEXT: andi a2, a2, 1 -; RV64XVENTANACONDOPS-NEXT: srl a1, a0, a1 -; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, a2 ; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a2 -; RV64XVENTANACONDOPS-NEXT: or a0, a1, a0 +; RV64XVENTANACONDOPS-NEXT: srl a0, a0, a1 ; RV64XVENTANACONDOPS-NEXT: ret ; ; RV64XTHEADCONDMOV-LABEL: lshr64: ; RV64XTHEADCONDMOV: # %bb.0: ; RV64XTHEADCONDMOV-NEXT: andi a2, a2, 1 -; RV64XTHEADCONDMOV-NEXT: srl a1, a0, a1 -; RV64XTHEADCONDMOV-NEXT: th.mvnez a0, a1, a2 +; RV64XTHEADCONDMOV-NEXT: th.mveqz a1, zero, a2 +; RV64XTHEADCONDMOV-NEXT: srl a0, a0, a1 ; RV64XTHEADCONDMOV-NEXT: ret ; ; RV32ZICOND-LABEL: lshr64: ; RV32ZICOND: # %bb.0: ; RV32ZICOND-NEXT: andi a4, a4, 1 -; RV32ZICOND-NEXT: srl a3, a0, a2 -; RV32ZICOND-NEXT: not a5, a2 -; RV32ZICOND-NEXT: slli a6, a1, 1 -; RV32ZICOND-NEXT: sll a5, a6, a5 -; RV32ZICOND-NEXT: or a3, a3, a5 -; RV32ZICOND-NEXT: addi a5, a2, -32 -; RV32ZICOND-NEXT: slti a5, a5, 0 -; RV32ZICOND-NEXT: czero.eqz a3, a3, a5 -; RV32ZICOND-NEXT: srl a2, a1, a2 -; RV32ZICOND-NEXT: czero.nez a6, a2, a5 -; RV32ZICOND-NEXT: or a3, a3, a6 -; RV32ZICOND-NEXT: czero.eqz a2, a2, a5 -; RV32ZICOND-NEXT: czero.nez a1, a1, a4 ; RV32ZICOND-NEXT: czero.eqz a2, a2, a4 -; RV32ZICOND-NEXT: or a1, a2, a1 -; RV32ZICOND-NEXT: czero.eqz a2, a3, a4 -; RV32ZICOND-NEXT: czero.nez a0, a0, a4 -; RV32ZICOND-NEXT: or a0, a2, a0 +; RV32ZICOND-NEXT: srl a3, a1, a2 +; RV32ZICOND-NEXT: addi a4, a2, -32 +; RV32ZICOND-NEXT: slti a4, a4, 0 +; RV32ZICOND-NEXT: czero.nez a5, a3, a4 +; RV32ZICOND-NEXT: srl a0, a0, a2 +; RV32ZICOND-NEXT: not a2, a2 +; RV32ZICOND-NEXT: slli a1, a1, 1 +; RV32ZICOND-NEXT: sll a1, a1, a2 +; RV32ZICOND-NEXT: or a0, a0, a1 +; RV32ZICOND-NEXT: czero.eqz a0, a0, a4 +; RV32ZICOND-NEXT: or a0, a0, a5 +; RV32ZICOND-NEXT: czero.eqz a1, a3, a4 ; RV32ZICOND-NEXT: ret ; ; RV64ZICOND-LABEL: lshr64: ; RV64ZICOND: # %bb.0: ; RV64ZICOND-NEXT: andi a2, a2, 1 -; RV64ZICOND-NEXT: srl a1, a0, a1 -; RV64ZICOND-NEXT: czero.nez a0, a0, a2 ; RV64ZICOND-NEXT: czero.eqz a1, a1, a2 -; RV64ZICOND-NEXT: or a0, a1, a0 +; RV64ZICOND-NEXT: srl a0, a0, a1 ; RV64ZICOND-NEXT: ret %binop = lshr i64 %x, %y %select_ = select i1 %c, i64 %binop, i64 %x diff --git a/llvm/test/CodeGen/RISCV/select.ll b/llvm/test/CodeGen/RISCV/select.ll --- a/llvm/test/CodeGen/RISCV/select.ll +++ b/llvm/test/CodeGen/RISCV/select.ll @@ -1152,44 +1152,34 @@ define i32 @select_shl_2(i1 zeroext %cond, i32 %a, i32 %b) { ; RV32IM-LABEL: select_shl_2: ; RV32IM: # %bb.0: # %entry -; RV32IM-NEXT: bnez a0, .LBB29_2 -; RV32IM-NEXT: # %bb.1: # %entry -; RV32IM-NEXT: sll a1, a1, a2 -; RV32IM-NEXT: .LBB29_2: # %entry -; RV32IM-NEXT: mv a0, a1 +; RV32IM-NEXT: addi a0, a0, -1 +; RV32IM-NEXT: and a0, a0, a2 +; RV32IM-NEXT: sll a0, a1, a0 ; RV32IM-NEXT: ret ; ; RV64IM-LABEL: select_shl_2: ; RV64IM: # %bb.0: # %entry -; RV64IM-NEXT: bnez a0, .LBB29_2 -; RV64IM-NEXT: # %bb.1: # %entry -; RV64IM-NEXT: sllw a1, a1, a2 -; RV64IM-NEXT: .LBB29_2: # %entry -; RV64IM-NEXT: mv a0, a1 +; RV64IM-NEXT: addiw a0, a0, -1 +; RV64IM-NEXT: and a0, a0, a2 +; RV64IM-NEXT: sllw a0, a1, a0 ; RV64IM-NEXT: ret ; ; RV64IMXVTCONDOPS-LABEL: select_shl_2: ; RV64IMXVTCONDOPS: # %bb.0: # %entry -; RV64IMXVTCONDOPS-NEXT: sllw a2, a1, a2 -; RV64IMXVTCONDOPS-NEXT: vt.maskc a1, a1, a0 ; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a2, a0 -; RV64IMXVTCONDOPS-NEXT: or a0, a1, a0 +; RV64IMXVTCONDOPS-NEXT: sllw a0, a1, a0 ; RV64IMXVTCONDOPS-NEXT: ret ; ; RV32IMZICOND-LABEL: select_shl_2: ; RV32IMZICOND: # %bb.0: # %entry -; RV32IMZICOND-NEXT: sll a2, a1, a2 -; RV32IMZICOND-NEXT: czero.eqz a1, a1, a0 ; RV32IMZICOND-NEXT: czero.nez a0, a2, a0 -; RV32IMZICOND-NEXT: or a0, a1, a0 +; RV32IMZICOND-NEXT: sll a0, a1, a0 ; RV32IMZICOND-NEXT: ret ; ; RV64IMZICOND-LABEL: select_shl_2: ; RV64IMZICOND: # %bb.0: # %entry -; RV64IMZICOND-NEXT: sllw a2, a1, a2 -; RV64IMZICOND-NEXT: czero.eqz a1, a1, a0 ; RV64IMZICOND-NEXT: czero.nez a0, a2, a0 -; RV64IMZICOND-NEXT: or a0, a1, a0 +; RV64IMZICOND-NEXT: sllw a0, a1, a0 ; RV64IMZICOND-NEXT: ret entry: %c = shl i32 %a, %b @@ -1259,44 +1249,34 @@ define i32 @select_ashr_2(i1 zeroext %cond, i32 %a, i32 %b) { ; RV32IM-LABEL: select_ashr_2: ; RV32IM: # %bb.0: # %entry -; RV32IM-NEXT: bnez a0, .LBB32_2 -; RV32IM-NEXT: # %bb.1: # %entry -; RV32IM-NEXT: sra a1, a1, a2 -; RV32IM-NEXT: .LBB32_2: # %entry -; RV32IM-NEXT: mv a0, a1 +; RV32IM-NEXT: addi a0, a0, -1 +; RV32IM-NEXT: and a0, a0, a2 +; RV32IM-NEXT: sra a0, a1, a0 ; RV32IM-NEXT: ret ; ; RV64IM-LABEL: select_ashr_2: ; RV64IM: # %bb.0: # %entry -; RV64IM-NEXT: bnez a0, .LBB32_2 -; RV64IM-NEXT: # %bb.1: # %entry -; RV64IM-NEXT: sraw a1, a1, a2 -; RV64IM-NEXT: .LBB32_2: # %entry -; RV64IM-NEXT: mv a0, a1 +; RV64IM-NEXT: addiw a0, a0, -1 +; RV64IM-NEXT: and a0, a0, a2 +; RV64IM-NEXT: sraw a0, a1, a0 ; RV64IM-NEXT: ret ; ; RV64IMXVTCONDOPS-LABEL: select_ashr_2: ; RV64IMXVTCONDOPS: # %bb.0: # %entry -; RV64IMXVTCONDOPS-NEXT: sraw a2, a1, a2 -; RV64IMXVTCONDOPS-NEXT: vt.maskc a1, a1, a0 ; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a2, a0 -; RV64IMXVTCONDOPS-NEXT: or a0, a1, a0 +; RV64IMXVTCONDOPS-NEXT: sraw a0, a1, a0 ; RV64IMXVTCONDOPS-NEXT: ret ; ; RV32IMZICOND-LABEL: select_ashr_2: ; RV32IMZICOND: # %bb.0: # %entry -; RV32IMZICOND-NEXT: sra a2, a1, a2 -; RV32IMZICOND-NEXT: czero.eqz a1, a1, a0 ; RV32IMZICOND-NEXT: czero.nez a0, a2, a0 -; RV32IMZICOND-NEXT: or a0, a1, a0 +; RV32IMZICOND-NEXT: sra a0, a1, a0 ; RV32IMZICOND-NEXT: ret ; ; RV64IMZICOND-LABEL: select_ashr_2: ; RV64IMZICOND: # %bb.0: # %entry -; RV64IMZICOND-NEXT: sraw a2, a1, a2 -; RV64IMZICOND-NEXT: czero.eqz a1, a1, a0 ; RV64IMZICOND-NEXT: czero.nez a0, a2, a0 -; RV64IMZICOND-NEXT: or a0, a1, a0 +; RV64IMZICOND-NEXT: sraw a0, a1, a0 ; RV64IMZICOND-NEXT: ret entry: %c = ashr i32 %a, %b @@ -1366,44 +1346,34 @@ define i32 @select_lshr_2(i1 zeroext %cond, i32 %a, i32 %b) { ; RV32IM-LABEL: select_lshr_2: ; RV32IM: # %bb.0: # %entry -; RV32IM-NEXT: bnez a0, .LBB35_2 -; RV32IM-NEXT: # %bb.1: # %entry -; RV32IM-NEXT: srl a1, a1, a2 -; RV32IM-NEXT: .LBB35_2: # %entry -; RV32IM-NEXT: mv a0, a1 +; RV32IM-NEXT: addi a0, a0, -1 +; RV32IM-NEXT: and a0, a0, a2 +; RV32IM-NEXT: srl a0, a1, a0 ; RV32IM-NEXT: ret ; ; RV64IM-LABEL: select_lshr_2: ; RV64IM: # %bb.0: # %entry -; RV64IM-NEXT: bnez a0, .LBB35_2 -; RV64IM-NEXT: # %bb.1: # %entry -; RV64IM-NEXT: srlw a1, a1, a2 -; RV64IM-NEXT: .LBB35_2: # %entry -; RV64IM-NEXT: mv a0, a1 +; RV64IM-NEXT: addiw a0, a0, -1 +; RV64IM-NEXT: and a0, a0, a2 +; RV64IM-NEXT: srlw a0, a1, a0 ; RV64IM-NEXT: ret ; ; RV64IMXVTCONDOPS-LABEL: select_lshr_2: ; RV64IMXVTCONDOPS: # %bb.0: # %entry -; RV64IMXVTCONDOPS-NEXT: srlw a2, a1, a2 -; RV64IMXVTCONDOPS-NEXT: vt.maskc a1, a1, a0 ; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a2, a0 -; RV64IMXVTCONDOPS-NEXT: or a0, a1, a0 +; RV64IMXVTCONDOPS-NEXT: srlw a0, a1, a0 ; RV64IMXVTCONDOPS-NEXT: ret ; ; RV32IMZICOND-LABEL: select_lshr_2: ; RV32IMZICOND: # %bb.0: # %entry -; RV32IMZICOND-NEXT: srl a2, a1, a2 -; RV32IMZICOND-NEXT: czero.eqz a1, a1, a0 ; RV32IMZICOND-NEXT: czero.nez a0, a2, a0 -; RV32IMZICOND-NEXT: or a0, a1, a0 +; RV32IMZICOND-NEXT: srl a0, a1, a0 ; RV32IMZICOND-NEXT: ret ; ; RV64IMZICOND-LABEL: select_lshr_2: ; RV64IMZICOND: # %bb.0: # %entry -; RV64IMZICOND-NEXT: srlw a2, a1, a2 -; RV64IMZICOND-NEXT: czero.eqz a1, a1, a0 ; RV64IMZICOND-NEXT: czero.nez a0, a2, a0 -; RV64IMZICOND-NEXT: or a0, a1, a0 +; RV64IMZICOND-NEXT: srlw a0, a1, a0 ; RV64IMZICOND-NEXT: ret entry: %c = lshr i32 %a, %b diff --git a/llvm/test/CodeGen/RISCV/sextw-removal.ll b/llvm/test/CodeGen/RISCV/sextw-removal.ll --- a/llvm/test/CodeGen/RISCV/sextw-removal.ll +++ b/llvm/test/CodeGen/RISCV/sextw-removal.ll @@ -1032,94 +1032,82 @@ define signext i32 @bug(i32 signext %x) { ; CHECK-LABEL: bug: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: beqz a0, .LBB18_11 +; CHECK-NEXT: beqz a0, .LBB18_4 ; CHECK-NEXT: # %bb.1: # %if.end -; CHECK-NEXT: srliw a1, a0, 16 -; CHECK-NEXT: beqz a1, .LBB18_3 +; CHECK-NEXT: srliw a2, a0, 16 +; CHECK-NEXT: seqz a1, a2 +; CHECK-NEXT: slli a1, a1, 4 +; CHECK-NEXT: sllw a1, a0, a1 +; CHECK-NEXT: li a0, 16 +; CHECK-NEXT: beqz a2, .LBB18_3 ; CHECK-NEXT: # %bb.2: # %if.end -; CHECK-NEXT: li a1, 32 -; CHECK-NEXT: j .LBB18_4 -; CHECK-NEXT: .LBB18_3: -; CHECK-NEXT: slli a0, a0, 16 -; CHECK-NEXT: li a1, 16 -; CHECK-NEXT: .LBB18_4: # %if.end -; CHECK-NEXT: srliw a3, a0, 24 -; CHECK-NEXT: snez a2, a3 -; CHECK-NEXT: bnez a3, .LBB18_6 -; CHECK-NEXT: # %bb.5: -; CHECK-NEXT: slli a0, a0, 8 -; CHECK-NEXT: .LBB18_6: # %if.end -; CHECK-NEXT: addi a2, a2, -1 +; CHECK-NEXT: li a0, 32 +; CHECK-NEXT: .LBB18_3: # %if.end +; CHECK-NEXT: srliw a2, a1, 24 +; CHECK-NEXT: seqz a2, a2 +; CHECK-NEXT: slli a3, a2, 3 +; CHECK-NEXT: sllw a1, a1, a3 +; CHECK-NEXT: neg a2, a2 ; CHECK-NEXT: andi a2, a2, -8 -; CHECK-NEXT: add a1, a1, a2 -; CHECK-NEXT: srliw a3, a0, 28 -; CHECK-NEXT: snez a2, a3 -; CHECK-NEXT: bnez a3, .LBB18_8 -; CHECK-NEXT: # %bb.7: -; CHECK-NEXT: slli a0, a0, 4 -; CHECK-NEXT: .LBB18_8: # %if.end -; CHECK-NEXT: addi a2, a2, -1 +; CHECK-NEXT: add a0, a0, a2 +; CHECK-NEXT: srliw a2, a1, 28 +; CHECK-NEXT: seqz a2, a2 +; CHECK-NEXT: slli a3, a2, 2 +; CHECK-NEXT: sllw a1, a1, a3 +; CHECK-NEXT: neg a2, a2 ; CHECK-NEXT: andi a2, a2, -4 -; CHECK-NEXT: add a1, a1, a2 -; CHECK-NEXT: srliw a3, a0, 30 -; CHECK-NEXT: snez a2, a3 -; CHECK-NEXT: bnez a3, .LBB18_10 -; CHECK-NEXT: # %bb.9: -; CHECK-NEXT: slli a0, a0, 2 -; CHECK-NEXT: .LBB18_10: # %if.end -; CHECK-NEXT: addi a2, a2, -1 +; CHECK-NEXT: add a0, a0, a2 +; CHECK-NEXT: srliw a2, a1, 30 +; CHECK-NEXT: seqz a2, a2 +; CHECK-NEXT: slli a3, a2, 1 +; CHECK-NEXT: sllw a1, a1, a3 +; CHECK-NEXT: neg a2, a2 ; CHECK-NEXT: andi a2, a2, -2 -; CHECK-NEXT: sraiw a0, a0, 31 -; CHECK-NEXT: not a0, a0 -; CHECK-NEXT: add a0, a2, a0 -; CHECK-NEXT: addw a0, a1, a0 -; CHECK-NEXT: .LBB18_11: # %cleanup +; CHECK-NEXT: add a0, a0, a2 +; CHECK-NEXT: srai a1, a1, 31 +; CHECK-NEXT: not a1, a1 +; CHECK-NEXT: addw a0, a0, a1 +; CHECK-NEXT: .LBB18_4: # %cleanup ; CHECK-NEXT: ret ; ; NOREMOVAL-LABEL: bug: ; NOREMOVAL: # %bb.0: # %entry -; NOREMOVAL-NEXT: beqz a0, .LBB18_11 +; NOREMOVAL-NEXT: beqz a0, .LBB18_4 ; NOREMOVAL-NEXT: # %bb.1: # %if.end -; NOREMOVAL-NEXT: srliw a1, a0, 16 -; NOREMOVAL-NEXT: beqz a1, .LBB18_3 +; NOREMOVAL-NEXT: srliw a2, a0, 16 +; NOREMOVAL-NEXT: seqz a1, a2 +; NOREMOVAL-NEXT: slli a1, a1, 4 +; NOREMOVAL-NEXT: sllw a1, a0, a1 +; NOREMOVAL-NEXT: li a0, 16 +; NOREMOVAL-NEXT: beqz a2, .LBB18_3 ; NOREMOVAL-NEXT: # %bb.2: # %if.end -; NOREMOVAL-NEXT: li a1, 32 -; NOREMOVAL-NEXT: j .LBB18_4 -; NOREMOVAL-NEXT: .LBB18_3: -; NOREMOVAL-NEXT: slli a0, a0, 16 -; NOREMOVAL-NEXT: li a1, 16 -; NOREMOVAL-NEXT: .LBB18_4: # %if.end -; NOREMOVAL-NEXT: srliw a3, a0, 24 -; NOREMOVAL-NEXT: snez a2, a3 -; NOREMOVAL-NEXT: bnez a3, .LBB18_6 -; NOREMOVAL-NEXT: # %bb.5: -; NOREMOVAL-NEXT: slli a0, a0, 8 -; NOREMOVAL-NEXT: .LBB18_6: # %if.end -; NOREMOVAL-NEXT: addi a2, a2, -1 +; NOREMOVAL-NEXT: li a0, 32 +; NOREMOVAL-NEXT: .LBB18_3: # %if.end +; NOREMOVAL-NEXT: srliw a2, a1, 24 +; NOREMOVAL-NEXT: seqz a2, a2 +; NOREMOVAL-NEXT: slli a3, a2, 3 +; NOREMOVAL-NEXT: sllw a1, a1, a3 +; NOREMOVAL-NEXT: neg a2, a2 ; NOREMOVAL-NEXT: andi a2, a2, -8 -; NOREMOVAL-NEXT: add a1, a1, a2 -; NOREMOVAL-NEXT: srliw a3, a0, 28 -; NOREMOVAL-NEXT: snez a2, a3 -; NOREMOVAL-NEXT: bnez a3, .LBB18_8 -; NOREMOVAL-NEXT: # %bb.7: -; NOREMOVAL-NEXT: slli a0, a0, 4 -; NOREMOVAL-NEXT: .LBB18_8: # %if.end -; NOREMOVAL-NEXT: addi a2, a2, -1 +; NOREMOVAL-NEXT: add a0, a0, a2 +; NOREMOVAL-NEXT: srliw a2, a1, 28 +; NOREMOVAL-NEXT: seqz a2, a2 +; NOREMOVAL-NEXT: slli a3, a2, 2 +; NOREMOVAL-NEXT: sllw a1, a1, a3 +; NOREMOVAL-NEXT: neg a2, a2 ; NOREMOVAL-NEXT: andi a2, a2, -4 -; NOREMOVAL-NEXT: add a1, a1, a2 -; NOREMOVAL-NEXT: srliw a3, a0, 30 -; NOREMOVAL-NEXT: snez a2, a3 -; NOREMOVAL-NEXT: bnez a3, .LBB18_10 -; NOREMOVAL-NEXT: # %bb.9: -; NOREMOVAL-NEXT: slli a0, a0, 2 -; NOREMOVAL-NEXT: .LBB18_10: # %if.end -; NOREMOVAL-NEXT: addi a2, a2, -1 +; NOREMOVAL-NEXT: add a0, a0, a2 +; NOREMOVAL-NEXT: srliw a2, a1, 30 +; NOREMOVAL-NEXT: seqz a2, a2 +; NOREMOVAL-NEXT: slli a3, a2, 1 +; NOREMOVAL-NEXT: sllw a1, a1, a3 +; NOREMOVAL-NEXT: neg a2, a2 ; NOREMOVAL-NEXT: andi a2, a2, -2 -; NOREMOVAL-NEXT: sraiw a0, a0, 31 -; NOREMOVAL-NEXT: not a0, a0 -; NOREMOVAL-NEXT: add a0, a2, a0 -; NOREMOVAL-NEXT: add a0, a1, a0 -; NOREMOVAL-NEXT: .LBB18_11: # %cleanup +; NOREMOVAL-NEXT: add a0, a0, a2 +; NOREMOVAL-NEXT: srai a1, a1, 31 +; NOREMOVAL-NEXT: not a1, a1 +; NOREMOVAL-NEXT: add a0, a0, a1 +; NOREMOVAL-NEXT: .LBB18_4: # %cleanup ; NOREMOVAL-NEXT: sext.w a0, a0 ; NOREMOVAL-NEXT: ret entry: