Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -12260,9 +12260,13 @@
                                    SDValue TrueVal, SDValue FalseVal,
                                    bool Swapped) {
   bool Commutative = true;
-  switch (TrueVal.getOpcode()) {
+  unsigned Opc = TrueVal.getOpcode();
+  switch (Opc) {
   default:
     return SDValue();
+  case ISD::SHL:
+  case ISD::SRA:
+  case ISD::SRL:
   case ISD::SUB:
     Commutative = false;
     break;
@@ -12285,12 +12289,16 @@
 
   EVT VT = N->getValueType(0);
   SDLoc DL(N);
-  SDValue Zero = DAG.getConstant(0, DL, VT);
   SDValue OtherOp = TrueVal.getOperand(1 - OpToFold);
+  EVT OtherOpVT = OtherOp->getValueType(0);
+  SDValue IdentityOperand = DAG.getNeutralElement(Opc, DL, OtherOpVT, N->getFlags());
+  if (!Commutative)
+    IdentityOperand = DAG.getConstant(0, DL, OtherOpVT);
+  assert(IdentityOperand && "No identity operand!");
 
   if (Swapped)
-    std::swap(OtherOp, Zero);
-  SDValue NewSel = DAG.getSelect(DL, VT, N->getOperand(0), OtherOp, Zero);
+    std::swap(OtherOp, IdentityOperand);
+  SDValue NewSel = DAG.getSelect(DL, OtherOpVT, N->getOperand(0), OtherOp, IdentityOperand);
   return DAG.getNode(TrueVal.getOpcode(), DL, VT, FalseVal, NewSel);
 }
 
Index: llvm/test/CodeGen/RISCV/select.ll
===================================================================
--- llvm/test/CodeGen/RISCV/select.ll
+++ llvm/test/CodeGen/RISCV/select.ll
@@ -1153,44 +1153,34 @@
 define i32 @select_shl_2(i1 zeroext %cond, i32 %a, i32 %b) {
 ; RV32IM-LABEL: select_shl_2:
 ; RV32IM:       # %bb.0: # %entry
-; RV32IM-NEXT:    bnez a0, .LBB29_2
-; RV32IM-NEXT:  # %bb.1: # %entry
-; RV32IM-NEXT:    sll a1, a1, a2
-; RV32IM-NEXT:  .LBB29_2: # %entry
-; RV32IM-NEXT:    mv a0, a1
+; RV32IM-NEXT:    addi a0, a0, -1
+; RV32IM-NEXT:    and a0, a0, a2
+; RV32IM-NEXT:    sll a0, a1, a0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64IM-LABEL: select_shl_2:
 ; RV64IM:       # %bb.0: # %entry
-; RV64IM-NEXT:    bnez a0, .LBB29_2
-; RV64IM-NEXT:  # %bb.1: # %entry
-; RV64IM-NEXT:    sllw a1, a1, a2
-; RV64IM-NEXT:  .LBB29_2: # %entry
-; RV64IM-NEXT:    mv a0, a1
+; RV64IM-NEXT:    addiw a0, a0, -1
+; RV64IM-NEXT:    and a0, a0, a2
+; RV64IM-NEXT:    sllw a0, a1, a0
 ; RV64IM-NEXT:    ret
 ;
 ; RV64IMXVTCONDOPS-LABEL: select_shl_2:
 ; RV64IMXVTCONDOPS:       # %bb.0: # %entry
-; RV64IMXVTCONDOPS-NEXT:    sllw a2, a1, a2
-; RV64IMXVTCONDOPS-NEXT:    vt.maskc a1, a1, a0
 ; RV64IMXVTCONDOPS-NEXT:    vt.maskcn a0, a2, a0
-; RV64IMXVTCONDOPS-NEXT:    or a0, a1, a0
+; RV64IMXVTCONDOPS-NEXT:    sllw a0, a1, a0
 ; RV64IMXVTCONDOPS-NEXT:    ret
 ;
 ; RV32IMZICOND-LABEL: select_shl_2:
 ; RV32IMZICOND:       # %bb.0: # %entry
-; RV32IMZICOND-NEXT:    sll a2, a1, a2
-; RV32IMZICOND-NEXT:    czero.eqz a1, a1, a0
 ; RV32IMZICOND-NEXT:    czero.nez a0, a2, a0
-; RV32IMZICOND-NEXT:    or a0, a1, a0
+; RV32IMZICOND-NEXT:    sll a0, a1, a0
 ; RV32IMZICOND-NEXT:    ret
 ;
 ; RV64IMZICOND-LABEL: select_shl_2:
 ; RV64IMZICOND:       # %bb.0: # %entry
-; RV64IMZICOND-NEXT:    sllw a2, a1, a2
-; RV64IMZICOND-NEXT:    czero.eqz a1, a1, a0
 ; RV64IMZICOND-NEXT:    czero.nez a0, a2, a0
-; RV64IMZICOND-NEXT:    or a0, a1, a0
+; RV64IMZICOND-NEXT:    sllw a0, a1, a0
 ; RV64IMZICOND-NEXT:    ret
 entry:
   %c = shl i32 %a, %b
@@ -1260,44 +1250,34 @@
 define i32 @select_ashr_2(i1 zeroext %cond, i32 %a, i32 %b) {
 ; RV32IM-LABEL: select_ashr_2:
 ; RV32IM:       # %bb.0: # %entry
-; RV32IM-NEXT:    bnez a0, .LBB32_2
-; RV32IM-NEXT:  # %bb.1: # %entry
-; RV32IM-NEXT:    sra a1, a1, a2
-; RV32IM-NEXT:  .LBB32_2: # %entry
-; RV32IM-NEXT:    mv a0, a1
+; RV32IM-NEXT:    addi a0, a0, -1
+; RV32IM-NEXT:    and a0, a0, a2
+; RV32IM-NEXT:    sra a0, a1, a0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64IM-LABEL: select_ashr_2:
 ; RV64IM:       # %bb.0: # %entry
-; RV64IM-NEXT:    bnez a0, .LBB32_2
-; RV64IM-NEXT:  # %bb.1: # %entry
-; RV64IM-NEXT:    sraw a1, a1, a2
-; RV64IM-NEXT:  .LBB32_2: # %entry
-; RV64IM-NEXT:    mv a0, a1
+; RV64IM-NEXT:    addiw a0, a0, -1
+; RV64IM-NEXT:    and a0, a0, a2
+; RV64IM-NEXT:    sraw a0, a1, a0
 ; RV64IM-NEXT:    ret
 ;
 ; RV64IMXVTCONDOPS-LABEL: select_ashr_2:
 ; RV64IMXVTCONDOPS:       # %bb.0: # %entry
-; RV64IMXVTCONDOPS-NEXT:    sraw a2, a1, a2
-; RV64IMXVTCONDOPS-NEXT:    vt.maskc a1, a1, a0
 ; RV64IMXVTCONDOPS-NEXT:    vt.maskcn a0, a2, a0
-; RV64IMXVTCONDOPS-NEXT:    or a0, a1, a0
+; RV64IMXVTCONDOPS-NEXT:    sraw a0, a1, a0
 ; RV64IMXVTCONDOPS-NEXT:    ret
 ;
 ; RV32IMZICOND-LABEL: select_ashr_2:
 ; RV32IMZICOND:       # %bb.0: # %entry
-; RV32IMZICOND-NEXT:    sra a2, a1, a2
-; RV32IMZICOND-NEXT:    czero.eqz a1, a1, a0
 ; RV32IMZICOND-NEXT:    czero.nez a0, a2, a0
-; RV32IMZICOND-NEXT:    or a0, a1, a0
+; RV32IMZICOND-NEXT:    sra a0, a1, a0
 ; RV32IMZICOND-NEXT:    ret
 ;
 ; RV64IMZICOND-LABEL: select_ashr_2:
 ; RV64IMZICOND:       # %bb.0: # %entry
-; RV64IMZICOND-NEXT:    sraw a2, a1, a2
-; RV64IMZICOND-NEXT:    czero.eqz a1, a1, a0
 ; RV64IMZICOND-NEXT:    czero.nez a0, a2, a0
-; RV64IMZICOND-NEXT:    or a0, a1, a0
+; RV64IMZICOND-NEXT:    sraw a0, a1, a0
 ; RV64IMZICOND-NEXT:    ret
 entry:
   %c = ashr i32 %a, %b
@@ -1367,44 +1347,34 @@
 define i32 @select_lshr_2(i1 zeroext %cond, i32 %a, i32 %b) {
 ; RV32IM-LABEL: select_lshr_2:
 ; RV32IM:       # %bb.0: # %entry
-; RV32IM-NEXT:    bnez a0, .LBB35_2
-; RV32IM-NEXT:  # %bb.1: # %entry
-; RV32IM-NEXT:    srl a1, a1, a2
-; RV32IM-NEXT:  .LBB35_2: # %entry
-; RV32IM-NEXT:    mv a0, a1
+; RV32IM-NEXT:    addi a0, a0, -1
+; RV32IM-NEXT:    and a0, a0, a2
+; RV32IM-NEXT:    srl a0, a1, a0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64IM-LABEL: select_lshr_2:
 ; RV64IM:       # %bb.0: # %entry
-; RV64IM-NEXT:    bnez a0, .LBB35_2
-; RV64IM-NEXT:  # %bb.1: # %entry
-; RV64IM-NEXT:    srlw a1, a1, a2
-; RV64IM-NEXT:  .LBB35_2: # %entry
-; RV64IM-NEXT:    mv a0, a1
+; RV64IM-NEXT:    addiw a0, a0, -1
+; RV64IM-NEXT:    and a0, a0, a2
+; RV64IM-NEXT:    srlw a0, a1, a0
 ; RV64IM-NEXT:    ret
 ;
 ; RV64IMXVTCONDOPS-LABEL: select_lshr_2:
 ; RV64IMXVTCONDOPS:       # %bb.0: # %entry
-; RV64IMXVTCONDOPS-NEXT:    srlw a2, a1, a2
-; RV64IMXVTCONDOPS-NEXT:    vt.maskc a1, a1, a0
 ; RV64IMXVTCONDOPS-NEXT:    vt.maskcn a0, a2, a0
-; RV64IMXVTCONDOPS-NEXT:    or a0, a1, a0
+; RV64IMXVTCONDOPS-NEXT:    srlw a0, a1, a0
 ; RV64IMXVTCONDOPS-NEXT:    ret
 ;
 ; RV32IMZICOND-LABEL: select_lshr_2:
 ; RV32IMZICOND:       # %bb.0: # %entry
-; RV32IMZICOND-NEXT:    srl a2, a1, a2
-; RV32IMZICOND-NEXT:    czero.eqz a1, a1, a0
 ; RV32IMZICOND-NEXT:    czero.nez a0, a2, a0
-; RV32IMZICOND-NEXT:    or a0, a1, a0
+; RV32IMZICOND-NEXT:    srl a0, a1, a0
 ; RV32IMZICOND-NEXT:    ret
 ;
 ; RV64IMZICOND-LABEL: select_lshr_2:
 ; RV64IMZICOND:       # %bb.0: # %entry
-; RV64IMZICOND-NEXT:    srlw a2, a1, a2
-; RV64IMZICOND-NEXT:    czero.eqz a1, a1, a0
 ; RV64IMZICOND-NEXT:    czero.nez a0, a2, a0
-; RV64IMZICOND-NEXT:    or a0, a1, a0
+; RV64IMZICOND-NEXT:    srlw a0, a1, a0
 ; RV64IMZICOND-NEXT:    ret
 entry:
   %c = lshr i32 %a, %b
Index: llvm/test/CodeGen/RISCV/sextw-removal.ll
===================================================================
--- llvm/test/CodeGen/RISCV/sextw-removal.ll
+++ llvm/test/CodeGen/RISCV/sextw-removal.ll
@@ -1032,94 +1032,82 @@
 define signext i32 @bug(i32 signext %x) {
 ; CHECK-LABEL: bug:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    beqz a0, .LBB18_11
+; CHECK-NEXT:    beqz a0, .LBB18_4
 ; CHECK-NEXT:  # %bb.1: # %if.end
-; CHECK-NEXT:    srliw a1, a0, 16
-; CHECK-NEXT:    beqz a1, .LBB18_3
+; CHECK-NEXT:    srliw a2, a0, 16
+; CHECK-NEXT:    seqz a1, a2
+; CHECK-NEXT:    slli a1, a1, 4
+; CHECK-NEXT:    sllw a1, a0, a1
+; CHECK-NEXT:    li a0, 16
+; CHECK-NEXT:    beqz a2, .LBB18_3
 ; CHECK-NEXT:  # %bb.2: # %if.end
-; CHECK-NEXT:    li a1, 32
-; CHECK-NEXT:    j .LBB18_4
-; CHECK-NEXT:  .LBB18_3:
-; CHECK-NEXT:    slli a0, a0, 16
-; CHECK-NEXT:    li a1, 16
-; CHECK-NEXT:  .LBB18_4: # %if.end
-; CHECK-NEXT:    srliw a3, a0, 24
-; CHECK-NEXT:    snez a2, a3
-; CHECK-NEXT:    bnez a3, .LBB18_6
-; CHECK-NEXT:  # %bb.5:
-; CHECK-NEXT:    slli a0, a0, 8
-; CHECK-NEXT:  .LBB18_6: # %if.end
-; CHECK-NEXT:    addi a2, a2, -1
+; CHECK-NEXT:    li a0, 32
+; CHECK-NEXT:  .LBB18_3: # %if.end
+; CHECK-NEXT:    srliw a2, a1, 24
+; CHECK-NEXT:    seqz a2, a2
+; CHECK-NEXT:    slli a3, a2, 3
+; CHECK-NEXT:    sllw a1, a1, a3
+; CHECK-NEXT:    neg a2, a2
 ; CHECK-NEXT:    andi a2, a2, -8
-; CHECK-NEXT:    add a1, a1, a2
-; CHECK-NEXT:    srliw a3, a0, 28
-; CHECK-NEXT:    snez a2, a3
-; CHECK-NEXT:    bnez a3, .LBB18_8
-; CHECK-NEXT:  # %bb.7:
-; CHECK-NEXT:    slli a0, a0, 4
-; CHECK-NEXT:  .LBB18_8: # %if.end
-; CHECK-NEXT:    addi a2, a2, -1
+; CHECK-NEXT:    add a0, a0, a2
+; CHECK-NEXT:    srliw a2, a1, 28
+; CHECK-NEXT:    seqz a2, a2
+; CHECK-NEXT:    slli a3, a2, 2
+; CHECK-NEXT:    sllw a1, a1, a3
+; CHECK-NEXT:    neg a2, a2
 ; CHECK-NEXT:    andi a2, a2, -4
-; CHECK-NEXT:    add a1, a1, a2
-; CHECK-NEXT:    srliw a3, a0, 30
-; CHECK-NEXT:    snez a2, a3
-; CHECK-NEXT:    bnez a3, .LBB18_10
-; CHECK-NEXT:  # %bb.9:
-; CHECK-NEXT:    slli a0, a0, 2
-; CHECK-NEXT:  .LBB18_10: # %if.end
-; CHECK-NEXT:    addi a2, a2, -1
+; CHECK-NEXT:    add a0, a0, a2
+; CHECK-NEXT:    srliw a2, a1, 30
+; CHECK-NEXT:    seqz a2, a2
+; CHECK-NEXT:    slli a3, a2, 1
+; CHECK-NEXT:    sllw a1, a1, a3
+; CHECK-NEXT:    neg a2, a2
 ; CHECK-NEXT:    andi a2, a2, -2
-; CHECK-NEXT:    sraiw a0, a0, 31
-; CHECK-NEXT:    not a0, a0
-; CHECK-NEXT:    add a0, a2, a0
-; CHECK-NEXT:    addw a0, a1, a0
-; CHECK-NEXT:  .LBB18_11: # %cleanup
+; CHECK-NEXT:    add a0, a0, a2
+; CHECK-NEXT:    srai a1, a1, 31
+; CHECK-NEXT:    not a1, a1
+; CHECK-NEXT:    addw a0, a0, a1
+; CHECK-NEXT:  .LBB18_4: # %cleanup
 ; CHECK-NEXT:    ret
 ;
 ; NOREMOVAL-LABEL: bug:
 ; NOREMOVAL:       # %bb.0: # %entry
-; NOREMOVAL-NEXT:    beqz a0, .LBB18_11
+; NOREMOVAL-NEXT:    beqz a0, .LBB18_4
 ; NOREMOVAL-NEXT:  # %bb.1: # %if.end
-; NOREMOVAL-NEXT:    srliw a1, a0, 16
-; NOREMOVAL-NEXT:    beqz a1, .LBB18_3
+; NOREMOVAL-NEXT:    srliw a2, a0, 16
+; NOREMOVAL-NEXT:    seqz a1, a2
+; NOREMOVAL-NEXT:    slli a1, a1, 4
+; NOREMOVAL-NEXT:    sllw a1, a0, a1
+; NOREMOVAL-NEXT:    li a0, 16
+; NOREMOVAL-NEXT:    beqz a2, .LBB18_3
 ; NOREMOVAL-NEXT:  # %bb.2: # %if.end
-; NOREMOVAL-NEXT:    li a1, 32
-; NOREMOVAL-NEXT:    j .LBB18_4
-; NOREMOVAL-NEXT:  .LBB18_3:
-; NOREMOVAL-NEXT:    slli a0, a0, 16
-; NOREMOVAL-NEXT:    li a1, 16
-; NOREMOVAL-NEXT:  .LBB18_4: # %if.end
-; NOREMOVAL-NEXT:    srliw a3, a0, 24
-; NOREMOVAL-NEXT:    snez a2, a3
-; NOREMOVAL-NEXT:    bnez a3, .LBB18_6
-; NOREMOVAL-NEXT:  # %bb.5:
-; NOREMOVAL-NEXT:    slli a0, a0, 8
-; NOREMOVAL-NEXT:  .LBB18_6: # %if.end
-; NOREMOVAL-NEXT:    addi a2, a2, -1
+; NOREMOVAL-NEXT:    li a0, 32
+; NOREMOVAL-NEXT:  .LBB18_3: # %if.end
+; NOREMOVAL-NEXT:    srliw a2, a1, 24
+; NOREMOVAL-NEXT:    seqz a2, a2
+; NOREMOVAL-NEXT:    slli a3, a2, 3
+; NOREMOVAL-NEXT:    sllw a1, a1, a3
+; NOREMOVAL-NEXT:    neg a2, a2
 ; NOREMOVAL-NEXT:    andi a2, a2, -8
-; NOREMOVAL-NEXT:    add a1, a1, a2
-; NOREMOVAL-NEXT:    srliw a3, a0, 28
-; NOREMOVAL-NEXT:    snez a2, a3
-; NOREMOVAL-NEXT:    bnez a3, .LBB18_8
-; NOREMOVAL-NEXT:  # %bb.7:
-; NOREMOVAL-NEXT:    slli a0, a0, 4
-; NOREMOVAL-NEXT:  .LBB18_8: # %if.end
-; NOREMOVAL-NEXT:    addi a2, a2, -1
+; NOREMOVAL-NEXT:    add a0, a0, a2
+; NOREMOVAL-NEXT:    srliw a2, a1, 28
+; NOREMOVAL-NEXT:    seqz a2, a2
+; NOREMOVAL-NEXT:    slli a3, a2, 2
+; NOREMOVAL-NEXT:    sllw a1, a1, a3
+; NOREMOVAL-NEXT:    neg a2, a2
 ; NOREMOVAL-NEXT:    andi a2, a2, -4
-; NOREMOVAL-NEXT:    add a1, a1, a2
-; NOREMOVAL-NEXT:    srliw a3, a0, 30
-; NOREMOVAL-NEXT:    snez a2, a3
-; NOREMOVAL-NEXT:    bnez a3, .LBB18_10
-; NOREMOVAL-NEXT:  # %bb.9:
-; NOREMOVAL-NEXT:    slli a0, a0, 2
-; NOREMOVAL-NEXT:  .LBB18_10: # %if.end
-; NOREMOVAL-NEXT:    addi a2, a2, -1
+; NOREMOVAL-NEXT:    add a0, a0, a2
+; NOREMOVAL-NEXT:    srliw a2, a1, 30
+; NOREMOVAL-NEXT:    seqz a2, a2
+; NOREMOVAL-NEXT:    slli a3, a2, 1
+; NOREMOVAL-NEXT:    sllw a1, a1, a3
+; NOREMOVAL-NEXT:    neg a2, a2
 ; NOREMOVAL-NEXT:    andi a2, a2, -2
-; NOREMOVAL-NEXT:    sraiw a0, a0, 31
-; NOREMOVAL-NEXT:    not a0, a0
-; NOREMOVAL-NEXT:    add a0, a2, a0
-; NOREMOVAL-NEXT:    add a0, a1, a0
-; NOREMOVAL-NEXT:  .LBB18_11: # %cleanup
+; NOREMOVAL-NEXT:    add a0, a0, a2
+; NOREMOVAL-NEXT:    srai a1, a1, 31
+; NOREMOVAL-NEXT:    not a1, a1
+; NOREMOVAL-NEXT:    add a0, a0, a1
+; NOREMOVAL-NEXT:  .LBB18_4: # %cleanup
 ; NOREMOVAL-NEXT:    sext.w a0, a0
 ; NOREMOVAL-NEXT:    ret
 entry: