diff --git a/compiler-rt/lib/lsan/lsan_common.cpp b/compiler-rt/lib/lsan/lsan_common.cpp
--- a/compiler-rt/lib/lsan/lsan_common.cpp
+++ b/compiler-rt/lib/lsan/lsan_common.cpp
@@ -263,18 +263,18 @@
   const uptr kMinAddress = 4 * 4096;
   if (p < kMinAddress)
     return false;
-#  if defined(__x86_64__)
-  // TODO: add logic similar to ARM when Intel LAM is available.
-  // Accept only canonical form user-space addresses.
-  return ((p >> 47) == 0);
-#  elif defined(__mips64)
-  return ((p >> 40) == 0);
-#  elif defined(__aarch64__)
-  // TBI (Top Byte Ignore) feature of AArch64: bits [63:56] are ignored in
-  // address translation and can be used to store a tag.
+#  if defined(__x86_64__) || defined(__aarch64__)
+  // This logic strips down the top byte and the lower 48 bits from the 64 bit
+  // value and checks if the remaining 8 bits are 0. The assumption is that we
+  // have 48 bit VMA and that the top byte can be used to store additional
+  // information on both AArch64 and X86_64. Even though on X86_64 we might use
+  // less than 8 bits from the top byte we want to error on the side of
+  // returning true rather than creating false positive memory leak report.
   constexpr uptr kPointerMask = 255ULL << 48;
   // Accept up to 48 bit VMA.
   return ((p & kPointerMask) == 0);
+#  elif defined(__mips64)
+  return ((p >> 40) == 0);
 #  elif defined(__loongarch_lp64)
   // Allow 47-bit user-space VMA at current.
   return ((p >> 47) == 0);