diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
--- a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
@@ -1665,6 +1665,7 @@
     }
     break;
   }
+  case Instruction::Freeze:
   case Instruction::FPTrunc:
   case Instruction::FPExt:
     simplifyAndSetOp(I, 0, DemandedElts, UndefElts);
diff --git a/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.ll b/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.ll
--- a/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.ll
+++ b/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.ll
@@ -53,8 +53,9 @@
 
 define amdgpu_ps float @extract_elt0_freeze_buffer_load_v2f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
 ; CHECK-LABEL: @extract_elt0_freeze_buffer_load_v2f32(
-; CHECK-NEXT:    [[DATA:%.*]] = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> [[RSRC:%.*]], i32 [[IDX:%.*]], i32 [[OFS:%.*]], i1 false, i1 false)
-; CHECK-NEXT:    [[FREEZE:%.*]] = freeze <2 x float> [[DATA]]
+; CHECK-NEXT:    [[DATA:%.*]] = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> [[RSRC:%.*]], i32 [[IDX:%.*]], i32 [[OFS:%.*]], i1 false, i1 false)
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x float> undef, float [[DATA]], i64 0
+; CHECK-NEXT:    [[FREEZE:%.*]] = freeze <2 x float> [[TMP1]]
 ; CHECK-NEXT:    [[ELT0:%.*]] = extractelement <2 x float> [[FREEZE]], i64 0
 ; CHECK-NEXT:    ret float [[ELT0]]
 ;
diff --git a/llvm/test/Transforms/InstCombine/shufflevector_freezepoison.ll b/llvm/test/Transforms/InstCombine/shufflevector_freezepoison.ll
--- a/llvm/test/Transforms/InstCombine/shufflevector_freezepoison.ll
+++ b/llvm/test/Transforms/InstCombine/shufflevector_freezepoison.ll
@@ -4,8 +4,7 @@
 
 define <4 x double> @shuffle_op0_freeze_poison(<2 x double> %a) {
 ; CHECK-LABEL: @shuffle_op0_freeze_poison(
-; CHECK-NEXT:    [[B:%.*]] = freeze <2 x double> poison
-; CHECK-NEXT:    [[SHUFFLE:%.*]] = shufflevector <2 x double> [[B]], <2 x double> [[A:%.*]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT:    [[SHUFFLE:%.*]] = shufflevector <2 x double> [[A:%.*]], <2 x double> undef, <4 x i32> <i32 poison, i32 poison, i32 0, i32 1>
 ; CHECK-NEXT:    ret <4 x double> [[SHUFFLE]]
 ;
   %b = freeze <2 x double> poison
@@ -15,8 +14,7 @@
 
 define <4 x double> @shuffle_op1_freeze_poison(<2 x double> %a) {
 ; CHECK-LABEL: @shuffle_op1_freeze_poison(
-; CHECK-NEXT:    [[B:%.*]] = freeze <2 x double> poison
-; CHECK-NEXT:    [[SHUFFLE:%.*]] = shufflevector <2 x double> [[A:%.*]], <2 x double> [[B]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT:    [[SHUFFLE:%.*]] = shufflevector <2 x double> [[A:%.*]], <2 x double> undef, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
 ; CHECK-NEXT:    ret <4 x double> [[SHUFFLE]]
 ;
   %b = freeze <2 x double> poison
@@ -78,9 +76,7 @@
 
 define <4 x double> @shuffle_bc1(<2 x double>  %a)  {
 ; CHECK-LABEL: @shuffle_bc1(
-; CHECK-NEXT:    [[B:%.*]] = freeze <4 x float> poison
-; CHECK-NEXT:    [[B1:%.*]] = bitcast <4 x float> [[B]] to <2 x double>
-; CHECK-NEXT:    [[SHUFFLE:%.*]] = shufflevector <2 x double> [[A:%.*]], <2 x double> [[B1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT:    [[SHUFFLE:%.*]] = shufflevector <2 x double> [[A:%.*]], <2 x double> undef, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
 ; CHECK-NEXT:    ret <4 x double> [[SHUFFLE]]
 ;
   %b = freeze <4 x float> poison
diff --git a/llvm/test/Transforms/InstCombine/vec_demanded_elts.ll b/llvm/test/Transforms/InstCombine/vec_demanded_elts.ll
--- a/llvm/test/Transforms/InstCombine/vec_demanded_elts.ll
+++ b/llvm/test/Transforms/InstCombine/vec_demanded_elts.ll
@@ -1162,7 +1162,7 @@
 
 define i32 @test_freeze(<4 x i32> %v, i32 %x) {
 ; CHECK-LABEL: @test_freeze(
-; CHECK-NEXT:    [[INS:%.*]] = insertelement <4 x i32> [[V:%.*]], i32 [[X:%.*]], i64 0
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <4 x i32> poison, i32 [[X:%.*]], i64 0
 ; CHECK-NEXT:    [[FR:%.*]] = freeze <4 x i32> [[INS]]
 ; CHECK-NEXT:    [[RET:%.*]] = extractelement <4 x i32> [[FR]], i64 0
 ; CHECK-NEXT:    ret i32 [[RET]]