diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -12823,6 +12823,14 @@ return DAG.getZExtOrTrunc(AndNode, SDLoc(N), N->getValueType(0)); } +static bool setCCWillBeInvertedWhenLegalized(SDValue V) { + assert(V.getOpcode() == ISD::SETCC && "Unexpected opcode."); + ISD::CondCode CCVal = cast(V.getOperand(2))->get(); + return V.getOperand(0).getValueType().isInteger() && + (CCVal == ISD::SETGE || CCVal == ISD::SETLE || CCVal == ISD::SETUGE || + CCVal == ISD::SETULE); +} + static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget) { if (SDValue Folded = foldSelectOfCTTZOrCTLZ(N, DAG)) @@ -12831,8 +12839,25 @@ if (Subtarget.hasShortForwardBranchOpt()) return SDValue(); + SDValue CondVal = N->getOperand(0); SDValue TrueVal = N->getOperand(1); SDValue FalseVal = N->getOperand(2); + // If CondVal is a setcc that will be inverted when legalized, take + // advantage of the freedom to swap TrueVal and FalseVal and convert the + // setcc to one that is natively supported. + if (CondVal.getOpcode() == ISD::SETCC && + setCCWillBeInvertedWhenLegalized(CondVal)) { + SDLoc DL(N); + EVT VT = N->getValueType(0); + ISD::CondCode NewCCVal = + ISD::getSetCCInverse(cast(CondVal.getOperand(2))->get(), + CondVal.getOperand(0).getValueType()); + return DAG.getSelect(DL, VT, + DAG.getSetCC(DL, CondVal.getValueType(), + CondVal.getOperand(0), + CondVal.getOperand(1), NewCCVal), + FalseVal, TrueVal); + } if (SDValue V = tryFoldSelectIntoOp(N, DAG, TrueVal, FalseVal, /*Swapped*/false)) return V; return tryFoldSelectIntoOp(N, DAG, FalseVal, TrueVal, /*Swapped*/true); diff --git a/llvm/test/CodeGen/RISCV/atomic-rmw.ll b/llvm/test/CodeGen/RISCV/atomic-rmw.ll --- a/llvm/test/CodeGen/RISCV/atomic-rmw.ll +++ b/llvm/test/CodeGen/RISCV/atomic-rmw.ll @@ -3893,11 +3893,11 @@ ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: srai a0, a0, 24 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bge s2, a0, .LBB50_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: blt s2, a0, .LBB50_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB50_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB50_1 ; RV32I-NEXT: .LBB50_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -3964,11 +3964,11 @@ ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: srai a0, a0, 56 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s2, a0, .LBB50_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: blt s2, a0, .LBB50_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB50_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB50_1 ; RV64I-NEXT: .LBB50_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -4039,11 +4039,11 @@ ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: srai a0, a0, 24 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bge s2, a0, .LBB51_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: blt s2, a0, .LBB51_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB51_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB51_1 ; RV32I-NEXT: .LBB51_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -4139,11 +4139,11 @@ ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: srai a0, a0, 56 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s2, a0, .LBB51_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: blt s2, a0, .LBB51_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB51_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB51_1 ; RV64I-NEXT: .LBB51_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -4243,11 +4243,11 @@ ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: srai a0, a0, 24 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bge s2, a0, .LBB52_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: blt s2, a0, .LBB52_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB52_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB52_1 ; RV32I-NEXT: .LBB52_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -4343,11 +4343,11 @@ ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: srai a0, a0, 56 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s2, a0, .LBB52_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: blt s2, a0, .LBB52_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB52_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB52_1 ; RV64I-NEXT: .LBB52_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -4447,11 +4447,11 @@ ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: srai a0, a0, 24 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bge s2, a0, .LBB53_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: blt s2, a0, .LBB53_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB53_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB53_1 ; RV32I-NEXT: .LBB53_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -4547,11 +4547,11 @@ ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: srai a0, a0, 56 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s2, a0, .LBB53_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: blt s2, a0, .LBB53_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB53_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB53_1 ; RV64I-NEXT: .LBB53_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -4651,11 +4651,11 @@ ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: srai a0, a0, 24 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bge s2, a0, .LBB54_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: blt s2, a0, .LBB54_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB54_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB54_1 ; RV32I-NEXT: .LBB54_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -4722,11 +4722,11 @@ ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: srai a0, a0, 56 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s2, a0, .LBB54_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: blt s2, a0, .LBB54_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB54_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB54_1 ; RV64I-NEXT: .LBB54_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -5599,11 +5599,11 @@ ; RV32I-NEXT: .LBB60_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: andi a0, a3, 255 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bgeu s2, a0, .LBB60_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: bltu s2, a0, .LBB60_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB60_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB60_1 ; RV32I-NEXT: .LBB60_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -5663,11 +5663,11 @@ ; RV64I-NEXT: .LBB60_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: andi a0, a3, 255 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s2, a0, .LBB60_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: bltu s2, a0, .LBB60_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB60_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB60_1 ; RV64I-NEXT: .LBB60_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -5731,11 +5731,11 @@ ; RV32I-NEXT: .LBB61_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: andi a0, a3, 255 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bgeu s2, a0, .LBB61_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: bltu s2, a0, .LBB61_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB61_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB61_1 ; RV32I-NEXT: .LBB61_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -5819,11 +5819,11 @@ ; RV64I-NEXT: .LBB61_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: andi a0, a3, 255 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s2, a0, .LBB61_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: bltu s2, a0, .LBB61_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB61_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB61_1 ; RV64I-NEXT: .LBB61_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -5911,11 +5911,11 @@ ; RV32I-NEXT: .LBB62_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: andi a0, a3, 255 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bgeu s2, a0, .LBB62_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: bltu s2, a0, .LBB62_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB62_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB62_1 ; RV32I-NEXT: .LBB62_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -5999,11 +5999,11 @@ ; RV64I-NEXT: .LBB62_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: andi a0, a3, 255 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s2, a0, .LBB62_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: bltu s2, a0, .LBB62_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB62_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB62_1 ; RV64I-NEXT: .LBB62_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -6091,11 +6091,11 @@ ; RV32I-NEXT: .LBB63_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: andi a0, a3, 255 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bgeu s2, a0, .LBB63_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: bltu s2, a0, .LBB63_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB63_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB63_1 ; RV32I-NEXT: .LBB63_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -6179,11 +6179,11 @@ ; RV64I-NEXT: .LBB63_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: andi a0, a3, 255 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s2, a0, .LBB63_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: bltu s2, a0, .LBB63_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB63_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB63_1 ; RV64I-NEXT: .LBB63_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -6271,11 +6271,11 @@ ; RV32I-NEXT: .LBB64_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: andi a0, a3, 255 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bgeu s2, a0, .LBB64_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: bltu s2, a0, .LBB64_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB64_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB64_1 ; RV32I-NEXT: .LBB64_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -6335,11 +6335,11 @@ ; RV64I-NEXT: .LBB64_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: andi a0, a3, 255 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s2, a0, .LBB64_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: bltu s2, a0, .LBB64_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB64_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB64_1 ; RV64I-NEXT: .LBB64_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -10414,11 +10414,11 @@ ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: srai a0, a0, 16 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bge s2, a0, .LBB115_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: blt s2, a0, .LBB115_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB115_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB115_1 ; RV32I-NEXT: .LBB115_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -10487,11 +10487,11 @@ ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: srai a0, a0, 48 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s2, a0, .LBB115_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: blt s2, a0, .LBB115_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB115_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB115_1 ; RV64I-NEXT: .LBB115_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -10564,11 +10564,11 @@ ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: srai a0, a0, 16 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bge s2, a0, .LBB116_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: blt s2, a0, .LBB116_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB116_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB116_1 ; RV32I-NEXT: .LBB116_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -10668,11 +10668,11 @@ ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: srai a0, a0, 48 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s2, a0, .LBB116_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: blt s2, a0, .LBB116_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB116_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB116_1 ; RV64I-NEXT: .LBB116_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -10776,11 +10776,11 @@ ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: srai a0, a0, 16 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bge s2, a0, .LBB117_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: blt s2, a0, .LBB117_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB117_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB117_1 ; RV32I-NEXT: .LBB117_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -10880,11 +10880,11 @@ ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: srai a0, a0, 48 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s2, a0, .LBB117_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: blt s2, a0, .LBB117_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB117_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB117_1 ; RV64I-NEXT: .LBB117_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -10988,11 +10988,11 @@ ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: srai a0, a0, 16 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bge s2, a0, .LBB118_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: blt s2, a0, .LBB118_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB118_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB118_1 ; RV32I-NEXT: .LBB118_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -11092,11 +11092,11 @@ ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: srai a0, a0, 48 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s2, a0, .LBB118_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: blt s2, a0, .LBB118_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB118_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB118_1 ; RV64I-NEXT: .LBB118_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -11200,11 +11200,11 @@ ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: srai a0, a0, 16 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bge s2, a0, .LBB119_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: blt s2, a0, .LBB119_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB119_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB119_1 ; RV32I-NEXT: .LBB119_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -11273,11 +11273,11 @@ ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: srai a0, a0, 48 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s2, a0, .LBB119_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: blt s2, a0, .LBB119_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB119_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB119_1 ; RV64I-NEXT: .LBB119_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -12211,11 +12211,11 @@ ; RV32I-NEXT: .LBB125_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: and a0, a1, s2 -; RV32I-NEXT: mv a2, a1 -; RV32I-NEXT: bgeu s3, a0, .LBB125_1 +; RV32I-NEXT: mv a2, s0 +; RV32I-NEXT: bltu s3, a0, .LBB125_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB125_2 Depth=1 -; RV32I-NEXT: mv a2, s0 +; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: j .LBB125_1 ; RV32I-NEXT: .LBB125_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a1 @@ -12280,11 +12280,11 @@ ; RV64I-NEXT: .LBB125_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: and a0, a1, s2 -; RV64I-NEXT: mv a2, a1 -; RV64I-NEXT: bgeu s3, a0, .LBB125_1 +; RV64I-NEXT: mv a2, s0 +; RV64I-NEXT: bltu s3, a0, .LBB125_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB125_2 Depth=1 -; RV64I-NEXT: mv a2, s0 +; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: j .LBB125_1 ; RV64I-NEXT: .LBB125_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a1 @@ -12353,11 +12353,11 @@ ; RV32I-NEXT: .LBB126_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: and a0, a1, s2 -; RV32I-NEXT: mv a2, a1 -; RV32I-NEXT: bgeu s3, a0, .LBB126_1 +; RV32I-NEXT: mv a2, s0 +; RV32I-NEXT: bltu s3, a0, .LBB126_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB126_2 Depth=1 -; RV32I-NEXT: mv a2, s0 +; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: j .LBB126_1 ; RV32I-NEXT: .LBB126_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a1 @@ -12447,11 +12447,11 @@ ; RV64I-NEXT: .LBB126_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: and a0, a1, s2 -; RV64I-NEXT: mv a2, a1 -; RV64I-NEXT: bgeu s3, a0, .LBB126_1 +; RV64I-NEXT: mv a2, s0 +; RV64I-NEXT: bltu s3, a0, .LBB126_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB126_2 Depth=1 -; RV64I-NEXT: mv a2, s0 +; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: j .LBB126_1 ; RV64I-NEXT: .LBB126_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a1 @@ -12545,11 +12545,11 @@ ; RV32I-NEXT: .LBB127_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: and a0, a1, s2 -; RV32I-NEXT: mv a2, a1 -; RV32I-NEXT: bgeu s3, a0, .LBB127_1 +; RV32I-NEXT: mv a2, s0 +; RV32I-NEXT: bltu s3, a0, .LBB127_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB127_2 Depth=1 -; RV32I-NEXT: mv a2, s0 +; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: j .LBB127_1 ; RV32I-NEXT: .LBB127_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a1 @@ -12639,11 +12639,11 @@ ; RV64I-NEXT: .LBB127_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: and a0, a1, s2 -; RV64I-NEXT: mv a2, a1 -; RV64I-NEXT: bgeu s3, a0, .LBB127_1 +; RV64I-NEXT: mv a2, s0 +; RV64I-NEXT: bltu s3, a0, .LBB127_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB127_2 Depth=1 -; RV64I-NEXT: mv a2, s0 +; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: j .LBB127_1 ; RV64I-NEXT: .LBB127_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a1 @@ -12737,11 +12737,11 @@ ; RV32I-NEXT: .LBB128_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: and a0, a1, s2 -; RV32I-NEXT: mv a2, a1 -; RV32I-NEXT: bgeu s3, a0, .LBB128_1 +; RV32I-NEXT: mv a2, s0 +; RV32I-NEXT: bltu s3, a0, .LBB128_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB128_2 Depth=1 -; RV32I-NEXT: mv a2, s0 +; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: j .LBB128_1 ; RV32I-NEXT: .LBB128_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a1 @@ -12831,11 +12831,11 @@ ; RV64I-NEXT: .LBB128_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: and a0, a1, s2 -; RV64I-NEXT: mv a2, a1 -; RV64I-NEXT: bgeu s3, a0, .LBB128_1 +; RV64I-NEXT: mv a2, s0 +; RV64I-NEXT: bltu s3, a0, .LBB128_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB128_2 Depth=1 -; RV64I-NEXT: mv a2, s0 +; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: j .LBB128_1 ; RV64I-NEXT: .LBB128_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a1 @@ -12929,11 +12929,11 @@ ; RV32I-NEXT: .LBB129_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: and a0, a1, s2 -; RV32I-NEXT: mv a2, a1 -; RV32I-NEXT: bgeu s3, a0, .LBB129_1 +; RV32I-NEXT: mv a2, s0 +; RV32I-NEXT: bltu s3, a0, .LBB129_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB129_2 Depth=1 -; RV32I-NEXT: mv a2, s0 +; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: j .LBB129_1 ; RV32I-NEXT: .LBB129_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a1 @@ -12998,11 +12998,11 @@ ; RV64I-NEXT: .LBB129_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: and a0, a1, s2 -; RV64I-NEXT: mv a2, a1 -; RV64I-NEXT: bgeu s3, a0, .LBB129_1 +; RV64I-NEXT: mv a2, s0 +; RV64I-NEXT: bltu s3, a0, .LBB129_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB129_2 Depth=1 -; RV64I-NEXT: mv a2, s0 +; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: j .LBB129_1 ; RV64I-NEXT: .LBB129_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a1 @@ -14852,11 +14852,11 @@ ; RV32I-NEXT: bnez a0, .LBB170_4 ; RV32I-NEXT: .LBB170_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bge s1, a3, .LBB170_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: blt s1, a3, .LBB170_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB170_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB170_1 ; RV32I-NEXT: .LBB170_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -14895,11 +14895,11 @@ ; RV64I-NEXT: bnez a0, .LBB170_4 ; RV64I-NEXT: .LBB170_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s2, a3, .LBB170_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: blt s2, a3, .LBB170_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB170_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB170_1 ; RV64I-NEXT: .LBB170_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -14941,11 +14941,11 @@ ; RV32I-NEXT: bnez a0, .LBB171_4 ; RV32I-NEXT: .LBB171_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bge s1, a3, .LBB171_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: blt s1, a3, .LBB171_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB171_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB171_1 ; RV32I-NEXT: .LBB171_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -14984,11 +14984,11 @@ ; RV64I-NEXT: bnez a0, .LBB171_4 ; RV64I-NEXT: .LBB171_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s2, a3, .LBB171_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: blt s2, a3, .LBB171_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB171_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB171_1 ; RV64I-NEXT: .LBB171_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -15030,11 +15030,11 @@ ; RV32I-NEXT: bnez a0, .LBB172_4 ; RV32I-NEXT: .LBB172_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bge s1, a3, .LBB172_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: blt s1, a3, .LBB172_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB172_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB172_1 ; RV32I-NEXT: .LBB172_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -15073,11 +15073,11 @@ ; RV64I-NEXT: bnez a0, .LBB172_4 ; RV64I-NEXT: .LBB172_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s2, a3, .LBB172_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: blt s2, a3, .LBB172_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB172_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB172_1 ; RV64I-NEXT: .LBB172_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -15119,11 +15119,11 @@ ; RV32I-NEXT: bnez a0, .LBB173_4 ; RV32I-NEXT: .LBB173_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bge s1, a3, .LBB173_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: blt s1, a3, .LBB173_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB173_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB173_1 ; RV32I-NEXT: .LBB173_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -15162,11 +15162,11 @@ ; RV64I-NEXT: bnez a0, .LBB173_4 ; RV64I-NEXT: .LBB173_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s2, a3, .LBB173_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: blt s2, a3, .LBB173_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB173_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB173_1 ; RV64I-NEXT: .LBB173_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -15208,11 +15208,11 @@ ; RV32I-NEXT: bnez a0, .LBB174_4 ; RV32I-NEXT: .LBB174_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bge s1, a3, .LBB174_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: blt s1, a3, .LBB174_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB174_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB174_1 ; RV32I-NEXT: .LBB174_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -15251,11 +15251,11 @@ ; RV64I-NEXT: bnez a0, .LBB174_4 ; RV64I-NEXT: .LBB174_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s2, a3, .LBB174_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: blt s2, a3, .LBB174_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB174_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB174_1 ; RV64I-NEXT: .LBB174_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -15742,11 +15742,11 @@ ; RV32I-NEXT: bnez a0, .LBB180_4 ; RV32I-NEXT: .LBB180_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bgeu s1, a3, .LBB180_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: bltu s1, a3, .LBB180_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB180_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB180_1 ; RV32I-NEXT: .LBB180_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -15785,11 +15785,11 @@ ; RV64I-NEXT: bnez a0, .LBB180_4 ; RV64I-NEXT: .LBB180_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s2, a3, .LBB180_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: bltu s2, a3, .LBB180_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB180_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB180_1 ; RV64I-NEXT: .LBB180_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -15831,11 +15831,11 @@ ; RV32I-NEXT: bnez a0, .LBB181_4 ; RV32I-NEXT: .LBB181_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bgeu s1, a3, .LBB181_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: bltu s1, a3, .LBB181_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB181_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB181_1 ; RV32I-NEXT: .LBB181_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -15874,11 +15874,11 @@ ; RV64I-NEXT: bnez a0, .LBB181_4 ; RV64I-NEXT: .LBB181_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s2, a3, .LBB181_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: bltu s2, a3, .LBB181_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB181_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB181_1 ; RV64I-NEXT: .LBB181_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -15920,11 +15920,11 @@ ; RV32I-NEXT: bnez a0, .LBB182_4 ; RV32I-NEXT: .LBB182_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bgeu s1, a3, .LBB182_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: bltu s1, a3, .LBB182_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB182_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB182_1 ; RV32I-NEXT: .LBB182_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -15963,11 +15963,11 @@ ; RV64I-NEXT: bnez a0, .LBB182_4 ; RV64I-NEXT: .LBB182_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s2, a3, .LBB182_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: bltu s2, a3, .LBB182_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB182_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB182_1 ; RV64I-NEXT: .LBB182_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -16009,11 +16009,11 @@ ; RV32I-NEXT: bnez a0, .LBB183_4 ; RV32I-NEXT: .LBB183_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bgeu s1, a3, .LBB183_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: bltu s1, a3, .LBB183_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB183_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB183_1 ; RV32I-NEXT: .LBB183_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -16052,11 +16052,11 @@ ; RV64I-NEXT: bnez a0, .LBB183_4 ; RV64I-NEXT: .LBB183_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s2, a3, .LBB183_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: bltu s2, a3, .LBB183_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB183_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB183_1 ; RV64I-NEXT: .LBB183_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -16098,11 +16098,11 @@ ; RV32I-NEXT: bnez a0, .LBB184_4 ; RV32I-NEXT: .LBB184_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bgeu s1, a3, .LBB184_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: bltu s1, a3, .LBB184_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB184_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB184_1 ; RV32I-NEXT: .LBB184_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -16141,11 +16141,11 @@ ; RV64I-NEXT: bnez a0, .LBB184_4 ; RV64I-NEXT: .LBB184_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s2, a3, .LBB184_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: bltu s2, a3, .LBB184_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB184_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB184_1 ; RV64I-NEXT: .LBB184_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -18407,13 +18407,13 @@ ; RV32I-NEXT: sltu a0, s2, a4 ; RV32I-NEXT: .LBB225_5: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB225_2 Depth=1 -; RV32I-NEXT: mv a2, a4 -; RV32I-NEXT: mv a3, a5 -; RV32I-NEXT: beqz a0, .LBB225_1 -; RV32I-NEXT: # %bb.6: # %atomicrmw.start -; RV32I-NEXT: # in Loop: Header=BB225_2 Depth=1 ; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a3, s1 +; RV32I-NEXT: bnez a0, .LBB225_1 +; RV32I-NEXT: # %bb.6: # %atomicrmw.start +; RV32I-NEXT: # in Loop: Header=BB225_2 Depth=1 +; RV32I-NEXT: mv a2, a4 +; RV32I-NEXT: mv a3, a5 ; RV32I-NEXT: j .LBB225_1 ; RV32I-NEXT: .LBB225_7: # %atomicrmw.end ; RV32I-NEXT: mv a0, a4 @@ -18461,13 +18461,13 @@ ; RV32IA-NEXT: sltu a0, s2, a4 ; RV32IA-NEXT: .LBB225_5: # %atomicrmw.start ; RV32IA-NEXT: # in Loop: Header=BB225_2 Depth=1 -; RV32IA-NEXT: mv a2, a4 -; RV32IA-NEXT: mv a3, a5 -; RV32IA-NEXT: beqz a0, .LBB225_1 -; RV32IA-NEXT: # %bb.6: # %atomicrmw.start -; RV32IA-NEXT: # in Loop: Header=BB225_2 Depth=1 ; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a3, s1 +; RV32IA-NEXT: bnez a0, .LBB225_1 +; RV32IA-NEXT: # %bb.6: # %atomicrmw.start +; RV32IA-NEXT: # in Loop: Header=BB225_2 Depth=1 +; RV32IA-NEXT: mv a2, a4 +; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: j .LBB225_1 ; RV32IA-NEXT: .LBB225_7: # %atomicrmw.end ; RV32IA-NEXT: mv a0, a4 @@ -18501,11 +18501,11 @@ ; RV64I-NEXT: bnez a0, .LBB225_4 ; RV64I-NEXT: .LBB225_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s1, a3, .LBB225_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: blt s1, a3, .LBB225_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB225_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB225_1 ; RV64I-NEXT: .LBB225_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -18560,13 +18560,13 @@ ; RV32I-NEXT: sltu a0, s2, a4 ; RV32I-NEXT: .LBB226_5: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB226_2 Depth=1 -; RV32I-NEXT: mv a2, a4 -; RV32I-NEXT: mv a3, a5 -; RV32I-NEXT: beqz a0, .LBB226_1 -; RV32I-NEXT: # %bb.6: # %atomicrmw.start -; RV32I-NEXT: # in Loop: Header=BB226_2 Depth=1 ; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a3, s1 +; RV32I-NEXT: bnez a0, .LBB226_1 +; RV32I-NEXT: # %bb.6: # %atomicrmw.start +; RV32I-NEXT: # in Loop: Header=BB226_2 Depth=1 +; RV32I-NEXT: mv a2, a4 +; RV32I-NEXT: mv a3, a5 ; RV32I-NEXT: j .LBB226_1 ; RV32I-NEXT: .LBB226_7: # %atomicrmw.end ; RV32I-NEXT: mv a0, a4 @@ -18614,13 +18614,13 @@ ; RV32IA-NEXT: sltu a0, s2, a4 ; RV32IA-NEXT: .LBB226_5: # %atomicrmw.start ; RV32IA-NEXT: # in Loop: Header=BB226_2 Depth=1 -; RV32IA-NEXT: mv a2, a4 -; RV32IA-NEXT: mv a3, a5 -; RV32IA-NEXT: beqz a0, .LBB226_1 -; RV32IA-NEXT: # %bb.6: # %atomicrmw.start -; RV32IA-NEXT: # in Loop: Header=BB226_2 Depth=1 ; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a3, s1 +; RV32IA-NEXT: bnez a0, .LBB226_1 +; RV32IA-NEXT: # %bb.6: # %atomicrmw.start +; RV32IA-NEXT: # in Loop: Header=BB226_2 Depth=1 +; RV32IA-NEXT: mv a2, a4 +; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: j .LBB226_1 ; RV32IA-NEXT: .LBB226_7: # %atomicrmw.end ; RV32IA-NEXT: mv a0, a4 @@ -18654,11 +18654,11 @@ ; RV64I-NEXT: bnez a0, .LBB226_4 ; RV64I-NEXT: .LBB226_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s1, a3, .LBB226_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: blt s1, a3, .LBB226_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB226_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB226_1 ; RV64I-NEXT: .LBB226_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -18713,13 +18713,13 @@ ; RV32I-NEXT: sltu a0, s2, a4 ; RV32I-NEXT: .LBB227_5: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB227_2 Depth=1 -; RV32I-NEXT: mv a2, a4 -; RV32I-NEXT: mv a3, a5 -; RV32I-NEXT: beqz a0, .LBB227_1 -; RV32I-NEXT: # %bb.6: # %atomicrmw.start -; RV32I-NEXT: # in Loop: Header=BB227_2 Depth=1 ; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a3, s1 +; RV32I-NEXT: bnez a0, .LBB227_1 +; RV32I-NEXT: # %bb.6: # %atomicrmw.start +; RV32I-NEXT: # in Loop: Header=BB227_2 Depth=1 +; RV32I-NEXT: mv a2, a4 +; RV32I-NEXT: mv a3, a5 ; RV32I-NEXT: j .LBB227_1 ; RV32I-NEXT: .LBB227_7: # %atomicrmw.end ; RV32I-NEXT: mv a0, a4 @@ -18767,13 +18767,13 @@ ; RV32IA-NEXT: sltu a0, s2, a4 ; RV32IA-NEXT: .LBB227_5: # %atomicrmw.start ; RV32IA-NEXT: # in Loop: Header=BB227_2 Depth=1 -; RV32IA-NEXT: mv a2, a4 -; RV32IA-NEXT: mv a3, a5 -; RV32IA-NEXT: beqz a0, .LBB227_1 -; RV32IA-NEXT: # %bb.6: # %atomicrmw.start -; RV32IA-NEXT: # in Loop: Header=BB227_2 Depth=1 ; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a3, s1 +; RV32IA-NEXT: bnez a0, .LBB227_1 +; RV32IA-NEXT: # %bb.6: # %atomicrmw.start +; RV32IA-NEXT: # in Loop: Header=BB227_2 Depth=1 +; RV32IA-NEXT: mv a2, a4 +; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: j .LBB227_1 ; RV32IA-NEXT: .LBB227_7: # %atomicrmw.end ; RV32IA-NEXT: mv a0, a4 @@ -18807,11 +18807,11 @@ ; RV64I-NEXT: bnez a0, .LBB227_4 ; RV64I-NEXT: .LBB227_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s1, a3, .LBB227_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: blt s1, a3, .LBB227_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB227_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB227_1 ; RV64I-NEXT: .LBB227_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -18866,13 +18866,13 @@ ; RV32I-NEXT: sltu a0, s2, a4 ; RV32I-NEXT: .LBB228_5: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB228_2 Depth=1 -; RV32I-NEXT: mv a2, a4 -; RV32I-NEXT: mv a3, a5 -; RV32I-NEXT: beqz a0, .LBB228_1 -; RV32I-NEXT: # %bb.6: # %atomicrmw.start -; RV32I-NEXT: # in Loop: Header=BB228_2 Depth=1 ; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a3, s1 +; RV32I-NEXT: bnez a0, .LBB228_1 +; RV32I-NEXT: # %bb.6: # %atomicrmw.start +; RV32I-NEXT: # in Loop: Header=BB228_2 Depth=1 +; RV32I-NEXT: mv a2, a4 +; RV32I-NEXT: mv a3, a5 ; RV32I-NEXT: j .LBB228_1 ; RV32I-NEXT: .LBB228_7: # %atomicrmw.end ; RV32I-NEXT: mv a0, a4 @@ -18920,13 +18920,13 @@ ; RV32IA-NEXT: sltu a0, s2, a4 ; RV32IA-NEXT: .LBB228_5: # %atomicrmw.start ; RV32IA-NEXT: # in Loop: Header=BB228_2 Depth=1 -; RV32IA-NEXT: mv a2, a4 -; RV32IA-NEXT: mv a3, a5 -; RV32IA-NEXT: beqz a0, .LBB228_1 -; RV32IA-NEXT: # %bb.6: # %atomicrmw.start -; RV32IA-NEXT: # in Loop: Header=BB228_2 Depth=1 ; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a3, s1 +; RV32IA-NEXT: bnez a0, .LBB228_1 +; RV32IA-NEXT: # %bb.6: # %atomicrmw.start +; RV32IA-NEXT: # in Loop: Header=BB228_2 Depth=1 +; RV32IA-NEXT: mv a2, a4 +; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: j .LBB228_1 ; RV32IA-NEXT: .LBB228_7: # %atomicrmw.end ; RV32IA-NEXT: mv a0, a4 @@ -18960,11 +18960,11 @@ ; RV64I-NEXT: bnez a0, .LBB228_4 ; RV64I-NEXT: .LBB228_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s1, a3, .LBB228_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: blt s1, a3, .LBB228_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB228_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB228_1 ; RV64I-NEXT: .LBB228_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -19019,13 +19019,13 @@ ; RV32I-NEXT: sltu a0, s2, a4 ; RV32I-NEXT: .LBB229_5: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB229_2 Depth=1 -; RV32I-NEXT: mv a2, a4 -; RV32I-NEXT: mv a3, a5 -; RV32I-NEXT: beqz a0, .LBB229_1 -; RV32I-NEXT: # %bb.6: # %atomicrmw.start -; RV32I-NEXT: # in Loop: Header=BB229_2 Depth=1 ; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a3, s1 +; RV32I-NEXT: bnez a0, .LBB229_1 +; RV32I-NEXT: # %bb.6: # %atomicrmw.start +; RV32I-NEXT: # in Loop: Header=BB229_2 Depth=1 +; RV32I-NEXT: mv a2, a4 +; RV32I-NEXT: mv a3, a5 ; RV32I-NEXT: j .LBB229_1 ; RV32I-NEXT: .LBB229_7: # %atomicrmw.end ; RV32I-NEXT: mv a0, a4 @@ -19073,13 +19073,13 @@ ; RV32IA-NEXT: sltu a0, s2, a4 ; RV32IA-NEXT: .LBB229_5: # %atomicrmw.start ; RV32IA-NEXT: # in Loop: Header=BB229_2 Depth=1 -; RV32IA-NEXT: mv a2, a4 -; RV32IA-NEXT: mv a3, a5 -; RV32IA-NEXT: beqz a0, .LBB229_1 -; RV32IA-NEXT: # %bb.6: # %atomicrmw.start -; RV32IA-NEXT: # in Loop: Header=BB229_2 Depth=1 ; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a3, s1 +; RV32IA-NEXT: bnez a0, .LBB229_1 +; RV32IA-NEXT: # %bb.6: # %atomicrmw.start +; RV32IA-NEXT: # in Loop: Header=BB229_2 Depth=1 +; RV32IA-NEXT: mv a2, a4 +; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: j .LBB229_1 ; RV32IA-NEXT: .LBB229_7: # %atomicrmw.end ; RV32IA-NEXT: mv a0, a4 @@ -19113,11 +19113,11 @@ ; RV64I-NEXT: bnez a0, .LBB229_4 ; RV64I-NEXT: .LBB229_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s1, a3, .LBB229_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: blt s1, a3, .LBB229_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB229_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB229_1 ; RV64I-NEXT: .LBB229_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -19937,13 +19937,13 @@ ; RV32I-NEXT: sltu a0, s2, a4 ; RV32I-NEXT: .LBB235_5: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB235_2 Depth=1 -; RV32I-NEXT: mv a2, a4 -; RV32I-NEXT: mv a3, a5 -; RV32I-NEXT: beqz a0, .LBB235_1 -; RV32I-NEXT: # %bb.6: # %atomicrmw.start -; RV32I-NEXT: # in Loop: Header=BB235_2 Depth=1 ; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a3, s1 +; RV32I-NEXT: bnez a0, .LBB235_1 +; RV32I-NEXT: # %bb.6: # %atomicrmw.start +; RV32I-NEXT: # in Loop: Header=BB235_2 Depth=1 +; RV32I-NEXT: mv a2, a4 +; RV32I-NEXT: mv a3, a5 ; RV32I-NEXT: j .LBB235_1 ; RV32I-NEXT: .LBB235_7: # %atomicrmw.end ; RV32I-NEXT: mv a0, a4 @@ -19991,13 +19991,13 @@ ; RV32IA-NEXT: sltu a0, s2, a4 ; RV32IA-NEXT: .LBB235_5: # %atomicrmw.start ; RV32IA-NEXT: # in Loop: Header=BB235_2 Depth=1 -; RV32IA-NEXT: mv a2, a4 -; RV32IA-NEXT: mv a3, a5 -; RV32IA-NEXT: beqz a0, .LBB235_1 -; RV32IA-NEXT: # %bb.6: # %atomicrmw.start -; RV32IA-NEXT: # in Loop: Header=BB235_2 Depth=1 ; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a3, s1 +; RV32IA-NEXT: bnez a0, .LBB235_1 +; RV32IA-NEXT: # %bb.6: # %atomicrmw.start +; RV32IA-NEXT: # in Loop: Header=BB235_2 Depth=1 +; RV32IA-NEXT: mv a2, a4 +; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: j .LBB235_1 ; RV32IA-NEXT: .LBB235_7: # %atomicrmw.end ; RV32IA-NEXT: mv a0, a4 @@ -20031,11 +20031,11 @@ ; RV64I-NEXT: bnez a0, .LBB235_4 ; RV64I-NEXT: .LBB235_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s1, a3, .LBB235_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: bltu s1, a3, .LBB235_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB235_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB235_1 ; RV64I-NEXT: .LBB235_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -20090,13 +20090,13 @@ ; RV32I-NEXT: sltu a0, s2, a4 ; RV32I-NEXT: .LBB236_5: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB236_2 Depth=1 -; RV32I-NEXT: mv a2, a4 -; RV32I-NEXT: mv a3, a5 -; RV32I-NEXT: beqz a0, .LBB236_1 -; RV32I-NEXT: # %bb.6: # %atomicrmw.start -; RV32I-NEXT: # in Loop: Header=BB236_2 Depth=1 ; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a3, s1 +; RV32I-NEXT: bnez a0, .LBB236_1 +; RV32I-NEXT: # %bb.6: # %atomicrmw.start +; RV32I-NEXT: # in Loop: Header=BB236_2 Depth=1 +; RV32I-NEXT: mv a2, a4 +; RV32I-NEXT: mv a3, a5 ; RV32I-NEXT: j .LBB236_1 ; RV32I-NEXT: .LBB236_7: # %atomicrmw.end ; RV32I-NEXT: mv a0, a4 @@ -20144,13 +20144,13 @@ ; RV32IA-NEXT: sltu a0, s2, a4 ; RV32IA-NEXT: .LBB236_5: # %atomicrmw.start ; RV32IA-NEXT: # in Loop: Header=BB236_2 Depth=1 -; RV32IA-NEXT: mv a2, a4 -; RV32IA-NEXT: mv a3, a5 -; RV32IA-NEXT: beqz a0, .LBB236_1 -; RV32IA-NEXT: # %bb.6: # %atomicrmw.start -; RV32IA-NEXT: # in Loop: Header=BB236_2 Depth=1 ; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a3, s1 +; RV32IA-NEXT: bnez a0, .LBB236_1 +; RV32IA-NEXT: # %bb.6: # %atomicrmw.start +; RV32IA-NEXT: # in Loop: Header=BB236_2 Depth=1 +; RV32IA-NEXT: mv a2, a4 +; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: j .LBB236_1 ; RV32IA-NEXT: .LBB236_7: # %atomicrmw.end ; RV32IA-NEXT: mv a0, a4 @@ -20184,11 +20184,11 @@ ; RV64I-NEXT: bnez a0, .LBB236_4 ; RV64I-NEXT: .LBB236_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s1, a3, .LBB236_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: bltu s1, a3, .LBB236_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB236_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB236_1 ; RV64I-NEXT: .LBB236_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -20243,13 +20243,13 @@ ; RV32I-NEXT: sltu a0, s2, a4 ; RV32I-NEXT: .LBB237_5: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB237_2 Depth=1 -; RV32I-NEXT: mv a2, a4 -; RV32I-NEXT: mv a3, a5 -; RV32I-NEXT: beqz a0, .LBB237_1 -; RV32I-NEXT: # %bb.6: # %atomicrmw.start -; RV32I-NEXT: # in Loop: Header=BB237_2 Depth=1 ; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a3, s1 +; RV32I-NEXT: bnez a0, .LBB237_1 +; RV32I-NEXT: # %bb.6: # %atomicrmw.start +; RV32I-NEXT: # in Loop: Header=BB237_2 Depth=1 +; RV32I-NEXT: mv a2, a4 +; RV32I-NEXT: mv a3, a5 ; RV32I-NEXT: j .LBB237_1 ; RV32I-NEXT: .LBB237_7: # %atomicrmw.end ; RV32I-NEXT: mv a0, a4 @@ -20297,13 +20297,13 @@ ; RV32IA-NEXT: sltu a0, s2, a4 ; RV32IA-NEXT: .LBB237_5: # %atomicrmw.start ; RV32IA-NEXT: # in Loop: Header=BB237_2 Depth=1 -; RV32IA-NEXT: mv a2, a4 -; RV32IA-NEXT: mv a3, a5 -; RV32IA-NEXT: beqz a0, .LBB237_1 -; RV32IA-NEXT: # %bb.6: # %atomicrmw.start -; RV32IA-NEXT: # in Loop: Header=BB237_2 Depth=1 ; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a3, s1 +; RV32IA-NEXT: bnez a0, .LBB237_1 +; RV32IA-NEXT: # %bb.6: # %atomicrmw.start +; RV32IA-NEXT: # in Loop: Header=BB237_2 Depth=1 +; RV32IA-NEXT: mv a2, a4 +; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: j .LBB237_1 ; RV32IA-NEXT: .LBB237_7: # %atomicrmw.end ; RV32IA-NEXT: mv a0, a4 @@ -20337,11 +20337,11 @@ ; RV64I-NEXT: bnez a0, .LBB237_4 ; RV64I-NEXT: .LBB237_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s1, a3, .LBB237_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: bltu s1, a3, .LBB237_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB237_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB237_1 ; RV64I-NEXT: .LBB237_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -20396,13 +20396,13 @@ ; RV32I-NEXT: sltu a0, s2, a4 ; RV32I-NEXT: .LBB238_5: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB238_2 Depth=1 -; RV32I-NEXT: mv a2, a4 -; RV32I-NEXT: mv a3, a5 -; RV32I-NEXT: beqz a0, .LBB238_1 -; RV32I-NEXT: # %bb.6: # %atomicrmw.start -; RV32I-NEXT: # in Loop: Header=BB238_2 Depth=1 ; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a3, s1 +; RV32I-NEXT: bnez a0, .LBB238_1 +; RV32I-NEXT: # %bb.6: # %atomicrmw.start +; RV32I-NEXT: # in Loop: Header=BB238_2 Depth=1 +; RV32I-NEXT: mv a2, a4 +; RV32I-NEXT: mv a3, a5 ; RV32I-NEXT: j .LBB238_1 ; RV32I-NEXT: .LBB238_7: # %atomicrmw.end ; RV32I-NEXT: mv a0, a4 @@ -20450,13 +20450,13 @@ ; RV32IA-NEXT: sltu a0, s2, a4 ; RV32IA-NEXT: .LBB238_5: # %atomicrmw.start ; RV32IA-NEXT: # in Loop: Header=BB238_2 Depth=1 -; RV32IA-NEXT: mv a2, a4 -; RV32IA-NEXT: mv a3, a5 -; RV32IA-NEXT: beqz a0, .LBB238_1 -; RV32IA-NEXT: # %bb.6: # %atomicrmw.start -; RV32IA-NEXT: # in Loop: Header=BB238_2 Depth=1 ; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a3, s1 +; RV32IA-NEXT: bnez a0, .LBB238_1 +; RV32IA-NEXT: # %bb.6: # %atomicrmw.start +; RV32IA-NEXT: # in Loop: Header=BB238_2 Depth=1 +; RV32IA-NEXT: mv a2, a4 +; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: j .LBB238_1 ; RV32IA-NEXT: .LBB238_7: # %atomicrmw.end ; RV32IA-NEXT: mv a0, a4 @@ -20490,11 +20490,11 @@ ; RV64I-NEXT: bnez a0, .LBB238_4 ; RV64I-NEXT: .LBB238_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s1, a3, .LBB238_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: bltu s1, a3, .LBB238_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB238_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB238_1 ; RV64I-NEXT: .LBB238_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -20549,13 +20549,13 @@ ; RV32I-NEXT: sltu a0, s2, a4 ; RV32I-NEXT: .LBB239_5: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB239_2 Depth=1 -; RV32I-NEXT: mv a2, a4 -; RV32I-NEXT: mv a3, a5 -; RV32I-NEXT: beqz a0, .LBB239_1 -; RV32I-NEXT: # %bb.6: # %atomicrmw.start -; RV32I-NEXT: # in Loop: Header=BB239_2 Depth=1 ; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a3, s1 +; RV32I-NEXT: bnez a0, .LBB239_1 +; RV32I-NEXT: # %bb.6: # %atomicrmw.start +; RV32I-NEXT: # in Loop: Header=BB239_2 Depth=1 +; RV32I-NEXT: mv a2, a4 +; RV32I-NEXT: mv a3, a5 ; RV32I-NEXT: j .LBB239_1 ; RV32I-NEXT: .LBB239_7: # %atomicrmw.end ; RV32I-NEXT: mv a0, a4 @@ -20603,13 +20603,13 @@ ; RV32IA-NEXT: sltu a0, s2, a4 ; RV32IA-NEXT: .LBB239_5: # %atomicrmw.start ; RV32IA-NEXT: # in Loop: Header=BB239_2 Depth=1 -; RV32IA-NEXT: mv a2, a4 -; RV32IA-NEXT: mv a3, a5 -; RV32IA-NEXT: beqz a0, .LBB239_1 -; RV32IA-NEXT: # %bb.6: # %atomicrmw.start -; RV32IA-NEXT: # in Loop: Header=BB239_2 Depth=1 ; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a3, s1 +; RV32IA-NEXT: bnez a0, .LBB239_1 +; RV32IA-NEXT: # %bb.6: # %atomicrmw.start +; RV32IA-NEXT: # in Loop: Header=BB239_2 Depth=1 +; RV32IA-NEXT: mv a2, a4 +; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: j .LBB239_1 ; RV32IA-NEXT: .LBB239_7: # %atomicrmw.end ; RV32IA-NEXT: mv a0, a4 @@ -20643,11 +20643,11 @@ ; RV64I-NEXT: bnez a0, .LBB239_4 ; RV64I-NEXT: .LBB239_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s1, a3, .LBB239_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: bltu s1, a3, .LBB239_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB239_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB239_1 ; RV64I-NEXT: .LBB239_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 diff --git a/llvm/test/CodeGen/RISCV/atomic-signext.ll b/llvm/test/CodeGen/RISCV/atomic-signext.ll --- a/llvm/test/CodeGen/RISCV/atomic-signext.ll +++ b/llvm/test/CodeGen/RISCV/atomic-signext.ll @@ -754,11 +754,11 @@ ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: srai a0, a0, 24 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bge s2, a0, .LBB11_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: blt s2, a0, .LBB11_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB11_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB11_1 ; RV32I-NEXT: .LBB11_4: # %atomicrmw.end ; RV32I-NEXT: slli a0, a3, 24 @@ -828,11 +828,11 @@ ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: srai a0, a0, 56 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s2, a0, .LBB11_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: blt s2, a0, .LBB11_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB11_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB11_1 ; RV64I-NEXT: .LBB11_4: # %atomicrmw.end ; RV64I-NEXT: slli a0, a3, 56 @@ -1042,11 +1042,11 @@ ; RV32I-NEXT: .LBB13_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: andi a0, a3, 255 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bgeu s2, a0, .LBB13_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: bltu s2, a0, .LBB13_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB13_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB13_1 ; RV32I-NEXT: .LBB13_4: # %atomicrmw.end ; RV32I-NEXT: slli a0, a3, 24 @@ -1109,11 +1109,11 @@ ; RV64I-NEXT: .LBB13_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: andi a0, a3, 255 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s2, a0, .LBB13_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: bltu s2, a0, .LBB13_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB13_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB13_1 ; RV64I-NEXT: .LBB13_4: # %atomicrmw.end ; RV64I-NEXT: slli a0, a3, 56 @@ -1806,11 +1806,11 @@ ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: srai a0, a0, 16 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bge s2, a0, .LBB22_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: blt s2, a0, .LBB22_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB22_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB22_1 ; RV32I-NEXT: .LBB22_4: # %atomicrmw.end ; RV32I-NEXT: slli a0, a3, 16 @@ -1882,11 +1882,11 @@ ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: srai a0, a0, 48 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s2, a0, .LBB22_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: blt s2, a0, .LBB22_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB22_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB22_1 ; RV64I-NEXT: .LBB22_4: # %atomicrmw.end ; RV64I-NEXT: slli a0, a3, 48 @@ -2111,11 +2111,11 @@ ; RV32I-NEXT: .LBB24_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: and a0, a1, s2 -; RV32I-NEXT: mv a2, a1 -; RV32I-NEXT: bgeu s3, a0, .LBB24_1 +; RV32I-NEXT: mv a2, s0 +; RV32I-NEXT: bltu s3, a0, .LBB24_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB24_2 Depth=1 -; RV32I-NEXT: mv a2, s0 +; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: j .LBB24_1 ; RV32I-NEXT: .LBB24_4: # %atomicrmw.end ; RV32I-NEXT: slli a0, a1, 16 @@ -2183,11 +2183,11 @@ ; RV64I-NEXT: .LBB24_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: and a0, a1, s2 -; RV64I-NEXT: mv a2, a1 -; RV64I-NEXT: bgeu s3, a0, .LBB24_1 +; RV64I-NEXT: mv a2, s0 +; RV64I-NEXT: bltu s3, a0, .LBB24_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB24_2 Depth=1 -; RV64I-NEXT: mv a2, s0 +; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: j .LBB24_1 ; RV64I-NEXT: .LBB24_4: # %atomicrmw.end ; RV64I-NEXT: slli a0, a1, 48 @@ -2603,11 +2603,11 @@ ; RV32I-NEXT: bnez a0, .LBB33_4 ; RV32I-NEXT: .LBB33_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bge s1, a3, .LBB33_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: blt s1, a3, .LBB33_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB33_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB33_1 ; RV32I-NEXT: .LBB33_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -2646,11 +2646,11 @@ ; RV64I-NEXT: bnez a0, .LBB33_4 ; RV64I-NEXT: .LBB33_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s2, a3, .LBB33_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: blt s2, a3, .LBB33_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB33_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB33_1 ; RV64I-NEXT: .LBB33_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -2781,11 +2781,11 @@ ; RV32I-NEXT: bnez a0, .LBB35_4 ; RV32I-NEXT: .LBB35_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bgeu s1, a3, .LBB35_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: bltu s1, a3, .LBB35_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB35_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB35_1 ; RV32I-NEXT: .LBB35_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -2824,11 +2824,11 @@ ; RV64I-NEXT: bnez a0, .LBB35_4 ; RV64I-NEXT: .LBB35_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s2, a3, .LBB35_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: bltu s2, a3, .LBB35_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB35_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB35_1 ; RV64I-NEXT: .LBB35_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -3318,13 +3318,13 @@ ; RV32I-NEXT: sltu a0, s2, a4 ; RV32I-NEXT: .LBB44_5: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB44_2 Depth=1 -; RV32I-NEXT: mv a2, a4 -; RV32I-NEXT: mv a3, a5 -; RV32I-NEXT: beqz a0, .LBB44_1 -; RV32I-NEXT: # %bb.6: # %atomicrmw.start -; RV32I-NEXT: # in Loop: Header=BB44_2 Depth=1 ; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a3, s1 +; RV32I-NEXT: bnez a0, .LBB44_1 +; RV32I-NEXT: # %bb.6: # %atomicrmw.start +; RV32I-NEXT: # in Loop: Header=BB44_2 Depth=1 +; RV32I-NEXT: mv a2, a4 +; RV32I-NEXT: mv a3, a5 ; RV32I-NEXT: j .LBB44_1 ; RV32I-NEXT: .LBB44_7: # %atomicrmw.end ; RV32I-NEXT: mv a0, a4 @@ -3372,13 +3372,13 @@ ; RV32IA-NEXT: sltu a0, s2, a4 ; RV32IA-NEXT: .LBB44_5: # %atomicrmw.start ; RV32IA-NEXT: # in Loop: Header=BB44_2 Depth=1 -; RV32IA-NEXT: mv a2, a4 -; RV32IA-NEXT: mv a3, a5 -; RV32IA-NEXT: beqz a0, .LBB44_1 -; RV32IA-NEXT: # %bb.6: # %atomicrmw.start -; RV32IA-NEXT: # in Loop: Header=BB44_2 Depth=1 ; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a3, s1 +; RV32IA-NEXT: bnez a0, .LBB44_1 +; RV32IA-NEXT: # %bb.6: # %atomicrmw.start +; RV32IA-NEXT: # in Loop: Header=BB44_2 Depth=1 +; RV32IA-NEXT: mv a2, a4 +; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: j .LBB44_1 ; RV32IA-NEXT: .LBB44_7: # %atomicrmw.end ; RV32IA-NEXT: mv a0, a4 @@ -3412,11 +3412,11 @@ ; RV64I-NEXT: bnez a0, .LBB44_4 ; RV64I-NEXT: .LBB44_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s1, a3, .LBB44_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: blt s1, a3, .LBB44_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB44_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB44_1 ; RV64I-NEXT: .LBB44_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -3624,13 +3624,13 @@ ; RV32I-NEXT: sltu a0, s2, a4 ; RV32I-NEXT: .LBB46_5: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB46_2 Depth=1 -; RV32I-NEXT: mv a2, a4 -; RV32I-NEXT: mv a3, a5 -; RV32I-NEXT: beqz a0, .LBB46_1 -; RV32I-NEXT: # %bb.6: # %atomicrmw.start -; RV32I-NEXT: # in Loop: Header=BB46_2 Depth=1 ; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a3, s1 +; RV32I-NEXT: bnez a0, .LBB46_1 +; RV32I-NEXT: # %bb.6: # %atomicrmw.start +; RV32I-NEXT: # in Loop: Header=BB46_2 Depth=1 +; RV32I-NEXT: mv a2, a4 +; RV32I-NEXT: mv a3, a5 ; RV32I-NEXT: j .LBB46_1 ; RV32I-NEXT: .LBB46_7: # %atomicrmw.end ; RV32I-NEXT: mv a0, a4 @@ -3678,13 +3678,13 @@ ; RV32IA-NEXT: sltu a0, s2, a4 ; RV32IA-NEXT: .LBB46_5: # %atomicrmw.start ; RV32IA-NEXT: # in Loop: Header=BB46_2 Depth=1 -; RV32IA-NEXT: mv a2, a4 -; RV32IA-NEXT: mv a3, a5 -; RV32IA-NEXT: beqz a0, .LBB46_1 -; RV32IA-NEXT: # %bb.6: # %atomicrmw.start -; RV32IA-NEXT: # in Loop: Header=BB46_2 Depth=1 ; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a3, s1 +; RV32IA-NEXT: bnez a0, .LBB46_1 +; RV32IA-NEXT: # %bb.6: # %atomicrmw.start +; RV32IA-NEXT: # in Loop: Header=BB46_2 Depth=1 +; RV32IA-NEXT: mv a2, a4 +; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: j .LBB46_1 ; RV32IA-NEXT: .LBB46_7: # %atomicrmw.end ; RV32IA-NEXT: mv a0, a4 @@ -3718,11 +3718,11 @@ ; RV64I-NEXT: bnez a0, .LBB46_4 ; RV64I-NEXT: .LBB46_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s1, a3, .LBB46_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: bltu s1, a3, .LBB46_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB46_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB46_1 ; RV64I-NEXT: .LBB46_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 diff --git a/llvm/test/CodeGen/RISCV/bfloat-select-icmp.ll b/llvm/test/CodeGen/RISCV/bfloat-select-icmp.ll --- a/llvm/test/CodeGen/RISCV/bfloat-select-icmp.ll +++ b/llvm/test/CodeGen/RISCV/bfloat-select-icmp.ll @@ -58,13 +58,13 @@ define bfloat @select_icmp_uge(i32 signext %a, i32 signext %b, bfloat %c, bfloat %d) { ; CHECK-LABEL: select_icmp_uge: ; CHECK: # %bb.0: -; CHECK-NEXT: bgeu a0, a1, .LBB3_2 +; CHECK-NEXT: bltu a0, a1, .LBB3_2 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: fcvt.s.bf16 fa5, fa1 +; CHECK-NEXT: fcvt.s.bf16 fa5, fa0 ; CHECK-NEXT: fcvt.bf16.s fa0, fa5 ; CHECK-NEXT: ret ; CHECK-NEXT: .LBB3_2: -; CHECK-NEXT: fcvt.s.bf16 fa5, fa0 +; CHECK-NEXT: fcvt.s.bf16 fa5, fa1 ; CHECK-NEXT: fcvt.bf16.s fa0, fa5 ; CHECK-NEXT: ret %1 = icmp uge i32 %a, %b @@ -92,13 +92,13 @@ define bfloat @select_icmp_ule(i32 signext %a, i32 signext %b, bfloat %c, bfloat %d) { ; CHECK-LABEL: select_icmp_ule: ; CHECK: # %bb.0: -; CHECK-NEXT: bgeu a1, a0, .LBB5_2 +; CHECK-NEXT: bltu a1, a0, .LBB5_2 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: fcvt.s.bf16 fa5, fa1 +; CHECK-NEXT: fcvt.s.bf16 fa5, fa0 ; CHECK-NEXT: fcvt.bf16.s fa0, fa5 ; CHECK-NEXT: ret ; CHECK-NEXT: .LBB5_2: -; CHECK-NEXT: fcvt.s.bf16 fa5, fa0 +; CHECK-NEXT: fcvt.s.bf16 fa5, fa1 ; CHECK-NEXT: fcvt.bf16.s fa0, fa5 ; CHECK-NEXT: ret %1 = icmp ule i32 %a, %b @@ -126,13 +126,13 @@ define bfloat @select_icmp_sge(i32 signext %a, i32 signext %b, bfloat %c, bfloat %d) { ; CHECK-LABEL: select_icmp_sge: ; CHECK: # %bb.0: -; CHECK-NEXT: bge a0, a1, .LBB7_2 +; CHECK-NEXT: blt a0, a1, .LBB7_2 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: fcvt.s.bf16 fa5, fa1 +; CHECK-NEXT: fcvt.s.bf16 fa5, fa0 ; CHECK-NEXT: fcvt.bf16.s fa0, fa5 ; CHECK-NEXT: ret ; CHECK-NEXT: .LBB7_2: -; CHECK-NEXT: fcvt.s.bf16 fa5, fa0 +; CHECK-NEXT: fcvt.s.bf16 fa5, fa1 ; CHECK-NEXT: fcvt.bf16.s fa0, fa5 ; CHECK-NEXT: ret %1 = icmp sge i32 %a, %b @@ -160,13 +160,13 @@ define bfloat @select_icmp_sle(i32 signext %a, i32 signext %b, bfloat %c, bfloat %d) { ; CHECK-LABEL: select_icmp_sle: ; CHECK: # %bb.0: -; CHECK-NEXT: bge a1, a0, .LBB9_2 +; CHECK-NEXT: blt a1, a0, .LBB9_2 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: fcvt.s.bf16 fa5, fa1 +; CHECK-NEXT: fcvt.s.bf16 fa5, fa0 ; CHECK-NEXT: fcvt.bf16.s fa0, fa5 ; CHECK-NEXT: ret ; CHECK-NEXT: .LBB9_2: -; CHECK-NEXT: fcvt.s.bf16 fa5, fa0 +; CHECK-NEXT: fcvt.s.bf16 fa5, fa1 ; CHECK-NEXT: fcvt.bf16.s fa0, fa5 ; CHECK-NEXT: ret %1 = icmp sle i32 %a, %b diff --git a/llvm/test/CodeGen/RISCV/compress.ll b/llvm/test/CodeGen/RISCV/compress.ll --- a/llvm/test/CodeGen/RISCV/compress.ll +++ b/llvm/test/CodeGen/RISCV/compress.ll @@ -59,26 +59,26 @@ ; RV32IC-NEXT: bltu a2, a0, 0x26 ; RV32IC-NEXT: c.mv a0, a2 ; RV32IC-NEXT: c.lw a2, 0(a1) -; RV32IC-NEXT: bgeu a0, a2, 0x2e -; RV32IC-NEXT: c.mv a0, a2 -; RV32IC-NEXT: c.lw a2, 0(a1) -; RV32IC-NEXT: bltu a0, a2, 0x36 -; RV32IC-NEXT: c.mv a0, a2 -; RV32IC-NEXT: c.lw a2, 0(a1) -; RV32IC-NEXT: bgeu a2, a0, 0x3e +; RV32IC-NEXT: bltu a0, a2, 0x2e +; RV32IC-NEXT: c.mv a2, a0 +; RV32IC-NEXT: c.lw a0, 0(a1) +; RV32IC-NEXT: bltu a2, a0, 0x36 +; RV32IC-NEXT: c.mv a2, a0 +; RV32IC-NEXT: c.lw a0, 0(a1) +; RV32IC-NEXT: bltu a0, a2, 0x3e ; RV32IC-NEXT: c.mv a0, a2 ; RV32IC-NEXT: c.lw a2, 0(a1) ; RV32IC-NEXT: blt a2, a0, 0x46 ; RV32IC-NEXT: c.mv a0, a2 ; RV32IC-NEXT: c.lw a2, 0(a1) -; RV32IC-NEXT: bge a0, a2, 0x4e -; RV32IC-NEXT: c.mv a0, a2 -; RV32IC-NEXT: c.lw a2, 0(a1) -; RV32IC-NEXT: blt a0, a2, 0x56 +; RV32IC-NEXT: blt a0, a2, 0x4e +; RV32IC-NEXT: c.mv a2, a0 +; RV32IC-NEXT: c.lw a0, 0(a1) +; RV32IC-NEXT: blt a2, a0, 0x56 +; RV32IC-NEXT: c.mv a2, a0 +; RV32IC-NEXT: c.lw a0, 0(a1) +; RV32IC-NEXT: blt a0, a2, 0x5e ; RV32IC-NEXT: c.mv a0, a2 -; RV32IC-NEXT: c.lw a1, 0(a1) -; RV32IC-NEXT: bge a1, a0, 0x5e -; RV32IC-NEXT: c.mv a0, a1 ; RV32IC-NEXT: c.jr ra %val1 = load volatile i32, ptr %b %tst1 = icmp eq i32 0, %val1 diff --git a/llvm/test/CodeGen/RISCV/condops.ll b/llvm/test/CodeGen/RISCV/condops.ll --- a/llvm/test/CodeGen/RISCV/condops.ll +++ b/llvm/test/CodeGen/RISCV/condops.ll @@ -1264,33 +1264,33 @@ ; RV32I-NEXT: beq a1, a3, .LBB24_2 ; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: slt a0, a1, a3 -; RV32I-NEXT: bnez a0, .LBB24_3 +; RV32I-NEXT: beqz a0, .LBB24_3 ; RV32I-NEXT: j .LBB24_4 ; RV32I-NEXT: .LBB24_2: ; RV32I-NEXT: sltu a0, a0, a2 -; RV32I-NEXT: beqz a0, .LBB24_4 +; RV32I-NEXT: bnez a0, .LBB24_4 ; RV32I-NEXT: .LBB24_3: -; RV32I-NEXT: mv a4, a6 -; RV32I-NEXT: mv a5, a7 +; RV32I-NEXT: mv a6, a4 +; RV32I-NEXT: mv a7, a5 ; RV32I-NEXT: .LBB24_4: -; RV32I-NEXT: mv a0, a4 -; RV32I-NEXT: mv a1, a5 +; RV32I-NEXT: mv a0, a6 +; RV32I-NEXT: mv a1, a7 ; RV32I-NEXT: ret ; ; RV64I-LABEL: setge: ; RV64I: # %bb.0: -; RV64I-NEXT: bge a0, a1, .LBB24_2 +; RV64I-NEXT: blt a0, a1, .LBB24_2 ; RV64I-NEXT: # %bb.1: -; RV64I-NEXT: mv a2, a3 +; RV64I-NEXT: mv a3, a2 ; RV64I-NEXT: .LBB24_2: -; RV64I-NEXT: mv a0, a2 +; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: ret ; ; RV64XVENTANACONDOPS-LABEL: setge: ; RV64XVENTANACONDOPS: # %bb.0: ; RV64XVENTANACONDOPS-NEXT: slt a0, a0, a1 -; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a3, a0 -; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a0 +; RV64XVENTANACONDOPS-NEXT: vt.maskcn a1, a2, a0 +; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a3, a0 ; RV64XVENTANACONDOPS-NEXT: or a0, a0, a1 ; RV64XVENTANACONDOPS-NEXT: ret ; @@ -1309,19 +1309,19 @@ ; RV32ZICOND-NEXT: sltu a0, a0, a2 ; RV32ZICOND-NEXT: czero.nez a0, a0, t0 ; RV32ZICOND-NEXT: or a1, a0, a1 -; RV32ZICOND-NEXT: czero.eqz a0, a6, a1 -; RV32ZICOND-NEXT: czero.nez a2, a4, a1 +; RV32ZICOND-NEXT: czero.nez a0, a4, a1 +; RV32ZICOND-NEXT: czero.eqz a2, a6, a1 ; RV32ZICOND-NEXT: or a0, a2, a0 -; RV32ZICOND-NEXT: czero.eqz a2, a7, a1 -; RV32ZICOND-NEXT: czero.nez a1, a5, a1 +; RV32ZICOND-NEXT: czero.nez a2, a5, a1 +; RV32ZICOND-NEXT: czero.eqz a1, a7, a1 ; RV32ZICOND-NEXT: or a1, a1, a2 ; RV32ZICOND-NEXT: ret ; ; RV64ZICOND-LABEL: setge: ; RV64ZICOND: # %bb.0: ; RV64ZICOND-NEXT: slt a0, a0, a1 -; RV64ZICOND-NEXT: czero.eqz a1, a3, a0 -; RV64ZICOND-NEXT: czero.nez a0, a2, a0 +; RV64ZICOND-NEXT: czero.nez a1, a2, a0 +; RV64ZICOND-NEXT: czero.eqz a0, a3, a0 ; RV64ZICOND-NEXT: or a0, a0, a1 ; RV64ZICOND-NEXT: ret %rc = icmp sge i64 %a, %b @@ -1406,33 +1406,33 @@ ; RV32I-NEXT: beq a1, a3, .LBB26_2 ; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: slt a0, a3, a1 -; RV32I-NEXT: bnez a0, .LBB26_3 +; RV32I-NEXT: beqz a0, .LBB26_3 ; RV32I-NEXT: j .LBB26_4 ; RV32I-NEXT: .LBB26_2: ; RV32I-NEXT: sltu a0, a2, a0 -; RV32I-NEXT: beqz a0, .LBB26_4 +; RV32I-NEXT: bnez a0, .LBB26_4 ; RV32I-NEXT: .LBB26_3: -; RV32I-NEXT: mv a4, a6 -; RV32I-NEXT: mv a5, a7 +; RV32I-NEXT: mv a6, a4 +; RV32I-NEXT: mv a7, a5 ; RV32I-NEXT: .LBB26_4: -; RV32I-NEXT: mv a0, a4 -; RV32I-NEXT: mv a1, a5 +; RV32I-NEXT: mv a0, a6 +; RV32I-NEXT: mv a1, a7 ; RV32I-NEXT: ret ; ; RV64I-LABEL: setle: ; RV64I: # %bb.0: -; RV64I-NEXT: bge a1, a0, .LBB26_2 +; RV64I-NEXT: blt a1, a0, .LBB26_2 ; RV64I-NEXT: # %bb.1: -; RV64I-NEXT: mv a2, a3 +; RV64I-NEXT: mv a3, a2 ; RV64I-NEXT: .LBB26_2: -; RV64I-NEXT: mv a0, a2 +; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: ret ; ; RV64XVENTANACONDOPS-LABEL: setle: ; RV64XVENTANACONDOPS: # %bb.0: ; RV64XVENTANACONDOPS-NEXT: slt a0, a1, a0 -; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a3, a0 -; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a0 +; RV64XVENTANACONDOPS-NEXT: vt.maskcn a1, a2, a0 +; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a3, a0 ; RV64XVENTANACONDOPS-NEXT: or a0, a0, a1 ; RV64XVENTANACONDOPS-NEXT: ret ; @@ -1451,19 +1451,19 @@ ; RV32ZICOND-NEXT: sltu a0, a2, a0 ; RV32ZICOND-NEXT: czero.nez a0, a0, t0 ; RV32ZICOND-NEXT: or a1, a0, a1 -; RV32ZICOND-NEXT: czero.eqz a0, a6, a1 -; RV32ZICOND-NEXT: czero.nez a2, a4, a1 +; RV32ZICOND-NEXT: czero.nez a0, a4, a1 +; RV32ZICOND-NEXT: czero.eqz a2, a6, a1 ; RV32ZICOND-NEXT: or a0, a2, a0 -; RV32ZICOND-NEXT: czero.eqz a2, a7, a1 -; RV32ZICOND-NEXT: czero.nez a1, a5, a1 +; RV32ZICOND-NEXT: czero.nez a2, a5, a1 +; RV32ZICOND-NEXT: czero.eqz a1, a7, a1 ; RV32ZICOND-NEXT: or a1, a1, a2 ; RV32ZICOND-NEXT: ret ; ; RV64ZICOND-LABEL: setle: ; RV64ZICOND: # %bb.0: ; RV64ZICOND-NEXT: slt a0, a1, a0 -; RV64ZICOND-NEXT: czero.eqz a1, a3, a0 -; RV64ZICOND-NEXT: czero.nez a0, a2, a0 +; RV64ZICOND-NEXT: czero.nez a1, a2, a0 +; RV64ZICOND-NEXT: czero.eqz a0, a3, a0 ; RV64ZICOND-NEXT: or a0, a0, a1 ; RV64ZICOND-NEXT: ret %rc = icmp sle i64 %a, %b @@ -1548,33 +1548,33 @@ ; RV32I-NEXT: beq a1, a3, .LBB28_2 ; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: sltu a0, a1, a3 -; RV32I-NEXT: bnez a0, .LBB28_3 +; RV32I-NEXT: beqz a0, .LBB28_3 ; RV32I-NEXT: j .LBB28_4 ; RV32I-NEXT: .LBB28_2: ; RV32I-NEXT: sltu a0, a0, a2 -; RV32I-NEXT: beqz a0, .LBB28_4 +; RV32I-NEXT: bnez a0, .LBB28_4 ; RV32I-NEXT: .LBB28_3: -; RV32I-NEXT: mv a4, a6 -; RV32I-NEXT: mv a5, a7 +; RV32I-NEXT: mv a6, a4 +; RV32I-NEXT: mv a7, a5 ; RV32I-NEXT: .LBB28_4: -; RV32I-NEXT: mv a0, a4 -; RV32I-NEXT: mv a1, a5 +; RV32I-NEXT: mv a0, a6 +; RV32I-NEXT: mv a1, a7 ; RV32I-NEXT: ret ; ; RV64I-LABEL: setuge: ; RV64I: # %bb.0: -; RV64I-NEXT: bgeu a0, a1, .LBB28_2 +; RV64I-NEXT: bltu a0, a1, .LBB28_2 ; RV64I-NEXT: # %bb.1: -; RV64I-NEXT: mv a2, a3 +; RV64I-NEXT: mv a3, a2 ; RV64I-NEXT: .LBB28_2: -; RV64I-NEXT: mv a0, a2 +; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: ret ; ; RV64XVENTANACONDOPS-LABEL: setuge: ; RV64XVENTANACONDOPS: # %bb.0: ; RV64XVENTANACONDOPS-NEXT: sltu a0, a0, a1 -; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a3, a0 -; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a0 +; RV64XVENTANACONDOPS-NEXT: vt.maskcn a1, a2, a0 +; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a3, a0 ; RV64XVENTANACONDOPS-NEXT: or a0, a0, a1 ; RV64XVENTANACONDOPS-NEXT: ret ; @@ -1593,19 +1593,19 @@ ; RV32ZICOND-NEXT: sltu a0, a0, a2 ; RV32ZICOND-NEXT: czero.nez a0, a0, t0 ; RV32ZICOND-NEXT: or a1, a0, a1 -; RV32ZICOND-NEXT: czero.eqz a0, a6, a1 -; RV32ZICOND-NEXT: czero.nez a2, a4, a1 +; RV32ZICOND-NEXT: czero.nez a0, a4, a1 +; RV32ZICOND-NEXT: czero.eqz a2, a6, a1 ; RV32ZICOND-NEXT: or a0, a2, a0 -; RV32ZICOND-NEXT: czero.eqz a2, a7, a1 -; RV32ZICOND-NEXT: czero.nez a1, a5, a1 +; RV32ZICOND-NEXT: czero.nez a2, a5, a1 +; RV32ZICOND-NEXT: czero.eqz a1, a7, a1 ; RV32ZICOND-NEXT: or a1, a1, a2 ; RV32ZICOND-NEXT: ret ; ; RV64ZICOND-LABEL: setuge: ; RV64ZICOND: # %bb.0: ; RV64ZICOND-NEXT: sltu a0, a0, a1 -; RV64ZICOND-NEXT: czero.eqz a1, a3, a0 -; RV64ZICOND-NEXT: czero.nez a0, a2, a0 +; RV64ZICOND-NEXT: czero.nez a1, a2, a0 +; RV64ZICOND-NEXT: czero.eqz a0, a3, a0 ; RV64ZICOND-NEXT: or a0, a0, a1 ; RV64ZICOND-NEXT: ret %rc = icmp uge i64 %a, %b @@ -1690,33 +1690,33 @@ ; RV32I-NEXT: beq a1, a3, .LBB30_2 ; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: sltu a0, a3, a1 -; RV32I-NEXT: bnez a0, .LBB30_3 +; RV32I-NEXT: beqz a0, .LBB30_3 ; RV32I-NEXT: j .LBB30_4 ; RV32I-NEXT: .LBB30_2: ; RV32I-NEXT: sltu a0, a2, a0 -; RV32I-NEXT: beqz a0, .LBB30_4 +; RV32I-NEXT: bnez a0, .LBB30_4 ; RV32I-NEXT: .LBB30_3: -; RV32I-NEXT: mv a4, a6 -; RV32I-NEXT: mv a5, a7 +; RV32I-NEXT: mv a6, a4 +; RV32I-NEXT: mv a7, a5 ; RV32I-NEXT: .LBB30_4: -; RV32I-NEXT: mv a0, a4 -; RV32I-NEXT: mv a1, a5 +; RV32I-NEXT: mv a0, a6 +; RV32I-NEXT: mv a1, a7 ; RV32I-NEXT: ret ; ; RV64I-LABEL: setule: ; RV64I: # %bb.0: -; RV64I-NEXT: bgeu a1, a0, .LBB30_2 +; RV64I-NEXT: bltu a1, a0, .LBB30_2 ; RV64I-NEXT: # %bb.1: -; RV64I-NEXT: mv a2, a3 +; RV64I-NEXT: mv a3, a2 ; RV64I-NEXT: .LBB30_2: -; RV64I-NEXT: mv a0, a2 +; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: ret ; ; RV64XVENTANACONDOPS-LABEL: setule: ; RV64XVENTANACONDOPS: # %bb.0: ; RV64XVENTANACONDOPS-NEXT: sltu a0, a1, a0 -; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a3, a0 -; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a0 +; RV64XVENTANACONDOPS-NEXT: vt.maskcn a1, a2, a0 +; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a3, a0 ; RV64XVENTANACONDOPS-NEXT: or a0, a0, a1 ; RV64XVENTANACONDOPS-NEXT: ret ; @@ -1735,19 +1735,19 @@ ; RV32ZICOND-NEXT: sltu a0, a2, a0 ; RV32ZICOND-NEXT: czero.nez a0, a0, t0 ; RV32ZICOND-NEXT: or a1, a0, a1 -; RV32ZICOND-NEXT: czero.eqz a0, a6, a1 -; RV32ZICOND-NEXT: czero.nez a2, a4, a1 +; RV32ZICOND-NEXT: czero.nez a0, a4, a1 +; RV32ZICOND-NEXT: czero.eqz a2, a6, a1 ; RV32ZICOND-NEXT: or a0, a2, a0 -; RV32ZICOND-NEXT: czero.eqz a2, a7, a1 -; RV32ZICOND-NEXT: czero.nez a1, a5, a1 +; RV32ZICOND-NEXT: czero.nez a2, a5, a1 +; RV32ZICOND-NEXT: czero.eqz a1, a7, a1 ; RV32ZICOND-NEXT: or a1, a1, a2 ; RV32ZICOND-NEXT: ret ; ; RV64ZICOND-LABEL: setule: ; RV64ZICOND: # %bb.0: ; RV64ZICOND-NEXT: sltu a0, a1, a0 -; RV64ZICOND-NEXT: czero.eqz a1, a3, a0 -; RV64ZICOND-NEXT: czero.nez a0, a2, a0 +; RV64ZICOND-NEXT: czero.nez a1, a2, a0 +; RV64ZICOND-NEXT: czero.eqz a0, a3, a0 ; RV64ZICOND-NEXT: or a0, a0, a1 ; RV64ZICOND-NEXT: ret %rc = icmp ule i64 %a, %b diff --git a/llvm/test/CodeGen/RISCV/double-select-icmp.ll b/llvm/test/CodeGen/RISCV/double-select-icmp.ll --- a/llvm/test/CodeGen/RISCV/double-select-icmp.ll +++ b/llvm/test/CodeGen/RISCV/double-select-icmp.ll @@ -144,29 +144,30 @@ define double @select_icmp_uge(i32 signext %a, i32 signext %b, double %c, double %d) { ; CHECK-LABEL: select_icmp_uge: ; CHECK: # %bb.0: -; CHECK-NEXT: bgeu a0, a1, .LBB3_2 +; CHECK-NEXT: bltu a0, a1, .LBB3_2 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: fmv.d fa0, fa1 +; CHECK-NEXT: fmv.d fa1, fa0 ; CHECK-NEXT: .LBB3_2: +; CHECK-NEXT: fmv.d fa0, fa1 ; CHECK-NEXT: ret ; ; RV32ZDINX-LABEL: select_icmp_uge: ; RV32ZDINX: # %bb.0: ; RV32ZDINX-NEXT: addi sp, sp, -16 ; RV32ZDINX-NEXT: .cfi_def_cfa_offset 16 -; RV32ZDINX-NEXT: sw a4, 8(sp) -; RV32ZDINX-NEXT: sw a5, 12(sp) -; RV32ZDINX-NEXT: lw a4, 8(sp) -; RV32ZDINX-NEXT: lw a5, 12(sp) ; RV32ZDINX-NEXT: sw a2, 8(sp) ; RV32ZDINX-NEXT: sw a3, 12(sp) -; RV32ZDINX-NEXT: bltu a0, a1, .LBB3_2 -; RV32ZDINX-NEXT: # %bb.1: -; RV32ZDINX-NEXT: lw a4, 8(sp) -; RV32ZDINX-NEXT: lw a5, 12(sp) -; RV32ZDINX-NEXT: .LBB3_2: +; RV32ZDINX-NEXT: lw a2, 8(sp) +; RV32ZDINX-NEXT: lw a3, 12(sp) ; RV32ZDINX-NEXT: sw a4, 8(sp) ; RV32ZDINX-NEXT: sw a5, 12(sp) +; RV32ZDINX-NEXT: bgeu a0, a1, .LBB3_2 +; RV32ZDINX-NEXT: # %bb.1: +; RV32ZDINX-NEXT: lw a2, 8(sp) +; RV32ZDINX-NEXT: lw a3, 12(sp) +; RV32ZDINX-NEXT: .LBB3_2: +; RV32ZDINX-NEXT: sw a2, 8(sp) +; RV32ZDINX-NEXT: sw a3, 12(sp) ; RV32ZDINX-NEXT: lw a0, 8(sp) ; RV32ZDINX-NEXT: lw a1, 12(sp) ; RV32ZDINX-NEXT: addi sp, sp, 16 @@ -174,11 +175,11 @@ ; ; RV64ZDINX-LABEL: select_icmp_uge: ; RV64ZDINX: # %bb.0: -; RV64ZDINX-NEXT: bgeu a0, a1, .LBB3_2 +; RV64ZDINX-NEXT: bltu a0, a1, .LBB3_2 ; RV64ZDINX-NEXT: # %bb.1: -; RV64ZDINX-NEXT: mv a2, a3 +; RV64ZDINX-NEXT: mv a3, a2 ; RV64ZDINX-NEXT: .LBB3_2: -; RV64ZDINX-NEXT: mv a0, a2 +; RV64ZDINX-NEXT: mv a0, a3 ; RV64ZDINX-NEXT: ret %1 = icmp uge i32 %a, %b %2 = select i1 %1, double %c, double %d @@ -232,29 +233,30 @@ define double @select_icmp_ule(i32 signext %a, i32 signext %b, double %c, double %d) { ; CHECK-LABEL: select_icmp_ule: ; CHECK: # %bb.0: -; CHECK-NEXT: bgeu a1, a0, .LBB5_2 +; CHECK-NEXT: bltu a1, a0, .LBB5_2 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: fmv.d fa0, fa1 +; CHECK-NEXT: fmv.d fa1, fa0 ; CHECK-NEXT: .LBB5_2: +; CHECK-NEXT: fmv.d fa0, fa1 ; CHECK-NEXT: ret ; ; RV32ZDINX-LABEL: select_icmp_ule: ; RV32ZDINX: # %bb.0: ; RV32ZDINX-NEXT: addi sp, sp, -16 ; RV32ZDINX-NEXT: .cfi_def_cfa_offset 16 -; RV32ZDINX-NEXT: sw a4, 8(sp) -; RV32ZDINX-NEXT: sw a5, 12(sp) -; RV32ZDINX-NEXT: lw a4, 8(sp) -; RV32ZDINX-NEXT: lw a5, 12(sp) ; RV32ZDINX-NEXT: sw a2, 8(sp) ; RV32ZDINX-NEXT: sw a3, 12(sp) -; RV32ZDINX-NEXT: bltu a1, a0, .LBB5_2 -; RV32ZDINX-NEXT: # %bb.1: -; RV32ZDINX-NEXT: lw a4, 8(sp) -; RV32ZDINX-NEXT: lw a5, 12(sp) -; RV32ZDINX-NEXT: .LBB5_2: +; RV32ZDINX-NEXT: lw a2, 8(sp) +; RV32ZDINX-NEXT: lw a3, 12(sp) ; RV32ZDINX-NEXT: sw a4, 8(sp) ; RV32ZDINX-NEXT: sw a5, 12(sp) +; RV32ZDINX-NEXT: bgeu a1, a0, .LBB5_2 +; RV32ZDINX-NEXT: # %bb.1: +; RV32ZDINX-NEXT: lw a2, 8(sp) +; RV32ZDINX-NEXT: lw a3, 12(sp) +; RV32ZDINX-NEXT: .LBB5_2: +; RV32ZDINX-NEXT: sw a2, 8(sp) +; RV32ZDINX-NEXT: sw a3, 12(sp) ; RV32ZDINX-NEXT: lw a0, 8(sp) ; RV32ZDINX-NEXT: lw a1, 12(sp) ; RV32ZDINX-NEXT: addi sp, sp, 16 @@ -262,11 +264,11 @@ ; ; RV64ZDINX-LABEL: select_icmp_ule: ; RV64ZDINX: # %bb.0: -; RV64ZDINX-NEXT: bgeu a1, a0, .LBB5_2 +; RV64ZDINX-NEXT: bltu a1, a0, .LBB5_2 ; RV64ZDINX-NEXT: # %bb.1: -; RV64ZDINX-NEXT: mv a2, a3 +; RV64ZDINX-NEXT: mv a3, a2 ; RV64ZDINX-NEXT: .LBB5_2: -; RV64ZDINX-NEXT: mv a0, a2 +; RV64ZDINX-NEXT: mv a0, a3 ; RV64ZDINX-NEXT: ret %1 = icmp ule i32 %a, %b %2 = select i1 %1, double %c, double %d @@ -320,29 +322,30 @@ define double @select_icmp_sge(i32 signext %a, i32 signext %b, double %c, double %d) { ; CHECK-LABEL: select_icmp_sge: ; CHECK: # %bb.0: -; CHECK-NEXT: bge a0, a1, .LBB7_2 +; CHECK-NEXT: blt a0, a1, .LBB7_2 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: fmv.d fa0, fa1 +; CHECK-NEXT: fmv.d fa1, fa0 ; CHECK-NEXT: .LBB7_2: +; CHECK-NEXT: fmv.d fa0, fa1 ; CHECK-NEXT: ret ; ; RV32ZDINX-LABEL: select_icmp_sge: ; RV32ZDINX: # %bb.0: ; RV32ZDINX-NEXT: addi sp, sp, -16 ; RV32ZDINX-NEXT: .cfi_def_cfa_offset 16 -; RV32ZDINX-NEXT: sw a4, 8(sp) -; RV32ZDINX-NEXT: sw a5, 12(sp) -; RV32ZDINX-NEXT: lw a4, 8(sp) -; RV32ZDINX-NEXT: lw a5, 12(sp) ; RV32ZDINX-NEXT: sw a2, 8(sp) ; RV32ZDINX-NEXT: sw a3, 12(sp) -; RV32ZDINX-NEXT: blt a0, a1, .LBB7_2 -; RV32ZDINX-NEXT: # %bb.1: -; RV32ZDINX-NEXT: lw a4, 8(sp) -; RV32ZDINX-NEXT: lw a5, 12(sp) -; RV32ZDINX-NEXT: .LBB7_2: +; RV32ZDINX-NEXT: lw a2, 8(sp) +; RV32ZDINX-NEXT: lw a3, 12(sp) ; RV32ZDINX-NEXT: sw a4, 8(sp) ; RV32ZDINX-NEXT: sw a5, 12(sp) +; RV32ZDINX-NEXT: bge a0, a1, .LBB7_2 +; RV32ZDINX-NEXT: # %bb.1: +; RV32ZDINX-NEXT: lw a2, 8(sp) +; RV32ZDINX-NEXT: lw a3, 12(sp) +; RV32ZDINX-NEXT: .LBB7_2: +; RV32ZDINX-NEXT: sw a2, 8(sp) +; RV32ZDINX-NEXT: sw a3, 12(sp) ; RV32ZDINX-NEXT: lw a0, 8(sp) ; RV32ZDINX-NEXT: lw a1, 12(sp) ; RV32ZDINX-NEXT: addi sp, sp, 16 @@ -350,11 +353,11 @@ ; ; RV64ZDINX-LABEL: select_icmp_sge: ; RV64ZDINX: # %bb.0: -; RV64ZDINX-NEXT: bge a0, a1, .LBB7_2 +; RV64ZDINX-NEXT: blt a0, a1, .LBB7_2 ; RV64ZDINX-NEXT: # %bb.1: -; RV64ZDINX-NEXT: mv a2, a3 +; RV64ZDINX-NEXT: mv a3, a2 ; RV64ZDINX-NEXT: .LBB7_2: -; RV64ZDINX-NEXT: mv a0, a2 +; RV64ZDINX-NEXT: mv a0, a3 ; RV64ZDINX-NEXT: ret %1 = icmp sge i32 %a, %b %2 = select i1 %1, double %c, double %d @@ -408,29 +411,30 @@ define double @select_icmp_sle(i32 signext %a, i32 signext %b, double %c, double %d) { ; CHECK-LABEL: select_icmp_sle: ; CHECK: # %bb.0: -; CHECK-NEXT: bge a1, a0, .LBB9_2 +; CHECK-NEXT: blt a1, a0, .LBB9_2 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: fmv.d fa0, fa1 +; CHECK-NEXT: fmv.d fa1, fa0 ; CHECK-NEXT: .LBB9_2: +; CHECK-NEXT: fmv.d fa0, fa1 ; CHECK-NEXT: ret ; ; RV32ZDINX-LABEL: select_icmp_sle: ; RV32ZDINX: # %bb.0: ; RV32ZDINX-NEXT: addi sp, sp, -16 ; RV32ZDINX-NEXT: .cfi_def_cfa_offset 16 -; RV32ZDINX-NEXT: sw a4, 8(sp) -; RV32ZDINX-NEXT: sw a5, 12(sp) -; RV32ZDINX-NEXT: lw a4, 8(sp) -; RV32ZDINX-NEXT: lw a5, 12(sp) ; RV32ZDINX-NEXT: sw a2, 8(sp) ; RV32ZDINX-NEXT: sw a3, 12(sp) -; RV32ZDINX-NEXT: blt a1, a0, .LBB9_2 -; RV32ZDINX-NEXT: # %bb.1: -; RV32ZDINX-NEXT: lw a4, 8(sp) -; RV32ZDINX-NEXT: lw a5, 12(sp) -; RV32ZDINX-NEXT: .LBB9_2: +; RV32ZDINX-NEXT: lw a2, 8(sp) +; RV32ZDINX-NEXT: lw a3, 12(sp) ; RV32ZDINX-NEXT: sw a4, 8(sp) ; RV32ZDINX-NEXT: sw a5, 12(sp) +; RV32ZDINX-NEXT: bge a1, a0, .LBB9_2 +; RV32ZDINX-NEXT: # %bb.1: +; RV32ZDINX-NEXT: lw a2, 8(sp) +; RV32ZDINX-NEXT: lw a3, 12(sp) +; RV32ZDINX-NEXT: .LBB9_2: +; RV32ZDINX-NEXT: sw a2, 8(sp) +; RV32ZDINX-NEXT: sw a3, 12(sp) ; RV32ZDINX-NEXT: lw a0, 8(sp) ; RV32ZDINX-NEXT: lw a1, 12(sp) ; RV32ZDINX-NEXT: addi sp, sp, 16 @@ -438,11 +442,11 @@ ; ; RV64ZDINX-LABEL: select_icmp_sle: ; RV64ZDINX: # %bb.0: -; RV64ZDINX-NEXT: bge a1, a0, .LBB9_2 +; RV64ZDINX-NEXT: blt a1, a0, .LBB9_2 ; RV64ZDINX-NEXT: # %bb.1: -; RV64ZDINX-NEXT: mv a2, a3 +; RV64ZDINX-NEXT: mv a3, a2 ; RV64ZDINX-NEXT: .LBB9_2: -; RV64ZDINX-NEXT: mv a0, a2 +; RV64ZDINX-NEXT: mv a0, a3 ; RV64ZDINX-NEXT: ret %1 = icmp sle i32 %a, %b %2 = select i1 %1, double %c, double %d diff --git a/llvm/test/CodeGen/RISCV/float-select-icmp.ll b/llvm/test/CodeGen/RISCV/float-select-icmp.ll --- a/llvm/test/CodeGen/RISCV/float-select-icmp.ll +++ b/llvm/test/CodeGen/RISCV/float-select-icmp.ll @@ -77,19 +77,20 @@ define float @select_icmp_uge(i32 signext %a, i32 signext %b, float %c, float %d) { ; CHECK-LABEL: select_icmp_uge: ; CHECK: # %bb.0: -; CHECK-NEXT: bgeu a0, a1, .LBB3_2 +; CHECK-NEXT: bltu a0, a1, .LBB3_2 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: fmv.s fa0, fa1 +; CHECK-NEXT: fmv.s fa1, fa0 ; CHECK-NEXT: .LBB3_2: +; CHECK-NEXT: fmv.s fa0, fa1 ; CHECK-NEXT: ret ; ; CHECKZFINX-LABEL: select_icmp_uge: ; CHECKZFINX: # %bb.0: -; CHECKZFINX-NEXT: bgeu a0, a1, .LBB3_2 +; CHECKZFINX-NEXT: bltu a0, a1, .LBB3_2 ; CHECKZFINX-NEXT: # %bb.1: -; CHECKZFINX-NEXT: mv a2, a3 +; CHECKZFINX-NEXT: mv a3, a2 ; CHECKZFINX-NEXT: .LBB3_2: -; CHECKZFINX-NEXT: mv a0, a2 +; CHECKZFINX-NEXT: mv a0, a3 ; CHECKZFINX-NEXT: ret %1 = icmp uge i32 %a, %b %2 = select i1 %1, float %c, float %d @@ -121,19 +122,20 @@ define float @select_icmp_ule(i32 signext %a, i32 signext %b, float %c, float %d) { ; CHECK-LABEL: select_icmp_ule: ; CHECK: # %bb.0: -; CHECK-NEXT: bgeu a1, a0, .LBB5_2 +; CHECK-NEXT: bltu a1, a0, .LBB5_2 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: fmv.s fa0, fa1 +; CHECK-NEXT: fmv.s fa1, fa0 ; CHECK-NEXT: .LBB5_2: +; CHECK-NEXT: fmv.s fa0, fa1 ; CHECK-NEXT: ret ; ; CHECKZFINX-LABEL: select_icmp_ule: ; CHECKZFINX: # %bb.0: -; CHECKZFINX-NEXT: bgeu a1, a0, .LBB5_2 +; CHECKZFINX-NEXT: bltu a1, a0, .LBB5_2 ; CHECKZFINX-NEXT: # %bb.1: -; CHECKZFINX-NEXT: mv a2, a3 +; CHECKZFINX-NEXT: mv a3, a2 ; CHECKZFINX-NEXT: .LBB5_2: -; CHECKZFINX-NEXT: mv a0, a2 +; CHECKZFINX-NEXT: mv a0, a3 ; CHECKZFINX-NEXT: ret %1 = icmp ule i32 %a, %b %2 = select i1 %1, float %c, float %d @@ -165,19 +167,20 @@ define float @select_icmp_sge(i32 signext %a, i32 signext %b, float %c, float %d) { ; CHECK-LABEL: select_icmp_sge: ; CHECK: # %bb.0: -; CHECK-NEXT: bge a0, a1, .LBB7_2 +; CHECK-NEXT: blt a0, a1, .LBB7_2 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: fmv.s fa0, fa1 +; CHECK-NEXT: fmv.s fa1, fa0 ; CHECK-NEXT: .LBB7_2: +; CHECK-NEXT: fmv.s fa0, fa1 ; CHECK-NEXT: ret ; ; CHECKZFINX-LABEL: select_icmp_sge: ; CHECKZFINX: # %bb.0: -; CHECKZFINX-NEXT: bge a0, a1, .LBB7_2 +; CHECKZFINX-NEXT: blt a0, a1, .LBB7_2 ; CHECKZFINX-NEXT: # %bb.1: -; CHECKZFINX-NEXT: mv a2, a3 +; CHECKZFINX-NEXT: mv a3, a2 ; CHECKZFINX-NEXT: .LBB7_2: -; CHECKZFINX-NEXT: mv a0, a2 +; CHECKZFINX-NEXT: mv a0, a3 ; CHECKZFINX-NEXT: ret %1 = icmp sge i32 %a, %b %2 = select i1 %1, float %c, float %d @@ -209,19 +212,20 @@ define float @select_icmp_sle(i32 signext %a, i32 signext %b, float %c, float %d) { ; CHECK-LABEL: select_icmp_sle: ; CHECK: # %bb.0: -; CHECK-NEXT: bge a1, a0, .LBB9_2 +; CHECK-NEXT: blt a1, a0, .LBB9_2 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: fmv.s fa0, fa1 +; CHECK-NEXT: fmv.s fa1, fa0 ; CHECK-NEXT: .LBB9_2: +; CHECK-NEXT: fmv.s fa0, fa1 ; CHECK-NEXT: ret ; ; CHECKZFINX-LABEL: select_icmp_sle: ; CHECKZFINX: # %bb.0: -; CHECKZFINX-NEXT: bge a1, a0, .LBB9_2 +; CHECKZFINX-NEXT: blt a1, a0, .LBB9_2 ; CHECKZFINX-NEXT: # %bb.1: -; CHECKZFINX-NEXT: mv a2, a3 +; CHECKZFINX-NEXT: mv a3, a2 ; CHECKZFINX-NEXT: .LBB9_2: -; CHECKZFINX-NEXT: mv a0, a2 +; CHECKZFINX-NEXT: mv a0, a3 ; CHECKZFINX-NEXT: ret %1 = icmp sle i32 %a, %b %2 = select i1 %1, float %c, float %d diff --git a/llvm/test/CodeGen/RISCV/forced-atomics.ll b/llvm/test/CodeGen/RISCV/forced-atomics.ll --- a/llvm/test/CodeGen/RISCV/forced-atomics.ll +++ b/llvm/test/CodeGen/RISCV/forced-atomics.ll @@ -1467,25 +1467,24 @@ ; RV32-NO-ATOMIC-NEXT: addi sp, sp, -16 ; RV32-NO-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NO-ATOMIC-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32-NO-ATOMIC-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32-NO-ATOMIC-NEXT: mv s0, a0 ; RV32-NO-ATOMIC-NEXT: lw a1, 0(a0) -; RV32-NO-ATOMIC-NEXT: li s1, 2 ; RV32-NO-ATOMIC-NEXT: j .LBB24_2 ; RV32-NO-ATOMIC-NEXT: .LBB24_1: # %atomicrmw.start ; RV32-NO-ATOMIC-NEXT: # in Loop: Header=BB24_2 Depth=1 -; RV32-NO-ATOMIC-NEXT: sw a1, 0(sp) -; RV32-NO-ATOMIC-NEXT: mv a1, sp +; RV32-NO-ATOMIC-NEXT: sw a1, 4(sp) +; RV32-NO-ATOMIC-NEXT: addi a1, sp, 4 ; RV32-NO-ATOMIC-NEXT: li a3, 5 ; RV32-NO-ATOMIC-NEXT: li a4, 5 ; RV32-NO-ATOMIC-NEXT: mv a0, s0 ; RV32-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4@plt -; RV32-NO-ATOMIC-NEXT: lw a1, 0(sp) +; RV32-NO-ATOMIC-NEXT: lw a1, 4(sp) ; RV32-NO-ATOMIC-NEXT: bnez a0, .LBB24_4 ; RV32-NO-ATOMIC-NEXT: .LBB24_2: # %atomicrmw.start ; RV32-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32-NO-ATOMIC-NEXT: li a0, 1 ; RV32-NO-ATOMIC-NEXT: mv a2, a1 -; RV32-NO-ATOMIC-NEXT: blt a1, s1, .LBB24_1 +; RV32-NO-ATOMIC-NEXT: bge a0, a1, .LBB24_1 ; RV32-NO-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start ; RV32-NO-ATOMIC-NEXT: # in Loop: Header=BB24_2 Depth=1 ; RV32-NO-ATOMIC-NEXT: li a2, 1 @@ -1494,7 +1493,6 @@ ; RV32-NO-ATOMIC-NEXT: mv a0, a1 ; RV32-NO-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NO-ATOMIC-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32-NO-ATOMIC-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV32-NO-ATOMIC-NEXT: ret ; @@ -1523,25 +1521,24 @@ ; RV64-NO-ATOMIC-NEXT: addi sp, sp, -32 ; RV64-NO-ATOMIC-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: sd s0, 16(sp) # 8-byte Folded Spill -; RV64-NO-ATOMIC-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: mv s0, a0 ; RV64-NO-ATOMIC-NEXT: lw a1, 0(a0) -; RV64-NO-ATOMIC-NEXT: li s1, 2 ; RV64-NO-ATOMIC-NEXT: j .LBB24_2 ; RV64-NO-ATOMIC-NEXT: .LBB24_1: # %atomicrmw.start ; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB24_2 Depth=1 -; RV64-NO-ATOMIC-NEXT: sw a1, 4(sp) -; RV64-NO-ATOMIC-NEXT: addi a1, sp, 4 +; RV64-NO-ATOMIC-NEXT: sw a1, 12(sp) +; RV64-NO-ATOMIC-NEXT: addi a1, sp, 12 ; RV64-NO-ATOMIC-NEXT: li a3, 5 ; RV64-NO-ATOMIC-NEXT: li a4, 5 ; RV64-NO-ATOMIC-NEXT: mv a0, s0 ; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4@plt -; RV64-NO-ATOMIC-NEXT: lw a1, 4(sp) +; RV64-NO-ATOMIC-NEXT: lw a1, 12(sp) ; RV64-NO-ATOMIC-NEXT: bnez a0, .LBB24_4 ; RV64-NO-ATOMIC-NEXT: .LBB24_2: # %atomicrmw.start ; RV64-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV64-NO-ATOMIC-NEXT: li a0, 1 ; RV64-NO-ATOMIC-NEXT: mv a2, a1 -; RV64-NO-ATOMIC-NEXT: blt a1, s1, .LBB24_1 +; RV64-NO-ATOMIC-NEXT: bge a0, a1, .LBB24_1 ; RV64-NO-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start ; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB24_2 Depth=1 ; RV64-NO-ATOMIC-NEXT: li a2, 1 @@ -1550,7 +1547,6 @@ ; RV64-NO-ATOMIC-NEXT: mv a0, a1 ; RV64-NO-ATOMIC-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: ld s0, 16(sp) # 8-byte Folded Reload -; RV64-NO-ATOMIC-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 32 ; RV64-NO-ATOMIC-NEXT: ret ; @@ -1687,25 +1683,24 @@ ; RV32-NO-ATOMIC-NEXT: addi sp, sp, -16 ; RV32-NO-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NO-ATOMIC-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32-NO-ATOMIC-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32-NO-ATOMIC-NEXT: mv s0, a0 ; RV32-NO-ATOMIC-NEXT: lw a1, 0(a0) -; RV32-NO-ATOMIC-NEXT: li s1, 2 ; RV32-NO-ATOMIC-NEXT: j .LBB26_2 ; RV32-NO-ATOMIC-NEXT: .LBB26_1: # %atomicrmw.start ; RV32-NO-ATOMIC-NEXT: # in Loop: Header=BB26_2 Depth=1 -; RV32-NO-ATOMIC-NEXT: sw a1, 0(sp) -; RV32-NO-ATOMIC-NEXT: mv a1, sp +; RV32-NO-ATOMIC-NEXT: sw a1, 4(sp) +; RV32-NO-ATOMIC-NEXT: addi a1, sp, 4 ; RV32-NO-ATOMIC-NEXT: li a3, 5 ; RV32-NO-ATOMIC-NEXT: li a4, 5 ; RV32-NO-ATOMIC-NEXT: mv a0, s0 ; RV32-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4@plt -; RV32-NO-ATOMIC-NEXT: lw a1, 0(sp) +; RV32-NO-ATOMIC-NEXT: lw a1, 4(sp) ; RV32-NO-ATOMIC-NEXT: bnez a0, .LBB26_4 ; RV32-NO-ATOMIC-NEXT: .LBB26_2: # %atomicrmw.start ; RV32-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32-NO-ATOMIC-NEXT: li a0, 1 ; RV32-NO-ATOMIC-NEXT: mv a2, a1 -; RV32-NO-ATOMIC-NEXT: bltu a1, s1, .LBB26_1 +; RV32-NO-ATOMIC-NEXT: bgeu a0, a1, .LBB26_1 ; RV32-NO-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start ; RV32-NO-ATOMIC-NEXT: # in Loop: Header=BB26_2 Depth=1 ; RV32-NO-ATOMIC-NEXT: li a2, 1 @@ -1714,7 +1709,6 @@ ; RV32-NO-ATOMIC-NEXT: mv a0, a1 ; RV32-NO-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NO-ATOMIC-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32-NO-ATOMIC-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV32-NO-ATOMIC-NEXT: ret ; @@ -1743,25 +1737,24 @@ ; RV64-NO-ATOMIC-NEXT: addi sp, sp, -32 ; RV64-NO-ATOMIC-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: sd s0, 16(sp) # 8-byte Folded Spill -; RV64-NO-ATOMIC-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: mv s0, a0 ; RV64-NO-ATOMIC-NEXT: lw a1, 0(a0) -; RV64-NO-ATOMIC-NEXT: li s1, 2 ; RV64-NO-ATOMIC-NEXT: j .LBB26_2 ; RV64-NO-ATOMIC-NEXT: .LBB26_1: # %atomicrmw.start ; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB26_2 Depth=1 -; RV64-NO-ATOMIC-NEXT: sw a1, 4(sp) -; RV64-NO-ATOMIC-NEXT: addi a1, sp, 4 +; RV64-NO-ATOMIC-NEXT: sw a1, 12(sp) +; RV64-NO-ATOMIC-NEXT: addi a1, sp, 12 ; RV64-NO-ATOMIC-NEXT: li a3, 5 ; RV64-NO-ATOMIC-NEXT: li a4, 5 ; RV64-NO-ATOMIC-NEXT: mv a0, s0 ; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4@plt -; RV64-NO-ATOMIC-NEXT: lw a1, 4(sp) +; RV64-NO-ATOMIC-NEXT: lw a1, 12(sp) ; RV64-NO-ATOMIC-NEXT: bnez a0, .LBB26_4 ; RV64-NO-ATOMIC-NEXT: .LBB26_2: # %atomicrmw.start ; RV64-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV64-NO-ATOMIC-NEXT: li a0, 1 ; RV64-NO-ATOMIC-NEXT: mv a2, a1 -; RV64-NO-ATOMIC-NEXT: bltu a1, s1, .LBB26_1 +; RV64-NO-ATOMIC-NEXT: bgeu a0, a1, .LBB26_1 ; RV64-NO-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start ; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB26_2 Depth=1 ; RV64-NO-ATOMIC-NEXT: li a2, 1 @@ -1770,7 +1763,6 @@ ; RV64-NO-ATOMIC-NEXT: mv a0, a1 ; RV64-NO-ATOMIC-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: ld s0, 16(sp) # 8-byte Folded Reload -; RV64-NO-ATOMIC-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 32 ; RV64-NO-ATOMIC-NEXT: ret ; @@ -3458,8 +3450,8 @@ ; RV32-NEXT: j .LBB50_2 ; RV32-NEXT: .LBB50_1: # %atomicrmw.start ; RV32-NEXT: # in Loop: Header=BB50_2 Depth=1 -; RV32-NEXT: neg a3, a0 -; RV32-NEXT: and a3, a3, a1 +; RV32-NEXT: addi a0, a0, -1 +; RV32-NEXT: and a3, a0, a1 ; RV32-NEXT: sw a4, 0(sp) ; RV32-NEXT: sw a1, 4(sp) ; RV32-NEXT: mv a1, sp @@ -3475,17 +3467,18 @@ ; RV32-NEXT: beqz a1, .LBB50_4 ; RV32-NEXT: # %bb.3: # %atomicrmw.start ; RV32-NEXT: # in Loop: Header=BB50_2 Depth=1 -; RV32-NEXT: slti a0, a1, 0 -; RV32-NEXT: mv a2, a4 +; RV32-NEXT: sgtz a0, a1 +; RV32-NEXT: li a2, 1 ; RV32-NEXT: bnez a0, .LBB50_1 ; RV32-NEXT: j .LBB50_5 ; RV32-NEXT: .LBB50_4: # in Loop: Header=BB50_2 Depth=1 ; RV32-NEXT: sltiu a0, a4, 2 -; RV32-NEXT: mv a2, a4 +; RV32-NEXT: xori a0, a0, 1 +; RV32-NEXT: li a2, 1 ; RV32-NEXT: bnez a0, .LBB50_1 ; RV32-NEXT: .LBB50_5: # %atomicrmw.start ; RV32-NEXT: # in Loop: Header=BB50_2 Depth=1 -; RV32-NEXT: li a2, 1 +; RV32-NEXT: mv a2, a4 ; RV32-NEXT: j .LBB50_1 ; RV32-NEXT: .LBB50_6: # %atomicrmw.end ; RV32-NEXT: mv a0, a4 @@ -3499,25 +3492,24 @@ ; RV64-NO-ATOMIC-NEXT: addi sp, sp, -32 ; RV64-NO-ATOMIC-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: sd s0, 16(sp) # 8-byte Folded Spill -; RV64-NO-ATOMIC-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: mv s0, a0 ; RV64-NO-ATOMIC-NEXT: ld a1, 0(a0) -; RV64-NO-ATOMIC-NEXT: li s1, 2 ; RV64-NO-ATOMIC-NEXT: j .LBB50_2 ; RV64-NO-ATOMIC-NEXT: .LBB50_1: # %atomicrmw.start ; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB50_2 Depth=1 -; RV64-NO-ATOMIC-NEXT: sd a1, 0(sp) -; RV64-NO-ATOMIC-NEXT: mv a1, sp +; RV64-NO-ATOMIC-NEXT: sd a1, 8(sp) +; RV64-NO-ATOMIC-NEXT: addi a1, sp, 8 ; RV64-NO-ATOMIC-NEXT: li a3, 5 ; RV64-NO-ATOMIC-NEXT: li a4, 5 ; RV64-NO-ATOMIC-NEXT: mv a0, s0 ; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_8@plt -; RV64-NO-ATOMIC-NEXT: ld a1, 0(sp) +; RV64-NO-ATOMIC-NEXT: ld a1, 8(sp) ; RV64-NO-ATOMIC-NEXT: bnez a0, .LBB50_4 ; RV64-NO-ATOMIC-NEXT: .LBB50_2: # %atomicrmw.start ; RV64-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV64-NO-ATOMIC-NEXT: li a0, 1 ; RV64-NO-ATOMIC-NEXT: mv a2, a1 -; RV64-NO-ATOMIC-NEXT: blt a1, s1, .LBB50_1 +; RV64-NO-ATOMIC-NEXT: bge a0, a1, .LBB50_1 ; RV64-NO-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start ; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB50_2 Depth=1 ; RV64-NO-ATOMIC-NEXT: li a2, 1 @@ -3526,7 +3518,6 @@ ; RV64-NO-ATOMIC-NEXT: mv a0, a1 ; RV64-NO-ATOMIC-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: ld s0, 16(sp) # 8-byte Folded Reload -; RV64-NO-ATOMIC-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 32 ; RV64-NO-ATOMIC-NEXT: ret ; @@ -3657,8 +3648,8 @@ ; RV32-NEXT: j .LBB52_2 ; RV32-NEXT: .LBB52_1: # %atomicrmw.start ; RV32-NEXT: # in Loop: Header=BB52_2 Depth=1 -; RV32-NEXT: neg a3, a0 -; RV32-NEXT: and a3, a3, a1 +; RV32-NEXT: addi a0, a0, -1 +; RV32-NEXT: and a3, a0, a1 ; RV32-NEXT: sw a4, 0(sp) ; RV32-NEXT: sw a1, 4(sp) ; RV32-NEXT: mv a1, sp @@ -3671,14 +3662,15 @@ ; RV32-NEXT: bnez a0, .LBB52_4 ; RV32-NEXT: .LBB52_2: # %atomicrmw.start ; RV32-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32-NEXT: sltiu a0, a4, 2 -; RV32-NEXT: seqz a2, a1 -; RV32-NEXT: and a0, a2, a0 -; RV32-NEXT: mv a2, a4 +; RV32-NEXT: snez a0, a1 +; RV32-NEXT: sltiu a2, a4, 2 +; RV32-NEXT: xori a2, a2, 1 +; RV32-NEXT: or a0, a2, a0 +; RV32-NEXT: li a2, 1 ; RV32-NEXT: bnez a0, .LBB52_1 ; RV32-NEXT: # %bb.3: # %atomicrmw.start ; RV32-NEXT: # in Loop: Header=BB52_2 Depth=1 -; RV32-NEXT: li a2, 1 +; RV32-NEXT: mv a2, a4 ; RV32-NEXT: j .LBB52_1 ; RV32-NEXT: .LBB52_4: # %atomicrmw.end ; RV32-NEXT: mv a0, a4 @@ -3692,25 +3684,24 @@ ; RV64-NO-ATOMIC-NEXT: addi sp, sp, -32 ; RV64-NO-ATOMIC-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: sd s0, 16(sp) # 8-byte Folded Spill -; RV64-NO-ATOMIC-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: mv s0, a0 ; RV64-NO-ATOMIC-NEXT: ld a1, 0(a0) -; RV64-NO-ATOMIC-NEXT: li s1, 2 ; RV64-NO-ATOMIC-NEXT: j .LBB52_2 ; RV64-NO-ATOMIC-NEXT: .LBB52_1: # %atomicrmw.start ; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB52_2 Depth=1 -; RV64-NO-ATOMIC-NEXT: sd a1, 0(sp) -; RV64-NO-ATOMIC-NEXT: mv a1, sp +; RV64-NO-ATOMIC-NEXT: sd a1, 8(sp) +; RV64-NO-ATOMIC-NEXT: addi a1, sp, 8 ; RV64-NO-ATOMIC-NEXT: li a3, 5 ; RV64-NO-ATOMIC-NEXT: li a4, 5 ; RV64-NO-ATOMIC-NEXT: mv a0, s0 ; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_8@plt -; RV64-NO-ATOMIC-NEXT: ld a1, 0(sp) +; RV64-NO-ATOMIC-NEXT: ld a1, 8(sp) ; RV64-NO-ATOMIC-NEXT: bnez a0, .LBB52_4 ; RV64-NO-ATOMIC-NEXT: .LBB52_2: # %atomicrmw.start ; RV64-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV64-NO-ATOMIC-NEXT: li a0, 1 ; RV64-NO-ATOMIC-NEXT: mv a2, a1 -; RV64-NO-ATOMIC-NEXT: bltu a1, s1, .LBB52_1 +; RV64-NO-ATOMIC-NEXT: bgeu a0, a1, .LBB52_1 ; RV64-NO-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start ; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB52_2 Depth=1 ; RV64-NO-ATOMIC-NEXT: li a2, 1 @@ -3719,7 +3710,6 @@ ; RV64-NO-ATOMIC-NEXT: mv a0, a1 ; RV64-NO-ATOMIC-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: ld s0, 16(sp) # 8-byte Folded Reload -; RV64-NO-ATOMIC-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 32 ; RV64-NO-ATOMIC-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/half-select-icmp.ll b/llvm/test/CodeGen/RISCV/half-select-icmp.ll --- a/llvm/test/CodeGen/RISCV/half-select-icmp.ll +++ b/llvm/test/CodeGen/RISCV/half-select-icmp.ll @@ -157,42 +157,43 @@ define half @select_icmp_uge(i32 signext %a, i32 signext %b, half %c, half %d) { ; CHECK-LABEL: select_icmp_uge: ; CHECK: # %bb.0: -; CHECK-NEXT: bgeu a0, a1, .LBB3_2 +; CHECK-NEXT: bltu a0, a1, .LBB3_2 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: fmv.h fa0, fa1 +; CHECK-NEXT: fmv.h fa1, fa0 ; CHECK-NEXT: .LBB3_2: +; CHECK-NEXT: fmv.h fa0, fa1 ; CHECK-NEXT: ret ; ; CHECKIZHINX-LABEL: select_icmp_uge: ; CHECKIZHINX: # %bb.0: -; CHECKIZHINX-NEXT: bgeu a0, a1, .LBB3_2 +; CHECKIZHINX-NEXT: bltu a0, a1, .LBB3_2 ; CHECKIZHINX-NEXT: # %bb.1: -; CHECKIZHINX-NEXT: mv a2, a3 +; CHECKIZHINX-NEXT: mv a3, a2 ; CHECKIZHINX-NEXT: .LBB3_2: -; CHECKIZHINX-NEXT: mv a0, a2 +; CHECKIZHINX-NEXT: mv a0, a3 ; CHECKIZHINX-NEXT: ret ; ; CHECKIZFHMIN-LABEL: select_icmp_uge: ; CHECKIZFHMIN: # %bb.0: -; CHECKIZFHMIN-NEXT: bgeu a0, a1, .LBB3_2 +; CHECKIZFHMIN-NEXT: bltu a0, a1, .LBB3_2 ; CHECKIZFHMIN-NEXT: # %bb.1: -; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1 +; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5 ; CHECKIZFHMIN-NEXT: ret ; CHECKIZFHMIN-NEXT: .LBB3_2: -; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0 +; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5 ; CHECKIZFHMIN-NEXT: ret ; ; CHECKIZHINXMIN-LABEL: select_icmp_uge: ; CHECKIZHINXMIN: # %bb.0: -; CHECKIZHINXMIN-NEXT: bgeu a0, a1, .LBB3_2 +; CHECKIZHINXMIN-NEXT: bltu a0, a1, .LBB3_2 ; CHECKIZHINXMIN-NEXT: # %bb.1: -; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a3 +; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a2 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0 ; CHECKIZHINXMIN-NEXT: ret ; CHECKIZHINXMIN-NEXT: .LBB3_2: -; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a2 +; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a3 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0 ; CHECKIZHINXMIN-NEXT: ret %1 = icmp uge i32 %a, %b @@ -249,42 +250,43 @@ define half @select_icmp_ule(i32 signext %a, i32 signext %b, half %c, half %d) { ; CHECK-LABEL: select_icmp_ule: ; CHECK: # %bb.0: -; CHECK-NEXT: bgeu a1, a0, .LBB5_2 +; CHECK-NEXT: bltu a1, a0, .LBB5_2 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: fmv.h fa0, fa1 +; CHECK-NEXT: fmv.h fa1, fa0 ; CHECK-NEXT: .LBB5_2: +; CHECK-NEXT: fmv.h fa0, fa1 ; CHECK-NEXT: ret ; ; CHECKIZHINX-LABEL: select_icmp_ule: ; CHECKIZHINX: # %bb.0: -; CHECKIZHINX-NEXT: bgeu a1, a0, .LBB5_2 +; CHECKIZHINX-NEXT: bltu a1, a0, .LBB5_2 ; CHECKIZHINX-NEXT: # %bb.1: -; CHECKIZHINX-NEXT: mv a2, a3 +; CHECKIZHINX-NEXT: mv a3, a2 ; CHECKIZHINX-NEXT: .LBB5_2: -; CHECKIZHINX-NEXT: mv a0, a2 +; CHECKIZHINX-NEXT: mv a0, a3 ; CHECKIZHINX-NEXT: ret ; ; CHECKIZFHMIN-LABEL: select_icmp_ule: ; CHECKIZFHMIN: # %bb.0: -; CHECKIZFHMIN-NEXT: bgeu a1, a0, .LBB5_2 +; CHECKIZFHMIN-NEXT: bltu a1, a0, .LBB5_2 ; CHECKIZFHMIN-NEXT: # %bb.1: -; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1 +; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5 ; CHECKIZFHMIN-NEXT: ret ; CHECKIZFHMIN-NEXT: .LBB5_2: -; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0 +; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5 ; CHECKIZFHMIN-NEXT: ret ; ; CHECKIZHINXMIN-LABEL: select_icmp_ule: ; CHECKIZHINXMIN: # %bb.0: -; CHECKIZHINXMIN-NEXT: bgeu a1, a0, .LBB5_2 +; CHECKIZHINXMIN-NEXT: bltu a1, a0, .LBB5_2 ; CHECKIZHINXMIN-NEXT: # %bb.1: -; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a3 +; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a2 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0 ; CHECKIZHINXMIN-NEXT: ret ; CHECKIZHINXMIN-NEXT: .LBB5_2: -; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a2 +; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a3 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0 ; CHECKIZHINXMIN-NEXT: ret %1 = icmp ule i32 %a, %b @@ -341,42 +343,43 @@ define half @select_icmp_sge(i32 signext %a, i32 signext %b, half %c, half %d) { ; CHECK-LABEL: select_icmp_sge: ; CHECK: # %bb.0: -; CHECK-NEXT: bge a0, a1, .LBB7_2 +; CHECK-NEXT: blt a0, a1, .LBB7_2 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: fmv.h fa0, fa1 +; CHECK-NEXT: fmv.h fa1, fa0 ; CHECK-NEXT: .LBB7_2: +; CHECK-NEXT: fmv.h fa0, fa1 ; CHECK-NEXT: ret ; ; CHECKIZHINX-LABEL: select_icmp_sge: ; CHECKIZHINX: # %bb.0: -; CHECKIZHINX-NEXT: bge a0, a1, .LBB7_2 +; CHECKIZHINX-NEXT: blt a0, a1, .LBB7_2 ; CHECKIZHINX-NEXT: # %bb.1: -; CHECKIZHINX-NEXT: mv a2, a3 +; CHECKIZHINX-NEXT: mv a3, a2 ; CHECKIZHINX-NEXT: .LBB7_2: -; CHECKIZHINX-NEXT: mv a0, a2 +; CHECKIZHINX-NEXT: mv a0, a3 ; CHECKIZHINX-NEXT: ret ; ; CHECKIZFHMIN-LABEL: select_icmp_sge: ; CHECKIZFHMIN: # %bb.0: -; CHECKIZFHMIN-NEXT: bge a0, a1, .LBB7_2 +; CHECKIZFHMIN-NEXT: blt a0, a1, .LBB7_2 ; CHECKIZFHMIN-NEXT: # %bb.1: -; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1 +; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5 ; CHECKIZFHMIN-NEXT: ret ; CHECKIZFHMIN-NEXT: .LBB7_2: -; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0 +; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5 ; CHECKIZFHMIN-NEXT: ret ; ; CHECKIZHINXMIN-LABEL: select_icmp_sge: ; CHECKIZHINXMIN: # %bb.0: -; CHECKIZHINXMIN-NEXT: bge a0, a1, .LBB7_2 +; CHECKIZHINXMIN-NEXT: blt a0, a1, .LBB7_2 ; CHECKIZHINXMIN-NEXT: # %bb.1: -; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a3 +; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a2 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0 ; CHECKIZHINXMIN-NEXT: ret ; CHECKIZHINXMIN-NEXT: .LBB7_2: -; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a2 +; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a3 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0 ; CHECKIZHINXMIN-NEXT: ret %1 = icmp sge i32 %a, %b @@ -433,42 +436,43 @@ define half @select_icmp_sle(i32 signext %a, i32 signext %b, half %c, half %d) { ; CHECK-LABEL: select_icmp_sle: ; CHECK: # %bb.0: -; CHECK-NEXT: bge a1, a0, .LBB9_2 +; CHECK-NEXT: blt a1, a0, .LBB9_2 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: fmv.h fa0, fa1 +; CHECK-NEXT: fmv.h fa1, fa0 ; CHECK-NEXT: .LBB9_2: +; CHECK-NEXT: fmv.h fa0, fa1 ; CHECK-NEXT: ret ; ; CHECKIZHINX-LABEL: select_icmp_sle: ; CHECKIZHINX: # %bb.0: -; CHECKIZHINX-NEXT: bge a1, a0, .LBB9_2 +; CHECKIZHINX-NEXT: blt a1, a0, .LBB9_2 ; CHECKIZHINX-NEXT: # %bb.1: -; CHECKIZHINX-NEXT: mv a2, a3 +; CHECKIZHINX-NEXT: mv a3, a2 ; CHECKIZHINX-NEXT: .LBB9_2: -; CHECKIZHINX-NEXT: mv a0, a2 +; CHECKIZHINX-NEXT: mv a0, a3 ; CHECKIZHINX-NEXT: ret ; ; CHECKIZFHMIN-LABEL: select_icmp_sle: ; CHECKIZFHMIN: # %bb.0: -; CHECKIZFHMIN-NEXT: bge a1, a0, .LBB9_2 +; CHECKIZFHMIN-NEXT: blt a1, a0, .LBB9_2 ; CHECKIZFHMIN-NEXT: # %bb.1: -; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1 +; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5 ; CHECKIZFHMIN-NEXT: ret ; CHECKIZFHMIN-NEXT: .LBB9_2: -; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0 +; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5 ; CHECKIZFHMIN-NEXT: ret ; ; CHECKIZHINXMIN-LABEL: select_icmp_sle: ; CHECKIZHINXMIN: # %bb.0: -; CHECKIZHINXMIN-NEXT: bge a1, a0, .LBB9_2 +; CHECKIZHINXMIN-NEXT: blt a1, a0, .LBB9_2 ; CHECKIZHINXMIN-NEXT: # %bb.1: -; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a3 +; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a2 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0 ; CHECKIZHINXMIN-NEXT: ret ; CHECKIZHINXMIN-NEXT: .LBB9_2: -; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a2 +; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a3 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0 ; CHECKIZHINXMIN-NEXT: ret %1 = icmp sle i32 %a, %b diff --git a/llvm/test/CodeGen/RISCV/select-cc.ll b/llvm/test/CodeGen/RISCV/select-cc.ll --- a/llvm/test/CodeGen/RISCV/select-cc.ll +++ b/llvm/test/CodeGen/RISCV/select-cc.ll @@ -23,17 +23,17 @@ ; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: .LBB0_6: ; RV32I-NEXT: lw a2, 0(a1) -; RV32I-NEXT: bgeu a0, a2, .LBB0_8 +; RV32I-NEXT: bltu a0, a2, .LBB0_8 ; RV32I-NEXT: # %bb.7: -; RV32I-NEXT: mv a0, a2 +; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: .LBB0_8: -; RV32I-NEXT: lw a2, 0(a1) -; RV32I-NEXT: bltu a0, a2, .LBB0_10 +; RV32I-NEXT: lw a0, 0(a1) +; RV32I-NEXT: bltu a2, a0, .LBB0_10 ; RV32I-NEXT: # %bb.9: -; RV32I-NEXT: mv a0, a2 +; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: .LBB0_10: -; RV32I-NEXT: lw a2, 0(a1) -; RV32I-NEXT: bgeu a2, a0, .LBB0_12 +; RV32I-NEXT: lw a0, 0(a1) +; RV32I-NEXT: bltu a0, a2, .LBB0_12 ; RV32I-NEXT: # %bb.11: ; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: .LBB0_12: @@ -43,17 +43,17 @@ ; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: .LBB0_14: ; RV32I-NEXT: lw a2, 0(a1) -; RV32I-NEXT: bge a0, a2, .LBB0_16 +; RV32I-NEXT: blt a0, a2, .LBB0_16 ; RV32I-NEXT: # %bb.15: -; RV32I-NEXT: mv a0, a2 +; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: .LBB0_16: -; RV32I-NEXT: lw a2, 0(a1) -; RV32I-NEXT: blt a0, a2, .LBB0_18 +; RV32I-NEXT: lw a0, 0(a1) +; RV32I-NEXT: blt a2, a0, .LBB0_18 ; RV32I-NEXT: # %bb.17: -; RV32I-NEXT: mv a0, a2 +; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: .LBB0_18: -; RV32I-NEXT: lw a2, 0(a1) -; RV32I-NEXT: bge a2, a0, .LBB0_20 +; RV32I-NEXT: lw a0, 0(a1) +; RV32I-NEXT: blt a0, a2, .LBB0_20 ; RV32I-NEXT: # %bb.19: ; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: .LBB0_20: @@ -99,17 +99,17 @@ ; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: .LBB0_6: ; RV64I-NEXT: lw a2, 0(a1) -; RV64I-NEXT: bgeu a0, a2, .LBB0_8 +; RV64I-NEXT: bltu a0, a2, .LBB0_8 ; RV64I-NEXT: # %bb.7: -; RV64I-NEXT: mv a0, a2 +; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: .LBB0_8: -; RV64I-NEXT: lw a2, 0(a1) -; RV64I-NEXT: bltu a0, a2, .LBB0_10 +; RV64I-NEXT: lw a0, 0(a1) +; RV64I-NEXT: bltu a2, a0, .LBB0_10 ; RV64I-NEXT: # %bb.9: -; RV64I-NEXT: mv a0, a2 +; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: .LBB0_10: -; RV64I-NEXT: lw a2, 0(a1) -; RV64I-NEXT: bgeu a2, a0, .LBB0_12 +; RV64I-NEXT: lw a0, 0(a1) +; RV64I-NEXT: bltu a0, a2, .LBB0_12 ; RV64I-NEXT: # %bb.11: ; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: .LBB0_12: @@ -119,17 +119,17 @@ ; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: .LBB0_14: ; RV64I-NEXT: lw a2, 0(a1) -; RV64I-NEXT: bge a0, a2, .LBB0_16 +; RV64I-NEXT: blt a0, a2, .LBB0_16 ; RV64I-NEXT: # %bb.15: -; RV64I-NEXT: mv a0, a2 +; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: .LBB0_16: -; RV64I-NEXT: lw a2, 0(a1) -; RV64I-NEXT: blt a0, a2, .LBB0_18 +; RV64I-NEXT: lw a0, 0(a1) +; RV64I-NEXT: blt a2, a0, .LBB0_18 ; RV64I-NEXT: # %bb.17: -; RV64I-NEXT: mv a0, a2 +; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: .LBB0_18: -; RV64I-NEXT: lw a2, 0(a1) -; RV64I-NEXT: bge a2, a0, .LBB0_20 +; RV64I-NEXT: lw a0, 0(a1) +; RV64I-NEXT: blt a0, a2, .LBB0_20 ; RV64I-NEXT: # %bb.19: ; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: .LBB0_20: @@ -277,23 +277,21 @@ ; RV32I-LABEL: select_sge_int16min: ; RV32I: # %bb.0: ; RV32I-NEXT: lui a3, 1048560 -; RV32I-NEXT: addi a3, a3, -1 -; RV32I-NEXT: blt a3, a0, .LBB2_2 +; RV32I-NEXT: blt a0, a3, .LBB2_2 ; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: mv a1, a2 +; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: .LBB2_2: -; RV32I-NEXT: mv a0, a1 +; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: ret ; ; RV64I-LABEL: select_sge_int16min: ; RV64I: # %bb.0: ; RV64I-NEXT: lui a3, 1048560 -; RV64I-NEXT: addiw a3, a3, -1 -; RV64I-NEXT: blt a3, a0, .LBB2_2 +; RV64I-NEXT: blt a0, a3, .LBB2_2 ; RV64I-NEXT: # %bb.1: -; RV64I-NEXT: mv a1, a2 +; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: .LBB2_2: -; RV64I-NEXT: mv a0, a1 +; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: ret %a = icmp sge i32 %x, -65536 %b = select i1 %a, i32 %y, i32 %z @@ -307,29 +305,28 @@ ; RV32I-NEXT: bne a1, a6, .LBB3_2 ; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: j .LBB3_3 ; RV32I-NEXT: .LBB3_2: -; RV32I-NEXT: slti a0, a1, 0 -; RV32I-NEXT: xori a0, a0, 1 +; RV32I-NEXT: slti a0, a1, -1 ; RV32I-NEXT: .LBB3_3: ; RV32I-NEXT: bnez a0, .LBB3_5 ; RV32I-NEXT: # %bb.4: -; RV32I-NEXT: mv a2, a4 -; RV32I-NEXT: mv a3, a5 +; RV32I-NEXT: mv a4, a2 +; RV32I-NEXT: mv a5, a3 ; RV32I-NEXT: .LBB3_5: -; RV32I-NEXT: mv a0, a2 -; RV32I-NEXT: mv a1, a3 +; RV32I-NEXT: mv a0, a4 +; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: ret ; ; RV64I-LABEL: select_sge_int32min: ; RV64I: # %bb.0: ; RV64I-NEXT: lui a3, 524288 -; RV64I-NEXT: addi a3, a3, -1 -; RV64I-NEXT: blt a3, a0, .LBB3_2 +; RV64I-NEXT: blt a0, a3, .LBB3_2 ; RV64I-NEXT: # %bb.1: -; RV64I-NEXT: mv a1, a2 +; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: .LBB3_2: -; RV64I-NEXT: mv a0, a1 +; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: ret %a = icmp sge i64 %x, -2147483648 %b = select i1 %a, i64 %y, i64 %z diff --git a/llvm/test/CodeGen/RISCV/select-constant-xor.ll b/llvm/test/CodeGen/RISCV/select-constant-xor.ll --- a/llvm/test/CodeGen/RISCV/select-constant-xor.ll +++ b/llvm/test/CodeGen/RISCV/select-constant-xor.ll @@ -215,11 +215,11 @@ ; RV32: # %bb.0: ; RV32-NEXT: srai a3, a0, 31 ; RV32-NEXT: xori a3, a3, 127 -; RV32-NEXT: bltz a0, .LBB10_2 +; RV32-NEXT: bgez a0, .LBB10_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: mv a2, a1 +; RV32-NEXT: mv a1, a2 ; RV32-NEXT: .LBB10_2: -; RV32-NEXT: add a0, a3, a2 +; RV32-NEXT: add a0, a3, a1 ; RV32-NEXT: ret ; ; RV64-LABEL: oneusecmp: @@ -227,11 +227,11 @@ ; RV64-NEXT: sext.w a3, a0 ; RV64-NEXT: sraiw a0, a0, 31 ; RV64-NEXT: xori a0, a0, 127 -; RV64-NEXT: bltz a3, .LBB10_2 +; RV64-NEXT: bgez a3, .LBB10_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: mv a2, a1 +; RV64-NEXT: mv a1, a2 ; RV64-NEXT: .LBB10_2: -; RV64-NEXT: addw a0, a0, a2 +; RV64-NEXT: addw a0, a0, a1 ; RV64-NEXT: ret %c = icmp sle i32 %a, -1 %s = select i1 %c, i32 -128, i32 127 diff --git a/llvm/test/CodeGen/RISCV/xaluo.ll b/llvm/test/CodeGen/RISCV/xaluo.ll --- a/llvm/test/CodeGen/RISCV/xaluo.ll +++ b/llvm/test/CodeGen/RISCV/xaluo.ll @@ -5634,7 +5634,7 @@ ; RV32-NEXT: sltu a0, a3, a0 ; RV32-NEXT: add a4, a1, a0 ; RV32-NEXT: sltu a1, a4, a1 -; RV32-NEXT: and a0, a0, a1 +; RV32-NEXT: and a0, a1, a0 ; RV32-NEXT: sw a3, 0(a2) ; RV32-NEXT: sw a4, 4(a2) ; RV32-NEXT: ret @@ -5652,7 +5652,7 @@ ; RV32ZBA-NEXT: sltu a0, a3, a0 ; RV32ZBA-NEXT: add a4, a1, a0 ; RV32ZBA-NEXT: sltu a1, a4, a1 -; RV32ZBA-NEXT: and a0, a0, a1 +; RV32ZBA-NEXT: and a0, a1, a0 ; RV32ZBA-NEXT: sw a3, 0(a2) ; RV32ZBA-NEXT: sw a4, 4(a2) ; RV32ZBA-NEXT: ret @@ -5670,7 +5670,7 @@ ; RV32ZICOND-NEXT: sltu a0, a3, a0 ; RV32ZICOND-NEXT: add a4, a1, a0 ; RV32ZICOND-NEXT: sltu a1, a4, a1 -; RV32ZICOND-NEXT: and a0, a0, a1 +; RV32ZICOND-NEXT: and a0, a1, a0 ; RV32ZICOND-NEXT: sw a3, 0(a2) ; RV32ZICOND-NEXT: sw a4, 4(a2) ; RV32ZICOND-NEXT: ret @@ -5697,7 +5697,7 @@ ; RV32-NEXT: sltu a0, a3, a0 ; RV32-NEXT: add a4, a1, a0 ; RV32-NEXT: sltu a1, a4, a1 -; RV32-NEXT: and a0, a0, a1 +; RV32-NEXT: and a0, a1, a0 ; RV32-NEXT: sw a3, 0(a2) ; RV32-NEXT: sw a4, 4(a2) ; RV32-NEXT: ret @@ -5717,7 +5717,7 @@ ; RV32ZBA-NEXT: sltu a0, a3, a0 ; RV32ZBA-NEXT: add a4, a1, a0 ; RV32ZBA-NEXT: sltu a1, a4, a1 -; RV32ZBA-NEXT: and a0, a0, a1 +; RV32ZBA-NEXT: and a0, a1, a0 ; RV32ZBA-NEXT: sw a3, 0(a2) ; RV32ZBA-NEXT: sw a4, 4(a2) ; RV32ZBA-NEXT: ret @@ -5737,7 +5737,7 @@ ; RV32ZICOND-NEXT: sltu a0, a3, a0 ; RV32ZICOND-NEXT: add a4, a1, a0 ; RV32ZICOND-NEXT: sltu a1, a4, a1 -; RV32ZICOND-NEXT: and a0, a0, a1 +; RV32ZICOND-NEXT: and a0, a1, a0 ; RV32ZICOND-NEXT: sw a3, 0(a2) ; RV32ZICOND-NEXT: sw a4, 4(a2) ; RV32ZICOND-NEXT: ret @@ -5765,7 +5765,7 @@ ; RV32-NEXT: sltu a0, a3, a0 ; RV32-NEXT: add a4, a1, a0 ; RV32-NEXT: sltu a1, a4, a1 -; RV32-NEXT: and a0, a0, a1 +; RV32-NEXT: and a0, a1, a0 ; RV32-NEXT: sw a3, 0(a2) ; RV32-NEXT: sw a4, 4(a2) ; RV32-NEXT: ret @@ -5785,7 +5785,7 @@ ; RV32ZBA-NEXT: sltu a0, a3, a0 ; RV32ZBA-NEXT: add a4, a1, a0 ; RV32ZBA-NEXT: sltu a1, a4, a1 -; RV32ZBA-NEXT: and a0, a0, a1 +; RV32ZBA-NEXT: and a0, a1, a0 ; RV32ZBA-NEXT: sw a3, 0(a2) ; RV32ZBA-NEXT: sw a4, 4(a2) ; RV32ZBA-NEXT: ret @@ -5805,7 +5805,7 @@ ; RV32ZICOND-NEXT: sltu a0, a3, a0 ; RV32ZICOND-NEXT: add a4, a1, a0 ; RV32ZICOND-NEXT: sltu a1, a4, a1 -; RV32ZICOND-NEXT: and a0, a0, a1 +; RV32ZICOND-NEXT: and a0, a1, a0 ; RV32ZICOND-NEXT: sw a3, 0(a2) ; RV32ZICOND-NEXT: sw a4, 4(a2) ; RV32ZICOND-NEXT: ret @@ -5834,7 +5834,7 @@ ; RV32-NEXT: sltu a3, a0, a1 ; RV32-NEXT: add a1, a2, a3 ; RV32-NEXT: sltu a2, a1, a2 -; RV32-NEXT: and a2, a3, a2 +; RV32-NEXT: and a2, a2, a3 ; RV32-NEXT: bnez a2, .LBB69_2 ; RV32-NEXT: # %bb.1: # %IfOverflow ; RV32-NEXT: li a0, 0 @@ -5860,7 +5860,7 @@ ; RV32ZBA-NEXT: sltu a3, a0, a1 ; RV32ZBA-NEXT: add a1, a2, a3 ; RV32ZBA-NEXT: sltu a2, a1, a2 -; RV32ZBA-NEXT: and a2, a3, a2 +; RV32ZBA-NEXT: and a2, a2, a3 ; RV32ZBA-NEXT: bnez a2, .LBB69_2 ; RV32ZBA-NEXT: # %bb.1: # %IfOverflow ; RV32ZBA-NEXT: li a0, 0 @@ -5886,7 +5886,7 @@ ; RV32ZICOND-NEXT: sltu a3, a0, a1 ; RV32ZICOND-NEXT: add a1, a2, a3 ; RV32ZICOND-NEXT: sltu a2, a1, a2 -; RV32ZICOND-NEXT: and a2, a3, a2 +; RV32ZICOND-NEXT: and a2, a2, a3 ; RV32ZICOND-NEXT: bnez a2, .LBB69_2 ; RV32ZICOND-NEXT: # %bb.1: # %IfOverflow ; RV32ZICOND-NEXT: li a0, 0