Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp =================================================================== --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -12294,13 +12294,38 @@ return DAG.getNode(TrueVal.getOpcode(), DL, VT, FalseVal, NewSel); } +static bool setCCWillBeInvertedWhenLegalized(SDValue V) { + assert(V.getOpcode() == ISD::SETCC && "Unexpected opcode."); + ISD::CondCode CCVal = cast(V.getOperand(2))->get(); + return V.getOperand(0).getValueType().isInteger() && + (CCVal == ISD::SETGE || CCVal == ISD::SETLE || CCVal == ISD::SETUGE || + CCVal == ISD::SETULE); +} + static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget) { if (Subtarget.hasShortForwardBranchOpt()) return SDValue(); + SDValue CondVal = N->getOperand(0); SDValue TrueVal = N->getOperand(1); SDValue FalseVal = N->getOperand(2); + // If CondVal is a setcc that will be inverted when legalized, take + // advantage of the freedom to swap TrueVal and FalseVal and convert the + // setcc to one that is natively supported. + if (CondVal.getOpcode() == ISD::SETCC && + setCCWillBeInvertedWhenLegalized(CondVal)) { + SDLoc DL(N); + EVT VT = N->getValueType(0); + ISD::CondCode NewCCVal = + ISD::getSetCCInverse(cast(CondVal.getOperand(2))->get(), + CondVal.getOperand(0).getValueType()); + return DAG.getSelect(DL, VT, + DAG.getSetCC(DL, CondVal.getValueType(), + CondVal.getOperand(0), + CondVal.getOperand(1), NewCCVal), + FalseVal, TrueVal); + } if (SDValue V = tryFoldSelectIntoOp(N, DAG, TrueVal, FalseVal, /*Swapped*/false)) return V; return tryFoldSelectIntoOp(N, DAG, FalseVal, TrueVal, /*Swapped*/true); Index: llvm/test/CodeGen/RISCV/atomic-rmw.ll =================================================================== --- llvm/test/CodeGen/RISCV/atomic-rmw.ll +++ llvm/test/CodeGen/RISCV/atomic-rmw.ll @@ -2760,11 +2760,11 @@ ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: srai a0, a0, 24 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bge s2, a0, .LBB40_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: blt s2, a0, .LBB40_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB40_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB40_1 ; RV32I-NEXT: .LBB40_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -2831,11 +2831,11 @@ ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: srai a0, a0, 56 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s2, a0, .LBB40_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: blt s2, a0, .LBB40_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB40_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB40_1 ; RV64I-NEXT: .LBB40_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -2906,11 +2906,11 @@ ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: srai a0, a0, 24 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bge s2, a0, .LBB41_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: blt s2, a0, .LBB41_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB41_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB41_1 ; RV32I-NEXT: .LBB41_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -2977,11 +2977,11 @@ ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: srai a0, a0, 56 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s2, a0, .LBB41_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: blt s2, a0, .LBB41_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB41_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB41_1 ; RV64I-NEXT: .LBB41_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -3052,11 +3052,11 @@ ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: srai a0, a0, 24 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bge s2, a0, .LBB42_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: blt s2, a0, .LBB42_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB42_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB42_1 ; RV32I-NEXT: .LBB42_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -3123,11 +3123,11 @@ ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: srai a0, a0, 56 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s2, a0, .LBB42_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: blt s2, a0, .LBB42_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB42_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB42_1 ; RV64I-NEXT: .LBB42_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -3198,11 +3198,11 @@ ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: srai a0, a0, 24 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bge s2, a0, .LBB43_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: blt s2, a0, .LBB43_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB43_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB43_1 ; RV32I-NEXT: .LBB43_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -3269,11 +3269,11 @@ ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: srai a0, a0, 56 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s2, a0, .LBB43_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: blt s2, a0, .LBB43_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB43_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB43_1 ; RV64I-NEXT: .LBB43_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -3344,11 +3344,11 @@ ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: srai a0, a0, 24 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bge s2, a0, .LBB44_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: blt s2, a0, .LBB44_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB44_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB44_1 ; RV32I-NEXT: .LBB44_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -3415,11 +3415,11 @@ ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: srai a0, a0, 56 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s2, a0, .LBB44_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: blt s2, a0, .LBB44_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB44_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB44_1 ; RV64I-NEXT: .LBB44_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -4148,11 +4148,11 @@ ; RV32I-NEXT: .LBB50_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: andi a0, a3, 255 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bgeu s2, a0, .LBB50_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: bltu s2, a0, .LBB50_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB50_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB50_1 ; RV32I-NEXT: .LBB50_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -4212,11 +4212,11 @@ ; RV64I-NEXT: .LBB50_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: andi a0, a3, 255 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s2, a0, .LBB50_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: bltu s2, a0, .LBB50_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB50_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB50_1 ; RV64I-NEXT: .LBB50_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -4280,11 +4280,11 @@ ; RV32I-NEXT: .LBB51_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: andi a0, a3, 255 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bgeu s2, a0, .LBB51_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: bltu s2, a0, .LBB51_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB51_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB51_1 ; RV32I-NEXT: .LBB51_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -4344,11 +4344,11 @@ ; RV64I-NEXT: .LBB51_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: andi a0, a3, 255 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s2, a0, .LBB51_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: bltu s2, a0, .LBB51_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB51_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB51_1 ; RV64I-NEXT: .LBB51_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -4412,11 +4412,11 @@ ; RV32I-NEXT: .LBB52_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: andi a0, a3, 255 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bgeu s2, a0, .LBB52_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: bltu s2, a0, .LBB52_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB52_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB52_1 ; RV32I-NEXT: .LBB52_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -4476,11 +4476,11 @@ ; RV64I-NEXT: .LBB52_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: andi a0, a3, 255 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s2, a0, .LBB52_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: bltu s2, a0, .LBB52_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB52_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB52_1 ; RV64I-NEXT: .LBB52_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -4544,11 +4544,11 @@ ; RV32I-NEXT: .LBB53_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: andi a0, a3, 255 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bgeu s2, a0, .LBB53_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: bltu s2, a0, .LBB53_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB53_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB53_1 ; RV32I-NEXT: .LBB53_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -4608,11 +4608,11 @@ ; RV64I-NEXT: .LBB53_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: andi a0, a3, 255 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s2, a0, .LBB53_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: bltu s2, a0, .LBB53_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB53_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB53_1 ; RV64I-NEXT: .LBB53_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -4676,11 +4676,11 @@ ; RV32I-NEXT: .LBB54_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: andi a0, a3, 255 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bgeu s2, a0, .LBB54_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: bltu s2, a0, .LBB54_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB54_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB54_1 ; RV32I-NEXT: .LBB54_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -4740,11 +4740,11 @@ ; RV64I-NEXT: .LBB54_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: andi a0, a3, 255 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s2, a0, .LBB54_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: bltu s2, a0, .LBB54_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB54_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB54_1 ; RV64I-NEXT: .LBB54_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -7620,11 +7620,11 @@ ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: srai a0, a0, 16 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bge s2, a0, .LBB95_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: blt s2, a0, .LBB95_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB95_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB95_1 ; RV32I-NEXT: .LBB95_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -7693,11 +7693,11 @@ ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: srai a0, a0, 48 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s2, a0, .LBB95_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: blt s2, a0, .LBB95_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB95_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB95_1 ; RV64I-NEXT: .LBB95_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -7770,11 +7770,11 @@ ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: srai a0, a0, 16 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bge s2, a0, .LBB96_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: blt s2, a0, .LBB96_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB96_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB96_1 ; RV32I-NEXT: .LBB96_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -7843,11 +7843,11 @@ ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: srai a0, a0, 48 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s2, a0, .LBB96_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: blt s2, a0, .LBB96_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB96_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB96_1 ; RV64I-NEXT: .LBB96_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -7920,11 +7920,11 @@ ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: srai a0, a0, 16 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bge s2, a0, .LBB97_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: blt s2, a0, .LBB97_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB97_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB97_1 ; RV32I-NEXT: .LBB97_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -7993,11 +7993,11 @@ ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: srai a0, a0, 48 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s2, a0, .LBB97_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: blt s2, a0, .LBB97_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB97_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB97_1 ; RV64I-NEXT: .LBB97_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -8070,11 +8070,11 @@ ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: srai a0, a0, 16 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bge s2, a0, .LBB98_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: blt s2, a0, .LBB98_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB98_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB98_1 ; RV32I-NEXT: .LBB98_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -8143,11 +8143,11 @@ ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: srai a0, a0, 48 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s2, a0, .LBB98_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: blt s2, a0, .LBB98_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB98_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB98_1 ; RV64I-NEXT: .LBB98_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -8220,11 +8220,11 @@ ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: srai a0, a0, 16 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bge s2, a0, .LBB99_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: blt s2, a0, .LBB99_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB99_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB99_1 ; RV32I-NEXT: .LBB99_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -8293,11 +8293,11 @@ ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: srai a0, a0, 48 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s2, a0, .LBB99_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: blt s2, a0, .LBB99_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB99_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB99_1 ; RV64I-NEXT: .LBB99_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -9081,11 +9081,11 @@ ; RV32I-NEXT: .LBB105_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: and a0, a1, s2 -; RV32I-NEXT: mv a2, a1 -; RV32I-NEXT: bgeu s3, a0, .LBB105_1 +; RV32I-NEXT: mv a2, s0 +; RV32I-NEXT: bltu s3, a0, .LBB105_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB105_2 Depth=1 -; RV32I-NEXT: mv a2, s0 +; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: j .LBB105_1 ; RV32I-NEXT: .LBB105_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a1 @@ -9150,11 +9150,11 @@ ; RV64I-NEXT: .LBB105_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: and a0, a1, s2 -; RV64I-NEXT: mv a2, a1 -; RV64I-NEXT: bgeu s3, a0, .LBB105_1 +; RV64I-NEXT: mv a2, s0 +; RV64I-NEXT: bltu s3, a0, .LBB105_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB105_2 Depth=1 -; RV64I-NEXT: mv a2, s0 +; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: j .LBB105_1 ; RV64I-NEXT: .LBB105_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a1 @@ -9223,11 +9223,11 @@ ; RV32I-NEXT: .LBB106_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: and a0, a1, s2 -; RV32I-NEXT: mv a2, a1 -; RV32I-NEXT: bgeu s3, a0, .LBB106_1 +; RV32I-NEXT: mv a2, s0 +; RV32I-NEXT: bltu s3, a0, .LBB106_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB106_2 Depth=1 -; RV32I-NEXT: mv a2, s0 +; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: j .LBB106_1 ; RV32I-NEXT: .LBB106_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a1 @@ -9292,11 +9292,11 @@ ; RV64I-NEXT: .LBB106_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: and a0, a1, s2 -; RV64I-NEXT: mv a2, a1 -; RV64I-NEXT: bgeu s3, a0, .LBB106_1 +; RV64I-NEXT: mv a2, s0 +; RV64I-NEXT: bltu s3, a0, .LBB106_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB106_2 Depth=1 -; RV64I-NEXT: mv a2, s0 +; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: j .LBB106_1 ; RV64I-NEXT: .LBB106_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a1 @@ -9365,11 +9365,11 @@ ; RV32I-NEXT: .LBB107_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: and a0, a1, s2 -; RV32I-NEXT: mv a2, a1 -; RV32I-NEXT: bgeu s3, a0, .LBB107_1 +; RV32I-NEXT: mv a2, s0 +; RV32I-NEXT: bltu s3, a0, .LBB107_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB107_2 Depth=1 -; RV32I-NEXT: mv a2, s0 +; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: j .LBB107_1 ; RV32I-NEXT: .LBB107_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a1 @@ -9434,11 +9434,11 @@ ; RV64I-NEXT: .LBB107_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: and a0, a1, s2 -; RV64I-NEXT: mv a2, a1 -; RV64I-NEXT: bgeu s3, a0, .LBB107_1 +; RV64I-NEXT: mv a2, s0 +; RV64I-NEXT: bltu s3, a0, .LBB107_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB107_2 Depth=1 -; RV64I-NEXT: mv a2, s0 +; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: j .LBB107_1 ; RV64I-NEXT: .LBB107_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a1 @@ -9507,11 +9507,11 @@ ; RV32I-NEXT: .LBB108_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: and a0, a1, s2 -; RV32I-NEXT: mv a2, a1 -; RV32I-NEXT: bgeu s3, a0, .LBB108_1 +; RV32I-NEXT: mv a2, s0 +; RV32I-NEXT: bltu s3, a0, .LBB108_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB108_2 Depth=1 -; RV32I-NEXT: mv a2, s0 +; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: j .LBB108_1 ; RV32I-NEXT: .LBB108_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a1 @@ -9576,11 +9576,11 @@ ; RV64I-NEXT: .LBB108_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: and a0, a1, s2 -; RV64I-NEXT: mv a2, a1 -; RV64I-NEXT: bgeu s3, a0, .LBB108_1 +; RV64I-NEXT: mv a2, s0 +; RV64I-NEXT: bltu s3, a0, .LBB108_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB108_2 Depth=1 -; RV64I-NEXT: mv a2, s0 +; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: j .LBB108_1 ; RV64I-NEXT: .LBB108_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a1 @@ -9649,11 +9649,11 @@ ; RV32I-NEXT: .LBB109_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: and a0, a1, s2 -; RV32I-NEXT: mv a2, a1 -; RV32I-NEXT: bgeu s3, a0, .LBB109_1 +; RV32I-NEXT: mv a2, s0 +; RV32I-NEXT: bltu s3, a0, .LBB109_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB109_2 Depth=1 -; RV32I-NEXT: mv a2, s0 +; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: j .LBB109_1 ; RV32I-NEXT: .LBB109_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a1 @@ -9718,11 +9718,11 @@ ; RV64I-NEXT: .LBB109_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: and a0, a1, s2 -; RV64I-NEXT: mv a2, a1 -; RV64I-NEXT: bgeu s3, a0, .LBB109_1 +; RV64I-NEXT: mv a2, s0 +; RV64I-NEXT: bltu s3, a0, .LBB109_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB109_2 Depth=1 -; RV64I-NEXT: mv a2, s0 +; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: j .LBB109_1 ; RV64I-NEXT: .LBB109_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a1 @@ -11500,11 +11500,11 @@ ; RV32I-NEXT: bnez a0, .LBB150_4 ; RV32I-NEXT: .LBB150_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bge s1, a3, .LBB150_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: blt s1, a3, .LBB150_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB150_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB150_1 ; RV32I-NEXT: .LBB150_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -11543,11 +11543,11 @@ ; RV64I-NEXT: bnez a0, .LBB150_4 ; RV64I-NEXT: .LBB150_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s2, a3, .LBB150_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: blt s2, a3, .LBB150_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB150_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB150_1 ; RV64I-NEXT: .LBB150_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -11589,11 +11589,11 @@ ; RV32I-NEXT: bnez a0, .LBB151_4 ; RV32I-NEXT: .LBB151_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bge s1, a3, .LBB151_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: blt s1, a3, .LBB151_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB151_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB151_1 ; RV32I-NEXT: .LBB151_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -11632,11 +11632,11 @@ ; RV64I-NEXT: bnez a0, .LBB151_4 ; RV64I-NEXT: .LBB151_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s2, a3, .LBB151_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: blt s2, a3, .LBB151_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB151_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB151_1 ; RV64I-NEXT: .LBB151_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -11678,11 +11678,11 @@ ; RV32I-NEXT: bnez a0, .LBB152_4 ; RV32I-NEXT: .LBB152_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bge s1, a3, .LBB152_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: blt s1, a3, .LBB152_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB152_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB152_1 ; RV32I-NEXT: .LBB152_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -11721,11 +11721,11 @@ ; RV64I-NEXT: bnez a0, .LBB152_4 ; RV64I-NEXT: .LBB152_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s2, a3, .LBB152_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: blt s2, a3, .LBB152_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB152_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB152_1 ; RV64I-NEXT: .LBB152_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -11767,11 +11767,11 @@ ; RV32I-NEXT: bnez a0, .LBB153_4 ; RV32I-NEXT: .LBB153_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bge s1, a3, .LBB153_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: blt s1, a3, .LBB153_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB153_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB153_1 ; RV32I-NEXT: .LBB153_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -11810,11 +11810,11 @@ ; RV64I-NEXT: bnez a0, .LBB153_4 ; RV64I-NEXT: .LBB153_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s2, a3, .LBB153_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: blt s2, a3, .LBB153_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB153_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB153_1 ; RV64I-NEXT: .LBB153_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -11856,11 +11856,11 @@ ; RV32I-NEXT: bnez a0, .LBB154_4 ; RV32I-NEXT: .LBB154_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bge s1, a3, .LBB154_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: blt s1, a3, .LBB154_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB154_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB154_1 ; RV32I-NEXT: .LBB154_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -11899,11 +11899,11 @@ ; RV64I-NEXT: bnez a0, .LBB154_4 ; RV64I-NEXT: .LBB154_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s2, a3, .LBB154_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: blt s2, a3, .LBB154_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB154_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB154_1 ; RV64I-NEXT: .LBB154_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -12390,11 +12390,11 @@ ; RV32I-NEXT: bnez a0, .LBB160_4 ; RV32I-NEXT: .LBB160_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bgeu s1, a3, .LBB160_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: bltu s1, a3, .LBB160_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB160_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB160_1 ; RV32I-NEXT: .LBB160_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -12433,11 +12433,11 @@ ; RV64I-NEXT: bnez a0, .LBB160_4 ; RV64I-NEXT: .LBB160_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s2, a3, .LBB160_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: bltu s2, a3, .LBB160_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB160_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB160_1 ; RV64I-NEXT: .LBB160_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -12479,11 +12479,11 @@ ; RV32I-NEXT: bnez a0, .LBB161_4 ; RV32I-NEXT: .LBB161_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bgeu s1, a3, .LBB161_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: bltu s1, a3, .LBB161_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB161_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB161_1 ; RV32I-NEXT: .LBB161_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -12522,11 +12522,11 @@ ; RV64I-NEXT: bnez a0, .LBB161_4 ; RV64I-NEXT: .LBB161_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s2, a3, .LBB161_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: bltu s2, a3, .LBB161_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB161_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB161_1 ; RV64I-NEXT: .LBB161_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -12568,11 +12568,11 @@ ; RV32I-NEXT: bnez a0, .LBB162_4 ; RV32I-NEXT: .LBB162_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bgeu s1, a3, .LBB162_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: bltu s1, a3, .LBB162_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB162_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB162_1 ; RV32I-NEXT: .LBB162_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -12611,11 +12611,11 @@ ; RV64I-NEXT: bnez a0, .LBB162_4 ; RV64I-NEXT: .LBB162_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s2, a3, .LBB162_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: bltu s2, a3, .LBB162_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB162_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB162_1 ; RV64I-NEXT: .LBB162_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -12657,11 +12657,11 @@ ; RV32I-NEXT: bnez a0, .LBB163_4 ; RV32I-NEXT: .LBB163_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bgeu s1, a3, .LBB163_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: bltu s1, a3, .LBB163_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB163_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB163_1 ; RV32I-NEXT: .LBB163_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -12700,11 +12700,11 @@ ; RV64I-NEXT: bnez a0, .LBB163_4 ; RV64I-NEXT: .LBB163_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s2, a3, .LBB163_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: bltu s2, a3, .LBB163_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB163_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB163_1 ; RV64I-NEXT: .LBB163_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -12746,11 +12746,11 @@ ; RV32I-NEXT: bnez a0, .LBB164_4 ; RV32I-NEXT: .LBB164_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bgeu s1, a3, .LBB164_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: bltu s1, a3, .LBB164_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB164_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB164_1 ; RV32I-NEXT: .LBB164_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -12789,11 +12789,11 @@ ; RV64I-NEXT: bnez a0, .LBB164_4 ; RV64I-NEXT: .LBB164_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s2, a3, .LBB164_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: bltu s2, a3, .LBB164_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB164_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB164_1 ; RV64I-NEXT: .LBB164_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -15019,14 +15019,13 @@ ; RV32I-NEXT: sltu a0, s2, a4 ; RV32I-NEXT: .LBB205_5: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB205_2 Depth=1 -; RV32I-NEXT: xori a0, a0, 1 -; RV32I-NEXT: mv a2, a4 -; RV32I-NEXT: mv a3, a5 +; RV32I-NEXT: mv a2, s2 +; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: bnez a0, .LBB205_1 ; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB205_2 Depth=1 -; RV32I-NEXT: mv a2, s2 -; RV32I-NEXT: mv a3, s1 +; RV32I-NEXT: mv a2, a4 +; RV32I-NEXT: mv a3, a5 ; RV32I-NEXT: j .LBB205_1 ; RV32I-NEXT: .LBB205_7: # %atomicrmw.end ; RV32I-NEXT: mv a0, a4 @@ -15074,14 +15073,13 @@ ; RV32IA-NEXT: sltu a0, s2, a4 ; RV32IA-NEXT: .LBB205_5: # %atomicrmw.start ; RV32IA-NEXT: # in Loop: Header=BB205_2 Depth=1 -; RV32IA-NEXT: xori a0, a0, 1 -; RV32IA-NEXT: mv a2, a4 -; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: mv a2, s2 +; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: bnez a0, .LBB205_1 ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # in Loop: Header=BB205_2 Depth=1 -; RV32IA-NEXT: mv a2, s2 -; RV32IA-NEXT: mv a3, s1 +; RV32IA-NEXT: mv a2, a4 +; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: j .LBB205_1 ; RV32IA-NEXT: .LBB205_7: # %atomicrmw.end ; RV32IA-NEXT: mv a0, a4 @@ -15115,11 +15113,11 @@ ; RV64I-NEXT: bnez a0, .LBB205_4 ; RV64I-NEXT: .LBB205_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s1, a3, .LBB205_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: blt s1, a3, .LBB205_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB205_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB205_1 ; RV64I-NEXT: .LBB205_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -15174,14 +15172,13 @@ ; RV32I-NEXT: sltu a0, s2, a4 ; RV32I-NEXT: .LBB206_5: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB206_2 Depth=1 -; RV32I-NEXT: xori a0, a0, 1 -; RV32I-NEXT: mv a2, a4 -; RV32I-NEXT: mv a3, a5 +; RV32I-NEXT: mv a2, s2 +; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: bnez a0, .LBB206_1 ; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB206_2 Depth=1 -; RV32I-NEXT: mv a2, s2 -; RV32I-NEXT: mv a3, s1 +; RV32I-NEXT: mv a2, a4 +; RV32I-NEXT: mv a3, a5 ; RV32I-NEXT: j .LBB206_1 ; RV32I-NEXT: .LBB206_7: # %atomicrmw.end ; RV32I-NEXT: mv a0, a4 @@ -15229,14 +15226,13 @@ ; RV32IA-NEXT: sltu a0, s2, a4 ; RV32IA-NEXT: .LBB206_5: # %atomicrmw.start ; RV32IA-NEXT: # in Loop: Header=BB206_2 Depth=1 -; RV32IA-NEXT: xori a0, a0, 1 -; RV32IA-NEXT: mv a2, a4 -; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: mv a2, s2 +; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: bnez a0, .LBB206_1 ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # in Loop: Header=BB206_2 Depth=1 -; RV32IA-NEXT: mv a2, s2 -; RV32IA-NEXT: mv a3, s1 +; RV32IA-NEXT: mv a2, a4 +; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: j .LBB206_1 ; RV32IA-NEXT: .LBB206_7: # %atomicrmw.end ; RV32IA-NEXT: mv a0, a4 @@ -15270,11 +15266,11 @@ ; RV64I-NEXT: bnez a0, .LBB206_4 ; RV64I-NEXT: .LBB206_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s1, a3, .LBB206_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: blt s1, a3, .LBB206_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB206_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB206_1 ; RV64I-NEXT: .LBB206_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -15329,14 +15325,13 @@ ; RV32I-NEXT: sltu a0, s2, a4 ; RV32I-NEXT: .LBB207_5: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB207_2 Depth=1 -; RV32I-NEXT: xori a0, a0, 1 -; RV32I-NEXT: mv a2, a4 -; RV32I-NEXT: mv a3, a5 +; RV32I-NEXT: mv a2, s2 +; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: bnez a0, .LBB207_1 ; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB207_2 Depth=1 -; RV32I-NEXT: mv a2, s2 -; RV32I-NEXT: mv a3, s1 +; RV32I-NEXT: mv a2, a4 +; RV32I-NEXT: mv a3, a5 ; RV32I-NEXT: j .LBB207_1 ; RV32I-NEXT: .LBB207_7: # %atomicrmw.end ; RV32I-NEXT: mv a0, a4 @@ -15384,14 +15379,13 @@ ; RV32IA-NEXT: sltu a0, s2, a4 ; RV32IA-NEXT: .LBB207_5: # %atomicrmw.start ; RV32IA-NEXT: # in Loop: Header=BB207_2 Depth=1 -; RV32IA-NEXT: xori a0, a0, 1 -; RV32IA-NEXT: mv a2, a4 -; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: mv a2, s2 +; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: bnez a0, .LBB207_1 ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # in Loop: Header=BB207_2 Depth=1 -; RV32IA-NEXT: mv a2, s2 -; RV32IA-NEXT: mv a3, s1 +; RV32IA-NEXT: mv a2, a4 +; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: j .LBB207_1 ; RV32IA-NEXT: .LBB207_7: # %atomicrmw.end ; RV32IA-NEXT: mv a0, a4 @@ -15425,11 +15419,11 @@ ; RV64I-NEXT: bnez a0, .LBB207_4 ; RV64I-NEXT: .LBB207_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s1, a3, .LBB207_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: blt s1, a3, .LBB207_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB207_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB207_1 ; RV64I-NEXT: .LBB207_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -15484,14 +15478,13 @@ ; RV32I-NEXT: sltu a0, s2, a4 ; RV32I-NEXT: .LBB208_5: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB208_2 Depth=1 -; RV32I-NEXT: xori a0, a0, 1 -; RV32I-NEXT: mv a2, a4 -; RV32I-NEXT: mv a3, a5 +; RV32I-NEXT: mv a2, s2 +; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: bnez a0, .LBB208_1 ; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB208_2 Depth=1 -; RV32I-NEXT: mv a2, s2 -; RV32I-NEXT: mv a3, s1 +; RV32I-NEXT: mv a2, a4 +; RV32I-NEXT: mv a3, a5 ; RV32I-NEXT: j .LBB208_1 ; RV32I-NEXT: .LBB208_7: # %atomicrmw.end ; RV32I-NEXT: mv a0, a4 @@ -15539,14 +15532,13 @@ ; RV32IA-NEXT: sltu a0, s2, a4 ; RV32IA-NEXT: .LBB208_5: # %atomicrmw.start ; RV32IA-NEXT: # in Loop: Header=BB208_2 Depth=1 -; RV32IA-NEXT: xori a0, a0, 1 -; RV32IA-NEXT: mv a2, a4 -; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: mv a2, s2 +; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: bnez a0, .LBB208_1 ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # in Loop: Header=BB208_2 Depth=1 -; RV32IA-NEXT: mv a2, s2 -; RV32IA-NEXT: mv a3, s1 +; RV32IA-NEXT: mv a2, a4 +; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: j .LBB208_1 ; RV32IA-NEXT: .LBB208_7: # %atomicrmw.end ; RV32IA-NEXT: mv a0, a4 @@ -15580,11 +15572,11 @@ ; RV64I-NEXT: bnez a0, .LBB208_4 ; RV64I-NEXT: .LBB208_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s1, a3, .LBB208_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: blt s1, a3, .LBB208_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB208_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB208_1 ; RV64I-NEXT: .LBB208_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -15639,14 +15631,13 @@ ; RV32I-NEXT: sltu a0, s2, a4 ; RV32I-NEXT: .LBB209_5: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB209_2 Depth=1 -; RV32I-NEXT: xori a0, a0, 1 -; RV32I-NEXT: mv a2, a4 -; RV32I-NEXT: mv a3, a5 +; RV32I-NEXT: mv a2, s2 +; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: bnez a0, .LBB209_1 ; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB209_2 Depth=1 -; RV32I-NEXT: mv a2, s2 -; RV32I-NEXT: mv a3, s1 +; RV32I-NEXT: mv a2, a4 +; RV32I-NEXT: mv a3, a5 ; RV32I-NEXT: j .LBB209_1 ; RV32I-NEXT: .LBB209_7: # %atomicrmw.end ; RV32I-NEXT: mv a0, a4 @@ -15694,14 +15685,13 @@ ; RV32IA-NEXT: sltu a0, s2, a4 ; RV32IA-NEXT: .LBB209_5: # %atomicrmw.start ; RV32IA-NEXT: # in Loop: Header=BB209_2 Depth=1 -; RV32IA-NEXT: xori a0, a0, 1 -; RV32IA-NEXT: mv a2, a4 -; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: mv a2, s2 +; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: bnez a0, .LBB209_1 ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # in Loop: Header=BB209_2 Depth=1 -; RV32IA-NEXT: mv a2, s2 -; RV32IA-NEXT: mv a3, s1 +; RV32IA-NEXT: mv a2, a4 +; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: j .LBB209_1 ; RV32IA-NEXT: .LBB209_7: # %atomicrmw.end ; RV32IA-NEXT: mv a0, a4 @@ -15735,11 +15725,11 @@ ; RV64I-NEXT: bnez a0, .LBB209_4 ; RV64I-NEXT: .LBB209_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s1, a3, .LBB209_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: blt s1, a3, .LBB209_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB209_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB209_1 ; RV64I-NEXT: .LBB209_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -16559,14 +16549,13 @@ ; RV32I-NEXT: sltu a0, s2, a4 ; RV32I-NEXT: .LBB215_5: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB215_2 Depth=1 -; RV32I-NEXT: xori a0, a0, 1 -; RV32I-NEXT: mv a2, a4 -; RV32I-NEXT: mv a3, a5 +; RV32I-NEXT: mv a2, s2 +; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: bnez a0, .LBB215_1 ; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB215_2 Depth=1 -; RV32I-NEXT: mv a2, s2 -; RV32I-NEXT: mv a3, s1 +; RV32I-NEXT: mv a2, a4 +; RV32I-NEXT: mv a3, a5 ; RV32I-NEXT: j .LBB215_1 ; RV32I-NEXT: .LBB215_7: # %atomicrmw.end ; RV32I-NEXT: mv a0, a4 @@ -16614,14 +16603,13 @@ ; RV32IA-NEXT: sltu a0, s2, a4 ; RV32IA-NEXT: .LBB215_5: # %atomicrmw.start ; RV32IA-NEXT: # in Loop: Header=BB215_2 Depth=1 -; RV32IA-NEXT: xori a0, a0, 1 -; RV32IA-NEXT: mv a2, a4 -; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: mv a2, s2 +; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: bnez a0, .LBB215_1 ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # in Loop: Header=BB215_2 Depth=1 -; RV32IA-NEXT: mv a2, s2 -; RV32IA-NEXT: mv a3, s1 +; RV32IA-NEXT: mv a2, a4 +; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: j .LBB215_1 ; RV32IA-NEXT: .LBB215_7: # %atomicrmw.end ; RV32IA-NEXT: mv a0, a4 @@ -16655,11 +16643,11 @@ ; RV64I-NEXT: bnez a0, .LBB215_4 ; RV64I-NEXT: .LBB215_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s1, a3, .LBB215_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: bltu s1, a3, .LBB215_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB215_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB215_1 ; RV64I-NEXT: .LBB215_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -16714,14 +16702,13 @@ ; RV32I-NEXT: sltu a0, s2, a4 ; RV32I-NEXT: .LBB216_5: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB216_2 Depth=1 -; RV32I-NEXT: xori a0, a0, 1 -; RV32I-NEXT: mv a2, a4 -; RV32I-NEXT: mv a3, a5 +; RV32I-NEXT: mv a2, s2 +; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: bnez a0, .LBB216_1 ; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB216_2 Depth=1 -; RV32I-NEXT: mv a2, s2 -; RV32I-NEXT: mv a3, s1 +; RV32I-NEXT: mv a2, a4 +; RV32I-NEXT: mv a3, a5 ; RV32I-NEXT: j .LBB216_1 ; RV32I-NEXT: .LBB216_7: # %atomicrmw.end ; RV32I-NEXT: mv a0, a4 @@ -16769,14 +16756,13 @@ ; RV32IA-NEXT: sltu a0, s2, a4 ; RV32IA-NEXT: .LBB216_5: # %atomicrmw.start ; RV32IA-NEXT: # in Loop: Header=BB216_2 Depth=1 -; RV32IA-NEXT: xori a0, a0, 1 -; RV32IA-NEXT: mv a2, a4 -; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: mv a2, s2 +; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: bnez a0, .LBB216_1 ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # in Loop: Header=BB216_2 Depth=1 -; RV32IA-NEXT: mv a2, s2 -; RV32IA-NEXT: mv a3, s1 +; RV32IA-NEXT: mv a2, a4 +; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: j .LBB216_1 ; RV32IA-NEXT: .LBB216_7: # %atomicrmw.end ; RV32IA-NEXT: mv a0, a4 @@ -16810,11 +16796,11 @@ ; RV64I-NEXT: bnez a0, .LBB216_4 ; RV64I-NEXT: .LBB216_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s1, a3, .LBB216_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: bltu s1, a3, .LBB216_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB216_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB216_1 ; RV64I-NEXT: .LBB216_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -16869,14 +16855,13 @@ ; RV32I-NEXT: sltu a0, s2, a4 ; RV32I-NEXT: .LBB217_5: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB217_2 Depth=1 -; RV32I-NEXT: xori a0, a0, 1 -; RV32I-NEXT: mv a2, a4 -; RV32I-NEXT: mv a3, a5 +; RV32I-NEXT: mv a2, s2 +; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: bnez a0, .LBB217_1 ; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB217_2 Depth=1 -; RV32I-NEXT: mv a2, s2 -; RV32I-NEXT: mv a3, s1 +; RV32I-NEXT: mv a2, a4 +; RV32I-NEXT: mv a3, a5 ; RV32I-NEXT: j .LBB217_1 ; RV32I-NEXT: .LBB217_7: # %atomicrmw.end ; RV32I-NEXT: mv a0, a4 @@ -16924,14 +16909,13 @@ ; RV32IA-NEXT: sltu a0, s2, a4 ; RV32IA-NEXT: .LBB217_5: # %atomicrmw.start ; RV32IA-NEXT: # in Loop: Header=BB217_2 Depth=1 -; RV32IA-NEXT: xori a0, a0, 1 -; RV32IA-NEXT: mv a2, a4 -; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: mv a2, s2 +; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: bnez a0, .LBB217_1 ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # in Loop: Header=BB217_2 Depth=1 -; RV32IA-NEXT: mv a2, s2 -; RV32IA-NEXT: mv a3, s1 +; RV32IA-NEXT: mv a2, a4 +; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: j .LBB217_1 ; RV32IA-NEXT: .LBB217_7: # %atomicrmw.end ; RV32IA-NEXT: mv a0, a4 @@ -16965,11 +16949,11 @@ ; RV64I-NEXT: bnez a0, .LBB217_4 ; RV64I-NEXT: .LBB217_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s1, a3, .LBB217_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: bltu s1, a3, .LBB217_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB217_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB217_1 ; RV64I-NEXT: .LBB217_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -17024,14 +17008,13 @@ ; RV32I-NEXT: sltu a0, s2, a4 ; RV32I-NEXT: .LBB218_5: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB218_2 Depth=1 -; RV32I-NEXT: xori a0, a0, 1 -; RV32I-NEXT: mv a2, a4 -; RV32I-NEXT: mv a3, a5 +; RV32I-NEXT: mv a2, s2 +; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: bnez a0, .LBB218_1 ; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB218_2 Depth=1 -; RV32I-NEXT: mv a2, s2 -; RV32I-NEXT: mv a3, s1 +; RV32I-NEXT: mv a2, a4 +; RV32I-NEXT: mv a3, a5 ; RV32I-NEXT: j .LBB218_1 ; RV32I-NEXT: .LBB218_7: # %atomicrmw.end ; RV32I-NEXT: mv a0, a4 @@ -17079,14 +17062,13 @@ ; RV32IA-NEXT: sltu a0, s2, a4 ; RV32IA-NEXT: .LBB218_5: # %atomicrmw.start ; RV32IA-NEXT: # in Loop: Header=BB218_2 Depth=1 -; RV32IA-NEXT: xori a0, a0, 1 -; RV32IA-NEXT: mv a2, a4 -; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: mv a2, s2 +; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: bnez a0, .LBB218_1 ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # in Loop: Header=BB218_2 Depth=1 -; RV32IA-NEXT: mv a2, s2 -; RV32IA-NEXT: mv a3, s1 +; RV32IA-NEXT: mv a2, a4 +; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: j .LBB218_1 ; RV32IA-NEXT: .LBB218_7: # %atomicrmw.end ; RV32IA-NEXT: mv a0, a4 @@ -17120,11 +17102,11 @@ ; RV64I-NEXT: bnez a0, .LBB218_4 ; RV64I-NEXT: .LBB218_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s1, a3, .LBB218_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: bltu s1, a3, .LBB218_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB218_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB218_1 ; RV64I-NEXT: .LBB218_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -17179,14 +17161,13 @@ ; RV32I-NEXT: sltu a0, s2, a4 ; RV32I-NEXT: .LBB219_5: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB219_2 Depth=1 -; RV32I-NEXT: xori a0, a0, 1 -; RV32I-NEXT: mv a2, a4 -; RV32I-NEXT: mv a3, a5 +; RV32I-NEXT: mv a2, s2 +; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: bnez a0, .LBB219_1 ; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB219_2 Depth=1 -; RV32I-NEXT: mv a2, s2 -; RV32I-NEXT: mv a3, s1 +; RV32I-NEXT: mv a2, a4 +; RV32I-NEXT: mv a3, a5 ; RV32I-NEXT: j .LBB219_1 ; RV32I-NEXT: .LBB219_7: # %atomicrmw.end ; RV32I-NEXT: mv a0, a4 @@ -17234,14 +17215,13 @@ ; RV32IA-NEXT: sltu a0, s2, a4 ; RV32IA-NEXT: .LBB219_5: # %atomicrmw.start ; RV32IA-NEXT: # in Loop: Header=BB219_2 Depth=1 -; RV32IA-NEXT: xori a0, a0, 1 -; RV32IA-NEXT: mv a2, a4 -; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: mv a2, s2 +; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: bnez a0, .LBB219_1 ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # in Loop: Header=BB219_2 Depth=1 -; RV32IA-NEXT: mv a2, s2 -; RV32IA-NEXT: mv a3, s1 +; RV32IA-NEXT: mv a2, a4 +; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: j .LBB219_1 ; RV32IA-NEXT: .LBB219_7: # %atomicrmw.end ; RV32IA-NEXT: mv a0, a4 @@ -17275,11 +17255,11 @@ ; RV64I-NEXT: bnez a0, .LBB219_4 ; RV64I-NEXT: .LBB219_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s1, a3, .LBB219_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: bltu s1, a3, .LBB219_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB219_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB219_1 ; RV64I-NEXT: .LBB219_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 Index: llvm/test/CodeGen/RISCV/atomic-signext.ll =================================================================== --- llvm/test/CodeGen/RISCV/atomic-signext.ll +++ llvm/test/CodeGen/RISCV/atomic-signext.ll @@ -754,11 +754,11 @@ ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: srai a0, a0, 24 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bge s2, a0, .LBB11_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: blt s2, a0, .LBB11_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB11_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB11_1 ; RV32I-NEXT: .LBB11_4: # %atomicrmw.end ; RV32I-NEXT: slli a0, a3, 24 @@ -828,11 +828,11 @@ ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: srai a0, a0, 56 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s2, a0, .LBB11_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: blt s2, a0, .LBB11_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB11_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB11_1 ; RV64I-NEXT: .LBB11_4: # %atomicrmw.end ; RV64I-NEXT: slli a0, a3, 56 @@ -1042,11 +1042,11 @@ ; RV32I-NEXT: .LBB13_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: andi a0, a3, 255 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bgeu s2, a0, .LBB13_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: bltu s2, a0, .LBB13_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB13_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB13_1 ; RV32I-NEXT: .LBB13_4: # %atomicrmw.end ; RV32I-NEXT: slli a0, a3, 24 @@ -1109,11 +1109,11 @@ ; RV64I-NEXT: .LBB13_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: andi a0, a3, 255 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s2, a0, .LBB13_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: bltu s2, a0, .LBB13_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB13_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB13_1 ; RV64I-NEXT: .LBB13_4: # %atomicrmw.end ; RV64I-NEXT: slli a0, a3, 56 @@ -1806,11 +1806,11 @@ ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: srai a0, a0, 16 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bge s2, a0, .LBB22_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: blt s2, a0, .LBB22_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB22_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB22_1 ; RV32I-NEXT: .LBB22_4: # %atomicrmw.end ; RV32I-NEXT: slli a0, a3, 16 @@ -1882,11 +1882,11 @@ ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: srai a0, a0, 48 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s2, a0, .LBB22_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: blt s2, a0, .LBB22_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB22_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB22_1 ; RV64I-NEXT: .LBB22_4: # %atomicrmw.end ; RV64I-NEXT: slli a0, a3, 48 @@ -2111,11 +2111,11 @@ ; RV32I-NEXT: .LBB24_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: and a0, a1, s2 -; RV32I-NEXT: mv a2, a1 -; RV32I-NEXT: bgeu s3, a0, .LBB24_1 +; RV32I-NEXT: mv a2, s0 +; RV32I-NEXT: bltu s3, a0, .LBB24_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB24_2 Depth=1 -; RV32I-NEXT: mv a2, s0 +; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: j .LBB24_1 ; RV32I-NEXT: .LBB24_4: # %atomicrmw.end ; RV32I-NEXT: slli a0, a1, 16 @@ -2183,11 +2183,11 @@ ; RV64I-NEXT: .LBB24_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: and a0, a1, s2 -; RV64I-NEXT: mv a2, a1 -; RV64I-NEXT: bgeu s3, a0, .LBB24_1 +; RV64I-NEXT: mv a2, s0 +; RV64I-NEXT: bltu s3, a0, .LBB24_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB24_2 Depth=1 -; RV64I-NEXT: mv a2, s0 +; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: j .LBB24_1 ; RV64I-NEXT: .LBB24_4: # %atomicrmw.end ; RV64I-NEXT: slli a0, a1, 48 @@ -2603,11 +2603,11 @@ ; RV32I-NEXT: bnez a0, .LBB33_4 ; RV32I-NEXT: .LBB33_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bge s1, a3, .LBB33_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: blt s1, a3, .LBB33_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB33_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB33_1 ; RV32I-NEXT: .LBB33_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -2646,11 +2646,11 @@ ; RV64I-NEXT: bnez a0, .LBB33_4 ; RV64I-NEXT: .LBB33_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s2, a3, .LBB33_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: blt s2, a3, .LBB33_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB33_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB33_1 ; RV64I-NEXT: .LBB33_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -2781,11 +2781,11 @@ ; RV32I-NEXT: bnez a0, .LBB35_4 ; RV32I-NEXT: .LBB35_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bgeu s1, a3, .LBB35_1 +; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: bltu s1, a3, .LBB35_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB35_2 Depth=1 -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: j .LBB35_1 ; RV32I-NEXT: .LBB35_4: # %atomicrmw.end ; RV32I-NEXT: mv a0, a3 @@ -2824,11 +2824,11 @@ ; RV64I-NEXT: bnez a0, .LBB35_4 ; RV64I-NEXT: .LBB35_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s2, a3, .LBB35_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: bltu s2, a3, .LBB35_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB35_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB35_1 ; RV64I-NEXT: .LBB35_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -3318,14 +3318,13 @@ ; RV32I-NEXT: sltu a0, s2, a4 ; RV32I-NEXT: .LBB44_5: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB44_2 Depth=1 -; RV32I-NEXT: xori a0, a0, 1 -; RV32I-NEXT: mv a2, a4 -; RV32I-NEXT: mv a3, a5 +; RV32I-NEXT: mv a2, s2 +; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: bnez a0, .LBB44_1 ; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB44_2 Depth=1 -; RV32I-NEXT: mv a2, s2 -; RV32I-NEXT: mv a3, s1 +; RV32I-NEXT: mv a2, a4 +; RV32I-NEXT: mv a3, a5 ; RV32I-NEXT: j .LBB44_1 ; RV32I-NEXT: .LBB44_7: # %atomicrmw.end ; RV32I-NEXT: mv a0, a4 @@ -3373,14 +3372,13 @@ ; RV32IA-NEXT: sltu a0, s2, a4 ; RV32IA-NEXT: .LBB44_5: # %atomicrmw.start ; RV32IA-NEXT: # in Loop: Header=BB44_2 Depth=1 -; RV32IA-NEXT: xori a0, a0, 1 -; RV32IA-NEXT: mv a2, a4 -; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: mv a2, s2 +; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: bnez a0, .LBB44_1 ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # in Loop: Header=BB44_2 Depth=1 -; RV32IA-NEXT: mv a2, s2 -; RV32IA-NEXT: mv a3, s1 +; RV32IA-NEXT: mv a2, a4 +; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: j .LBB44_1 ; RV32IA-NEXT: .LBB44_7: # %atomicrmw.end ; RV32IA-NEXT: mv a0, a4 @@ -3414,11 +3412,11 @@ ; RV64I-NEXT: bnez a0, .LBB44_4 ; RV64I-NEXT: .LBB44_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s1, a3, .LBB44_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: blt s1, a3, .LBB44_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB44_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB44_1 ; RV64I-NEXT: .LBB44_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 @@ -3626,14 +3624,13 @@ ; RV32I-NEXT: sltu a0, s2, a4 ; RV32I-NEXT: .LBB46_5: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB46_2 Depth=1 -; RV32I-NEXT: xori a0, a0, 1 -; RV32I-NEXT: mv a2, a4 -; RV32I-NEXT: mv a3, a5 +; RV32I-NEXT: mv a2, s2 +; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: bnez a0, .LBB46_1 ; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB46_2 Depth=1 -; RV32I-NEXT: mv a2, s2 -; RV32I-NEXT: mv a3, s1 +; RV32I-NEXT: mv a2, a4 +; RV32I-NEXT: mv a3, a5 ; RV32I-NEXT: j .LBB46_1 ; RV32I-NEXT: .LBB46_7: # %atomicrmw.end ; RV32I-NEXT: mv a0, a4 @@ -3681,14 +3678,13 @@ ; RV32IA-NEXT: sltu a0, s2, a4 ; RV32IA-NEXT: .LBB46_5: # %atomicrmw.start ; RV32IA-NEXT: # in Loop: Header=BB46_2 Depth=1 -; RV32IA-NEXT: xori a0, a0, 1 -; RV32IA-NEXT: mv a2, a4 -; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: mv a2, s2 +; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: bnez a0, .LBB46_1 ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # in Loop: Header=BB46_2 Depth=1 -; RV32IA-NEXT: mv a2, s2 -; RV32IA-NEXT: mv a3, s1 +; RV32IA-NEXT: mv a2, a4 +; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: j .LBB46_1 ; RV32IA-NEXT: .LBB46_7: # %atomicrmw.end ; RV32IA-NEXT: mv a0, a4 @@ -3722,11 +3718,11 @@ ; RV64I-NEXT: bnez a0, .LBB46_4 ; RV64I-NEXT: .LBB46_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s1, a3, .LBB46_1 +; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: bltu s1, a3, .LBB46_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB46_2 Depth=1 -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: j .LBB46_1 ; RV64I-NEXT: .LBB46_4: # %atomicrmw.end ; RV64I-NEXT: mv a0, a3 Index: llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll =================================================================== --- llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll +++ llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll @@ -478,11 +478,10 @@ ; RV32I-NEXT: sltu a0, a5, s1 ; RV32I-NEXT: .LBB3_2: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB3_3 Depth=1 -; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: addi a1, a4, 1 ; RV32I-NEXT: seqz a2, a1 ; RV32I-NEXT: add a3, a5, a2 -; RV32I-NEXT: addi a0, a0, -1 +; RV32I-NEXT: neg a0, a0 ; RV32I-NEXT: and a2, a0, a1 ; RV32I-NEXT: and a3, a0, a3 ; RV32I-NEXT: sw a4, 8(sp) @@ -534,11 +533,10 @@ ; RV32IA-NEXT: sltu a0, a5, s1 ; RV32IA-NEXT: .LBB3_2: # %atomicrmw.start ; RV32IA-NEXT: # in Loop: Header=BB3_3 Depth=1 -; RV32IA-NEXT: xori a0, a0, 1 ; RV32IA-NEXT: addi a1, a4, 1 ; RV32IA-NEXT: seqz a2, a1 ; RV32IA-NEXT: add a3, a5, a2 -; RV32IA-NEXT: addi a0, a0, -1 +; RV32IA-NEXT: neg a0, a0 ; RV32IA-NEXT: and a2, a0, a1 ; RV32IA-NEXT: and a3, a0, a3 ; RV32IA-NEXT: sw a4, 8(sp) Index: llvm/test/CodeGen/RISCV/compress.ll =================================================================== --- llvm/test/CodeGen/RISCV/compress.ll +++ llvm/test/CodeGen/RISCV/compress.ll @@ -59,26 +59,26 @@ ; RV32IC-NEXT: bltu a2, a0, 0x26 ; RV32IC-NEXT: c.mv a0, a2 ; RV32IC-NEXT: c.lw a2, 0(a1) -; RV32IC-NEXT: bgeu a0, a2, 0x2e -; RV32IC-NEXT: c.mv a0, a2 -; RV32IC-NEXT: c.lw a2, 0(a1) -; RV32IC-NEXT: bltu a0, a2, 0x36 -; RV32IC-NEXT: c.mv a0, a2 -; RV32IC-NEXT: c.lw a2, 0(a1) -; RV32IC-NEXT: bgeu a2, a0, 0x3e +; RV32IC-NEXT: bltu a0, a2, 0x2e +; RV32IC-NEXT: c.mv a2, a0 +; RV32IC-NEXT: c.lw a0, 0(a1) +; RV32IC-NEXT: bltu a2, a0, 0x36 +; RV32IC-NEXT: c.mv a2, a0 +; RV32IC-NEXT: c.lw a0, 0(a1) +; RV32IC-NEXT: bltu a0, a2, 0x3e ; RV32IC-NEXT: c.mv a0, a2 ; RV32IC-NEXT: c.lw a2, 0(a1) ; RV32IC-NEXT: blt a2, a0, 0x46 ; RV32IC-NEXT: c.mv a0, a2 ; RV32IC-NEXT: c.lw a2, 0(a1) -; RV32IC-NEXT: bge a0, a2, 0x4e -; RV32IC-NEXT: c.mv a0, a2 -; RV32IC-NEXT: c.lw a2, 0(a1) -; RV32IC-NEXT: blt a0, a2, 0x56 +; RV32IC-NEXT: blt a0, a2, 0x4e +; RV32IC-NEXT: c.mv a2, a0 +; RV32IC-NEXT: c.lw a0, 0(a1) +; RV32IC-NEXT: blt a2, a0, 0x56 +; RV32IC-NEXT: c.mv a2, a0 +; RV32IC-NEXT: c.lw a0, 0(a1) +; RV32IC-NEXT: blt a0, a2, 0x5e ; RV32IC-NEXT: c.mv a0, a2 -; RV32IC-NEXT: c.lw a1, 0(a1) -; RV32IC-NEXT: bge a1, a0, 0x5e -; RV32IC-NEXT: c.mv a0, a1 ; RV32IC-NEXT: c.jr ra %val1 = load volatile i32, ptr %b %tst1 = icmp eq i32 0, %val1 Index: llvm/test/CodeGen/RISCV/condops.ll =================================================================== --- llvm/test/CodeGen/RISCV/condops.ll +++ llvm/test/CodeGen/RISCV/condops.ll @@ -1264,28 +1264,26 @@ ; RV32I-NEXT: beq a1, a3, .LBB24_2 ; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: slt a0, a1, a3 -; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: beqz a0, .LBB24_3 ; RV32I-NEXT: j .LBB24_4 ; RV32I-NEXT: .LBB24_2: ; RV32I-NEXT: sltu a0, a0, a2 -; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: bnez a0, .LBB24_4 ; RV32I-NEXT: .LBB24_3: -; RV32I-NEXT: mv a4, a6 -; RV32I-NEXT: mv a5, a7 +; RV32I-NEXT: mv a6, a4 +; RV32I-NEXT: mv a7, a5 ; RV32I-NEXT: .LBB24_4: -; RV32I-NEXT: mv a0, a4 -; RV32I-NEXT: mv a1, a5 +; RV32I-NEXT: mv a0, a6 +; RV32I-NEXT: mv a1, a7 ; RV32I-NEXT: ret ; ; RV64I-LABEL: setge: ; RV64I: # %bb.0: -; RV64I-NEXT: bge a0, a1, .LBB24_2 +; RV64I-NEXT: blt a0, a1, .LBB24_2 ; RV64I-NEXT: # %bb.1: -; RV64I-NEXT: mv a2, a3 +; RV64I-NEXT: mv a3, a2 ; RV64I-NEXT: .LBB24_2: -; RV64I-NEXT: mv a0, a2 +; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: ret ; ; RV64XVENTANACONDOPS-LABEL: setge: @@ -1307,26 +1305,23 @@ ; RV32ZICOND: # %bb.0: ; RV32ZICOND-NEXT: xor t0, a1, a3 ; RV32ZICOND-NEXT: sltu a0, a0, a2 -; RV32ZICOND-NEXT: xori a0, a0, 1 ; RV32ZICOND-NEXT: czero.nez a0, a0, t0 ; RV32ZICOND-NEXT: slt a1, a1, a3 -; RV32ZICOND-NEXT: xori a1, a1, 1 ; RV32ZICOND-NEXT: czero.eqz a1, a1, t0 ; RV32ZICOND-NEXT: or a1, a1, a0 -; RV32ZICOND-NEXT: czero.nez a0, a6, a1 -; RV32ZICOND-NEXT: czero.eqz a2, a4, a1 +; RV32ZICOND-NEXT: czero.nez a0, a4, a1 +; RV32ZICOND-NEXT: czero.eqz a2, a6, a1 ; RV32ZICOND-NEXT: or a0, a2, a0 -; RV32ZICOND-NEXT: czero.nez a2, a7, a1 -; RV32ZICOND-NEXT: czero.eqz a1, a5, a1 +; RV32ZICOND-NEXT: czero.nez a2, a5, a1 +; RV32ZICOND-NEXT: czero.eqz a1, a7, a1 ; RV32ZICOND-NEXT: or a1, a1, a2 ; RV32ZICOND-NEXT: ret ; ; RV64ZICOND-LABEL: setge: ; RV64ZICOND: # %bb.0: ; RV64ZICOND-NEXT: slt a0, a0, a1 -; RV64ZICOND-NEXT: xori a0, a0, 1 -; RV64ZICOND-NEXT: czero.nez a1, a3, a0 -; RV64ZICOND-NEXT: czero.eqz a0, a2, a0 +; RV64ZICOND-NEXT: czero.nez a1, a2, a0 +; RV64ZICOND-NEXT: czero.eqz a0, a3, a0 ; RV64ZICOND-NEXT: or a0, a0, a1 ; RV64ZICOND-NEXT: ret %rc = icmp sge i64 %a, %b @@ -1411,28 +1406,26 @@ ; RV32I-NEXT: beq a1, a3, .LBB26_2 ; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: slt a0, a3, a1 -; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: beqz a0, .LBB26_3 ; RV32I-NEXT: j .LBB26_4 ; RV32I-NEXT: .LBB26_2: ; RV32I-NEXT: sltu a0, a2, a0 -; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: bnez a0, .LBB26_4 ; RV32I-NEXT: .LBB26_3: -; RV32I-NEXT: mv a4, a6 -; RV32I-NEXT: mv a5, a7 +; RV32I-NEXT: mv a6, a4 +; RV32I-NEXT: mv a7, a5 ; RV32I-NEXT: .LBB26_4: -; RV32I-NEXT: mv a0, a4 -; RV32I-NEXT: mv a1, a5 +; RV32I-NEXT: mv a0, a6 +; RV32I-NEXT: mv a1, a7 ; RV32I-NEXT: ret ; ; RV64I-LABEL: setle: ; RV64I: # %bb.0: -; RV64I-NEXT: bge a1, a0, .LBB26_2 +; RV64I-NEXT: blt a1, a0, .LBB26_2 ; RV64I-NEXT: # %bb.1: -; RV64I-NEXT: mv a2, a3 +; RV64I-NEXT: mv a3, a2 ; RV64I-NEXT: .LBB26_2: -; RV64I-NEXT: mv a0, a2 +; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: ret ; ; RV64XVENTANACONDOPS-LABEL: setle: @@ -1454,26 +1447,23 @@ ; RV32ZICOND: # %bb.0: ; RV32ZICOND-NEXT: xor t0, a1, a3 ; RV32ZICOND-NEXT: sltu a0, a2, a0 -; RV32ZICOND-NEXT: xori a0, a0, 1 ; RV32ZICOND-NEXT: czero.nez a0, a0, t0 ; RV32ZICOND-NEXT: slt a1, a3, a1 -; RV32ZICOND-NEXT: xori a1, a1, 1 ; RV32ZICOND-NEXT: czero.eqz a1, a1, t0 ; RV32ZICOND-NEXT: or a1, a1, a0 -; RV32ZICOND-NEXT: czero.nez a0, a6, a1 -; RV32ZICOND-NEXT: czero.eqz a2, a4, a1 +; RV32ZICOND-NEXT: czero.nez a0, a4, a1 +; RV32ZICOND-NEXT: czero.eqz a2, a6, a1 ; RV32ZICOND-NEXT: or a0, a2, a0 -; RV32ZICOND-NEXT: czero.nez a2, a7, a1 -; RV32ZICOND-NEXT: czero.eqz a1, a5, a1 +; RV32ZICOND-NEXT: czero.nez a2, a5, a1 +; RV32ZICOND-NEXT: czero.eqz a1, a7, a1 ; RV32ZICOND-NEXT: or a1, a1, a2 ; RV32ZICOND-NEXT: ret ; ; RV64ZICOND-LABEL: setle: ; RV64ZICOND: # %bb.0: ; RV64ZICOND-NEXT: slt a0, a1, a0 -; RV64ZICOND-NEXT: xori a0, a0, 1 -; RV64ZICOND-NEXT: czero.nez a1, a3, a0 -; RV64ZICOND-NEXT: czero.eqz a0, a2, a0 +; RV64ZICOND-NEXT: czero.nez a1, a2, a0 +; RV64ZICOND-NEXT: czero.eqz a0, a3, a0 ; RV64ZICOND-NEXT: or a0, a0, a1 ; RV64ZICOND-NEXT: ret %rc = icmp sle i64 %a, %b @@ -1558,28 +1548,26 @@ ; RV32I-NEXT: beq a1, a3, .LBB28_2 ; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: sltu a0, a1, a3 -; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: beqz a0, .LBB28_3 ; RV32I-NEXT: j .LBB28_4 ; RV32I-NEXT: .LBB28_2: ; RV32I-NEXT: sltu a0, a0, a2 -; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: bnez a0, .LBB28_4 ; RV32I-NEXT: .LBB28_3: -; RV32I-NEXT: mv a4, a6 -; RV32I-NEXT: mv a5, a7 +; RV32I-NEXT: mv a6, a4 +; RV32I-NEXT: mv a7, a5 ; RV32I-NEXT: .LBB28_4: -; RV32I-NEXT: mv a0, a4 -; RV32I-NEXT: mv a1, a5 +; RV32I-NEXT: mv a0, a6 +; RV32I-NEXT: mv a1, a7 ; RV32I-NEXT: ret ; ; RV64I-LABEL: setuge: ; RV64I: # %bb.0: -; RV64I-NEXT: bgeu a0, a1, .LBB28_2 +; RV64I-NEXT: bltu a0, a1, .LBB28_2 ; RV64I-NEXT: # %bb.1: -; RV64I-NEXT: mv a2, a3 +; RV64I-NEXT: mv a3, a2 ; RV64I-NEXT: .LBB28_2: -; RV64I-NEXT: mv a0, a2 +; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: ret ; ; RV64XVENTANACONDOPS-LABEL: setuge: @@ -1601,26 +1589,23 @@ ; RV32ZICOND: # %bb.0: ; RV32ZICOND-NEXT: xor t0, a1, a3 ; RV32ZICOND-NEXT: sltu a0, a0, a2 -; RV32ZICOND-NEXT: xori a0, a0, 1 ; RV32ZICOND-NEXT: czero.nez a0, a0, t0 ; RV32ZICOND-NEXT: sltu a1, a1, a3 -; RV32ZICOND-NEXT: xori a1, a1, 1 ; RV32ZICOND-NEXT: czero.eqz a1, a1, t0 ; RV32ZICOND-NEXT: or a1, a1, a0 -; RV32ZICOND-NEXT: czero.nez a0, a6, a1 -; RV32ZICOND-NEXT: czero.eqz a2, a4, a1 +; RV32ZICOND-NEXT: czero.nez a0, a4, a1 +; RV32ZICOND-NEXT: czero.eqz a2, a6, a1 ; RV32ZICOND-NEXT: or a0, a2, a0 -; RV32ZICOND-NEXT: czero.nez a2, a7, a1 -; RV32ZICOND-NEXT: czero.eqz a1, a5, a1 +; RV32ZICOND-NEXT: czero.nez a2, a5, a1 +; RV32ZICOND-NEXT: czero.eqz a1, a7, a1 ; RV32ZICOND-NEXT: or a1, a1, a2 ; RV32ZICOND-NEXT: ret ; ; RV64ZICOND-LABEL: setuge: ; RV64ZICOND: # %bb.0: ; RV64ZICOND-NEXT: sltu a0, a0, a1 -; RV64ZICOND-NEXT: xori a0, a0, 1 -; RV64ZICOND-NEXT: czero.nez a1, a3, a0 -; RV64ZICOND-NEXT: czero.eqz a0, a2, a0 +; RV64ZICOND-NEXT: czero.nez a1, a2, a0 +; RV64ZICOND-NEXT: czero.eqz a0, a3, a0 ; RV64ZICOND-NEXT: or a0, a0, a1 ; RV64ZICOND-NEXT: ret %rc = icmp uge i64 %a, %b @@ -1705,28 +1690,26 @@ ; RV32I-NEXT: beq a1, a3, .LBB30_2 ; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: sltu a0, a3, a1 -; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: beqz a0, .LBB30_3 ; RV32I-NEXT: j .LBB30_4 ; RV32I-NEXT: .LBB30_2: ; RV32I-NEXT: sltu a0, a2, a0 -; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: bnez a0, .LBB30_4 ; RV32I-NEXT: .LBB30_3: -; RV32I-NEXT: mv a4, a6 -; RV32I-NEXT: mv a5, a7 +; RV32I-NEXT: mv a6, a4 +; RV32I-NEXT: mv a7, a5 ; RV32I-NEXT: .LBB30_4: -; RV32I-NEXT: mv a0, a4 -; RV32I-NEXT: mv a1, a5 +; RV32I-NEXT: mv a0, a6 +; RV32I-NEXT: mv a1, a7 ; RV32I-NEXT: ret ; ; RV64I-LABEL: setule: ; RV64I: # %bb.0: -; RV64I-NEXT: bgeu a1, a0, .LBB30_2 +; RV64I-NEXT: bltu a1, a0, .LBB30_2 ; RV64I-NEXT: # %bb.1: -; RV64I-NEXT: mv a2, a3 +; RV64I-NEXT: mv a3, a2 ; RV64I-NEXT: .LBB30_2: -; RV64I-NEXT: mv a0, a2 +; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: ret ; ; RV64XVENTANACONDOPS-LABEL: setule: @@ -1748,26 +1731,23 @@ ; RV32ZICOND: # %bb.0: ; RV32ZICOND-NEXT: xor t0, a1, a3 ; RV32ZICOND-NEXT: sltu a0, a2, a0 -; RV32ZICOND-NEXT: xori a0, a0, 1 ; RV32ZICOND-NEXT: czero.nez a0, a0, t0 ; RV32ZICOND-NEXT: sltu a1, a3, a1 -; RV32ZICOND-NEXT: xori a1, a1, 1 ; RV32ZICOND-NEXT: czero.eqz a1, a1, t0 ; RV32ZICOND-NEXT: or a1, a1, a0 -; RV32ZICOND-NEXT: czero.nez a0, a6, a1 -; RV32ZICOND-NEXT: czero.eqz a2, a4, a1 +; RV32ZICOND-NEXT: czero.nez a0, a4, a1 +; RV32ZICOND-NEXT: czero.eqz a2, a6, a1 ; RV32ZICOND-NEXT: or a0, a2, a0 -; RV32ZICOND-NEXT: czero.nez a2, a7, a1 -; RV32ZICOND-NEXT: czero.eqz a1, a5, a1 +; RV32ZICOND-NEXT: czero.nez a2, a5, a1 +; RV32ZICOND-NEXT: czero.eqz a1, a7, a1 ; RV32ZICOND-NEXT: or a1, a1, a2 ; RV32ZICOND-NEXT: ret ; ; RV64ZICOND-LABEL: setule: ; RV64ZICOND: # %bb.0: ; RV64ZICOND-NEXT: sltu a0, a1, a0 -; RV64ZICOND-NEXT: xori a0, a0, 1 -; RV64ZICOND-NEXT: czero.nez a1, a3, a0 -; RV64ZICOND-NEXT: czero.eqz a0, a2, a0 +; RV64ZICOND-NEXT: czero.nez a1, a2, a0 +; RV64ZICOND-NEXT: czero.eqz a0, a3, a0 ; RV64ZICOND-NEXT: or a0, a0, a1 ; RV64ZICOND-NEXT: ret %rc = icmp ule i64 %a, %b Index: llvm/test/CodeGen/RISCV/double-select-icmp.ll =================================================================== --- llvm/test/CodeGen/RISCV/double-select-icmp.ll +++ llvm/test/CodeGen/RISCV/double-select-icmp.ll @@ -144,29 +144,30 @@ define double @select_icmp_uge(i32 signext %a, i32 signext %b, double %c, double %d) { ; CHECK-LABEL: select_icmp_uge: ; CHECK: # %bb.0: -; CHECK-NEXT: bgeu a0, a1, .LBB3_2 +; CHECK-NEXT: bltu a0, a1, .LBB3_2 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: fmv.d fa0, fa1 +; CHECK-NEXT: fmv.d fa1, fa0 ; CHECK-NEXT: .LBB3_2: +; CHECK-NEXT: fmv.d fa0, fa1 ; CHECK-NEXT: ret ; ; RV32ZDINX-LABEL: select_icmp_uge: ; RV32ZDINX: # %bb.0: ; RV32ZDINX-NEXT: addi sp, sp, -16 ; RV32ZDINX-NEXT: .cfi_def_cfa_offset 16 -; RV32ZDINX-NEXT: sw a4, 8(sp) -; RV32ZDINX-NEXT: sw a5, 12(sp) -; RV32ZDINX-NEXT: lw a4, 8(sp) -; RV32ZDINX-NEXT: lw a5, 12(sp) ; RV32ZDINX-NEXT: sw a2, 8(sp) ; RV32ZDINX-NEXT: sw a3, 12(sp) -; RV32ZDINX-NEXT: bltu a0, a1, .LBB3_2 -; RV32ZDINX-NEXT: # %bb.1: -; RV32ZDINX-NEXT: lw a4, 8(sp) -; RV32ZDINX-NEXT: lw a5, 12(sp) -; RV32ZDINX-NEXT: .LBB3_2: +; RV32ZDINX-NEXT: lw a2, 8(sp) +; RV32ZDINX-NEXT: lw a3, 12(sp) ; RV32ZDINX-NEXT: sw a4, 8(sp) ; RV32ZDINX-NEXT: sw a5, 12(sp) +; RV32ZDINX-NEXT: bgeu a0, a1, .LBB3_2 +; RV32ZDINX-NEXT: # %bb.1: +; RV32ZDINX-NEXT: lw a2, 8(sp) +; RV32ZDINX-NEXT: lw a3, 12(sp) +; RV32ZDINX-NEXT: .LBB3_2: +; RV32ZDINX-NEXT: sw a2, 8(sp) +; RV32ZDINX-NEXT: sw a3, 12(sp) ; RV32ZDINX-NEXT: lw a0, 8(sp) ; RV32ZDINX-NEXT: lw a1, 12(sp) ; RV32ZDINX-NEXT: addi sp, sp, 16 @@ -174,11 +175,11 @@ ; ; RV64ZDINX-LABEL: select_icmp_uge: ; RV64ZDINX: # %bb.0: -; RV64ZDINX-NEXT: bgeu a0, a1, .LBB3_2 +; RV64ZDINX-NEXT: bltu a0, a1, .LBB3_2 ; RV64ZDINX-NEXT: # %bb.1: -; RV64ZDINX-NEXT: mv a2, a3 +; RV64ZDINX-NEXT: mv a3, a2 ; RV64ZDINX-NEXT: .LBB3_2: -; RV64ZDINX-NEXT: mv a0, a2 +; RV64ZDINX-NEXT: mv a0, a3 ; RV64ZDINX-NEXT: ret %1 = icmp uge i32 %a, %b %2 = select i1 %1, double %c, double %d @@ -232,29 +233,30 @@ define double @select_icmp_ule(i32 signext %a, i32 signext %b, double %c, double %d) { ; CHECK-LABEL: select_icmp_ule: ; CHECK: # %bb.0: -; CHECK-NEXT: bgeu a1, a0, .LBB5_2 +; CHECK-NEXT: bltu a1, a0, .LBB5_2 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: fmv.d fa0, fa1 +; CHECK-NEXT: fmv.d fa1, fa0 ; CHECK-NEXT: .LBB5_2: +; CHECK-NEXT: fmv.d fa0, fa1 ; CHECK-NEXT: ret ; ; RV32ZDINX-LABEL: select_icmp_ule: ; RV32ZDINX: # %bb.0: ; RV32ZDINX-NEXT: addi sp, sp, -16 ; RV32ZDINX-NEXT: .cfi_def_cfa_offset 16 -; RV32ZDINX-NEXT: sw a4, 8(sp) -; RV32ZDINX-NEXT: sw a5, 12(sp) -; RV32ZDINX-NEXT: lw a4, 8(sp) -; RV32ZDINX-NEXT: lw a5, 12(sp) ; RV32ZDINX-NEXT: sw a2, 8(sp) ; RV32ZDINX-NEXT: sw a3, 12(sp) -; RV32ZDINX-NEXT: bltu a1, a0, .LBB5_2 -; RV32ZDINX-NEXT: # %bb.1: -; RV32ZDINX-NEXT: lw a4, 8(sp) -; RV32ZDINX-NEXT: lw a5, 12(sp) -; RV32ZDINX-NEXT: .LBB5_2: +; RV32ZDINX-NEXT: lw a2, 8(sp) +; RV32ZDINX-NEXT: lw a3, 12(sp) ; RV32ZDINX-NEXT: sw a4, 8(sp) ; RV32ZDINX-NEXT: sw a5, 12(sp) +; RV32ZDINX-NEXT: bgeu a1, a0, .LBB5_2 +; RV32ZDINX-NEXT: # %bb.1: +; RV32ZDINX-NEXT: lw a2, 8(sp) +; RV32ZDINX-NEXT: lw a3, 12(sp) +; RV32ZDINX-NEXT: .LBB5_2: +; RV32ZDINX-NEXT: sw a2, 8(sp) +; RV32ZDINX-NEXT: sw a3, 12(sp) ; RV32ZDINX-NEXT: lw a0, 8(sp) ; RV32ZDINX-NEXT: lw a1, 12(sp) ; RV32ZDINX-NEXT: addi sp, sp, 16 @@ -262,11 +264,11 @@ ; ; RV64ZDINX-LABEL: select_icmp_ule: ; RV64ZDINX: # %bb.0: -; RV64ZDINX-NEXT: bgeu a1, a0, .LBB5_2 +; RV64ZDINX-NEXT: bltu a1, a0, .LBB5_2 ; RV64ZDINX-NEXT: # %bb.1: -; RV64ZDINX-NEXT: mv a2, a3 +; RV64ZDINX-NEXT: mv a3, a2 ; RV64ZDINX-NEXT: .LBB5_2: -; RV64ZDINX-NEXT: mv a0, a2 +; RV64ZDINX-NEXT: mv a0, a3 ; RV64ZDINX-NEXT: ret %1 = icmp ule i32 %a, %b %2 = select i1 %1, double %c, double %d @@ -320,29 +322,30 @@ define double @select_icmp_sge(i32 signext %a, i32 signext %b, double %c, double %d) { ; CHECK-LABEL: select_icmp_sge: ; CHECK: # %bb.0: -; CHECK-NEXT: bge a0, a1, .LBB7_2 +; CHECK-NEXT: blt a0, a1, .LBB7_2 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: fmv.d fa0, fa1 +; CHECK-NEXT: fmv.d fa1, fa0 ; CHECK-NEXT: .LBB7_2: +; CHECK-NEXT: fmv.d fa0, fa1 ; CHECK-NEXT: ret ; ; RV32ZDINX-LABEL: select_icmp_sge: ; RV32ZDINX: # %bb.0: ; RV32ZDINX-NEXT: addi sp, sp, -16 ; RV32ZDINX-NEXT: .cfi_def_cfa_offset 16 -; RV32ZDINX-NEXT: sw a4, 8(sp) -; RV32ZDINX-NEXT: sw a5, 12(sp) -; RV32ZDINX-NEXT: lw a4, 8(sp) -; RV32ZDINX-NEXT: lw a5, 12(sp) ; RV32ZDINX-NEXT: sw a2, 8(sp) ; RV32ZDINX-NEXT: sw a3, 12(sp) -; RV32ZDINX-NEXT: blt a0, a1, .LBB7_2 -; RV32ZDINX-NEXT: # %bb.1: -; RV32ZDINX-NEXT: lw a4, 8(sp) -; RV32ZDINX-NEXT: lw a5, 12(sp) -; RV32ZDINX-NEXT: .LBB7_2: +; RV32ZDINX-NEXT: lw a2, 8(sp) +; RV32ZDINX-NEXT: lw a3, 12(sp) ; RV32ZDINX-NEXT: sw a4, 8(sp) ; RV32ZDINX-NEXT: sw a5, 12(sp) +; RV32ZDINX-NEXT: bge a0, a1, .LBB7_2 +; RV32ZDINX-NEXT: # %bb.1: +; RV32ZDINX-NEXT: lw a2, 8(sp) +; RV32ZDINX-NEXT: lw a3, 12(sp) +; RV32ZDINX-NEXT: .LBB7_2: +; RV32ZDINX-NEXT: sw a2, 8(sp) +; RV32ZDINX-NEXT: sw a3, 12(sp) ; RV32ZDINX-NEXT: lw a0, 8(sp) ; RV32ZDINX-NEXT: lw a1, 12(sp) ; RV32ZDINX-NEXT: addi sp, sp, 16 @@ -350,11 +353,11 @@ ; ; RV64ZDINX-LABEL: select_icmp_sge: ; RV64ZDINX: # %bb.0: -; RV64ZDINX-NEXT: bge a0, a1, .LBB7_2 +; RV64ZDINX-NEXT: blt a0, a1, .LBB7_2 ; RV64ZDINX-NEXT: # %bb.1: -; RV64ZDINX-NEXT: mv a2, a3 +; RV64ZDINX-NEXT: mv a3, a2 ; RV64ZDINX-NEXT: .LBB7_2: -; RV64ZDINX-NEXT: mv a0, a2 +; RV64ZDINX-NEXT: mv a0, a3 ; RV64ZDINX-NEXT: ret %1 = icmp sge i32 %a, %b %2 = select i1 %1, double %c, double %d @@ -408,29 +411,30 @@ define double @select_icmp_sle(i32 signext %a, i32 signext %b, double %c, double %d) { ; CHECK-LABEL: select_icmp_sle: ; CHECK: # %bb.0: -; CHECK-NEXT: bge a1, a0, .LBB9_2 +; CHECK-NEXT: blt a1, a0, .LBB9_2 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: fmv.d fa0, fa1 +; CHECK-NEXT: fmv.d fa1, fa0 ; CHECK-NEXT: .LBB9_2: +; CHECK-NEXT: fmv.d fa0, fa1 ; CHECK-NEXT: ret ; ; RV32ZDINX-LABEL: select_icmp_sle: ; RV32ZDINX: # %bb.0: ; RV32ZDINX-NEXT: addi sp, sp, -16 ; RV32ZDINX-NEXT: .cfi_def_cfa_offset 16 -; RV32ZDINX-NEXT: sw a4, 8(sp) -; RV32ZDINX-NEXT: sw a5, 12(sp) -; RV32ZDINX-NEXT: lw a4, 8(sp) -; RV32ZDINX-NEXT: lw a5, 12(sp) ; RV32ZDINX-NEXT: sw a2, 8(sp) ; RV32ZDINX-NEXT: sw a3, 12(sp) -; RV32ZDINX-NEXT: blt a1, a0, .LBB9_2 -; RV32ZDINX-NEXT: # %bb.1: -; RV32ZDINX-NEXT: lw a4, 8(sp) -; RV32ZDINX-NEXT: lw a5, 12(sp) -; RV32ZDINX-NEXT: .LBB9_2: +; RV32ZDINX-NEXT: lw a2, 8(sp) +; RV32ZDINX-NEXT: lw a3, 12(sp) ; RV32ZDINX-NEXT: sw a4, 8(sp) ; RV32ZDINX-NEXT: sw a5, 12(sp) +; RV32ZDINX-NEXT: bge a1, a0, .LBB9_2 +; RV32ZDINX-NEXT: # %bb.1: +; RV32ZDINX-NEXT: lw a2, 8(sp) +; RV32ZDINX-NEXT: lw a3, 12(sp) +; RV32ZDINX-NEXT: .LBB9_2: +; RV32ZDINX-NEXT: sw a2, 8(sp) +; RV32ZDINX-NEXT: sw a3, 12(sp) ; RV32ZDINX-NEXT: lw a0, 8(sp) ; RV32ZDINX-NEXT: lw a1, 12(sp) ; RV32ZDINX-NEXT: addi sp, sp, 16 @@ -438,11 +442,11 @@ ; ; RV64ZDINX-LABEL: select_icmp_sle: ; RV64ZDINX: # %bb.0: -; RV64ZDINX-NEXT: bge a1, a0, .LBB9_2 +; RV64ZDINX-NEXT: blt a1, a0, .LBB9_2 ; RV64ZDINX-NEXT: # %bb.1: -; RV64ZDINX-NEXT: mv a2, a3 +; RV64ZDINX-NEXT: mv a3, a2 ; RV64ZDINX-NEXT: .LBB9_2: -; RV64ZDINX-NEXT: mv a0, a2 +; RV64ZDINX-NEXT: mv a0, a3 ; RV64ZDINX-NEXT: ret %1 = icmp sle i32 %a, %b %2 = select i1 %1, double %c, double %d Index: llvm/test/CodeGen/RISCV/float-select-icmp.ll =================================================================== --- llvm/test/CodeGen/RISCV/float-select-icmp.ll +++ llvm/test/CodeGen/RISCV/float-select-icmp.ll @@ -77,19 +77,20 @@ define float @select_icmp_uge(i32 signext %a, i32 signext %b, float %c, float %d) { ; CHECK-LABEL: select_icmp_uge: ; CHECK: # %bb.0: -; CHECK-NEXT: bgeu a0, a1, .LBB3_2 +; CHECK-NEXT: bltu a0, a1, .LBB3_2 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: fmv.s fa0, fa1 +; CHECK-NEXT: fmv.s fa1, fa0 ; CHECK-NEXT: .LBB3_2: +; CHECK-NEXT: fmv.s fa0, fa1 ; CHECK-NEXT: ret ; ; CHECKZFINX-LABEL: select_icmp_uge: ; CHECKZFINX: # %bb.0: -; CHECKZFINX-NEXT: bgeu a0, a1, .LBB3_2 +; CHECKZFINX-NEXT: bltu a0, a1, .LBB3_2 ; CHECKZFINX-NEXT: # %bb.1: -; CHECKZFINX-NEXT: mv a2, a3 +; CHECKZFINX-NEXT: mv a3, a2 ; CHECKZFINX-NEXT: .LBB3_2: -; CHECKZFINX-NEXT: mv a0, a2 +; CHECKZFINX-NEXT: mv a0, a3 ; CHECKZFINX-NEXT: ret %1 = icmp uge i32 %a, %b %2 = select i1 %1, float %c, float %d @@ -121,19 +122,20 @@ define float @select_icmp_ule(i32 signext %a, i32 signext %b, float %c, float %d) { ; CHECK-LABEL: select_icmp_ule: ; CHECK: # %bb.0: -; CHECK-NEXT: bgeu a1, a0, .LBB5_2 +; CHECK-NEXT: bltu a1, a0, .LBB5_2 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: fmv.s fa0, fa1 +; CHECK-NEXT: fmv.s fa1, fa0 ; CHECK-NEXT: .LBB5_2: +; CHECK-NEXT: fmv.s fa0, fa1 ; CHECK-NEXT: ret ; ; CHECKZFINX-LABEL: select_icmp_ule: ; CHECKZFINX: # %bb.0: -; CHECKZFINX-NEXT: bgeu a1, a0, .LBB5_2 +; CHECKZFINX-NEXT: bltu a1, a0, .LBB5_2 ; CHECKZFINX-NEXT: # %bb.1: -; CHECKZFINX-NEXT: mv a2, a3 +; CHECKZFINX-NEXT: mv a3, a2 ; CHECKZFINX-NEXT: .LBB5_2: -; CHECKZFINX-NEXT: mv a0, a2 +; CHECKZFINX-NEXT: mv a0, a3 ; CHECKZFINX-NEXT: ret %1 = icmp ule i32 %a, %b %2 = select i1 %1, float %c, float %d @@ -165,19 +167,20 @@ define float @select_icmp_sge(i32 signext %a, i32 signext %b, float %c, float %d) { ; CHECK-LABEL: select_icmp_sge: ; CHECK: # %bb.0: -; CHECK-NEXT: bge a0, a1, .LBB7_2 +; CHECK-NEXT: blt a0, a1, .LBB7_2 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: fmv.s fa0, fa1 +; CHECK-NEXT: fmv.s fa1, fa0 ; CHECK-NEXT: .LBB7_2: +; CHECK-NEXT: fmv.s fa0, fa1 ; CHECK-NEXT: ret ; ; CHECKZFINX-LABEL: select_icmp_sge: ; CHECKZFINX: # %bb.0: -; CHECKZFINX-NEXT: bge a0, a1, .LBB7_2 +; CHECKZFINX-NEXT: blt a0, a1, .LBB7_2 ; CHECKZFINX-NEXT: # %bb.1: -; CHECKZFINX-NEXT: mv a2, a3 +; CHECKZFINX-NEXT: mv a3, a2 ; CHECKZFINX-NEXT: .LBB7_2: -; CHECKZFINX-NEXT: mv a0, a2 +; CHECKZFINX-NEXT: mv a0, a3 ; CHECKZFINX-NEXT: ret %1 = icmp sge i32 %a, %b %2 = select i1 %1, float %c, float %d @@ -209,19 +212,20 @@ define float @select_icmp_sle(i32 signext %a, i32 signext %b, float %c, float %d) { ; CHECK-LABEL: select_icmp_sle: ; CHECK: # %bb.0: -; CHECK-NEXT: bge a1, a0, .LBB9_2 +; CHECK-NEXT: blt a1, a0, .LBB9_2 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: fmv.s fa0, fa1 +; CHECK-NEXT: fmv.s fa1, fa0 ; CHECK-NEXT: .LBB9_2: +; CHECK-NEXT: fmv.s fa0, fa1 ; CHECK-NEXT: ret ; ; CHECKZFINX-LABEL: select_icmp_sle: ; CHECKZFINX: # %bb.0: -; CHECKZFINX-NEXT: bge a1, a0, .LBB9_2 +; CHECKZFINX-NEXT: blt a1, a0, .LBB9_2 ; CHECKZFINX-NEXT: # %bb.1: -; CHECKZFINX-NEXT: mv a2, a3 +; CHECKZFINX-NEXT: mv a3, a2 ; CHECKZFINX-NEXT: .LBB9_2: -; CHECKZFINX-NEXT: mv a0, a2 +; CHECKZFINX-NEXT: mv a0, a3 ; CHECKZFINX-NEXT: ret %1 = icmp sle i32 %a, %b %2 = select i1 %1, float %c, float %d Index: llvm/test/CodeGen/RISCV/forced-atomics.ll =================================================================== --- llvm/test/CodeGen/RISCV/forced-atomics.ll +++ llvm/test/CodeGen/RISCV/forced-atomics.ll @@ -1467,25 +1467,24 @@ ; RV32-NO-ATOMIC-NEXT: addi sp, sp, -16 ; RV32-NO-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NO-ATOMIC-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32-NO-ATOMIC-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32-NO-ATOMIC-NEXT: mv s0, a0 ; RV32-NO-ATOMIC-NEXT: lw a1, 0(a0) -; RV32-NO-ATOMIC-NEXT: li s1, 2 ; RV32-NO-ATOMIC-NEXT: j .LBB24_2 ; RV32-NO-ATOMIC-NEXT: .LBB24_1: # %atomicrmw.start ; RV32-NO-ATOMIC-NEXT: # in Loop: Header=BB24_2 Depth=1 -; RV32-NO-ATOMIC-NEXT: sw a1, 0(sp) -; RV32-NO-ATOMIC-NEXT: mv a1, sp +; RV32-NO-ATOMIC-NEXT: sw a1, 4(sp) +; RV32-NO-ATOMIC-NEXT: addi a1, sp, 4 ; RV32-NO-ATOMIC-NEXT: li a3, 5 ; RV32-NO-ATOMIC-NEXT: li a4, 5 ; RV32-NO-ATOMIC-NEXT: mv a0, s0 ; RV32-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4@plt -; RV32-NO-ATOMIC-NEXT: lw a1, 0(sp) +; RV32-NO-ATOMIC-NEXT: lw a1, 4(sp) ; RV32-NO-ATOMIC-NEXT: bnez a0, .LBB24_4 ; RV32-NO-ATOMIC-NEXT: .LBB24_2: # %atomicrmw.start ; RV32-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32-NO-ATOMIC-NEXT: li a0, 1 ; RV32-NO-ATOMIC-NEXT: mv a2, a1 -; RV32-NO-ATOMIC-NEXT: blt a1, s1, .LBB24_1 +; RV32-NO-ATOMIC-NEXT: bge a0, a1, .LBB24_1 ; RV32-NO-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start ; RV32-NO-ATOMIC-NEXT: # in Loop: Header=BB24_2 Depth=1 ; RV32-NO-ATOMIC-NEXT: li a2, 1 @@ -1494,7 +1493,6 @@ ; RV32-NO-ATOMIC-NEXT: mv a0, a1 ; RV32-NO-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NO-ATOMIC-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32-NO-ATOMIC-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV32-NO-ATOMIC-NEXT: ret ; @@ -1523,25 +1521,24 @@ ; RV64-NO-ATOMIC-NEXT: addi sp, sp, -32 ; RV64-NO-ATOMIC-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: sd s0, 16(sp) # 8-byte Folded Spill -; RV64-NO-ATOMIC-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: mv s0, a0 ; RV64-NO-ATOMIC-NEXT: lw a1, 0(a0) -; RV64-NO-ATOMIC-NEXT: li s1, 2 ; RV64-NO-ATOMIC-NEXT: j .LBB24_2 ; RV64-NO-ATOMIC-NEXT: .LBB24_1: # %atomicrmw.start ; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB24_2 Depth=1 -; RV64-NO-ATOMIC-NEXT: sw a1, 4(sp) -; RV64-NO-ATOMIC-NEXT: addi a1, sp, 4 +; RV64-NO-ATOMIC-NEXT: sw a1, 12(sp) +; RV64-NO-ATOMIC-NEXT: addi a1, sp, 12 ; RV64-NO-ATOMIC-NEXT: li a3, 5 ; RV64-NO-ATOMIC-NEXT: li a4, 5 ; RV64-NO-ATOMIC-NEXT: mv a0, s0 ; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4@plt -; RV64-NO-ATOMIC-NEXT: lw a1, 4(sp) +; RV64-NO-ATOMIC-NEXT: lw a1, 12(sp) ; RV64-NO-ATOMIC-NEXT: bnez a0, .LBB24_4 ; RV64-NO-ATOMIC-NEXT: .LBB24_2: # %atomicrmw.start ; RV64-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV64-NO-ATOMIC-NEXT: li a0, 1 ; RV64-NO-ATOMIC-NEXT: mv a2, a1 -; RV64-NO-ATOMIC-NEXT: blt a1, s1, .LBB24_1 +; RV64-NO-ATOMIC-NEXT: bge a0, a1, .LBB24_1 ; RV64-NO-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start ; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB24_2 Depth=1 ; RV64-NO-ATOMIC-NEXT: li a2, 1 @@ -1550,7 +1547,6 @@ ; RV64-NO-ATOMIC-NEXT: mv a0, a1 ; RV64-NO-ATOMIC-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: ld s0, 16(sp) # 8-byte Folded Reload -; RV64-NO-ATOMIC-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 32 ; RV64-NO-ATOMIC-NEXT: ret ; @@ -1687,25 +1683,24 @@ ; RV32-NO-ATOMIC-NEXT: addi sp, sp, -16 ; RV32-NO-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NO-ATOMIC-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32-NO-ATOMIC-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32-NO-ATOMIC-NEXT: mv s0, a0 ; RV32-NO-ATOMIC-NEXT: lw a1, 0(a0) -; RV32-NO-ATOMIC-NEXT: li s1, 2 ; RV32-NO-ATOMIC-NEXT: j .LBB26_2 ; RV32-NO-ATOMIC-NEXT: .LBB26_1: # %atomicrmw.start ; RV32-NO-ATOMIC-NEXT: # in Loop: Header=BB26_2 Depth=1 -; RV32-NO-ATOMIC-NEXT: sw a1, 0(sp) -; RV32-NO-ATOMIC-NEXT: mv a1, sp +; RV32-NO-ATOMIC-NEXT: sw a1, 4(sp) +; RV32-NO-ATOMIC-NEXT: addi a1, sp, 4 ; RV32-NO-ATOMIC-NEXT: li a3, 5 ; RV32-NO-ATOMIC-NEXT: li a4, 5 ; RV32-NO-ATOMIC-NEXT: mv a0, s0 ; RV32-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4@plt -; RV32-NO-ATOMIC-NEXT: lw a1, 0(sp) +; RV32-NO-ATOMIC-NEXT: lw a1, 4(sp) ; RV32-NO-ATOMIC-NEXT: bnez a0, .LBB26_4 ; RV32-NO-ATOMIC-NEXT: .LBB26_2: # %atomicrmw.start ; RV32-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32-NO-ATOMIC-NEXT: li a0, 1 ; RV32-NO-ATOMIC-NEXT: mv a2, a1 -; RV32-NO-ATOMIC-NEXT: bltu a1, s1, .LBB26_1 +; RV32-NO-ATOMIC-NEXT: bgeu a0, a1, .LBB26_1 ; RV32-NO-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start ; RV32-NO-ATOMIC-NEXT: # in Loop: Header=BB26_2 Depth=1 ; RV32-NO-ATOMIC-NEXT: li a2, 1 @@ -1714,7 +1709,6 @@ ; RV32-NO-ATOMIC-NEXT: mv a0, a1 ; RV32-NO-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NO-ATOMIC-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32-NO-ATOMIC-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV32-NO-ATOMIC-NEXT: ret ; @@ -1743,25 +1737,24 @@ ; RV64-NO-ATOMIC-NEXT: addi sp, sp, -32 ; RV64-NO-ATOMIC-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: sd s0, 16(sp) # 8-byte Folded Spill -; RV64-NO-ATOMIC-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: mv s0, a0 ; RV64-NO-ATOMIC-NEXT: lw a1, 0(a0) -; RV64-NO-ATOMIC-NEXT: li s1, 2 ; RV64-NO-ATOMIC-NEXT: j .LBB26_2 ; RV64-NO-ATOMIC-NEXT: .LBB26_1: # %atomicrmw.start ; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB26_2 Depth=1 -; RV64-NO-ATOMIC-NEXT: sw a1, 4(sp) -; RV64-NO-ATOMIC-NEXT: addi a1, sp, 4 +; RV64-NO-ATOMIC-NEXT: sw a1, 12(sp) +; RV64-NO-ATOMIC-NEXT: addi a1, sp, 12 ; RV64-NO-ATOMIC-NEXT: li a3, 5 ; RV64-NO-ATOMIC-NEXT: li a4, 5 ; RV64-NO-ATOMIC-NEXT: mv a0, s0 ; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4@plt -; RV64-NO-ATOMIC-NEXT: lw a1, 4(sp) +; RV64-NO-ATOMIC-NEXT: lw a1, 12(sp) ; RV64-NO-ATOMIC-NEXT: bnez a0, .LBB26_4 ; RV64-NO-ATOMIC-NEXT: .LBB26_2: # %atomicrmw.start ; RV64-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV64-NO-ATOMIC-NEXT: li a0, 1 ; RV64-NO-ATOMIC-NEXT: mv a2, a1 -; RV64-NO-ATOMIC-NEXT: bltu a1, s1, .LBB26_1 +; RV64-NO-ATOMIC-NEXT: bgeu a0, a1, .LBB26_1 ; RV64-NO-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start ; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB26_2 Depth=1 ; RV64-NO-ATOMIC-NEXT: li a2, 1 @@ -1770,7 +1763,6 @@ ; RV64-NO-ATOMIC-NEXT: mv a0, a1 ; RV64-NO-ATOMIC-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: ld s0, 16(sp) # 8-byte Folded Reload -; RV64-NO-ATOMIC-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 32 ; RV64-NO-ATOMIC-NEXT: ret ; @@ -3458,8 +3450,8 @@ ; RV32-NEXT: j .LBB50_2 ; RV32-NEXT: .LBB50_1: # %atomicrmw.start ; RV32-NEXT: # in Loop: Header=BB50_2 Depth=1 -; RV32-NEXT: neg a3, a0 -; RV32-NEXT: and a3, a3, a1 +; RV32-NEXT: addi a0, a0, -1 +; RV32-NEXT: and a3, a0, a1 ; RV32-NEXT: sw a4, 0(sp) ; RV32-NEXT: sw a1, 4(sp) ; RV32-NEXT: mv a1, sp @@ -3475,17 +3467,18 @@ ; RV32-NEXT: beqz a1, .LBB50_4 ; RV32-NEXT: # %bb.3: # %atomicrmw.start ; RV32-NEXT: # in Loop: Header=BB50_2 Depth=1 -; RV32-NEXT: slti a0, a1, 0 -; RV32-NEXT: mv a2, a4 +; RV32-NEXT: sgtz a0, a1 +; RV32-NEXT: li a2, 1 ; RV32-NEXT: bnez a0, .LBB50_1 ; RV32-NEXT: j .LBB50_5 ; RV32-NEXT: .LBB50_4: # in Loop: Header=BB50_2 Depth=1 ; RV32-NEXT: sltiu a0, a4, 2 -; RV32-NEXT: mv a2, a4 +; RV32-NEXT: xori a0, a0, 1 +; RV32-NEXT: li a2, 1 ; RV32-NEXT: bnez a0, .LBB50_1 ; RV32-NEXT: .LBB50_5: # %atomicrmw.start ; RV32-NEXT: # in Loop: Header=BB50_2 Depth=1 -; RV32-NEXT: li a2, 1 +; RV32-NEXT: mv a2, a4 ; RV32-NEXT: j .LBB50_1 ; RV32-NEXT: .LBB50_6: # %atomicrmw.end ; RV32-NEXT: mv a0, a4 @@ -3499,25 +3492,24 @@ ; RV64-NO-ATOMIC-NEXT: addi sp, sp, -32 ; RV64-NO-ATOMIC-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: sd s0, 16(sp) # 8-byte Folded Spill -; RV64-NO-ATOMIC-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: mv s0, a0 ; RV64-NO-ATOMIC-NEXT: ld a1, 0(a0) -; RV64-NO-ATOMIC-NEXT: li s1, 2 ; RV64-NO-ATOMIC-NEXT: j .LBB50_2 ; RV64-NO-ATOMIC-NEXT: .LBB50_1: # %atomicrmw.start ; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB50_2 Depth=1 -; RV64-NO-ATOMIC-NEXT: sd a1, 0(sp) -; RV64-NO-ATOMIC-NEXT: mv a1, sp +; RV64-NO-ATOMIC-NEXT: sd a1, 8(sp) +; RV64-NO-ATOMIC-NEXT: addi a1, sp, 8 ; RV64-NO-ATOMIC-NEXT: li a3, 5 ; RV64-NO-ATOMIC-NEXT: li a4, 5 ; RV64-NO-ATOMIC-NEXT: mv a0, s0 ; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_8@plt -; RV64-NO-ATOMIC-NEXT: ld a1, 0(sp) +; RV64-NO-ATOMIC-NEXT: ld a1, 8(sp) ; RV64-NO-ATOMIC-NEXT: bnez a0, .LBB50_4 ; RV64-NO-ATOMIC-NEXT: .LBB50_2: # %atomicrmw.start ; RV64-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV64-NO-ATOMIC-NEXT: li a0, 1 ; RV64-NO-ATOMIC-NEXT: mv a2, a1 -; RV64-NO-ATOMIC-NEXT: blt a1, s1, .LBB50_1 +; RV64-NO-ATOMIC-NEXT: bge a0, a1, .LBB50_1 ; RV64-NO-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start ; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB50_2 Depth=1 ; RV64-NO-ATOMIC-NEXT: li a2, 1 @@ -3526,7 +3518,6 @@ ; RV64-NO-ATOMIC-NEXT: mv a0, a1 ; RV64-NO-ATOMIC-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: ld s0, 16(sp) # 8-byte Folded Reload -; RV64-NO-ATOMIC-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 32 ; RV64-NO-ATOMIC-NEXT: ret ; @@ -3657,8 +3648,8 @@ ; RV32-NEXT: j .LBB52_2 ; RV32-NEXT: .LBB52_1: # %atomicrmw.start ; RV32-NEXT: # in Loop: Header=BB52_2 Depth=1 -; RV32-NEXT: neg a3, a0 -; RV32-NEXT: and a3, a3, a1 +; RV32-NEXT: addi a0, a0, -1 +; RV32-NEXT: and a3, a0, a1 ; RV32-NEXT: sw a4, 0(sp) ; RV32-NEXT: sw a1, 4(sp) ; RV32-NEXT: mv a1, sp @@ -3671,14 +3662,15 @@ ; RV32-NEXT: bnez a0, .LBB52_4 ; RV32-NEXT: .LBB52_2: # %atomicrmw.start ; RV32-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32-NEXT: sltiu a0, a4, 2 -; RV32-NEXT: seqz a2, a1 -; RV32-NEXT: and a0, a2, a0 -; RV32-NEXT: mv a2, a4 +; RV32-NEXT: snez a0, a1 +; RV32-NEXT: sltiu a2, a4, 2 +; RV32-NEXT: xori a2, a2, 1 +; RV32-NEXT: or a0, a2, a0 +; RV32-NEXT: li a2, 1 ; RV32-NEXT: bnez a0, .LBB52_1 ; RV32-NEXT: # %bb.3: # %atomicrmw.start ; RV32-NEXT: # in Loop: Header=BB52_2 Depth=1 -; RV32-NEXT: li a2, 1 +; RV32-NEXT: mv a2, a4 ; RV32-NEXT: j .LBB52_1 ; RV32-NEXT: .LBB52_4: # %atomicrmw.end ; RV32-NEXT: mv a0, a4 @@ -3692,25 +3684,24 @@ ; RV64-NO-ATOMIC-NEXT: addi sp, sp, -32 ; RV64-NO-ATOMIC-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: sd s0, 16(sp) # 8-byte Folded Spill -; RV64-NO-ATOMIC-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: mv s0, a0 ; RV64-NO-ATOMIC-NEXT: ld a1, 0(a0) -; RV64-NO-ATOMIC-NEXT: li s1, 2 ; RV64-NO-ATOMIC-NEXT: j .LBB52_2 ; RV64-NO-ATOMIC-NEXT: .LBB52_1: # %atomicrmw.start ; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB52_2 Depth=1 -; RV64-NO-ATOMIC-NEXT: sd a1, 0(sp) -; RV64-NO-ATOMIC-NEXT: mv a1, sp +; RV64-NO-ATOMIC-NEXT: sd a1, 8(sp) +; RV64-NO-ATOMIC-NEXT: addi a1, sp, 8 ; RV64-NO-ATOMIC-NEXT: li a3, 5 ; RV64-NO-ATOMIC-NEXT: li a4, 5 ; RV64-NO-ATOMIC-NEXT: mv a0, s0 ; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_8@plt -; RV64-NO-ATOMIC-NEXT: ld a1, 0(sp) +; RV64-NO-ATOMIC-NEXT: ld a1, 8(sp) ; RV64-NO-ATOMIC-NEXT: bnez a0, .LBB52_4 ; RV64-NO-ATOMIC-NEXT: .LBB52_2: # %atomicrmw.start ; RV64-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 +; RV64-NO-ATOMIC-NEXT: li a0, 1 ; RV64-NO-ATOMIC-NEXT: mv a2, a1 -; RV64-NO-ATOMIC-NEXT: bltu a1, s1, .LBB52_1 +; RV64-NO-ATOMIC-NEXT: bgeu a0, a1, .LBB52_1 ; RV64-NO-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start ; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB52_2 Depth=1 ; RV64-NO-ATOMIC-NEXT: li a2, 1 @@ -3719,7 +3710,6 @@ ; RV64-NO-ATOMIC-NEXT: mv a0, a1 ; RV64-NO-ATOMIC-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: ld s0, 16(sp) # 8-byte Folded Reload -; RV64-NO-ATOMIC-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 32 ; RV64-NO-ATOMIC-NEXT: ret ; Index: llvm/test/CodeGen/RISCV/half-select-icmp.ll =================================================================== --- llvm/test/CodeGen/RISCV/half-select-icmp.ll +++ llvm/test/CodeGen/RISCV/half-select-icmp.ll @@ -157,42 +157,43 @@ define half @select_icmp_uge(i32 signext %a, i32 signext %b, half %c, half %d) { ; CHECK-LABEL: select_icmp_uge: ; CHECK: # %bb.0: -; CHECK-NEXT: bgeu a0, a1, .LBB3_2 +; CHECK-NEXT: bltu a0, a1, .LBB3_2 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: fmv.h fa0, fa1 +; CHECK-NEXT: fmv.h fa1, fa0 ; CHECK-NEXT: .LBB3_2: +; CHECK-NEXT: fmv.h fa0, fa1 ; CHECK-NEXT: ret ; ; CHECKIZHINX-LABEL: select_icmp_uge: ; CHECKIZHINX: # %bb.0: -; CHECKIZHINX-NEXT: bgeu a0, a1, .LBB3_2 +; CHECKIZHINX-NEXT: bltu a0, a1, .LBB3_2 ; CHECKIZHINX-NEXT: # %bb.1: -; CHECKIZHINX-NEXT: mv a2, a3 +; CHECKIZHINX-NEXT: mv a3, a2 ; CHECKIZHINX-NEXT: .LBB3_2: -; CHECKIZHINX-NEXT: mv a0, a2 +; CHECKIZHINX-NEXT: mv a0, a3 ; CHECKIZHINX-NEXT: ret ; ; CHECKIZFHMIN-LABEL: select_icmp_uge: ; CHECKIZFHMIN: # %bb.0: -; CHECKIZFHMIN-NEXT: bgeu a0, a1, .LBB3_2 +; CHECKIZFHMIN-NEXT: bltu a0, a1, .LBB3_2 ; CHECKIZFHMIN-NEXT: # %bb.1: -; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1 +; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5 ; CHECKIZFHMIN-NEXT: ret ; CHECKIZFHMIN-NEXT: .LBB3_2: -; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0 +; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5 ; CHECKIZFHMIN-NEXT: ret ; ; CHECKIZHINXMIN-LABEL: select_icmp_uge: ; CHECKIZHINXMIN: # %bb.0: -; CHECKIZHINXMIN-NEXT: bgeu a0, a1, .LBB3_2 +; CHECKIZHINXMIN-NEXT: bltu a0, a1, .LBB3_2 ; CHECKIZHINXMIN-NEXT: # %bb.1: -; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a3 +; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a2 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0 ; CHECKIZHINXMIN-NEXT: ret ; CHECKIZHINXMIN-NEXT: .LBB3_2: -; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a2 +; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a3 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0 ; CHECKIZHINXMIN-NEXT: ret %1 = icmp uge i32 %a, %b @@ -249,42 +250,43 @@ define half @select_icmp_ule(i32 signext %a, i32 signext %b, half %c, half %d) { ; CHECK-LABEL: select_icmp_ule: ; CHECK: # %bb.0: -; CHECK-NEXT: bgeu a1, a0, .LBB5_2 +; CHECK-NEXT: bltu a1, a0, .LBB5_2 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: fmv.h fa0, fa1 +; CHECK-NEXT: fmv.h fa1, fa0 ; CHECK-NEXT: .LBB5_2: +; CHECK-NEXT: fmv.h fa0, fa1 ; CHECK-NEXT: ret ; ; CHECKIZHINX-LABEL: select_icmp_ule: ; CHECKIZHINX: # %bb.0: -; CHECKIZHINX-NEXT: bgeu a1, a0, .LBB5_2 +; CHECKIZHINX-NEXT: bltu a1, a0, .LBB5_2 ; CHECKIZHINX-NEXT: # %bb.1: -; CHECKIZHINX-NEXT: mv a2, a3 +; CHECKIZHINX-NEXT: mv a3, a2 ; CHECKIZHINX-NEXT: .LBB5_2: -; CHECKIZHINX-NEXT: mv a0, a2 +; CHECKIZHINX-NEXT: mv a0, a3 ; CHECKIZHINX-NEXT: ret ; ; CHECKIZFHMIN-LABEL: select_icmp_ule: ; CHECKIZFHMIN: # %bb.0: -; CHECKIZFHMIN-NEXT: bgeu a1, a0, .LBB5_2 +; CHECKIZFHMIN-NEXT: bltu a1, a0, .LBB5_2 ; CHECKIZFHMIN-NEXT: # %bb.1: -; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1 +; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5 ; CHECKIZFHMIN-NEXT: ret ; CHECKIZFHMIN-NEXT: .LBB5_2: -; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0 +; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5 ; CHECKIZFHMIN-NEXT: ret ; ; CHECKIZHINXMIN-LABEL: select_icmp_ule: ; CHECKIZHINXMIN: # %bb.0: -; CHECKIZHINXMIN-NEXT: bgeu a1, a0, .LBB5_2 +; CHECKIZHINXMIN-NEXT: bltu a1, a0, .LBB5_2 ; CHECKIZHINXMIN-NEXT: # %bb.1: -; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a3 +; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a2 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0 ; CHECKIZHINXMIN-NEXT: ret ; CHECKIZHINXMIN-NEXT: .LBB5_2: -; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a2 +; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a3 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0 ; CHECKIZHINXMIN-NEXT: ret %1 = icmp ule i32 %a, %b @@ -341,42 +343,43 @@ define half @select_icmp_sge(i32 signext %a, i32 signext %b, half %c, half %d) { ; CHECK-LABEL: select_icmp_sge: ; CHECK: # %bb.0: -; CHECK-NEXT: bge a0, a1, .LBB7_2 +; CHECK-NEXT: blt a0, a1, .LBB7_2 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: fmv.h fa0, fa1 +; CHECK-NEXT: fmv.h fa1, fa0 ; CHECK-NEXT: .LBB7_2: +; CHECK-NEXT: fmv.h fa0, fa1 ; CHECK-NEXT: ret ; ; CHECKIZHINX-LABEL: select_icmp_sge: ; CHECKIZHINX: # %bb.0: -; CHECKIZHINX-NEXT: bge a0, a1, .LBB7_2 +; CHECKIZHINX-NEXT: blt a0, a1, .LBB7_2 ; CHECKIZHINX-NEXT: # %bb.1: -; CHECKIZHINX-NEXT: mv a2, a3 +; CHECKIZHINX-NEXT: mv a3, a2 ; CHECKIZHINX-NEXT: .LBB7_2: -; CHECKIZHINX-NEXT: mv a0, a2 +; CHECKIZHINX-NEXT: mv a0, a3 ; CHECKIZHINX-NEXT: ret ; ; CHECKIZFHMIN-LABEL: select_icmp_sge: ; CHECKIZFHMIN: # %bb.0: -; CHECKIZFHMIN-NEXT: bge a0, a1, .LBB7_2 +; CHECKIZFHMIN-NEXT: blt a0, a1, .LBB7_2 ; CHECKIZFHMIN-NEXT: # %bb.1: -; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1 +; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5 ; CHECKIZFHMIN-NEXT: ret ; CHECKIZFHMIN-NEXT: .LBB7_2: -; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0 +; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5 ; CHECKIZFHMIN-NEXT: ret ; ; CHECKIZHINXMIN-LABEL: select_icmp_sge: ; CHECKIZHINXMIN: # %bb.0: -; CHECKIZHINXMIN-NEXT: bge a0, a1, .LBB7_2 +; CHECKIZHINXMIN-NEXT: blt a0, a1, .LBB7_2 ; CHECKIZHINXMIN-NEXT: # %bb.1: -; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a3 +; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a2 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0 ; CHECKIZHINXMIN-NEXT: ret ; CHECKIZHINXMIN-NEXT: .LBB7_2: -; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a2 +; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a3 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0 ; CHECKIZHINXMIN-NEXT: ret %1 = icmp sge i32 %a, %b @@ -433,42 +436,43 @@ define half @select_icmp_sle(i32 signext %a, i32 signext %b, half %c, half %d) { ; CHECK-LABEL: select_icmp_sle: ; CHECK: # %bb.0: -; CHECK-NEXT: bge a1, a0, .LBB9_2 +; CHECK-NEXT: blt a1, a0, .LBB9_2 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: fmv.h fa0, fa1 +; CHECK-NEXT: fmv.h fa1, fa0 ; CHECK-NEXT: .LBB9_2: +; CHECK-NEXT: fmv.h fa0, fa1 ; CHECK-NEXT: ret ; ; CHECKIZHINX-LABEL: select_icmp_sle: ; CHECKIZHINX: # %bb.0: -; CHECKIZHINX-NEXT: bge a1, a0, .LBB9_2 +; CHECKIZHINX-NEXT: blt a1, a0, .LBB9_2 ; CHECKIZHINX-NEXT: # %bb.1: -; CHECKIZHINX-NEXT: mv a2, a3 +; CHECKIZHINX-NEXT: mv a3, a2 ; CHECKIZHINX-NEXT: .LBB9_2: -; CHECKIZHINX-NEXT: mv a0, a2 +; CHECKIZHINX-NEXT: mv a0, a3 ; CHECKIZHINX-NEXT: ret ; ; CHECKIZFHMIN-LABEL: select_icmp_sle: ; CHECKIZFHMIN: # %bb.0: -; CHECKIZFHMIN-NEXT: bge a1, a0, .LBB9_2 +; CHECKIZFHMIN-NEXT: blt a1, a0, .LBB9_2 ; CHECKIZFHMIN-NEXT: # %bb.1: -; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1 +; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5 ; CHECKIZFHMIN-NEXT: ret ; CHECKIZFHMIN-NEXT: .LBB9_2: -; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0 +; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5 ; CHECKIZFHMIN-NEXT: ret ; ; CHECKIZHINXMIN-LABEL: select_icmp_sle: ; CHECKIZHINXMIN: # %bb.0: -; CHECKIZHINXMIN-NEXT: bge a1, a0, .LBB9_2 +; CHECKIZHINXMIN-NEXT: blt a1, a0, .LBB9_2 ; CHECKIZHINXMIN-NEXT: # %bb.1: -; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a3 +; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a2 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0 ; CHECKIZHINXMIN-NEXT: ret ; CHECKIZHINXMIN-NEXT: .LBB9_2: -; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a2 +; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a3 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0 ; CHECKIZHINXMIN-NEXT: ret %1 = icmp sle i32 %a, %b Index: llvm/test/CodeGen/RISCV/select-cc.ll =================================================================== --- llvm/test/CodeGen/RISCV/select-cc.ll +++ llvm/test/CodeGen/RISCV/select-cc.ll @@ -23,17 +23,17 @@ ; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: .LBB0_6: ; RV32I-NEXT: lw a2, 0(a1) -; RV32I-NEXT: bgeu a0, a2, .LBB0_8 +; RV32I-NEXT: bltu a0, a2, .LBB0_8 ; RV32I-NEXT: # %bb.7: -; RV32I-NEXT: mv a0, a2 +; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: .LBB0_8: -; RV32I-NEXT: lw a2, 0(a1) -; RV32I-NEXT: bltu a0, a2, .LBB0_10 +; RV32I-NEXT: lw a0, 0(a1) +; RV32I-NEXT: bltu a2, a0, .LBB0_10 ; RV32I-NEXT: # %bb.9: -; RV32I-NEXT: mv a0, a2 +; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: .LBB0_10: -; RV32I-NEXT: lw a2, 0(a1) -; RV32I-NEXT: bgeu a2, a0, .LBB0_12 +; RV32I-NEXT: lw a0, 0(a1) +; RV32I-NEXT: bltu a0, a2, .LBB0_12 ; RV32I-NEXT: # %bb.11: ; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: .LBB0_12: @@ -43,17 +43,17 @@ ; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: .LBB0_14: ; RV32I-NEXT: lw a2, 0(a1) -; RV32I-NEXT: bge a0, a2, .LBB0_16 +; RV32I-NEXT: blt a0, a2, .LBB0_16 ; RV32I-NEXT: # %bb.15: -; RV32I-NEXT: mv a0, a2 +; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: .LBB0_16: -; RV32I-NEXT: lw a2, 0(a1) -; RV32I-NEXT: blt a0, a2, .LBB0_18 +; RV32I-NEXT: lw a0, 0(a1) +; RV32I-NEXT: blt a2, a0, .LBB0_18 ; RV32I-NEXT: # %bb.17: -; RV32I-NEXT: mv a0, a2 +; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: .LBB0_18: -; RV32I-NEXT: lw a2, 0(a1) -; RV32I-NEXT: bge a2, a0, .LBB0_20 +; RV32I-NEXT: lw a0, 0(a1) +; RV32I-NEXT: blt a0, a2, .LBB0_20 ; RV32I-NEXT: # %bb.19: ; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: .LBB0_20: @@ -99,17 +99,17 @@ ; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: .LBB0_6: ; RV64I-NEXT: lw a2, 0(a1) -; RV64I-NEXT: bgeu a0, a2, .LBB0_8 +; RV64I-NEXT: bltu a0, a2, .LBB0_8 ; RV64I-NEXT: # %bb.7: -; RV64I-NEXT: mv a0, a2 +; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: .LBB0_8: -; RV64I-NEXT: lw a2, 0(a1) -; RV64I-NEXT: bltu a0, a2, .LBB0_10 +; RV64I-NEXT: lw a0, 0(a1) +; RV64I-NEXT: bltu a2, a0, .LBB0_10 ; RV64I-NEXT: # %bb.9: -; RV64I-NEXT: mv a0, a2 +; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: .LBB0_10: -; RV64I-NEXT: lw a2, 0(a1) -; RV64I-NEXT: bgeu a2, a0, .LBB0_12 +; RV64I-NEXT: lw a0, 0(a1) +; RV64I-NEXT: bltu a0, a2, .LBB0_12 ; RV64I-NEXT: # %bb.11: ; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: .LBB0_12: @@ -119,17 +119,17 @@ ; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: .LBB0_14: ; RV64I-NEXT: lw a2, 0(a1) -; RV64I-NEXT: bge a0, a2, .LBB0_16 +; RV64I-NEXT: blt a0, a2, .LBB0_16 ; RV64I-NEXT: # %bb.15: -; RV64I-NEXT: mv a0, a2 +; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: .LBB0_16: -; RV64I-NEXT: lw a2, 0(a1) -; RV64I-NEXT: blt a0, a2, .LBB0_18 +; RV64I-NEXT: lw a0, 0(a1) +; RV64I-NEXT: blt a2, a0, .LBB0_18 ; RV64I-NEXT: # %bb.17: -; RV64I-NEXT: mv a0, a2 +; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: .LBB0_18: -; RV64I-NEXT: lw a2, 0(a1) -; RV64I-NEXT: bge a2, a0, .LBB0_20 +; RV64I-NEXT: lw a0, 0(a1) +; RV64I-NEXT: blt a0, a2, .LBB0_20 ; RV64I-NEXT: # %bb.19: ; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: .LBB0_20: @@ -277,23 +277,21 @@ ; RV32I-LABEL: select_sge_int16min: ; RV32I: # %bb.0: ; RV32I-NEXT: lui a3, 1048560 -; RV32I-NEXT: addi a3, a3, -1 -; RV32I-NEXT: blt a3, a0, .LBB2_2 +; RV32I-NEXT: blt a0, a3, .LBB2_2 ; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: mv a1, a2 +; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: .LBB2_2: -; RV32I-NEXT: mv a0, a1 +; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: ret ; ; RV64I-LABEL: select_sge_int16min: ; RV64I: # %bb.0: ; RV64I-NEXT: lui a3, 1048560 -; RV64I-NEXT: addiw a3, a3, -1 -; RV64I-NEXT: blt a3, a0, .LBB2_2 +; RV64I-NEXT: blt a0, a3, .LBB2_2 ; RV64I-NEXT: # %bb.1: -; RV64I-NEXT: mv a1, a2 +; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: .LBB2_2: -; RV64I-NEXT: mv a0, a1 +; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: ret %a = icmp sge i32 %x, -65536 %b = select i1 %a, i32 %y, i32 %z @@ -307,29 +305,28 @@ ; RV32I-NEXT: bne a1, a6, .LBB3_2 ; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: j .LBB3_3 ; RV32I-NEXT: .LBB3_2: -; RV32I-NEXT: slti a0, a1, 0 -; RV32I-NEXT: xori a0, a0, 1 +; RV32I-NEXT: slti a0, a1, -1 ; RV32I-NEXT: .LBB3_3: ; RV32I-NEXT: bnez a0, .LBB3_5 ; RV32I-NEXT: # %bb.4: -; RV32I-NEXT: mv a2, a4 -; RV32I-NEXT: mv a3, a5 +; RV32I-NEXT: mv a4, a2 +; RV32I-NEXT: mv a5, a3 ; RV32I-NEXT: .LBB3_5: -; RV32I-NEXT: mv a0, a2 -; RV32I-NEXT: mv a1, a3 +; RV32I-NEXT: mv a0, a4 +; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: ret ; ; RV64I-LABEL: select_sge_int32min: ; RV64I: # %bb.0: ; RV64I-NEXT: lui a3, 524288 -; RV64I-NEXT: addi a3, a3, -1 -; RV64I-NEXT: blt a3, a0, .LBB3_2 +; RV64I-NEXT: blt a0, a3, .LBB3_2 ; RV64I-NEXT: # %bb.1: -; RV64I-NEXT: mv a1, a2 +; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: .LBB3_2: -; RV64I-NEXT: mv a0, a1 +; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: ret %a = icmp sge i64 %x, -2147483648 %b = select i1 %a, i64 %y, i64 %z Index: llvm/test/CodeGen/RISCV/select-constant-xor.ll =================================================================== --- llvm/test/CodeGen/RISCV/select-constant-xor.ll +++ llvm/test/CodeGen/RISCV/select-constant-xor.ll @@ -215,11 +215,11 @@ ; RV32: # %bb.0: ; RV32-NEXT: srai a3, a0, 31 ; RV32-NEXT: xori a3, a3, 127 -; RV32-NEXT: bltz a0, .LBB10_2 +; RV32-NEXT: bgez a0, .LBB10_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: mv a2, a1 +; RV32-NEXT: mv a1, a2 ; RV32-NEXT: .LBB10_2: -; RV32-NEXT: add a0, a3, a2 +; RV32-NEXT: add a0, a3, a1 ; RV32-NEXT: ret ; ; RV64-LABEL: oneusecmp: @@ -227,11 +227,11 @@ ; RV64-NEXT: sext.w a3, a0 ; RV64-NEXT: sraiw a0, a0, 31 ; RV64-NEXT: xori a0, a0, 127 -; RV64-NEXT: bltz a3, .LBB10_2 +; RV64-NEXT: bgez a3, .LBB10_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: mv a2, a1 +; RV64-NEXT: mv a1, a2 ; RV64-NEXT: .LBB10_2: -; RV64-NEXT: addw a0, a0, a2 +; RV64-NEXT: addw a0, a0, a1 ; RV64-NEXT: ret %c = icmp sle i32 %a, -1 %s = select i1 %c, i32 -128, i32 127 Index: llvm/test/CodeGen/RISCV/xaluo.ll =================================================================== --- llvm/test/CodeGen/RISCV/xaluo.ll +++ llvm/test/CodeGen/RISCV/xaluo.ll @@ -3951,7 +3951,7 @@ ; RV32-NEXT: sltu a0, a3, a0 ; RV32-NEXT: add a4, a1, a0 ; RV32-NEXT: sltu a1, a4, a1 -; RV32-NEXT: and a0, a0, a1 +; RV32-NEXT: and a0, a1, a0 ; RV32-NEXT: sw a3, 0(a2) ; RV32-NEXT: sw a4, 4(a2) ; RV32-NEXT: ret @@ -3969,7 +3969,7 @@ ; RV32ZBA-NEXT: sltu a0, a3, a0 ; RV32ZBA-NEXT: add a4, a1, a0 ; RV32ZBA-NEXT: sltu a1, a4, a1 -; RV32ZBA-NEXT: and a0, a0, a1 +; RV32ZBA-NEXT: and a0, a1, a0 ; RV32ZBA-NEXT: sw a3, 0(a2) ; RV32ZBA-NEXT: sw a4, 4(a2) ; RV32ZBA-NEXT: ret @@ -3996,7 +3996,7 @@ ; RV32-NEXT: sltu a0, a3, a0 ; RV32-NEXT: add a4, a1, a0 ; RV32-NEXT: sltu a1, a4, a1 -; RV32-NEXT: and a0, a0, a1 +; RV32-NEXT: and a0, a1, a0 ; RV32-NEXT: sw a3, 0(a2) ; RV32-NEXT: sw a4, 4(a2) ; RV32-NEXT: ret @@ -4016,7 +4016,7 @@ ; RV32ZBA-NEXT: sltu a0, a3, a0 ; RV32ZBA-NEXT: add a4, a1, a0 ; RV32ZBA-NEXT: sltu a1, a4, a1 -; RV32ZBA-NEXT: and a0, a0, a1 +; RV32ZBA-NEXT: and a0, a1, a0 ; RV32ZBA-NEXT: sw a3, 0(a2) ; RV32ZBA-NEXT: sw a4, 4(a2) ; RV32ZBA-NEXT: ret @@ -4044,7 +4044,7 @@ ; RV32-NEXT: sltu a0, a3, a0 ; RV32-NEXT: add a4, a1, a0 ; RV32-NEXT: sltu a1, a4, a1 -; RV32-NEXT: and a0, a0, a1 +; RV32-NEXT: and a0, a1, a0 ; RV32-NEXT: sw a3, 0(a2) ; RV32-NEXT: sw a4, 4(a2) ; RV32-NEXT: ret @@ -4064,7 +4064,7 @@ ; RV32ZBA-NEXT: sltu a0, a3, a0 ; RV32ZBA-NEXT: add a4, a1, a0 ; RV32ZBA-NEXT: sltu a1, a4, a1 -; RV32ZBA-NEXT: and a0, a0, a1 +; RV32ZBA-NEXT: and a0, a1, a0 ; RV32ZBA-NEXT: sw a3, 0(a2) ; RV32ZBA-NEXT: sw a4, 4(a2) ; RV32ZBA-NEXT: ret @@ -4093,7 +4093,7 @@ ; RV32-NEXT: sltu a3, a0, a1 ; RV32-NEXT: add a1, a2, a3 ; RV32-NEXT: sltu a2, a1, a2 -; RV32-NEXT: and a2, a3, a2 +; RV32-NEXT: and a2, a2, a3 ; RV32-NEXT: bnez a2, .LBB69_2 ; RV32-NEXT: # %bb.1: # %IfOverflow ; RV32-NEXT: li a0, 0 @@ -4119,7 +4119,7 @@ ; RV32ZBA-NEXT: sltu a3, a0, a1 ; RV32ZBA-NEXT: add a1, a2, a3 ; RV32ZBA-NEXT: sltu a2, a1, a2 -; RV32ZBA-NEXT: and a2, a3, a2 +; RV32ZBA-NEXT: and a2, a2, a3 ; RV32ZBA-NEXT: bnez a2, .LBB69_2 ; RV32ZBA-NEXT: # %bb.1: # %IfOverflow ; RV32ZBA-NEXT: li a0, 0