Index: include/llvm/Support/ELFRelocs/Mips.def
===================================================================
--- include/llvm/Support/ELFRelocs/Mips.def
+++ include/llvm/Support/ELFRelocs/Mips.def
@@ -108,7 +108,7 @@
 ELF_RELOC(R_MICROMIPS_TLS_TPREL_LO16,   170)
 ELF_RELOC(R_MICROMIPS_GPREL7_S2,        172)
 ELF_RELOC(R_MICROMIPS_PC23_S2,          173)
-ELF_RELOC(R_MICROMIPS_PC21_S2,          174)
+ELF_RELOC(R_MICROMIPS_PC21_S1,          174)
 ELF_RELOC(R_MICROMIPS_PC26_S2,          175)
 ELF_RELOC(R_MICROMIPS_PC18_S3,          176)
 ELF_RELOC(R_MICROMIPS_PC19_S2,          177)
Index: lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
===================================================================
--- lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
+++ lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
@@ -160,6 +160,15 @@
       return 0;
     }
     break;
+  case Mips::fixup_MICROMIPS_PC21_S1:
+    // Forcing a signed division because Value can be negative.
+    Value = (int64_t)Value / 2;
+    // We now check if Value can be encoded as a 21-bit signed immediate.
+    if (!isInt<21>(Value) && Ctx) {
+      Ctx->reportError(Fixup.getLoc(), "out of range PC21 fixup");
+      return 0;
+    }
+    break;
   }
 
   return Value;
@@ -316,6 +325,7 @@
     { "fixup_MICROMIPS_PC7_S1",  0,      7,   MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MICROMIPS_PC10_S1", 0,     10,   MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MICROMIPS_PC16_S1", 0,     16,   MCFixupKindInfo::FKF_IsPCRel },
+    { "fixup_MICROMIPS_PC21_S1", 0,     21,   MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MICROMIPS_CALL16",  0,     16,   0 },
     { "fixup_MICROMIPS_GOT_DISP",        0,     16,   0 },
     { "fixup_MICROMIPS_GOT_PAGE",        0,     16,   0 },
@@ -382,6 +392,7 @@
     { "fixup_MICROMIPS_PC7_S1",  9,      7,   MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MICROMIPS_PC10_S1", 6,     10,   MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MICROMIPS_PC16_S1",16,     16,   MCFixupKindInfo::FKF_IsPCRel },
+    { "fixup_MICROMIPS_PC21_S1",11,     21,   MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MICROMIPS_CALL16", 16,     16,   0 },
     { "fixup_MICROMIPS_GOT_DISP",        16,     16,   0 },
     { "fixup_MICROMIPS_GOT_PAGE",        16,     16,   0 },
Index: lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp
===================================================================
--- lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp
+++ lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp
@@ -89,6 +89,8 @@
       return ELF::R_MICROMIPS_PC10_S1;
     case Mips::fixup_MICROMIPS_PC16_S1:
       return ELF::R_MICROMIPS_PC16_S1;
+    case Mips::fixup_MICROMIPS_PC21_S1:
+      return ELF::R_MICROMIPS_PC21_S1;
     case Mips::fixup_MIPS_PC19_S2:
       return ELF::R_MIPS_PC19_S2;
     case Mips::fixup_MIPS_PC18_S3:
Index: lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h
===================================================================
--- lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h
+++ lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h
@@ -170,6 +170,9 @@
     // resulting in - R_MICROMIPS_PC16_S1
     fixup_MICROMIPS_PC16_S1,
 
+    // resulting in - R_MICROMIPS_PC21_S1
+    fixup_MICROMIPS_PC21_S1,
+
     // resulting in - R_MICROMIPS_CALL16
     fixup_MICROMIPS_CALL16,
 
Index: lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
===================================================================
--- lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
+++ lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
@@ -343,7 +343,10 @@
   assert(MO.isExpr() &&
     "getBranchTarget21OpValueMM expects only expressions or immediates");
 
-  // TODO: Push fixup.
+  const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
+      MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
+  Fixups.push_back(MCFixup::create(0, FixupExpression,
+                                   MCFixupKind(Mips::fixup_MICROMIPS_PC21_S1)));
   return 0;
 }
 
Index: test/MC/Mips/micromips32r6/relocations.s
===================================================================
--- /dev/null
+++ test/MC/Mips/micromips32r6/relocations.s
@@ -0,0 +1,24 @@
+# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \
+# RUN:   -mattr=micromips | FileCheck %s -check-prefix=CHECK-FIXUP
+# RUN: llvm-mc %s -filetype=obj -triple=mips-unknown-linux -mcpu=mips32r6 \
+# RUN:   -mattr=micromips | llvm-readobj -r | FileCheck %s -check-prefix=CHECK-ELF
+#------------------------------------------------------------------------------
+# Check that the assembler can handle the documented syntax for fixups.
+#------------------------------------------------------------------------------
+# CHECK-FIXUP: beqzc $3, bar        # encoding: [0x80,0b011AAAAA,A,A]
+# CHECK-FIXUP:                      #   fixup A - offset: 0,
+# CHECK-FIXUP:                          value: bar-4, kind: fixup_MICROMIPS_PC21_S1
+# CHECK-FIXUP: bnezc $3, bar        # encoding: [0xa0,0b011AAAAA,A,A]
+# CHECK-FIXUP:                      #   fixup A - offset: 0,
+# CHECK-FIXUP:                          value: bar-4, kind: fixup_MICROMIPS_PC21_S1
+#------------------------------------------------------------------------------
+# Check that the appropriate relocations were created.
+#------------------------------------------------------------------------------
+# CHECK-ELF: Relocations [
+# CHECK-ELF:     0x0 R_MICROMIPS_PC21_S1 bar 0x0
+# CHECK-ELF:     0x4 R_MICROMIPS_PC21_S1 bar 0x0
+# CHECK-ELF: ]
+
+  beqzc  $3, bar
+  bnezc  $3, bar
+
Index: test/MC/Mips/micromips64r6/relocations.s
===================================================================
--- /dev/null
+++ test/MC/Mips/micromips64r6/relocations.s
@@ -0,0 +1,24 @@
+# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r6 \
+# RUN:   -mattr=micromips | FileCheck %s -check-prefix=CHECK-FIXUP
+# RUN: llvm-mc %s -filetype=obj -triple=mips-unknown-linux -mcpu=mips64r6 \
+# RUN:   -mattr=micromips | llvm-readobj -r | FileCheck %s -check-prefix=CHECK-ELF
+#------------------------------------------------------------------------------
+# Check that the assembler can handle the documented syntax for fixups.
+#------------------------------------------------------------------------------
+# CHECK-FIXUP: beqzc $3, bar        # encoding: [0x80,0b011AAAAA,A,A]
+# CHECK-FIXUP:                      #   fixup A - offset: 0,
+# CHECK-FIXUP:                          value: bar-4, kind: fixup_MICROMIPS_PC21_S1
+# CHECK-FIXUP: bnezc $3, bar        # encoding: [0xa0,0b011AAAAA,A,A]
+# CHECK-FIXUP:                      #   fixup A - offset: 0,
+# CHECK-FIXUP:                          value: bar-4, kind: fixup_MICROMIPS_PC21_S1
+#------------------------------------------------------------------------------
+# Check that the appropriate relocations were created.
+#------------------------------------------------------------------------------
+# CHECK-ELF: Relocations [
+# CHECK-ELF:     0x0 R_MICROMIPS_PC21_S1 bar 0x0
+# CHECK-ELF:     0x4 R_MICROMIPS_PC21_S1 bar 0x0
+# CHECK-ELF: ]
+
+  beqzc  $3, bar
+  bnezc  $3, bar
+