diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -700,6 +700,10 @@ - Add ISA of ``AMX-COMPLEX`` which supports ``tcmmimfp16ps`` and ``tcmmrlfp16ps``. +- Support ISA of ``SM3``. + * Support intrinsic of ``_mm_sm3msg1_epi32``. + * Support intrinsic of ``_mm_sm3msg2_epi32``. + * Support intrinsic of ``_mm_sm3rnds2_epi32``. Arm and AArch64 Support ^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/clang/include/clang/Basic/BuiltinsX86.def b/clang/include/clang/Basic/BuiltinsX86.def --- a/clang/include/clang/Basic/BuiltinsX86.def +++ b/clang/include/clang/Basic/BuiltinsX86.def @@ -2141,6 +2141,11 @@ TARGET_HEADER_BUILTIN(_InterlockedOr64, "WiWiD*Wi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedXor64, "WiWiD*Wi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "") +// SM3 +TARGET_BUILTIN(__builtin_ia32_vsm3msg1, "V4UiV4UiV4UiV4Ui", "nV:128:", "sm3") +TARGET_BUILTIN(__builtin_ia32_vsm3msg2, "V4UiV4UiV4UiV4Ui", "nV:128:", "sm3") +TARGET_BUILTIN(__builtin_ia32_vsm3rnds2, "V4UiV4UiV4UiV4UiIUi", "nV:128:", "sm3") + #undef BUILTIN #undef TARGET_BUILTIN #undef TARGET_HEADER_BUILTIN diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -5043,6 +5043,8 @@ def mno_sgx : Flag<["-"], "mno-sgx">, Group; def msha : Flag<["-"], "msha">, Group; def mno_sha : Flag<["-"], "mno-sha">, Group; +def msm3 : Flag<["-"], "msm3">, Group; +def mno_sm3 : Flag<["-"], "mno-sm3">, Group; def mtbm : Flag<["-"], "mtbm">, Group; def mno_tbm : Flag<["-"], "mno-tbm">, Group; def mtsxldtrk : Flag<["-"], "mtsxldtrk">, Group; diff --git a/clang/lib/Basic/Targets/X86.h b/clang/lib/Basic/Targets/X86.h --- a/clang/lib/Basic/Targets/X86.h +++ b/clang/lib/Basic/Targets/X86.h @@ -113,6 +113,7 @@ bool HasAVX512VP2INTERSECT = false; bool HasSHA = false; bool HasSHSTK = false; + bool HasSM3 = false; bool HasSGX = false; bool HasCX8 = false; bool HasCX16 = false; diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp --- a/clang/lib/Basic/Targets/X86.cpp +++ b/clang/lib/Basic/Targets/X86.cpp @@ -263,6 +263,8 @@ HasSHA = true; } else if (Feature == "+shstk") { HasSHSTK = true; + } else if (Feature == "+sm3") { + HasSM3 = true; } else if (Feature == "+movbe") { HasMOVBE = true; } else if (Feature == "+sgx") { @@ -772,6 +774,8 @@ Builder.defineMacro("__SHSTK__"); if (HasSGX) Builder.defineMacro("__SGX__"); + if (HasSM3) + Builder.defineMacro("__SM3__"); if (HasPREFETCHI) Builder.defineMacro("__PREFETCHI__"); if (HasPREFETCHWT1) @@ -1000,6 +1004,7 @@ .Case("sgx", true) .Case("sha", true) .Case("shstk", true) + .Case("sm3", true) .Case("sse", true) .Case("sse2", true) .Case("sse3", true) @@ -1105,6 +1110,7 @@ .Case("sgx", HasSGX) .Case("sha", HasSHA) .Case("shstk", HasSHSTK) + .Case("sm3", HasSM3) .Case("sse", SSELevel >= SSE1) .Case("sse2", SSELevel >= SSE2) .Case("sse3", SSELevel >= SSE3) diff --git a/clang/lib/Headers/CMakeLists.txt b/clang/lib/Headers/CMakeLists.txt --- a/clang/lib/Headers/CMakeLists.txt +++ b/clang/lib/Headers/CMakeLists.txt @@ -204,6 +204,7 @@ serializeintrin.h sgxintrin.h shaintrin.h + sm3intrin.h smmintrin.h tbmintrin.h tmmintrin.h diff --git a/clang/lib/Headers/immintrin.h b/clang/lib/Headers/immintrin.h --- a/clang/lib/Headers/immintrin.h +++ b/clang/lib/Headers/immintrin.h @@ -269,6 +269,11 @@ #include #endif +#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) || \ + defined(__SM3__) +#include +#endif + #if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) || \ defined(__RDPID__) /// Returns the value of the IA32_TSC_AUX MSR (0xc0000103). diff --git a/clang/lib/Headers/sm3intrin.h b/clang/lib/Headers/sm3intrin.h new file mode 100644 --- /dev/null +++ b/clang/lib/Headers/sm3intrin.h @@ -0,0 +1,235 @@ +/*===-------------------- sm3intrin.h - SM3 intrinsics ---------------------=== + * + * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. + * See https://llvm.org/LICENSE.txt for license information. + * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception + * + *===-----------------------------------------------------------------------=== + */ + +#ifndef __IMMINTRIN_H +#error "Never use directly; include instead." +#endif // __IMMINTRIN_H + +#ifndef __SM3INTRIN_H +#define __SM3INTRIN_H + +#define __DEFAULT_FN_ATTRS128 \ + __attribute__((__always_inline__, __nodebug__, __target__("sm3"), \ + __min_vector_width__(128))) + +/// The VSM3MSG1 instruction is one of the two SM3 message scheduling +/// intrinsics. The intrinsic performs an initial calculation for the next +/// four SM3 message words. The calculated results are stored in \a dst. +/// +/// \headerfile +/// +/// \code +/// _mm_sm3msg1_epi32(__m128i __A, __m128i __B, __m128i __C) +/// \endcode +/// +/// This intrinsic corresponds to the \c VPDPBSSD instruction. +/// +/// \param __A +/// A 128-bit vector of [4 x int]. +/// \param __B +/// A 128-bit vector of [4 x int]. +/// \param __C +/// A 128-bit vector of [4 x int]. +/// \returns +/// A 128-bit vector of [4 x int]. +/// +/// \code{.operation} +/// DEFINE ROL32(dword, n) { +/// count := n % 32 +/// dest := (dword << count) | (dword >> (32 - count)) +/// RETURN dest +/// } +/// DEFINE P1(x) { +/// RETURN x ^ ROL32(x, 15) ^ ROL32(x, 23) +/// } +/// W[0] := __C.dword[0] +/// W[1] := __C.dword[1] +/// W[2] := __C.dword[2] +/// W[3] := __C.dword[3] +/// W[7] := __A.dword[0] +/// W[8] := __A.dword[1] +/// W[9] := __A.dword[2] +/// W[10] := __A.dword[3] +/// W[13] := __B.dword[0] +/// W[14] := __B.dword[1] +/// W[15] := __B.dword[2] +/// TMP0 := W[7] ^ W[0] ^ ROL32(W[13], 15) +/// TMP1 := W[8] ^ W[1] ^ ROL32(W[14], 15) +/// TMP2 := W[9] ^ W[2] ^ ROL32(W[15], 15) +/// TMP3 := W[10] ^ W[3] +/// dst.dword[0] := P1(TMP0) +/// dst.dword[1] := P1(TMP1) +/// dst.dword[2] := P1(TMP2) +/// dst.dword[3] := P1(TMP3) +/// \endcode +static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_sm3msg1_epi32(__m128i __A, + __m128i __B, + __m128i __C) { + return (__m128i)__builtin_ia32_vsm3msg1((__v4su)__A, (__v4su)__B, + (__v4su)__C); +} + +/// The VSM3MSG1 instruction is one of the two SM3 message scheduling +/// intrinsics. The intrinsic performs the final calculation for the next +/// four SM3 message words. The calculated results are stored in \a dst. +/// +/// \headerfile +/// +/// \code +/// _mm_sm3msg2_epi32(__m128i __A, __m128i __B, __m128i __C) +/// \endcode +/// +/// This intrinsic corresponds to the \c VPDPBSSD instruction. +/// +/// \param __A +/// A 128-bit vector of [4 x int]. +/// \param __B +/// A 128-bit vector of [4 x int]. +/// \param __C +/// A 128-bit vector of [4 x int]. +/// \returns +/// A 128-bit vector of [4 x int]. +/// +/// \code{.operation} +/// DEFINE ROL32(dword, n) { +/// count := n % 32 +/// dest := (dword << count) | (dword >> (32-count)) +/// RETURN dest +/// } +/// WTMP[0] := __A.dword[0] +/// WTMP[1] := __A.dword[1] +/// WTMP[2] := __A.dword[2] +/// WTMP[3] := __A.dword[3] +/// W[3] := __B.dword[0] +/// W[4] := __B.dword[1] +/// W[5] := __B.dword[2] +/// W[6] := __B.dword[3] +/// W[10] := __C.dword[0] +/// W[11] := __C.dword[1] +/// W[12] := __C.dword[2] +/// W[13] := __C.dword[3] +/// W[16] := ROL32(W[3], 7) ^ W[10] ^ WTMP[0] +/// W[17] := ROL32(W[4], 7) ^ W[11] ^ WTMP[1] +/// W[18] := ROL32(W[5], 7) ^ W[12] ^ WTMP[2] +/// W[19] := ROL32(W[6], 7) ^ W[13] ^ WTMP[3] +/// W[19] := W[19] ^ ROL32(W[16], 6) ^ ROL32(W[16], 15) ^ ROL32(W[16], 30) +/// dst.dword[0] := W[16] +/// dst.dword[1] := W[17] +/// dst.dword[2] := W[18] +/// dst.dword[3] := W[19] +/// \endcode +static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_sm3msg2_epi32(__m128i __A, + __m128i __B, + __m128i __C) { + return (__m128i)__builtin_ia32_vsm3msg2((__v4su)__A, (__v4su)__B, + (__v4su)__C); +} + +/// The intrinsic performs two rounds of SM3 operation using initial SM3 state +/// (C, D, G, H) from \a __A, an initial SM3 states (A, B, E, F) +/// from \a __B and a pre-computed words from the \a __C. \a __A with +/// initial SM3 state of (C, D, G, H) assumes input of non-rotated left +/// variables from previous state. The updated SM3 state (A, B, E, F) is +/// written to \a __A. The \a imm8 should contain the even round number +/// for the first of the two rounds computed by this instruction. The +/// computation masks the \a imm8 value by AND’ing it with 0x3E so that only +/// even round numbers from 0 through 62 are used for this operation. The +/// calculated results are stored in \a dst. +/// +/// \headerfile +/// +/// \code +/// _mm_sm3rnds2_epi32(__m128i __A, __m128i __B, __m128i __C, const int imm8) +/// \endcode +/// +/// This intrinsic corresponds to the \c VPDPBSSD instruction. +/// +/// \param __A +/// A 128-bit vector of [4 x int]. +/// \param __B +/// A 128-bit vector of [4 x int]. +/// \param __C +/// A 128-bit vector of [4 x int]. +/// \param imm8 +/// A 128-bit vector of [4 x int]. +/// \returns +/// A 32-bit int. +/// +/// \code{.operation} +/// DEFINE ROL32(dword, n) { +/// count := n % 32 +/// dest := (dword << count) | (dword >> (32-count)) +/// RETURN dest +/// } +/// DEFINE P0(dword) { +/// RETURN dword ^ ROL32(dword, 9) ^ ROL32(dword, 17) +/// } +/// DEFINE FF(x,y,z, round){ +/// IF round < 16 +/// RETURN (x ^ y ^ z) +/// ELSE +/// RETURN (x & y) | (x & z) | (y & z) +/// FI +/// } +/// DEFINE GG(x, y, z, round){ +/// IF round < 16 +/// RETURN (x ^ y ^ z) +/// ELSE +/// RETURN (x & y) | (~x & z) +/// FI +/// } +/// A[0] := __B.dword[3] +/// B[0] := __B.dword[2] +/// C[0] := __A.dword[3] +/// D[0] := __A.dword[2] +/// E[0] := __B.dword[1] +/// F[0] := __B.dword[0] +/// G[0] := __A.dword[1] +/// H[0] := __A.dword[0] +/// W[0] := __C.dword[0] +/// W[1] := __C.dword[1] +/// W[4] := __C.dword[2] +/// W[5] := __C.dword[3] +/// C[0] := ROL32(C[0], 9) +/// D[0] := ROL32(D[0], 9) +/// G[0] := ROL32(G[0], 19) +/// H[0] := ROL32(H[0], 19) +/// ROUND := __D & 0x3E +/// IF ROUND < 16 +/// CONST := 0x79CC4519 +/// ELSE +/// CONST := 0x7A879D8A +/// FI +/// CONST := ROL32(CONST,ROUND) +/// FOR i:= 0 to 1 +/// S1 := ROL32((ROL32(A[i], 12) + E[i] + CONST), 7) +/// S2 := S1 ^ ROL32(A[i], 12) +/// T1 := FF(A[i], B[i], C[i], ROUND) + D[i] + S2 + (W[i] ^ W[i+4]) +/// T2 := GG(E[i], F[i], G[i], ROUND) + H[i] + S1 + W[i] +/// D[i+1] := C[i] +/// C[i+1] := ROL32(B[i],9) +/// B[i+1] := A[i] +/// A[i+1] := T1 +/// H[i+1] := G[i] +/// G[i+1] := ROL32(F[i], 19) +/// F[i+1] := E[i] +/// E[i+1] := P0(T2) +/// CONST := ROL32(CONST, 1) +/// ENDFOR +/// dst.dword[3] := A[2] +/// dst.dword[2] := B[2] +/// dst.dword[1] := E[2] +/// dst.dword[0] := F[2] +/// \endcode +#define _mm_sm3rnds2_epi32(A, B, C, D) \ + (__m128i) __builtin_ia32_vsm3rnds2((__v4su)A, (__v4su)B, (__v4su)C, (int)D) + +#undef __DEFAULT_FN_ATTRS128 + +#endif // __SM3INTRIN_H diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp --- a/clang/lib/Sema/SemaChecking.cpp +++ b/clang/lib/Sema/SemaChecking.cpp @@ -5864,6 +5864,7 @@ case X86::BI__builtin_ia32_pternlogq128_maskz: case X86::BI__builtin_ia32_pternlogq256_mask: case X86::BI__builtin_ia32_pternlogq256_maskz: + case X86::BI__builtin_ia32_vsm3rnds2: i = 3; l = 0; u = 255; break; case X86::BI__builtin_ia32_gatherpfdpd: diff --git a/clang/test/CodeGen/X86/sm3-builtins.c b/clang/test/CodeGen/X86/sm3-builtins.c new file mode 100644 --- /dev/null +++ b/clang/test/CodeGen/X86/sm3-builtins.c @@ -0,0 +1,22 @@ +// RUN: %clang_cc1 %s -ffreestanding -triple=x86_64-unknown-unknown -target-feature +sm3 -emit-llvm -o - -Wall -Werror | FileCheck %s +// RUN: %clang_cc1 %s -ffreestanding -triple=i386-unknown-unknown -target-feature +sm3 -emit-llvm -o - -Wall -Werror | FileCheck %s + +#include + +__m128i test_mm_sm3msg1_epi32(__m128i __A, __m128i __B, __m128i __C) { + // CHECK-LABEL: @test_mm_sm3msg1_epi32( + // CHECK: call <4 x i32> @llvm.x86.vsm3msg1(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> %{{.*}}) + return _mm_sm3msg1_epi32(__A, __B, __C); +} + +__m128i test_mm_sm3msg2_epi32(__m128i __A, __m128i __B, __m128i __C) { + // CHECK-LABEL: @test_mm_sm3msg2_epi32( + // CHECK: call <4 x i32> @llvm.x86.vsm3msg2(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> %{{.*}}) + return _mm_sm3msg2_epi32(__A, __B, __C); +} + +__m128i test_mm_sm3rnds2_epi32(__m128i __A, __m128i __B, __m128i __C) { + // CHECK-LABEL: @test_mm_sm3rnds2_epi32( + // CHECK: call <4 x i32> @llvm.x86.vsm3rnds2(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> %{{.*}}, i32 127) + return _mm_sm3rnds2_epi32(__A, __B, __C, 127); +} diff --git a/clang/test/CodeGen/X86/sm3-error.c b/clang/test/CodeGen/X86/sm3-error.c new file mode 100644 --- /dev/null +++ b/clang/test/CodeGen/X86/sm3-error.c @@ -0,0 +1,7 @@ +// RUN: %clang_cc1 %s -ffreestanding -triple=i686-unknown-unknown -target-feature +sm3 -emit-llvm -fsyntax-only -verify + +#include + +__m128i test_mm_sm3rnds2_epi32(__m128i __A, __m128i __B, __m128i __C) { + return _mm_sm3rnds2_epi32(__A, __B, __C, 256); // expected-error {{argument value 256 is outside the valid range [0, 255]}} +} diff --git a/clang/test/CodeGen/attr-target-x86.c b/clang/test/CodeGen/attr-target-x86.c --- a/clang/test/CodeGen/attr-target-x86.c +++ b/clang/test/CodeGen/attr-target-x86.c @@ -54,9 +54,9 @@ // CHECK: #0 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87" "tune-cpu"="i686" // CHECK: #1 = {{.*}}"target-cpu"="ivybridge" "target-features"="+avx,+cmov,+crc32,+cx16,+cx8,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt" // CHECK-NOT: tune-cpu -// CHECK: #2 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87,-aes,-avx,-avx2,-avx512bf16,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512fp16,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vp2intersect,-avx512vpopcntdq,-avxifma,-avxneconvert,-avxvnni,-avxvnniint8,-f16c,-fma,-fma4,-gfni,-kl,-pclmul,-sha,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-vaes,-vpclmulqdq,-widekl,-xop" "tune-cpu"="i686" +// CHECK: #2 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87,-aes,-avx,-avx2,-avx512bf16,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512fp16,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vp2intersect,-avx512vpopcntdq,-avxifma,-avxneconvert,-avxvnni,-avxvnniint8,-f16c,-fma,-fma4,-gfni,-kl,-pclmul,-sha,-sm3,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-vaes,-vpclmulqdq,-widekl,-xop" "tune-cpu"="i686" // CHECK: #3 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+crc32,+cx8,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87" "tune-cpu"="i686" -// CHECK: #4 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87,-avx,-avx2,-avx512bf16,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512fp16,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vp2intersect,-avx512vpopcntdq,-avxifma,-avxneconvert,-avxvnni,-avxvnniint8,-f16c,-fma,-fma4,-sse4.1,-sse4.2,-vaes,-vpclmulqdq,-xop" "tune-cpu"="i686" +// CHECK: #4 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87,-avx,-avx2,-avx512bf16,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512fp16,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vp2intersect,-avx512vpopcntdq,-avxifma,-avxneconvert,-avxvnni,-avxvnniint8,-f16c,-fma,-fma4,-sm3,-sse4.1,-sse4.2,-vaes,-vpclmulqdq,-xop" "tune-cpu"="i686" // CHECK: #5 = {{.*}}"target-cpu"="ivybridge" "target-features"="+avx,+cmov,+crc32,+cx16,+cx8,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt,-aes,-vaes" // CHECK-NOT: tune-cpu // CHECK: #6 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87,-3dnow,-3dnowa,-mmx" diff --git a/clang/test/Driver/x86-target-features.c b/clang/test/Driver/x86-target-features.c --- a/clang/test/Driver/x86-target-features.c +++ b/clang/test/Driver/x86-target-features.c @@ -349,6 +349,11 @@ // AVXNECONVERT: "-target-feature" "+avxneconvert" // NO-AVXNECONVERT: "-target-feature" "-avxneconvert" +// RUN: %clang --target=i386 -msm3 %s -### -o %t.o 2>&1 | FileCheck -check-prefix=SM3 %s +// RUN: %clang --target=i386 -mno-sm3 %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-SM3 %s +// SM3: "-target-feature" "+sm3" +// NO-SM3: "-target-feature" "-sm3" + // RUN: %clang --target=i386 -march=i386 -mcrc32 %s -### 2>&1 | FileCheck -check-prefix=CRC32 %s // RUN: %clang --target=i386 -march=i386 -mno-crc32 %s -### 2>&1 | FileCheck -check-prefix=NO-CRC32 %s // CRC32: "-target-feature" "+crc32" diff --git a/clang/test/Preprocessor/x86_target_features.c b/clang/test/Preprocessor/x86_target_features.c --- a/clang/test/Preprocessor/x86_target_features.c +++ b/clang/test/Preprocessor/x86_target_features.c @@ -660,6 +660,20 @@ // AVXNECONVERTNOAVX2-NOT: #define __AVX2__ 1 // AVXNECONVERTNOAVX2-NOT: #define __AVXNECONVERT__ 1 +// RUN: %clang -target i686-unknown-linux-gnu -march=atom -msm3 -x c -E -dM -o - %s | FileCheck -check-prefix=SM3 %s + +// SM3: #define __AVX__ 1 +// SM3: #define __SM3__ 1 + +// RUN: %clang -target i686-unknown-linux-gnu -march=atom -mno-sm3 -x c -E -dM -o - %s | FileCheck -check-prefix=NOSM3 %s + +// NOSM3-NOT: #define __SM3__ 1 + +// RUN: %clang -target i686-unknown-linux-gnu -march=atom -msm3 -mno-avx -x c -E -dM -o - %s | FileCheck -check-prefix=SM3NOAVX %s + +// SM3NOAVX-NOT: #define __SM3__ 1 +// SM3NOAVX-NOT: #define __AVX__ 1 + // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mcrc32 -x c -E -dM -o - %s | FileCheck -check-prefix=CRC32 %s // CRC32: #define __CRC32__ 1 diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -276,7 +276,7 @@ * ``__builtin_unpredictable`` (unpredictable metadata in LLVM IR), is handled by X86 Backend. ``X86CmovConversion`` pass now respects this builtin and does not convert CMOVs to branches. - +* Support ISA of ``SM3``. Changes to the OCaml bindings ----------------------------- diff --git a/llvm/include/llvm/IR/IntrinsicsX86.td b/llvm/include/llvm/IR/IntrinsicsX86.td --- a/llvm/include/llvm/IR/IntrinsicsX86.td +++ b/llvm/include/llvm/IR/IntrinsicsX86.td @@ -5513,6 +5513,25 @@ DefaultAttrsIntrinsic<[llvm_v8bf16_ty], [llvm_v8f32_ty], [IntrNoMem]>; } //===----------------------------------------------------------------------===// +// SM3 intrinsics +let TargetPrefix = "x86" in { + def int_x86_vsm3msg1 + : ClangBuiltin<"__builtin_ia32_vsm3msg1">, + DefaultAttrsIntrinsic<[llvm_v4i32_ty], + [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], + [IntrNoMem]>; + def int_x86_vsm3msg2 + : ClangBuiltin<"__builtin_ia32_vsm3msg2">, + DefaultAttrsIntrinsic<[llvm_v4i32_ty], + [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], + [IntrNoMem]>; + def int_x86_vsm3rnds2 + : ClangBuiltin<"__builtin_ia32_vsm3rnds2">, + DefaultAttrsIntrinsic<[llvm_v4i32_ty], + [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty, llvm_i32_ty], + [ImmArg>, IntrNoMem]>; +} +//===----------------------------------------------------------------------===// // RAO-INT intrinsics let TargetPrefix = "x86" in { def int_x86_aadd32 diff --git a/llvm/include/llvm/TargetParser/X86TargetParser.def b/llvm/include/llvm/TargetParser/X86TargetParser.def --- a/llvm/include/llvm/TargetParser/X86TargetParser.def +++ b/llvm/include/llvm/TargetParser/X86TargetParser.def @@ -221,6 +221,7 @@ X86_FEATURE (HRESET, "hreset") X86_FEATURE (RAOINT, "raoint") X86_FEATURE (AVX512FP16, "avx512fp16") +X86_FEATURE (SM3, "sm3") X86_FEATURE (AMX_FP16, "amx-fp16") X86_FEATURE (CMPCCXADD, "cmpccxadd") X86_FEATURE (AVXNECONVERT, "avxneconvert") diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td --- a/llvm/lib/Target/X86/X86.td +++ b/llvm/lib/Target/X86/X86.td @@ -242,6 +242,9 @@ // using Shadow Stack def FeatureSHSTK : SubtargetFeature<"shstk", "HasSHSTK", "true", "Support CET Shadow-Stack instructions">; +def FeatureSM3 : SubtargetFeature<"sm3", "HasSM3", "true", + "Support SM3 instructions", + [FeatureAVX]>; def FeaturePRFCHW : SubtargetFeature<"prfchw", "HasPRFCHW", "true", "Support PRFCHW instructions">; def FeatureRDSEED : SubtargetFeature<"rdseed", "HasRDSEED", "true", diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td --- a/llvm/lib/Target/X86/X86InstrInfo.td +++ b/llvm/lib/Target/X86/X86InstrInfo.td @@ -968,6 +968,7 @@ def HasADX : Predicate<"Subtarget->hasADX()">; def HasSHA : Predicate<"Subtarget->hasSHA()">; def HasSGX : Predicate<"Subtarget->hasSGX()">; +def HasSM3 : Predicate<"Subtarget->hasSM3()">; def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">; def HasSSEPrefetch : Predicate<"Subtarget->hasSSEPrefetch()">; def NoSSEPrefetch : Predicate<"!Subtarget->hasSSEPrefetch()">; diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td --- a/llvm/lib/Target/X86/X86InstrSSE.td +++ b/llvm/lib/Target/X86/X86InstrSSE.td @@ -8295,3 +8295,44 @@ (VCVTNEPS2BF16rr VR128:$dst, VR128:$src), 0, "att">; def : InstAlias<"vcvtneps2bf16y\t{$src, $dst|$dst, $src}", (VCVTNEPS2BF16Yrr VR128:$dst, VR256:$src), 0, "att">; + +// FIXME: Is there a better scheduler class for SM3 than WriteVecIMul? +let Predicates = [HasSM3], Constraints = "$src1 = $dst" in { + multiclass SM3_Base { + def rr : I<0xda, MRMSrcReg, (outs VR128:$dst), + (ins VR128:$src1, VR128:$src2, VR128:$src3), + !strconcat(OpStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), + [(set VR128:$dst, + (!cast("int_x86_"#OpStr) VR128:$src1, + VR128:$src2, VR128:$src3))]>, + Sched<[WriteVecIMul]>, VEX_4V; + def rm : I<0xda, MRMSrcMem, (outs VR128:$dst), + (ins VR128:$src1, VR128:$src2, i128mem:$src3), + !strconcat(OpStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), + [(set VR128:$dst, + (!cast("int_x86_"#OpStr) VR128:$src1, + VR128:$src2, (loadv4i32 addr:$src3)))]>, + Sched<[WriteVecIMul]>, VEX_4V; + } + + multiclass VSM3RNDS2_Base { + def rr : Ii8<0xde, MRMSrcReg, (outs VR128:$dst), + (ins VR128:$src1, VR128:$src2, VR128:$src3, i32u8imm:$src4), + "vsm3rnds2\t{$src4, $src3, $src2, $dst|$dst, $src2, $src3, $src4}", + [(set VR128:$dst, + (int_x86_vsm3rnds2 VR128:$src1, + VR128:$src2, VR128:$src3, timm:$src4))]>, + Sched<[WriteVecIMul]>; + def rm : Ii8<0xde, MRMSrcMem, (outs VR128:$dst), + (ins VR128:$src1, VR128:$src2, i128mem:$src3, i32u8imm:$src4), + "vsm3rnds2\t{$src4, $src3, $src2, $dst|$dst, $src2, $src3, $src4}", + [(set VR128:$dst, + (int_x86_vsm3rnds2 VR128:$src1, + VR128:$src2, (loadv4i32 addr:$src3), timm:$src4))]>, + Sched<[WriteVecIMul]>; + } +} + +defm VSM3MSG1 : SM3_Base<"vsm3msg1">, T8PS; +defm VSM3MSG2 : SM3_Base<"vsm3msg2">, T8PD; +defm VSM3RNDS2 : VSM3RNDS2_Base, VEX_4V, TAPD; diff --git a/llvm/lib/TargetParser/Host.cpp b/llvm/lib/TargetParser/Host.cpp --- a/llvm/lib/TargetParser/Host.cpp +++ b/llvm/lib/TargetParser/Host.cpp @@ -1746,6 +1746,7 @@ Features["amx-int8"] = HasLeaf7 && ((EDX >> 25) & 1) && HasAMXSave; bool HasLeaf7Subleaf1 = MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX); + Features["sm3"] = HasLeaf7Subleaf1 && ((EAX >> 1) & 1); Features["raoint"] = HasLeaf7Subleaf1 && ((EAX >> 3) & 1); Features["avxvnni"] = HasLeaf7Subleaf1 && ((EAX >> 4) & 1) && HasAVXSave; Features["avx512bf16"] = HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save; diff --git a/llvm/lib/TargetParser/X86TargetParser.cpp b/llvm/lib/TargetParser/X86TargetParser.cpp --- a/llvm/lib/TargetParser/X86TargetParser.cpp +++ b/llvm/lib/TargetParser/X86TargetParser.cpp @@ -613,6 +613,7 @@ constexpr FeatureBitset ImpliedFeaturesSHA = FeatureSSE2; constexpr FeatureBitset ImpliedFeaturesVAES = FeatureAES | FeatureAVX; constexpr FeatureBitset ImpliedFeaturesVPCLMULQDQ = FeatureAVX | FeaturePCLMUL; +constexpr FeatureBitset ImpliedFeaturesSM3 = FeatureAVX; // AVX512 features. constexpr FeatureBitset ImpliedFeaturesAVX512CD = FeatureAVX512F; diff --git a/llvm/test/CodeGen/X86/sm3-intrinsics.ll b/llvm/test/CodeGen/X86/sm3-intrinsics.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/X86/sm3-intrinsics.ll @@ -0,0 +1,34 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+sm3 | FileCheck %s +; RUN: llc < %s -verify-machineinstrs -mtriple=i686-unknown-unknown --show-mc-encoding -mattr=+sm3 | FileCheck %s + +define <4 x i32> @test_int_x86_vsm3msg1(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) { +; CHECK-LABEL: test_int_x86_vsm3msg1: +; CHECK: # %bb.0: +; CHECK-NEXT: vsm3msg1 %xmm2, %xmm1, %xmm0 # encoding: [0xc4,0xe2,0x70,0xda,0xc2] +; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3] + %ret = call <4 x i32> @llvm.x86.vsm3msg1(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) + ret <4 x i32> %ret +} +declare <4 x i32> @llvm.x86.vsm3msg1(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) + +define <4 x i32> @test_int_x86_vsm3msg2(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) { +; CHECK-LABEL: test_int_x86_vsm3msg2: +; CHECK: # %bb.0: +; CHECK-NEXT: vsm3msg2 %xmm2, %xmm1, %xmm0 # encoding: [0xc4,0xe2,0x71,0xda,0xc2] +; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3] + %ret = call <4 x i32> @llvm.x86.vsm3msg2(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) + ret <4 x i32> %ret +} +declare <4 x i32> @llvm.x86.vsm3msg2(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) + +define <4 x i32> @test_int_x86_vsm3rnds2(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) { +; CHECK-LABEL: test_int_x86_vsm3rnds2: +; CHECK: # %bb.0: +; CHECK-NEXT: vsm3rnds2 $127, %xmm2, %xmm1, %xmm0 # encoding: [0xc4,0xe3,0x71,0xde,0xc2,0x7f] +; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3] + %ret = call <4 x i32> @llvm.x86.vsm3rnds2(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, i32 127) + ret <4 x i32> %ret +} +declare <4 x i32> @llvm.x86.vsm3rnds2(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, i32 %D) + diff --git a/llvm/test/MC/Disassembler/X86/sm3-32.txt b/llvm/test/MC/Disassembler/X86/sm3-32.txt new file mode 100644 --- /dev/null +++ b/llvm/test/MC/Disassembler/X86/sm3-32.txt @@ -0,0 +1,87 @@ +# RUN: llvm-mc --disassemble %s -triple=i386-unknown-unknown | FileCheck %s --check-prefixes=ATT +# RUN: llvm-mc --disassemble %s -triple=i386-unknown-unknown --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL + +# ATT: vsm3msg1 %xmm4, %xmm3, %xmm2 +# INTEL: vsm3msg1 xmm2, xmm3, xmm4 +0xc4,0xe2,0x60,0xda,0xd4 + +# ATT: vsm3msg1 268435456(%esp,%esi,8), %xmm3, %xmm2 +# INTEL: vsm3msg1 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456] +0xc4,0xe2,0x60,0xda,0x94,0xf4,0x00,0x00,0x00,0x10 + +# ATT: vsm3msg1 291(%edi,%eax,4), %xmm3, %xmm2 +# INTEL: vsm3msg1 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291] +0xc4,0xe2,0x60,0xda,0x94,0x87,0x23,0x01,0x00,0x00 + +# ATT: vsm3msg1 (%eax), %xmm3, %xmm2 +# INTEL: vsm3msg1 xmm2, xmm3, xmmword ptr [eax] +0xc4,0xe2,0x60,0xda,0x10 + +# ATT: vsm3msg1 -512(,%ebp,2), %xmm3, %xmm2 +# INTEL: vsm3msg1 xmm2, xmm3, xmmword ptr [2*ebp - 512] +0xc4,0xe2,0x60,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff + +# ATT: vsm3msg1 2032(%ecx), %xmm3, %xmm2 +# INTEL: vsm3msg1 xmm2, xmm3, xmmword ptr [ecx + 2032] +0xc4,0xe2,0x60,0xda,0x91,0xf0,0x07,0x00,0x00 + +# ATT: vsm3msg1 -2048(%edx), %xmm3, %xmm2 +# INTEL: vsm3msg1 xmm2, xmm3, xmmword ptr [edx - 2048] +0xc4,0xe2,0x60,0xda,0x92,0x00,0xf8,0xff,0xff + +# ATT: vsm3msg2 %xmm4, %xmm3, %xmm2 +# INTEL: vsm3msg2 xmm2, xmm3, xmm4 +0xc4,0xe2,0x61,0xda,0xd4 + +# ATT: vsm3msg2 268435456(%esp,%esi,8), %xmm3, %xmm2 +# INTEL: vsm3msg2 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456] +0xc4,0xe2,0x61,0xda,0x94,0xf4,0x00,0x00,0x00,0x10 + +# ATT: vsm3msg2 291(%edi,%eax,4), %xmm3, %xmm2 +# INTEL: vsm3msg2 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291] +0xc4,0xe2,0x61,0xda,0x94,0x87,0x23,0x01,0x00,0x00 + +# ATT: vsm3msg2 (%eax), %xmm3, %xmm2 +# INTEL: vsm3msg2 xmm2, xmm3, xmmword ptr [eax] +0xc4,0xe2,0x61,0xda,0x10 + +# ATT: vsm3msg2 -512(,%ebp,2), %xmm3, %xmm2 +# INTEL: vsm3msg2 xmm2, xmm3, xmmword ptr [2*ebp - 512] +0xc4,0xe2,0x61,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff + +# ATT: vsm3msg2 2032(%ecx), %xmm3, %xmm2 +# INTEL: vsm3msg2 xmm2, xmm3, xmmword ptr [ecx + 2032] +0xc4,0xe2,0x61,0xda,0x91,0xf0,0x07,0x00,0x00 + +# ATT: vsm3msg2 -2048(%edx), %xmm3, %xmm2 +# INTEL: vsm3msg2 xmm2, xmm3, xmmword ptr [edx - 2048] +0xc4,0xe2,0x61,0xda,0x92,0x00,0xf8,0xff,0xff + +# ATT: vsm3rnds2 $123, %xmm4, %xmm3, %xmm2 +# INTEL: vsm3rnds2 xmm2, xmm3, xmm4, 123 +0xc4,0xe3,0x61,0xde,0xd4,0x7b + +# ATT: vsm3rnds2 $123, 268435456(%esp,%esi,8), %xmm3, %xmm2 +# INTEL: vsm3rnds2 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456], 123 +0xc4,0xe3,0x61,0xde,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b + +# ATT: vsm3rnds2 $123, 291(%edi,%eax,4), %xmm3, %xmm2 +# INTEL: vsm3rnds2 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291], 123 +0xc4,0xe3,0x61,0xde,0x94,0x87,0x23,0x01,0x00,0x00,0x7b + +# ATT: vsm3rnds2 $123, (%eax), %xmm3, %xmm2 +# INTEL: vsm3rnds2 xmm2, xmm3, xmmword ptr [eax], 123 +0xc4,0xe3,0x61,0xde,0x10,0x7b + +# ATT: vsm3rnds2 $123, -512(,%ebp,2), %xmm3, %xmm2 +# INTEL: vsm3rnds2 xmm2, xmm3, xmmword ptr [2*ebp - 512], 123 +0xc4,0xe3,0x61,0xde,0x14,0x6d,0x00,0xfe,0xff,0xff,0x7b + +# ATT: vsm3rnds2 $123, 2032(%ecx), %xmm3, %xmm2 +# INTEL: vsm3rnds2 xmm2, xmm3, xmmword ptr [ecx + 2032], 123 +0xc4,0xe3,0x61,0xde,0x91,0xf0,0x07,0x00,0x00,0x7b + +# ATT: vsm3rnds2 $123, -2048(%edx), %xmm3, %xmm2 +# INTEL: vsm3rnds2 xmm2, xmm3, xmmword ptr [edx - 2048], 123 +0xc4,0xe3,0x61,0xde,0x92,0x00,0xf8,0xff,0xff,0x7b + diff --git a/llvm/test/MC/Disassembler/X86/sm3-64.txt b/llvm/test/MC/Disassembler/X86/sm3-64.txt new file mode 100644 --- /dev/null +++ b/llvm/test/MC/Disassembler/X86/sm3-64.txt @@ -0,0 +1,87 @@ +# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT +# RUN: llvm-mc --disassemble %s -triple=x86_64 --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL + +# ATT: vsm3msg1 %xmm4, %xmm13, %xmm12 +# INTEL: vsm3msg1 xmm12, xmm13, xmm4 +0xc4,0x62,0x10,0xda,0xe4 + +# ATT: vsm3msg1 268435456(%rbp,%r14,8), %xmm13, %xmm12 +# INTEL: vsm3msg1 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456] +0xc4,0x22,0x10,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10 + +# ATT: vsm3msg1 291(%r8,%rax,4), %xmm13, %xmm12 +# INTEL: vsm3msg1 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291] +0xc4,0x42,0x10,0xda,0xa4,0x80,0x23,0x01,0x00,0x00 + +# ATT: vsm3msg1 (%rip), %xmm13, %xmm12 +# INTEL: vsm3msg1 xmm12, xmm13, xmmword ptr [rip] +0xc4,0x62,0x10,0xda,0x25,0x00,0x00,0x00,0x00 + +# ATT: vsm3msg1 -512(,%rbp,2), %xmm13, %xmm12 +# INTEL: vsm3msg1 xmm12, xmm13, xmmword ptr [2*rbp - 512] +0xc4,0x62,0x10,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff + +# ATT: vsm3msg1 2032(%rcx), %xmm13, %xmm12 +# INTEL: vsm3msg1 xmm12, xmm13, xmmword ptr [rcx + 2032] +0xc4,0x62,0x10,0xda,0xa1,0xf0,0x07,0x00,0x00 + +# ATT: vsm3msg1 -2048(%rdx), %xmm13, %xmm12 +# INTEL: vsm3msg1 xmm12, xmm13, xmmword ptr [rdx - 2048] +0xc4,0x62,0x10,0xda,0xa2,0x00,0xf8,0xff,0xff + +# ATT: vsm3msg2 %xmm4, %xmm13, %xmm12 +# INTEL: vsm3msg2 xmm12, xmm13, xmm4 +0xc4,0x62,0x11,0xda,0xe4 + +# ATT: vsm3msg2 268435456(%rbp,%r14,8), %xmm13, %xmm12 +# INTEL: vsm3msg2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456] +0xc4,0x22,0x11,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10 + +# ATT: vsm3msg2 291(%r8,%rax,4), %xmm13, %xmm12 +# INTEL: vsm3msg2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291] +0xc4,0x42,0x11,0xda,0xa4,0x80,0x23,0x01,0x00,0x00 + +# ATT: vsm3msg2 (%rip), %xmm13, %xmm12 +# INTEL: vsm3msg2 xmm12, xmm13, xmmword ptr [rip] +0xc4,0x62,0x11,0xda,0x25,0x00,0x00,0x00,0x00 + +# ATT: vsm3msg2 -512(,%rbp,2), %xmm13, %xmm12 +# INTEL: vsm3msg2 xmm12, xmm13, xmmword ptr [2*rbp - 512] +0xc4,0x62,0x11,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff + +# ATT: vsm3msg2 2032(%rcx), %xmm13, %xmm12 +# INTEL: vsm3msg2 xmm12, xmm13, xmmword ptr [rcx + 2032] +0xc4,0x62,0x11,0xda,0xa1,0xf0,0x07,0x00,0x00 + +# ATT: vsm3msg2 -2048(%rdx), %xmm13, %xmm12 +# INTEL: vsm3msg2 xmm12, xmm13, xmmword ptr [rdx - 2048] +0xc4,0x62,0x11,0xda,0xa2,0x00,0xf8,0xff,0xff + +# ATT: vsm3rnds2 $123, %xmm4, %xmm13, %xmm12 +# INTEL: vsm3rnds2 xmm12, xmm13, xmm4, 123 +0xc4,0x63,0x11,0xde,0xe4,0x7b + +# ATT: vsm3rnds2 $123, 268435456(%rbp,%r14,8), %xmm13, %xmm12 +# INTEL: vsm3rnds2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456], 123 +0xc4,0x23,0x11,0xde,0xa4,0xf5,0x00,0x00,0x00,0x10,0x7b + +# ATT: vsm3rnds2 $123, 291(%r8,%rax,4), %xmm13, %xmm12 +# INTEL: vsm3rnds2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291], 123 +0xc4,0x43,0x11,0xde,0xa4,0x80,0x23,0x01,0x00,0x00,0x7b + +# ATT: vsm3rnds2 $123, (%rip), %xmm13, %xmm12 +# INTEL: vsm3rnds2 xmm12, xmm13, xmmword ptr [rip], 123 +0xc4,0x63,0x11,0xde,0x25,0x00,0x00,0x00,0x00,0x7b + +# ATT: vsm3rnds2 $123, -512(,%rbp,2), %xmm13, %xmm12 +# INTEL: vsm3rnds2 xmm12, xmm13, xmmword ptr [2*rbp - 512], 123 +0xc4,0x63,0x11,0xde,0x24,0x6d,0x00,0xfe,0xff,0xff,0x7b + +# ATT: vsm3rnds2 $123, 2032(%rcx), %xmm13, %xmm12 +# INTEL: vsm3rnds2 xmm12, xmm13, xmmword ptr [rcx + 2032], 123 +0xc4,0x63,0x11,0xde,0xa1,0xf0,0x07,0x00,0x00,0x7b + +# ATT: vsm3rnds2 $123, -2048(%rdx), %xmm13, %xmm12 +# INTEL: vsm3rnds2 xmm12, xmm13, xmmword ptr [rdx - 2048], 123 +0xc4,0x63,0x11,0xde,0xa2,0x00,0xf8,0xff,0xff,0x7b + diff --git a/llvm/test/MC/X86/sm3-att-32.s b/llvm/test/MC/X86/sm3-att-32.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/X86/sm3-att-32.s @@ -0,0 +1,86 @@ +// RUN: llvm-mc -triple i686-unknown-unknown --show-encoding %s | FileCheck %s + +// CHECK: vsm3msg1 %xmm4, %xmm3, %xmm2 +// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0xd4] + vsm3msg1 %xmm4, %xmm3, %xmm2 + +// CHECK: vsm3msg1 268435456(%esp,%esi,8), %xmm3, %xmm2 +// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x94,0xf4,0x00,0x00,0x00,0x10] + vsm3msg1 268435456(%esp,%esi,8), %xmm3, %xmm2 + +// CHECK: vsm3msg1 291(%edi,%eax,4), %xmm3, %xmm2 +// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x94,0x87,0x23,0x01,0x00,0x00] + vsm3msg1 291(%edi,%eax,4), %xmm3, %xmm2 + +// CHECK: vsm3msg1 (%eax), %xmm3, %xmm2 +// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x10] + vsm3msg1 (%eax), %xmm3, %xmm2 + +// CHECK: vsm3msg1 -512(,%ebp,2), %xmm3, %xmm2 +// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff] + vsm3msg1 -512(,%ebp,2), %xmm3, %xmm2 + +// CHECK: vsm3msg1 2032(%ecx), %xmm3, %xmm2 +// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x91,0xf0,0x07,0x00,0x00] + vsm3msg1 2032(%ecx), %xmm3, %xmm2 + +// CHECK: vsm3msg1 -2048(%edx), %xmm3, %xmm2 +// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x92,0x00,0xf8,0xff,0xff] + vsm3msg1 -2048(%edx), %xmm3, %xmm2 + +// CHECK: vsm3msg2 %xmm4, %xmm3, %xmm2 +// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0xd4] + vsm3msg2 %xmm4, %xmm3, %xmm2 + +// CHECK: vsm3msg2 268435456(%esp,%esi,8), %xmm3, %xmm2 +// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x94,0xf4,0x00,0x00,0x00,0x10] + vsm3msg2 268435456(%esp,%esi,8), %xmm3, %xmm2 + +// CHECK: vsm3msg2 291(%edi,%eax,4), %xmm3, %xmm2 +// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x94,0x87,0x23,0x01,0x00,0x00] + vsm3msg2 291(%edi,%eax,4), %xmm3, %xmm2 + +// CHECK: vsm3msg2 (%eax), %xmm3, %xmm2 +// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x10] + vsm3msg2 (%eax), %xmm3, %xmm2 + +// CHECK: vsm3msg2 -512(,%ebp,2), %xmm3, %xmm2 +// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff] + vsm3msg2 -512(,%ebp,2), %xmm3, %xmm2 + +// CHECK: vsm3msg2 2032(%ecx), %xmm3, %xmm2 +// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x91,0xf0,0x07,0x00,0x00] + vsm3msg2 2032(%ecx), %xmm3, %xmm2 + +// CHECK: vsm3msg2 -2048(%edx), %xmm3, %xmm2 +// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x92,0x00,0xf8,0xff,0xff] + vsm3msg2 -2048(%edx), %xmm3, %xmm2 + +// CHECK: vsm3rnds2 $123, %xmm4, %xmm3, %xmm2 +// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0xd4,0x7b] + vsm3rnds2 $123, %xmm4, %xmm3, %xmm2 + +// CHECK: vsm3rnds2 $123, 268435456(%esp,%esi,8), %xmm3, %xmm2 +// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b] + vsm3rnds2 $123, 268435456(%esp,%esi,8), %xmm3, %xmm2 + +// CHECK: vsm3rnds2 $123, 291(%edi,%eax,4), %xmm3, %xmm2 +// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x94,0x87,0x23,0x01,0x00,0x00,0x7b] + vsm3rnds2 $123, 291(%edi,%eax,4), %xmm3, %xmm2 + +// CHECK: vsm3rnds2 $123, (%eax), %xmm3, %xmm2 +// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x10,0x7b] + vsm3rnds2 $123, (%eax), %xmm3, %xmm2 + +// CHECK: vsm3rnds2 $123, -512(,%ebp,2), %xmm3, %xmm2 +// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x14,0x6d,0x00,0xfe,0xff,0xff,0x7b] + vsm3rnds2 $123, -512(,%ebp,2), %xmm3, %xmm2 + +// CHECK: vsm3rnds2 $123, 2032(%ecx), %xmm3, %xmm2 +// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x91,0xf0,0x07,0x00,0x00,0x7b] + vsm3rnds2 $123, 2032(%ecx), %xmm3, %xmm2 + +// CHECK: vsm3rnds2 $123, -2048(%edx), %xmm3, %xmm2 +// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x92,0x00,0xf8,0xff,0xff,0x7b] + vsm3rnds2 $123, -2048(%edx), %xmm3, %xmm2 + diff --git a/llvm/test/MC/X86/sm3-att-64.s b/llvm/test/MC/X86/sm3-att-64.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/X86/sm3-att-64.s @@ -0,0 +1,86 @@ +// RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s + +// CHECK: vsm3msg1 %xmm4, %xmm13, %xmm12 +// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xe4] + vsm3msg1 %xmm4, %xmm13, %xmm12 + +// CHECK: vsm3msg1 268435456(%rbp,%r14,8), %xmm13, %xmm12 +// CHECK: encoding: [0xc4,0x22,0x10,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10] + vsm3msg1 268435456(%rbp,%r14,8), %xmm13, %xmm12 + +// CHECK: vsm3msg1 291(%r8,%rax,4), %xmm13, %xmm12 +// CHECK: encoding: [0xc4,0x42,0x10,0xda,0xa4,0x80,0x23,0x01,0x00,0x00] + vsm3msg1 291(%r8,%rax,4), %xmm13, %xmm12 + +// CHECK: vsm3msg1 (%rip), %xmm13, %xmm12 +// CHECK: encoding: [0xc4,0x62,0x10,0xda,0x25,0x00,0x00,0x00,0x00] + vsm3msg1 (%rip), %xmm13, %xmm12 + +// CHECK: vsm3msg1 -512(,%rbp,2), %xmm13, %xmm12 +// CHECK: encoding: [0xc4,0x62,0x10,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff] + vsm3msg1 -512(,%rbp,2), %xmm13, %xmm12 + +// CHECK: vsm3msg1 2032(%rcx), %xmm13, %xmm12 +// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xa1,0xf0,0x07,0x00,0x00] + vsm3msg1 2032(%rcx), %xmm13, %xmm12 + +// CHECK: vsm3msg1 -2048(%rdx), %xmm13, %xmm12 +// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xa2,0x00,0xf8,0xff,0xff] + vsm3msg1 -2048(%rdx), %xmm13, %xmm12 + +// CHECK: vsm3msg2 %xmm4, %xmm13, %xmm12 +// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xe4] + vsm3msg2 %xmm4, %xmm13, %xmm12 + +// CHECK: vsm3msg2 268435456(%rbp,%r14,8), %xmm13, %xmm12 +// CHECK: encoding: [0xc4,0x22,0x11,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10] + vsm3msg2 268435456(%rbp,%r14,8), %xmm13, %xmm12 + +// CHECK: vsm3msg2 291(%r8,%rax,4), %xmm13, %xmm12 +// CHECK: encoding: [0xc4,0x42,0x11,0xda,0xa4,0x80,0x23,0x01,0x00,0x00] + vsm3msg2 291(%r8,%rax,4), %xmm13, %xmm12 + +// CHECK: vsm3msg2 (%rip), %xmm13, %xmm12 +// CHECK: encoding: [0xc4,0x62,0x11,0xda,0x25,0x00,0x00,0x00,0x00] + vsm3msg2 (%rip), %xmm13, %xmm12 + +// CHECK: vsm3msg2 -512(,%rbp,2), %xmm13, %xmm12 +// CHECK: encoding: [0xc4,0x62,0x11,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff] + vsm3msg2 -512(,%rbp,2), %xmm13, %xmm12 + +// CHECK: vsm3msg2 2032(%rcx), %xmm13, %xmm12 +// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xa1,0xf0,0x07,0x00,0x00] + vsm3msg2 2032(%rcx), %xmm13, %xmm12 + +// CHECK: vsm3msg2 -2048(%rdx), %xmm13, %xmm12 +// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xa2,0x00,0xf8,0xff,0xff] + vsm3msg2 -2048(%rdx), %xmm13, %xmm12 + +// CHECK: vsm3rnds2 $123, %xmm4, %xmm13, %xmm12 +// CHECK: encoding: [0xc4,0x63,0x11,0xde,0xe4,0x7b] + vsm3rnds2 $123, %xmm4, %xmm13, %xmm12 + +// CHECK: vsm3rnds2 $123, 268435456(%rbp,%r14,8), %xmm13, %xmm12 +// CHECK: encoding: [0xc4,0x23,0x11,0xde,0xa4,0xf5,0x00,0x00,0x00,0x10,0x7b] + vsm3rnds2 $123, 268435456(%rbp,%r14,8), %xmm13, %xmm12 + +// CHECK: vsm3rnds2 $123, 291(%r8,%rax,4), %xmm13, %xmm12 +// CHECK: encoding: [0xc4,0x43,0x11,0xde,0xa4,0x80,0x23,0x01,0x00,0x00,0x7b] + vsm3rnds2 $123, 291(%r8,%rax,4), %xmm13, %xmm12 + +// CHECK: vsm3rnds2 $123, (%rip), %xmm13, %xmm12 +// CHECK: encoding: [0xc4,0x63,0x11,0xde,0x25,0x00,0x00,0x00,0x00,0x7b] + vsm3rnds2 $123, (%rip), %xmm13, %xmm12 + +// CHECK: vsm3rnds2 $123, -512(,%rbp,2), %xmm13, %xmm12 +// CHECK: encoding: [0xc4,0x63,0x11,0xde,0x24,0x6d,0x00,0xfe,0xff,0xff,0x7b] + vsm3rnds2 $123, -512(,%rbp,2), %xmm13, %xmm12 + +// CHECK: vsm3rnds2 $123, 2032(%rcx), %xmm13, %xmm12 +// CHECK: encoding: [0xc4,0x63,0x11,0xde,0xa1,0xf0,0x07,0x00,0x00,0x7b] + vsm3rnds2 $123, 2032(%rcx), %xmm13, %xmm12 + +// CHECK: vsm3rnds2 $123, -2048(%rdx), %xmm13, %xmm12 +// CHECK: encoding: [0xc4,0x63,0x11,0xde,0xa2,0x00,0xf8,0xff,0xff,0x7b] + vsm3rnds2 $123, -2048(%rdx), %xmm13, %xmm12 + diff --git a/llvm/test/MC/X86/sm3-intel-32.s b/llvm/test/MC/X86/sm3-intel-32.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/X86/sm3-intel-32.s @@ -0,0 +1,86 @@ +// RUN: llvm-mc -triple i686-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s + +// CHECK: vsm3msg1 xmm2, xmm3, xmm4 +// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0xd4] + vsm3msg1 xmm2, xmm3, xmm4 + +// CHECK: vsm3msg1 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456] +// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x94,0xf4,0x00,0x00,0x00,0x10] + vsm3msg1 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456] + +// CHECK: vsm3msg1 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291] +// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x94,0x87,0x23,0x01,0x00,0x00] + vsm3msg1 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291] + +// CHECK: vsm3msg1 xmm2, xmm3, xmmword ptr [eax] +// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x10] + vsm3msg1 xmm2, xmm3, xmmword ptr [eax] + +// CHECK: vsm3msg1 xmm2, xmm3, xmmword ptr [2*ebp - 512] +// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff] + vsm3msg1 xmm2, xmm3, xmmword ptr [2*ebp - 512] + +// CHECK: vsm3msg1 xmm2, xmm3, xmmword ptr [ecx + 2032] +// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x91,0xf0,0x07,0x00,0x00] + vsm3msg1 xmm2, xmm3, xmmword ptr [ecx + 2032] + +// CHECK: vsm3msg1 xmm2, xmm3, xmmword ptr [edx - 2048] +// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x92,0x00,0xf8,0xff,0xff] + vsm3msg1 xmm2, xmm3, xmmword ptr [edx - 2048] + +// CHECK: vsm3msg2 xmm2, xmm3, xmm4 +// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0xd4] + vsm3msg2 xmm2, xmm3, xmm4 + +// CHECK: vsm3msg2 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456] +// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x94,0xf4,0x00,0x00,0x00,0x10] + vsm3msg2 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456] + +// CHECK: vsm3msg2 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291] +// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x94,0x87,0x23,0x01,0x00,0x00] + vsm3msg2 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291] + +// CHECK: vsm3msg2 xmm2, xmm3, xmmword ptr [eax] +// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x10] + vsm3msg2 xmm2, xmm3, xmmword ptr [eax] + +// CHECK: vsm3msg2 xmm2, xmm3, xmmword ptr [2*ebp - 512] +// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff] + vsm3msg2 xmm2, xmm3, xmmword ptr [2*ebp - 512] + +// CHECK: vsm3msg2 xmm2, xmm3, xmmword ptr [ecx + 2032] +// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x91,0xf0,0x07,0x00,0x00] + vsm3msg2 xmm2, xmm3, xmmword ptr [ecx + 2032] + +// CHECK: vsm3msg2 xmm2, xmm3, xmmword ptr [edx - 2048] +// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x92,0x00,0xf8,0xff,0xff] + vsm3msg2 xmm2, xmm3, xmmword ptr [edx - 2048] + +// CHECK: vsm3rnds2 xmm2, xmm3, xmm4, 123 +// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0xd4,0x7b] + vsm3rnds2 xmm2, xmm3, xmm4, 123 + +// CHECK: vsm3rnds2 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456], 123 +// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b] + vsm3rnds2 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456], 123 + +// CHECK: vsm3rnds2 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291], 123 +// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x94,0x87,0x23,0x01,0x00,0x00,0x7b] + vsm3rnds2 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291], 123 + +// CHECK: vsm3rnds2 xmm2, xmm3, xmmword ptr [eax], 123 +// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x10,0x7b] + vsm3rnds2 xmm2, xmm3, xmmword ptr [eax], 123 + +// CHECK: vsm3rnds2 xmm2, xmm3, xmmword ptr [2*ebp - 512], 123 +// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x14,0x6d,0x00,0xfe,0xff,0xff,0x7b] + vsm3rnds2 xmm2, xmm3, xmmword ptr [2*ebp - 512], 123 + +// CHECK: vsm3rnds2 xmm2, xmm3, xmmword ptr [ecx + 2032], 123 +// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x91,0xf0,0x07,0x00,0x00,0x7b] + vsm3rnds2 xmm2, xmm3, xmmword ptr [ecx + 2032], 123 + +// CHECK: vsm3rnds2 xmm2, xmm3, xmmword ptr [edx - 2048], 123 +// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x92,0x00,0xf8,0xff,0xff,0x7b] + vsm3rnds2 xmm2, xmm3, xmmword ptr [edx - 2048], 123 + diff --git a/llvm/test/MC/X86/sm3-intel-64.s b/llvm/test/MC/X86/sm3-intel-64.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/X86/sm3-intel-64.s @@ -0,0 +1,86 @@ +// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s + +// CHECK: vsm3msg1 xmm12, xmm13, xmm4 +// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xe4] + vsm3msg1 xmm12, xmm13, xmm4 + +// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456] +// CHECK: encoding: [0xc4,0x22,0x10,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10] + vsm3msg1 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456] + +// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291] +// CHECK: encoding: [0xc4,0x42,0x10,0xda,0xa4,0x80,0x23,0x01,0x00,0x00] + vsm3msg1 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291] + +// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rip] +// CHECK: encoding: [0xc4,0x62,0x10,0xda,0x25,0x00,0x00,0x00,0x00] + vsm3msg1 xmm12, xmm13, xmmword ptr [rip] + +// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [2*rbp - 512] +// CHECK: encoding: [0xc4,0x62,0x10,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff] + vsm3msg1 xmm12, xmm13, xmmword ptr [2*rbp - 512] + +// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rcx + 2032] +// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xa1,0xf0,0x07,0x00,0x00] + vsm3msg1 xmm12, xmm13, xmmword ptr [rcx + 2032] + +// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rdx - 2048] +// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xa2,0x00,0xf8,0xff,0xff] + vsm3msg1 xmm12, xmm13, xmmword ptr [rdx - 2048] + +// CHECK: vsm3msg2 xmm12, xmm13, xmm4 +// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xe4] + vsm3msg2 xmm12, xmm13, xmm4 + +// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456] +// CHECK: encoding: [0xc4,0x22,0x11,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10] + vsm3msg2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456] + +// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291] +// CHECK: encoding: [0xc4,0x42,0x11,0xda,0xa4,0x80,0x23,0x01,0x00,0x00] + vsm3msg2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291] + +// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rip] +// CHECK: encoding: [0xc4,0x62,0x11,0xda,0x25,0x00,0x00,0x00,0x00] + vsm3msg2 xmm12, xmm13, xmmword ptr [rip] + +// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [2*rbp - 512] +// CHECK: encoding: [0xc4,0x62,0x11,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff] + vsm3msg2 xmm12, xmm13, xmmword ptr [2*rbp - 512] + +// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rcx + 2032] +// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xa1,0xf0,0x07,0x00,0x00] + vsm3msg2 xmm12, xmm13, xmmword ptr [rcx + 2032] + +// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rdx - 2048] +// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xa2,0x00,0xf8,0xff,0xff] + vsm3msg2 xmm12, xmm13, xmmword ptr [rdx - 2048] + +// CHECK: vsm3rnds2 xmm12, xmm13, xmm4, 123 +// CHECK: encoding: [0xc4,0x63,0x11,0xde,0xe4,0x7b] + vsm3rnds2 xmm12, xmm13, xmm4, 123 + +// CHECK: vsm3rnds2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456], 123 +// CHECK: encoding: [0xc4,0x23,0x11,0xde,0xa4,0xf5,0x00,0x00,0x00,0x10,0x7b] + vsm3rnds2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456], 123 + +// CHECK: vsm3rnds2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291], 123 +// CHECK: encoding: [0xc4,0x43,0x11,0xde,0xa4,0x80,0x23,0x01,0x00,0x00,0x7b] + vsm3rnds2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291], 123 + +// CHECK: vsm3rnds2 xmm12, xmm13, xmmword ptr [rip], 123 +// CHECK: encoding: [0xc4,0x63,0x11,0xde,0x25,0x00,0x00,0x00,0x00,0x7b] + vsm3rnds2 xmm12, xmm13, xmmword ptr [rip], 123 + +// CHECK: vsm3rnds2 xmm12, xmm13, xmmword ptr [2*rbp - 512], 123 +// CHECK: encoding: [0xc4,0x63,0x11,0xde,0x24,0x6d,0x00,0xfe,0xff,0xff,0x7b] + vsm3rnds2 xmm12, xmm13, xmmword ptr [2*rbp - 512], 123 + +// CHECK: vsm3rnds2 xmm12, xmm13, xmmword ptr [rcx + 2032], 123 +// CHECK: encoding: [0xc4,0x63,0x11,0xde,0xa1,0xf0,0x07,0x00,0x00,0x7b] + vsm3rnds2 xmm12, xmm13, xmmword ptr [rcx + 2032], 123 + +// CHECK: vsm3rnds2 xmm12, xmm13, xmmword ptr [rdx - 2048], 123 +// CHECK: encoding: [0xc4,0x63,0x11,0xde,0xa2,0x00,0xf8,0xff,0xff,0x7b] + vsm3rnds2 xmm12, xmm13, xmmword ptr [rdx - 2048], 123 +