diff --git a/mlir/test/Conversion/MemRefToSPIRV/alloc.mlir b/mlir/test/Conversion/MemRefToSPIRV/alloc.mlir --- a/mlir/test/Conversion/MemRefToSPIRV/alloc.mlir +++ b/mlir/test/Conversion/MemRefToSPIRV/alloc.mlir @@ -13,15 +13,15 @@ return } } -// CHECK: spirv.GlobalVariable @[[VAR:.+]] : !spirv.ptr)>, Workgroup> -// CHECK: func @alloc_dealloc_workgroup_mem -// CHECK-NOT: memref.alloc -// CHECK: %[[PTR:.+]] = spirv.mlir.addressof @[[VAR]] -// CHECK: %[[LOADPTR:.+]] = spirv.AccessChain %[[PTR]] -// CHECK: %[[VAL:.+]] = spirv.Load "Workgroup" %[[LOADPTR]] : f32 -// CHECK: %[[STOREPTR:.+]] = spirv.AccessChain %[[PTR]] -// CHECK: spirv.Store "Workgroup" %[[STOREPTR]], %[[VAL]] : f32 -// CHECK-NOT: memref.dealloc +// CHECK: spirv.GlobalVariable @[[$VAR:.+]] : !spirv.ptr)>, Workgroup> +// CHECK-LABEL: func @alloc_dealloc_workgroup_mem +// CHECK-NOT: memref.alloc +// CHECK: %[[PTR:.+]] = spirv.mlir.addressof @[[$VAR]] +// CHECK: %[[LOADPTR:.+]] = spirv.AccessChain %[[PTR]] +// CHECK: %[[VAL:.+]] = spirv.Load "Workgroup" %[[LOADPTR]] : f32 +// CHECK: %[[STOREPTR:.+]] = spirv.AccessChain %[[PTR]] +// CHECK: spirv.Store "Workgroup" %[[STOREPTR]], %[[VAL]] : f32 +// CHECK-NOT: memref.dealloc // ----- @@ -41,7 +41,7 @@ // CHECK: spirv.GlobalVariable @__workgroup_mem__{{[0-9]+}} // CHECK-SAME: !spirv.ptr)>, Workgroup> -// CHECK: func @alloc_dealloc_workgroup_mem +// CHECK-LABEL: func @alloc_dealloc_workgroup_mem // CHECK: %[[VAR:.+]] = spirv.mlir.addressof @__workgroup_mem__0 // CHECK: %[[LOC:.+]] = spirv.SDiv // CHECK: %[[PTR:.+]] = spirv.AccessChain %[[VAR]][%{{.+}}, %[[LOC]]] @@ -66,11 +66,11 @@ } } -// CHECK-DAG: spirv.GlobalVariable @__workgroup_mem__{{[0-9]+}} -// CHECK-SAME: !spirv.ptr)>, Workgroup> -// CHECK-DAG: spirv.GlobalVariable @__workgroup_mem__{{[0-9]+}} -// CHECK-SAME: !spirv.ptr)>, Workgroup> -// CHECK: func @two_allocs() +// CHECK-DAG: spirv.GlobalVariable @__workgroup_mem__{{[0-9]+}} +// CHECK-SAME: !spirv.ptr)>, Workgroup> +// CHECK-DAG: spirv.GlobalVariable @__workgroup_mem__{{[0-9]+}} +// CHECK-SAME: !spirv.ptr)>, Workgroup> +// CHECK-LABEL: func @two_allocs() // ----- @@ -86,11 +86,11 @@ } } -// CHECK-DAG: spirv.GlobalVariable @__workgroup_mem__{{[0-9]+}} -// CHECK-SAME: !spirv.ptr>)>, Workgroup> -// CHECK-DAG: spirv.GlobalVariable @__workgroup_mem__{{[0-9]+}} -// CHECK-SAME: !spirv.ptr>)>, Workgroup> -// CHECK: func @two_allocs_vector() +// CHECK-DAG: spirv.GlobalVariable @__workgroup_mem__{{[0-9]+}} +// CHECK-SAME: !spirv.ptr>)>, Workgroup> +// CHECK-DAG: spirv.GlobalVariable @__workgroup_mem__{{[0-9]+}} +// CHECK-SAME: !spirv.ptr>)>, Workgroup> +// CHECK-LABEL: func @two_allocs_vector() // ----- @@ -170,12 +170,12 @@ return } } -// CHECK: spirv.GlobalVariable @[[VAR:.+]] : !spirv.ptr, Workgroup> -// CHECK: func @alloc_dealloc_workgroup_mem -// CHECK-NOT: memref.alloc -// CHECK: %[[PTR:.+]] = spirv.mlir.addressof @[[VAR]] -// CHECK: %[[LOADPTR:.+]] = spirv.AccessChain %[[PTR]] -// CHECK: %[[VAL:.+]] = spirv.Load "Workgroup" %[[LOADPTR]] : f32 -// CHECK: %[[STOREPTR:.+]] = spirv.AccessChain %[[PTR]] -// CHECK: spirv.Store "Workgroup" %[[STOREPTR]], %[[VAL]] : f32 -// CHECK-NOT: memref.dealloc +// CHECK: spirv.GlobalVariable @[[$VAR:.+]] : !spirv.ptr, Workgroup> +// CHECK-LABEL: func @alloc_dealloc_workgroup_mem +// CHECK-NOT: memref.alloc +// CHECK: %[[PTR:.+]] = spirv.mlir.addressof @[[$VAR]] +// CHECK: %[[LOADPTR:.+]] = spirv.AccessChain %[[PTR]] +// CHECK: %[[VAL:.+]] = spirv.Load "Workgroup" %[[LOADPTR]] : f32 +// CHECK: %[[STOREPTR:.+]] = spirv.AccessChain %[[PTR]] +// CHECK: spirv.Store "Workgroup" %[[STOREPTR]], %[[VAL]] : f32 +// CHECK-NOT: memref.dealloc