diff --git a/llvm/lib/CodeGen/RegAllocFast.cpp b/llvm/lib/CodeGen/RegAllocFast.cpp --- a/llvm/lib/CodeGen/RegAllocFast.cpp +++ b/llvm/lib/CodeGen/RegAllocFast.cpp @@ -833,8 +833,10 @@ if (!BestReg) { // Nothing we can do: Report an error and keep going with an invalid // allocation. - if (MI.isInlineAsm()) + if (MI.isInlineAsm()) { MI.emitError("inline assembly requires more registers than available"); + report_fatal_error("inline assembly requires more registers than available", false); + } else MI.emitError("ran out of registers during register allocation"); diff --git a/llvm/test/CodeGen/X86/inline-asm-assertion.ll b/llvm/test/CodeGen/X86/inline-asm-assertion.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/X86/inline-asm-assertion.ll @@ -0,0 +1,75 @@ +; REQUIRES: x86-registered-target +; RUN: not llc -O0 < %s 2>&1 | FileCheck %s +; CHECK: LLVM ERROR: inline assembly requires more registers than available +; CHECK-NOT: Assertion `PhysReg != 0 && "Register not assigned"' failed + +; ModuleID = 'test.c' +source_filename = "test.c" +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +; Function Attrs: noinline nounwind optnone uwtable +define dso_local i32 @main() #0 { +entry: + %r0 = alloca i32, align 4 + %r1 = alloca i32, align 4 + %r2 = alloca i32, align 4 + %r3 = alloca i32, align 4 + %r4 = alloca i32, align 4 + %r5 = alloca i32, align 4 + %r6 = alloca i32, align 4 + %r7 = alloca i32, align 4 + %r8 = alloca i32, align 4 + %r9 = alloca i32, align 4 + %r10 = alloca i32, align 4 + %r11 = alloca i32, align 4 + %r12 = alloca i32, align 4 + %r13 = alloca i32, align 4 + %r14 = alloca i32, align 4 + %0 = call { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } asm "movl $$0, $0;movl $$11, $1;movl $$22, $2;movl $$33, $3;movl $$44, $4;movl $$55, $5;movl $$66, $6;movl $$77, $7;movl $$88, $8;movl $$99, $9;movl $$110, $10;movl $$121, $11;movl $$132, $12;movl $$143, $13;movl $$143, $14;", "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,~{dirflag},~{fpsr},~{flags}"() #1, !srcloc !6 + %asmresult = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %0, 0 + %asmresult1 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %0, 1 + %asmresult2 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %0, 2 + %asmresult3 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %0, 3 + %asmresult4 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %0, 4 + %asmresult5 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %0, 5 + %asmresult6 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %0, 6 + %asmresult7 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %0, 7 + %asmresult8 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %0, 8 + %asmresult9 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %0, 9 + %asmresult10 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %0, 10 + %asmresult11 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %0, 11 + %asmresult12 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %0, 12 + %asmresult13 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %0, 13 + %asmresult14 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %0, 14 + store i32 %asmresult, ptr %r0, align 4 + store i32 %asmresult1, ptr %r1, align 4 + store i32 %asmresult2, ptr %r2, align 4 + store i32 %asmresult3, ptr %r3, align 4 + store i32 %asmresult4, ptr %r4, align 4 + store i32 %asmresult5, ptr %r5, align 4 + store i32 %asmresult6, ptr %r6, align 4 + store i32 %asmresult7, ptr %r7, align 4 + store i32 %asmresult8, ptr %r8, align 4 + store i32 %asmresult9, ptr %r9, align 4 + store i32 %asmresult10, ptr %r10, align 4 + store i32 %asmresult11, ptr %r11, align 4 + store i32 %asmresult12, ptr %r12, align 4 + store i32 %asmresult13, ptr %r13, align 4 + store i32 %asmresult14, ptr %r14, align 4 + ret i32 0 +} + +attributes #0 = { noinline nounwind optnone uwtable "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" } +attributes #1 = { nounwind readnone } + +!llvm.module.flags = !{!0, !1, !2, !3, !4} +!llvm.ident = !{!5} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 7, !"PIC Level", i32 2} +!2 = !{i32 7, !"PIE Level", i32 2} +!3 = !{i32 7, !"uwtable", i32 2} +!4 = !{i32 7, !"frame-pointer", i32 2} +!5 = !{!"Huawei BiSheng Compiler clang version 15.0.4"} +!6 = !{i64 102}