diff --git a/llvm/lib/Target/RISCV/RISCV.h b/llvm/lib/Target/RISCV/RISCV.h
--- a/llvm/lib/Target/RISCV/RISCV.h
+++ b/llvm/lib/Target/RISCV/RISCV.h
@@ -70,6 +70,10 @@
 void initializeRISCVInitUndefPass(PassRegistry &);
 extern char &RISCVInitUndefID;
 
+FunctionPass *createRISCVInitSubUndefPass();
+void initializeRISCVInitSubUndefPass(PassRegistry &);
+extern char &RISCVInitSubUndefID;
+
 FunctionPass *createRISCVMoveMergePass();
 void initializeRISCVMoveMergePass(PassRegistry &);
 
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -5425,7 +5425,13 @@
   def PseudoRVVInitUndefM2 : Pseudo<(outs VRM2:$vd), (ins), [], "">;
   def PseudoRVVInitUndefM4 : Pseudo<(outs VRM4:$vd), (ins), [], "">;
   def PseudoRVVInitUndefM8 : Pseudo<(outs VRM8:$vd), (ins), [], "">;
-}
+  // RVVInitSubUndef will transform into RVVInitUndef
+  let Constraints = "$vd = $vs1" in {
+    def PseudoRVVInitSubUndefM2 : Pseudo<(outs VRM2:$vd), (ins VRM2:$vs1, i32imm:$subidx), [], "">;
+    def PseudoRVVInitSubUndefM4 : Pseudo<(outs VRM4:$vd), (ins VRM4:$vs1, i32imm:$subidx), [], "">;
+    def PseudoRVVInitSubUndefM8 : Pseudo<(outs VRM8:$vd), (ins VRM8:$vs1, i32imm:$subidx), [], "">;
+  } // Constraints = "$vd = $vs1"
+} // hasSideEffects = 0, mayLoad = 0, mayStore = 0, Size = 0, isCodeGenOnly = 1
 
 //===----------------------------------------------------------------------===//
 // 6. Configuration-Setting Instructions
diff --git a/llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp b/llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp
--- a/llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp
@@ -24,9 +24,9 @@
 // When we enable the subregister liveness option, it will also trigger same
 // issue due to the partial of register is undef. If we pseudoinit the whole
 // register, then it will generate redundant COPY instruction. Currently, it
-// will generate INSERT_SUBREG to make sure the whole register is occupied
-// when program encounter operation that has early-clobber constraint.
-//
+// will generate RVVInitSubUndef and transform it into RVVInitUndef to make
+// sure the whole register is occupied when program encounter operation that
+// has early-clobber constraint.
 //
 // See also: https://github.com/llvm/llvm-project/issues/50157
 //
@@ -40,6 +40,7 @@
 
 #define DEBUG_TYPE "riscv-init-undef"
 #define RISCV_INIT_UNDEF_NAME "RISC-V init undef pass"
+#define RISCV_INIT_SUB_UNDEF_NAME "RISC-V init sub undef pass"
 
 namespace {
 
@@ -70,20 +71,46 @@
   bool handleImplicitDef(MachineBasicBlock &MBB,
                          MachineBasicBlock::iterator &Inst);
   bool isVectorRegClass(const Register R);
-  const TargetRegisterClass *
-  getVRLargestSuperClass(const TargetRegisterClass *RC) const;
   bool handleSubReg(MachineFunction &MF, MachineInstr &MI,
                     const DeadLaneDetector &DLD);
 };
 
+class RISCVInitSubUndef : public MachineFunctionPass {
+  const TargetInstrInfo *TII;
+  MachineRegisterInfo *MRI;
+  const RISCVSubtarget *ST;
+  const TargetRegisterInfo *TRI;
+
+public:
+  static char ID;
+
+  RISCVInitSubUndef() : MachineFunctionPass(ID) {
+    initializeRISCVInitSubUndefPass(*PassRegistry::getPassRegistry());
+  }
+  bool runOnMachineFunction(MachineFunction &MF) override;
+
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
+    AU.setPreservesCFG();
+    MachineFunctionPass::getAnalysisUsage(AU);
+  }
+
+  StringRef getPassName() const override { return RISCV_INIT_SUB_UNDEF_NAME; }
+};
+
 } // end anonymous namespace
 
 char RISCVInitUndef::ID = 0;
-INITIALIZE_PASS(RISCVInitUndef, DEBUG_TYPE, RISCV_INIT_UNDEF_NAME, false, false)
+INITIALIZE_PASS(RISCVInitUndef, "riscv-init-undef", RISCV_INIT_UNDEF_NAME,
+                false, false)
 char &llvm::RISCVInitUndefID = RISCVInitUndef::ID;
 
-const TargetRegisterClass *
-RISCVInitUndef::getVRLargestSuperClass(const TargetRegisterClass *RC) const {
+char RISCVInitSubUndef::ID = 0;
+INITIALIZE_PASS(RISCVInitSubUndef, "riscv-sub-init-undef",
+                RISCV_INIT_SUB_UNDEF_NAME, false, false)
+char &llvm::RISCVInitSubUndefID = RISCVInitSubUndef::ID;
+
+static const TargetRegisterClass *
+getVRLargestSuperClass(const TargetRegisterClass *RC) {
   if (RISCV::VRM8RegClass.hasSubClassEq(RC))
     return &RISCV::VRM8RegClass;
   if (RISCV::VRM4RegClass.hasSubClassEq(RC))
@@ -177,6 +204,19 @@
   });
 }
 
+static unsigned getUndefSubInitOpcode(unsigned RegClassID) {
+  switch (RegClassID) {
+  case RISCV::VRM2RegClassID:
+    return RISCV::PseudoRVVInitSubUndefM2;
+  case RISCV::VRM4RegClassID:
+    return RISCV::PseudoRVVInitSubUndefM4;
+  case RISCV::VRM8RegClassID:
+    return RISCV::PseudoRVVInitSubUndefM8;
+  default:
+    llvm_unreachable("Unexpected register class.");
+  }
+}
+
 bool RISCVInitUndef::handleSubReg(MachineFunction &MF, MachineInstr &MI,
                                   const DeadLaneDetector &DLD) {
   bool Changed = false;
@@ -214,21 +254,13 @@
     Register LatestReg = Reg;
     for (auto ind : SubRegIndexNeedInsert) {
       Changed = true;
-      const TargetRegisterClass *SubRegClass =
-          getVRLargestSuperClass(TRI->getSubRegisterClass(TargetRegClass, ind));
-      Register TmpInitSubReg = MRI->createVirtualRegister(SubRegClass);
-      BuildMI(*MI.getParent(), &MI, MI.getDebugLoc(),
-              TII->get(getUndefInitOpcode(SubRegClass->getID())),
-              TmpInitSubReg);
       Register NewReg = MRI->createVirtualRegister(TargetRegClass);
       BuildMI(*MI.getParent(), &MI, MI.getDebugLoc(),
-              TII->get(TargetOpcode::INSERT_SUBREG), NewReg)
+              TII->get(getUndefSubInitOpcode(TargetRegClass->getID())), NewReg)
           .addReg(LatestReg)
-          .addReg(TmpInitSubReg)
           .addImm(ind);
       LatestReg = NewReg;
     }
-
     UseMO.setReg(LatestReg);
   }
 
@@ -271,4 +303,90 @@
   return Changed;
 }
 
+static bool isRVVInitSubUndef(unsigned Opcode) {
+  switch (Opcode) {
+  case RISCV::PseudoRVVInitSubUndefM2:
+  case RISCV::PseudoRVVInitSubUndefM4:
+  case RISCV::PseudoRVVInitSubUndefM8:
+    return true;
+  default:
+    return false;
+  }
+}
+
+// Here is a sub-register example
+//
+// %0:vrm2 = IMPLICIT_DEF
+// %1:vr = from func args
+// %2:vrm2 = INSERT_SUBREG %0, %1, %subreg.sub_vrm1_0
+// early-clobber %3:vr = op %2:vrm2
+//
+// %3 may overlap with %2 due to %2 has partial undef.
+// Init undef pass will detect and try to fix it.
+//
+// Apply init undef pass
+//
+// %0:vrm2 = IMPLICIT_DEF
+// %1:vr = from func args
+// %2:vrm2 = INSERT_SUBREG %0, %1, %subreg.sub_vrm1_0
+// %4:vrm2 = RVVInitSubUndef %2, %subreg.sub_vrm1_1
+// early-clobber %3:vr = op %4:vrm2
+//
+// Apply TwoAddr pass
+//
+// %0:vrm2 = IMPLICIT_DEF
+// %1:vr = from func args
+// %2:vrm2 = INSERT_SUBREG %0, %1, %subreg.sub_vrm1_0
+// %3:vrm2 = COPY %2
+// %3:vrm2 = RVVInitSubUndef %3, %subreg.sub_vrm1_1
+// early-clobber %4:vr = op %3:vrm2
+//
+// Apply init sub undef pass
+//
+// %0:vrm2 = IMPLICIT_DEF
+// %1:vr = from func args
+// %2:vrm2 = INSERT_SUBREG %0, %1, %subreg.sub_vrm1_0
+// %3:vrm2 = COPY %2
+// %3.sub_vrm1_1:vrm2 = RVVInitUndef
+// early-clobber %4:vr = op %3:vrm2
+//
+bool RISCVInitSubUndef::runOnMachineFunction(MachineFunction &MF) {
+  ST = &MF.getSubtarget<RISCVSubtarget>();
+  if (!ST->hasVInstructions())
+    return false;
+
+  MRI = &MF.getRegInfo();
+  TII = ST->getInstrInfo();
+  TRI = MRI->getTargetRegisterInfo();
+
+  bool Changed = false;
+
+  for (MachineBasicBlock &BB : MF) {
+    for (MachineInstr &MI : BB) {
+      if (isRVVInitSubUndef(MI.getOpcode())) {
+        Changed = true;
+        // RVVInitSubUndef -> RVVInitUndef
+        // %3:vrm2 = RVVInitSubUndef %3, %subreg.sub_vrm1_1
+        // =>
+        // %3.sub_vrm1_1:vrm2 = RVVInitUndef
+        unsigned SubIdx = MI.getOperand(2).getImm();
+        MI.removeOperand(2);
+        MI.getOperand(0).setReg(MI.getOperand(1).getReg());
+        MI.getOperand(0).setSubReg(SubIdx);
+        MI.setDesc(TII->get(getUndefInitOpcode(
+            getVRLargestSuperClass(
+                TRI->getSubRegisterClass(
+                    MRI->getRegClass(MI.getOperand(1).getReg()), SubIdx))
+                ->getID())));
+        MI.removeOperand(1);
+      }
+    }
+  }
+
+  return Changed;
+}
+
 FunctionPass *llvm::createRISCVInitUndefPass() { return new RISCVInitUndef(); }
+FunctionPass *llvm::createRISCVInitSubUndefPass() {
+  return new RISCVInitSubUndef();
+}
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -88,6 +88,7 @@
   initializeRISCVInsertReadWriteCSRPass(*PR);
   initializeRISCVDAGToDAGISelPass(*PR);
   initializeRISCVInitUndefPass(*PR);
+  initializeRISCVInitSubUndefPass(*PR);
   initializeRISCVMoveMergePass(*PR);
   initializeRISCVPushPopOptPass(*PR);
 }
@@ -392,8 +393,10 @@
 }
 
 void RISCVPassConfig::addOptimizedRegAlloc() {
-  if (getOptimizeRegAlloc())
+  if (getOptimizeRegAlloc()) {
     insertPass(&DetectDeadLanesID, &RISCVInitUndefID);
+    insertPass(&TwoAddressInstructionPassID, &RISCVInitSubUndefID);
+  }
 
   TargetPassConfig::addOptimizedRegAlloc();
 }
diff --git a/llvm/test/CodeGen/RISCV/O3-pipeline.ll b/llvm/test/CodeGen/RISCV/O3-pipeline.ll
--- a/llvm/test/CodeGen/RISCV/O3-pipeline.ll
+++ b/llvm/test/CodeGen/RISCV/O3-pipeline.ll
@@ -116,6 +116,7 @@
 ; CHECK-NEXT:       Live Variable Analysis
 ; CHECK-NEXT:       Eliminate PHI nodes for register allocation
 ; CHECK-NEXT:       Two-Address instruction pass
+; CHECK-NEXT:       RISC-V init sub undef pass
 ; CHECK-NEXT:       MachineDominator Tree Construction
 ; CHECK-NEXT:       Slot index numbering
 ; CHECK-NEXT:       Live Interval Analysis
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
@@ -656,15 +656,15 @@
 ; RV64-NEXT:    addi sp, sp, -16
 ; RV64-NEXT:    .cfi_def_cfa_offset 16
 ; RV64-NEXT:    csrr a2, vlenb
-; RV64-NEXT:    li a3, 86
+; RV64-NEXT:    li a3, 92
 ; RV64-NEXT:    mul a2, a2, a3
 ; RV64-NEXT:    sub sp, sp, a2
-; RV64-NEXT:    .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0xd6, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 86 * vlenb
+; RV64-NEXT:    .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0xdc, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 92 * vlenb
 ; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
 ; RV64-NEXT:    addi a2, a1, 256
 ; RV64-NEXT:    vle64.v v16, (a2)
 ; RV64-NEXT:    csrr a2, vlenb
-; RV64-NEXT:    li a3, 53
+; RV64-NEXT:    li a3, 60
 ; RV64-NEXT:    mul a2, a2, a3
 ; RV64-NEXT:    add a2, sp, a2
 ; RV64-NEXT:    addi a2, a2, 16
@@ -672,14 +672,14 @@
 ; RV64-NEXT:    addi a2, a1, 128
 ; RV64-NEXT:    vle64.v v8, (a2)
 ; RV64-NEXT:    csrr a2, vlenb
-; RV64-NEXT:    li a3, 77
+; RV64-NEXT:    li a3, 84
 ; RV64-NEXT:    mul a2, a2, a3
 ; RV64-NEXT:    add a2, sp, a2
 ; RV64-NEXT:    addi a2, a2, 16
 ; RV64-NEXT:    vs8r.v v8, (a2) # Unknown-size Folded Spill
 ; RV64-NEXT:    vle64.v v8, (a1)
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 69
+; RV64-NEXT:    li a2, 76
 ; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
@@ -692,7 +692,7 @@
 ; RV64-NEXT:    vsetivli zero, 8, e64, m8, ta, ma
 ; RV64-NEXT:    vslidedown.vi v24, v16, 8
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 45
+; RV64-NEXT:    li a2, 52
 ; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
@@ -700,8 +700,8 @@
 ; RV64-NEXT:    vsetivli zero, 8, e64, m4, ta, mu
 ; RV64-NEXT:    vmv1r.v v0, v1
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    slli a2, a1, 5
-; RV64-NEXT:    add a1, a2, a1
+; RV64-NEXT:    li a2, 40
+; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vs1r.v v1, (a1) # Unknown-size Folded Spill
@@ -712,14 +712,14 @@
 ; RV64-NEXT:    vid.v v16
 ; RV64-NEXT:    vmul.vx v24, v16, a1
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 61
+; RV64-NEXT:    li a2, 68
 ; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vs8r.v v24, (a1) # Unknown-size Folded Spill
 ; RV64-NEXT:    li a1, 56
 ; RV64-NEXT:    csrr a2, vlenb
-; RV64-NEXT:    li a3, 69
+; RV64-NEXT:    li a3, 76
 ; RV64-NEXT:    mul a2, a2, a3
 ; RV64-NEXT:    add a2, sp, a2
 ; RV64-NEXT:    addi a2, a2, 16
@@ -729,14 +729,14 @@
 ; RV64-NEXT:    vsetivli zero, 1, e16, mf4, ta, ma
 ; RV64-NEXT:    vmv.v.x v0, a1
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 37
+; RV64-NEXT:    li a2, 44
 ; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vs1r.v v0, (a1) # Unknown-size Folded Spill
 ; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 77
+; RV64-NEXT:    li a2, 84
 ; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
@@ -745,14 +745,13 @@
 ; RV64-NEXT:    vsetivli zero, 6, e64, m4, tu, ma
 ; RV64-NEXT:    vmv.v.v v4, v16
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 25
-; RV64-NEXT:    mul a1, a1, a2
+; RV64-NEXT:    slli a1, a1, 5
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vs4r.v v4, (a1) # Unknown-size Folded Spill
 ; RV64-NEXT:    vsetivli zero, 8, e64, m4, ta, mu
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 53
+; RV64-NEXT:    li a2, 60
 ; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
@@ -760,28 +759,28 @@
 ; RV64-NEXT:    vrgather.vi v12, v8, 5
 ; RV64-NEXT:    vmv1r.v v0, v1
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 45
+; RV64-NEXT:    li a2, 52
 ; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vl8r.v v24, (a1) # Unknown-size Folded Reload
 ; RV64-NEXT:    vrgather.vi v12, v24, 3, v0.t
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 41
+; RV64-NEXT:    li a2, 48
 ; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vs4r.v v12, (a1) # Unknown-size Folded Spill
 ; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 61
+; RV64-NEXT:    li a2, 68
 ; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vl8r.v v8, (a1) # Unknown-size Folded Reload
 ; RV64-NEXT:    vadd.vi v0, v8, 1
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 69
+; RV64-NEXT:    li a2, 76
 ; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
@@ -789,13 +788,13 @@
 ; RV64-NEXT:    vrgather.vv v16, v24, v0
 ; RV64-NEXT:    vadd.vi v24, v8, -15
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 37
+; RV64-NEXT:    li a2, 44
 ; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vl1r.v v0, (a1) # Unknown-size Folded Reload
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 77
+; RV64-NEXT:    li a2, 84
 ; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
@@ -803,14 +802,14 @@
 ; RV64-NEXT:    vrgather.vv v16, v8, v24, v0.t
 ; RV64-NEXT:    vsetivli zero, 6, e64, m4, tu, ma
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 41
+; RV64-NEXT:    li a2, 48
 ; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vl4r.v v8, (a1) # Unknown-size Folded Reload
 ; RV64-NEXT:    vmv.v.v v8, v16
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 41
+; RV64-NEXT:    li a2, 48
 ; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
@@ -818,7 +817,7 @@
 ; RV64-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
 ; RV64-NEXT:    vmv.v.i v8, 6
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 29
+; RV64-NEXT:    li a2, 36
 ; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
@@ -826,57 +825,56 @@
 ; RV64-NEXT:    vmv.s.x v12, zero
 ; RV64-NEXT:    vsetivli zero, 6, e64, m4, tu, ma
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    slli a2, a1, 3
-; RV64-NEXT:    add a1, a2, a1
+; RV64-NEXT:    slli a1, a1, 4
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vs4r.v v12, (a1) # Unknown-size Folded Spill
 ; RV64-NEXT:    vslideup.vi v8, v12, 5
 ; RV64-NEXT:    vsetivli zero, 8, e64, m4, ta, mu
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 53
+; RV64-NEXT:    li a2, 60
 ; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vl8r.v v16, (a1) # Unknown-size Folded Reload
 ; RV64-NEXT:    vrgather.vv v12, v16, v8
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    slli a2, a1, 5
-; RV64-NEXT:    add a1, a2, a1
+; RV64-NEXT:    li a2, 40
+; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vl1r.v v0, (a1) # Unknown-size Folded Reload
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 45
+; RV64-NEXT:    li a2, 52
 ; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vl8r.v v16, (a1) # Unknown-size Folded Reload
 ; RV64-NEXT:    vrgather.vi v12, v16, 4, v0.t
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 37
+; RV64-NEXT:    li a2, 44
 ; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vs4r.v v12, (a1) # Unknown-size Folded Spill
 ; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 61
+; RV64-NEXT:    li a2, 68
 ; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vl8r.v v0, (a1) # Unknown-size Folded Reload
 ; RV64-NEXT:    vadd.vi v8, v0, 2
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 69
+; RV64-NEXT:    li a2, 76
 ; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vl8r.v v24, (a1) # Unknown-size Folded Reload
 ; RV64-NEXT:    vrgather.vv v16, v24, v8
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    slli a2, a1, 4
-; RV64-NEXT:    add a1, a2, a1
+; RV64-NEXT:    li a2, 24
+; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vs8r.v v16, (a1) # Unknown-size Folded Spill
@@ -888,28 +886,28 @@
 ; RV64-NEXT:    vs1r.v v0, (a1) # Unknown-size Folded Spill
 ; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 77
+; RV64-NEXT:    li a2, 84
 ; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vl8r.v v16, (a1) # Unknown-size Folded Reload
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    slli a2, a1, 4
-; RV64-NEXT:    add a1, a2, a1
+; RV64-NEXT:    li a2, 24
+; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vl8r.v v24, (a1) # Unknown-size Folded Reload
 ; RV64-NEXT:    vrgather.vv v24, v16, v8, v0.t
 ; RV64-NEXT:    vsetivli zero, 5, e64, m4, tu, ma
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 37
+; RV64-NEXT:    li a2, 44
 ; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vl4r.v v8, (a1) # Unknown-size Folded Reload
 ; RV64-NEXT:    vmv.v.v v8, v24
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 37
+; RV64-NEXT:    li a2, 44
 ; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
@@ -918,15 +916,15 @@
 ; RV64-NEXT:    li a1, 1
 ; RV64-NEXT:    vmv.v.i v8, 7
 ; RV64-NEXT:    csrr a2, vlenb
-; RV64-NEXT:    slli a3, a2, 4
-; RV64-NEXT:    add a2, a3, a2
+; RV64-NEXT:    li a3, 24
+; RV64-NEXT:    mul a2, a2, a3
 ; RV64-NEXT:    add a2, sp, a2
 ; RV64-NEXT:    addi a2, a2, 16
 ; RV64-NEXT:    vs4r.v v8, (a2) # Unknown-size Folded Spill
 ; RV64-NEXT:    vmv.s.x v12, a1
 ; RV64-NEXT:    vsetivli zero, 6, e64, m4, tu, ma
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 13
+; RV64-NEXT:    li a2, 20
 ; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
@@ -934,265 +932,266 @@
 ; RV64-NEXT:    vslideup.vi v8, v12, 5
 ; RV64-NEXT:    vsetivli zero, 8, e64, m4, ta, mu
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 53
+; RV64-NEXT:    li a2, 60
 ; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
-; RV64-NEXT:    vl8r.v v16, (a1) # Unknown-size Folded Reload
-; RV64-NEXT:    vrgather.vv v12, v16, v8
+; RV64-NEXT:    vl8r.v v24, (a1) # Unknown-size Folded Reload
+; RV64-NEXT:    vrgather.vv v12, v24, v8
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    slli a2, a1, 5
-; RV64-NEXT:    add a1, a2, a1
+; RV64-NEXT:    li a2, 40
+; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vl1r.v v0, (a1) # Unknown-size Folded Reload
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 45
+; RV64-NEXT:    li a2, 52
 ; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vl8r.v v16, (a1) # Unknown-size Folded Reload
 ; RV64-NEXT:    vrgather.vi v12, v16, 5, v0.t
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    slli a2, a1, 5
-; RV64-NEXT:    add a1, a2, a1
+; RV64-NEXT:    li a2, 40
+; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vs4r.v v12, (a1) # Unknown-size Folded Spill
 ; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 61
+; RV64-NEXT:    li a2, 68
 ; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vl8r.v v0, (a1) # Unknown-size Folded Reload
 ; RV64-NEXT:    vadd.vi v24, v0, 3
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 69
+; RV64-NEXT:    li a2, 76
 ; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
-; RV64-NEXT:    vl8r.v v16, (a1) # Unknown-size Folded Reload
-; RV64-NEXT:    vrgather.vv v8, v16, v24
+; RV64-NEXT:    vl8r.v v8, (a1) # Unknown-size Folded Reload
+; RV64-NEXT:    vrgather.vv v16, v8, v24
 ; RV64-NEXT:    csrr a1, vlenb
+; RV64-NEXT:    slli a1, a1, 3
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
-; RV64-NEXT:    vs8r.v v8, (a1) # Unknown-size Folded Spill
-; RV64-NEXT:    vadd.vi v16, v0, -13
+; RV64-NEXT:    vs8r.v v16, (a1) # Unknown-size Folded Spill
+; RV64-NEXT:    vadd.vi v8, v0, -13
 ; RV64-NEXT:    addi a1, sp, 16
 ; RV64-NEXT:    vl1r.v v0, (a1) # Unknown-size Folded Reload
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 77
+; RV64-NEXT:    li a2, 84
 ; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vl8r.v v24, (a1) # Unknown-size Folded Reload
 ; RV64-NEXT:    csrr a1, vlenb
+; RV64-NEXT:    slli a1, a1, 3
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
-; RV64-NEXT:    vl8r.v v8, (a1) # Unknown-size Folded Reload
-; RV64-NEXT:    vrgather.vv v8, v24, v16, v0.t
+; RV64-NEXT:    vl8r.v v16, (a1) # Unknown-size Folded Reload
+; RV64-NEXT:    vrgather.vv v16, v24, v8, v0.t
 ; RV64-NEXT:    vsetivli zero, 5, e64, m4, tu, ma
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    slli a2, a1, 5
-; RV64-NEXT:    add a1, a2, a1
+; RV64-NEXT:    li a2, 40
+; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
-; RV64-NEXT:    vl4r.v v12, (a1) # Unknown-size Folded Reload
-; RV64-NEXT:    vmv.v.v v12, v8
+; RV64-NEXT:    vl4r.v v8, (a1) # Unknown-size Folded Reload
+; RV64-NEXT:    vmv.v.v v8, v16
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    slli a2, a1, 5
-; RV64-NEXT:    add a1, a2, a1
+; RV64-NEXT:    li a2, 40
+; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
-; RV64-NEXT:    vs4r.v v12, (a1) # Unknown-size Folded Spill
+; RV64-NEXT:    vs4r.v v8, (a1) # Unknown-size Folded Spill
 ; RV64-NEXT:    vsetivli zero, 7, e64, m4, tu, ma
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    slli a2, a1, 3
-; RV64-NEXT:    add a1, a2, a1
+; RV64-NEXT:    slli a1, a1, 4
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vl4r.v v8, (a1) # Unknown-size Folded Reload
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 29
+; RV64-NEXT:    li a2, 36
 ; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
-; RV64-NEXT:    vl4r.v v16, (a1) # Unknown-size Folded Reload
-; RV64-NEXT:    vslideup.vi v16, v8, 6
+; RV64-NEXT:    vl4r.v v24, (a1) # Unknown-size Folded Reload
+; RV64-NEXT:    vslideup.vi v24, v8, 6
 ; RV64-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
 ; RV64-NEXT:    li a1, 192
 ; RV64-NEXT:    csrr a2, vlenb
-; RV64-NEXT:    li a3, 53
+; RV64-NEXT:    li a3, 60
 ; RV64-NEXT:    mul a2, a2, a3
 ; RV64-NEXT:    add a2, sp, a2
 ; RV64-NEXT:    addi a2, a2, 16
 ; RV64-NEXT:    vl8r.v v8, (a2) # Unknown-size Folded Reload
-; RV64-NEXT:    vrgather.vi v20, v8, 2
+; RV64-NEXT:    vrgather.vi v16, v8, 2
 ; RV64-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma
 ; RV64-NEXT:    vmv.v.x v0, a1
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    slli a2, a1, 3
-; RV64-NEXT:    add a1, a2, a1
+; RV64-NEXT:    slli a1, a1, 4
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vs1r.v v0, (a1) # Unknown-size Folded Spill
 ; RV64-NEXT:    vsetivli zero, 8, e64, m4, ta, mu
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 45
+; RV64-NEXT:    li a2, 52
 ; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vl8r.v v8, (a1) # Unknown-size Folded Reload
-; RV64-NEXT:    vrgather.vv v20, v8, v16, v0.t
+; RV64-NEXT:    vrgather.vv v16, v8, v24, v0.t
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 29
+; RV64-NEXT:    li a2, 36
 ; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
-; RV64-NEXT:    vs4r.v v20, (a1) # Unknown-size Folded Spill
+; RV64-NEXT:    vs4r.v v16, (a1) # Unknown-size Folded Spill
 ; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 61
+; RV64-NEXT:    li a2, 68
 ; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
-; RV64-NEXT:    vl8r.v v0, (a1) # Unknown-size Folded Reload
-; RV64-NEXT:    vadd.vi v24, v0, 4
+; RV64-NEXT:    vl8r.v v8, (a1) # Unknown-size Folded Reload
+; RV64-NEXT:    vadd.vi v24, v8, 4
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 69
+; RV64-NEXT:    li a2, 76
 ; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
-; RV64-NEXT:    vl8r.v v16, (a1) # Unknown-size Folded Reload
-; RV64-NEXT:    vrgather.vv v8, v16, v24
+; RV64-NEXT:    vl8r.v v0, (a1) # Unknown-size Folded Reload
+; RV64-NEXT:    vrgather.vv v16, v0, v24
+; RV64-NEXT:    addi a1, sp, 16
+; RV64-NEXT:    vs8r.v v16, (a1) # Unknown-size Folded Spill
 ; RV64-NEXT:    li a1, 28
-; RV64-NEXT:    vadd.vi v16, v0, -12
-; RV64-NEXT:    csrr a2, vlenb
-; RV64-NEXT:    add a2, sp, a2
-; RV64-NEXT:    addi a2, a2, 16
-; RV64-NEXT:    vs8r.v v16, (a2) # Unknown-size Folded Spill
+; RV64-NEXT:    vadd.vi v16, v8, -12
 ; RV64-NEXT:    vsetivli zero, 1, e16, mf4, ta, ma
 ; RV64-NEXT:    vmv.v.x v0, a1
-; RV64-NEXT:    addi a1, sp, 16
+; RV64-NEXT:    csrr a1, vlenb
+; RV64-NEXT:    slli a1, a1, 3
+; RV64-NEXT:    add a1, sp, a1
+; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vs1r.v v0, (a1) # Unknown-size Folded Spill
 ; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 77
+; RV64-NEXT:    li a2, 84
 ; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vl8r.v v24, (a1) # Unknown-size Folded Reload
-; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    add a1, sp, a1
-; RV64-NEXT:    addi a1, a1, 16
-; RV64-NEXT:    vl8r.v v16, (a1) # Unknown-size Folded Reload
+; RV64-NEXT:    addi a1, sp, 16
+; RV64-NEXT:    vl8r.v v8, (a1) # Unknown-size Folded Reload
 ; RV64-NEXT:    vrgather.vv v8, v24, v16, v0.t
 ; RV64-NEXT:    vsetivli zero, 5, e64, m4, tu, ma
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 29
+; RV64-NEXT:    li a2, 36
 ; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vl4r.v v12, (a1) # Unknown-size Folded Reload
 ; RV64-NEXT:    vmv.v.v v12, v8
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 29
+; RV64-NEXT:    li a2, 36
 ; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vs4r.v v12, (a1) # Unknown-size Folded Spill
 ; RV64-NEXT:    vsetivli zero, 7, e64, m4, tu, ma
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 13
+; RV64-NEXT:    li a2, 20
 ; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vl4r.v v8, (a1) # Unknown-size Folded Reload
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    slli a2, a1, 4
-; RV64-NEXT:    add a1, a2, a1
+; RV64-NEXT:    li a2, 24
+; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vl4r.v v24, (a1) # Unknown-size Folded Reload
 ; RV64-NEXT:    vslideup.vi v24, v8, 6
 ; RV64-NEXT:    vsetivli zero, 8, e64, m4, ta, mu
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 53
+; RV64-NEXT:    li a2, 60
 ; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vl8r.v v8, (a1) # Unknown-size Folded Reload
 ; RV64-NEXT:    vrgather.vi v16, v8, 3
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    slli a2, a1, 3
-; RV64-NEXT:    add a1, a2, a1
+; RV64-NEXT:    slli a1, a1, 4
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vl1r.v v0, (a1) # Unknown-size Folded Reload
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 45
+; RV64-NEXT:    li a2, 52
 ; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vl8r.v v8, (a1) # Unknown-size Folded Reload
 ; RV64-NEXT:    vrgather.vv v16, v8, v24, v0.t
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    slli a2, a1, 4
-; RV64-NEXT:    add a1, a2, a1
+; RV64-NEXT:    li a2, 24
+; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vs4r.v v16, (a1) # Unknown-size Folded Spill
 ; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 61
+; RV64-NEXT:    li a2, 68
 ; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vl8r.v v8, (a1) # Unknown-size Folded Reload
 ; RV64-NEXT:    vadd.vi v24, v8, 5
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 69
+; RV64-NEXT:    li a2, 76
 ; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vl8r.v v0, (a1) # Unknown-size Folded Reload
 ; RV64-NEXT:    vrgather.vv v8, v0, v24
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 53
+; RV64-NEXT:    li a2, 60
 ; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vs8r.v v8, (a1) # Unknown-size Folded Spill
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 61
+; RV64-NEXT:    li a2, 68
 ; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vl8r.v v24, (a1) # Unknown-size Folded Reload
 ; RV64-NEXT:    vadd.vi v8, v24, -11
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 69
+; RV64-NEXT:    li a2, 76
 ; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vs8r.v v8, (a1) # Unknown-size Folded Spill
-; RV64-NEXT:    addi a1, sp, 16
+; RV64-NEXT:    csrr a1, vlenb
+; RV64-NEXT:    slli a1, a1, 3
+; RV64-NEXT:    add a1, sp, a1
+; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vl1r.v v0, (a1) # Unknown-size Folded Reload
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 77
+; RV64-NEXT:    li a2, 84
 ; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vl8r.v v24, (a1) # Unknown-size Folded Reload
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 69
+; RV64-NEXT:    li a2, 76
 ; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vl8r.v v8, (a1) # Unknown-size Folded Reload
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 53
+; RV64-NEXT:    li a2, 60
 ; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
@@ -1200,16 +1199,15 @@
 ; RV64-NEXT:    vrgather.vv v16, v24, v8, v0.t
 ; RV64-NEXT:    vsetivli zero, 5, e64, m4, tu, ma
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    slli a2, a1, 4
-; RV64-NEXT:    add a1, a2, a1
+; RV64-NEXT:    li a2, 24
+; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vl4r.v v12, (a1) # Unknown-size Folded Reload
 ; RV64-NEXT:    vmv.v.v v12, v16
 ; RV64-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 25
-; RV64-NEXT:    mul a1, a1, a2
+; RV64-NEXT:    slli a1, a1, 5
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vl4r.v v8, (a1) # Unknown-size Folded Reload
@@ -1218,7 +1216,7 @@
 ; RV64-NEXT:    vse64.v v12, (a1)
 ; RV64-NEXT:    addi a1, a0, 256
 ; RV64-NEXT:    csrr a2, vlenb
-; RV64-NEXT:    li a3, 29
+; RV64-NEXT:    li a3, 36
 ; RV64-NEXT:    mul a2, a2, a3
 ; RV64-NEXT:    add a2, sp, a2
 ; RV64-NEXT:    addi a2, a2, 16
@@ -1226,15 +1224,15 @@
 ; RV64-NEXT:    vse64.v v8, (a1)
 ; RV64-NEXT:    addi a1, a0, 192
 ; RV64-NEXT:    csrr a2, vlenb
-; RV64-NEXT:    slli a3, a2, 5
-; RV64-NEXT:    add a2, a3, a2
+; RV64-NEXT:    li a3, 40
+; RV64-NEXT:    mul a2, a2, a3
 ; RV64-NEXT:    add a2, sp, a2
 ; RV64-NEXT:    addi a2, a2, 16
 ; RV64-NEXT:    vl4r.v v8, (a2) # Unknown-size Folded Reload
 ; RV64-NEXT:    vse64.v v8, (a1)
 ; RV64-NEXT:    addi a1, a0, 128
 ; RV64-NEXT:    csrr a2, vlenb
-; RV64-NEXT:    li a3, 37
+; RV64-NEXT:    li a3, 44
 ; RV64-NEXT:    mul a2, a2, a3
 ; RV64-NEXT:    add a2, sp, a2
 ; RV64-NEXT:    addi a2, a2, 16
@@ -1242,14 +1240,14 @@
 ; RV64-NEXT:    vse64.v v8, (a1)
 ; RV64-NEXT:    addi a0, a0, 64
 ; RV64-NEXT:    csrr a1, vlenb
-; RV64-NEXT:    li a2, 41
+; RV64-NEXT:    li a2, 48
 ; RV64-NEXT:    mul a1, a1, a2
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vl4r.v v8, (a1) # Unknown-size Folded Reload
 ; RV64-NEXT:    vse64.v v8, (a0)
 ; RV64-NEXT:    csrr a0, vlenb
-; RV64-NEXT:    li a1, 86
+; RV64-NEXT:    li a1, 92
 ; RV64-NEXT:    mul a0, a0, a1
 ; RV64-NEXT:    add sp, sp, a0
 ; RV64-NEXT:    addi sp, sp, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
@@ -300,21 +300,21 @@
 ; CHECK-NEXT:    mul a5, a5, a6
 ; CHECK-NEXT:    add a5, sp, a5
 ; CHECK-NEXT:    addi a5, a5, 16
-; CHECK-NEXT:    vl8r.v v24, (a5) # Unknown-size Folded Reload
-; CHECK-NEXT:    vnsrl.wi v8, v24, 0, v0.t
+; CHECK-NEXT:    vl8r.v v8, (a5) # Unknown-size Folded Reload
+; CHECK-NEXT:    vnsrl.wi v24, v8, 0, v0.t
 ; CHECK-NEXT:    csrr a5, vlenb
 ; CHECK-NEXT:    li a6, 48
 ; CHECK-NEXT:    mul a5, a5, a6
 ; CHECK-NEXT:    add a5, sp, a5
 ; CHECK-NEXT:    addi a5, a5, 16
-; CHECK-NEXT:    vs8r.v v8, (a5) # Unknown-size Folded Spill
+; CHECK-NEXT:    vs8r.v v24, (a5) # Unknown-size Folded Spill
 ; CHECK-NEXT:    bltu a7, a3, .LBB16_4
 ; CHECK-NEXT:  # %bb.3:
 ; CHECK-NEXT:    li a7, 64
 ; CHECK-NEXT:  .LBB16_4:
 ; CHECK-NEXT:    li a3, 32
 ; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
-; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vle64.v v24, (a1)
 ; CHECK-NEXT:    addi a5, a7, -32
 ; CHECK-NEXT:    sltu a6, a7, a5
 ; CHECK-NEXT:    addi a6, a6, -1
@@ -325,9 +325,9 @@
 ; CHECK-NEXT:    and a6, t0, a6
 ; CHECK-NEXT:    vsetvli zero, a6, e32, m4, ta, ma
 ; CHECK-NEXT:    vmv1r.v v0, v4
-; CHECK-NEXT:    vnsrl.wi v24, v16, 0, v0.t
+; CHECK-NEXT:    vnsrl.wi v8, v16, 0, v0.t
 ; CHECK-NEXT:    addi a6, sp, 16
-; CHECK-NEXT:    vs8r.v v24, (a6) # Unknown-size Folded Spill
+; CHECK-NEXT:    vs8r.v v8, (a6) # Unknown-size Folded Spill
 ; CHECK-NEXT:    bltu a5, a2, .LBB16_6
 ; CHECK-NEXT:  # %bb.5:
 ; CHECK-NEXT:    li a5, 16
@@ -336,22 +336,22 @@
 ; CHECK-NEXT:    addi a1, a1, 256
 ; CHECK-NEXT:    vsetvli zero, a5, e32, m4, ta, ma
 ; CHECK-NEXT:    vmv1r.v v0, v2
-; CHECK-NEXT:    vnsrl.wi v16, v8, 0, v0.t
+; CHECK-NEXT:    vnsrl.wi v8, v24, 0, v0.t
 ; CHECK-NEXT:    csrr a5, vlenb
 ; CHECK-NEXT:    li t0, 40
 ; CHECK-NEXT:    mul a5, a5, t0
 ; CHECK-NEXT:    add a5, sp, a5
 ; CHECK-NEXT:    addi a5, a5, 16
-; CHECK-NEXT:    vs8r.v v16, (a5) # Unknown-size Folded Spill
+; CHECK-NEXT:    vs8r.v v8, (a5) # Unknown-size Folded Spill
 ; CHECK-NEXT:    bltu a4, a3, .LBB16_8
 ; CHECK-NEXT:  # %bb.7:
 ; CHECK-NEXT:    li a4, 32
 ; CHECK-NEXT:  .LBB16_8:
 ; CHECK-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-NEXT:    vslidedown.vi v20, v3, 2
+; CHECK-NEXT:    vslidedown.vi v12, v3, 2
 ; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
 ; CHECK-NEXT:    vle64.v v24, (a6)
-; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vle64.v v16, (a1)
 ; CHECK-NEXT:    mv a1, a4
 ; CHECK-NEXT:    bltu a4, a2, .LBB16_10
 ; CHECK-NEXT:  # %bb.9:
@@ -361,19 +361,19 @@
 ; CHECK-NEXT:    vslidedown.vi v2, v1, 2
 ; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma
 ; CHECK-NEXT:    vmv1r.v v0, v3
-; CHECK-NEXT:    vnsrl.wi v16, v8, 0, v0.t
+; CHECK-NEXT:    vnsrl.wi v8, v16, 0, v0.t
 ; CHECK-NEXT:    csrr a1, vlenb
 ; CHECK-NEXT:    slli a1, a1, 5
 ; CHECK-NEXT:    add a1, sp, a1
 ; CHECK-NEXT:    addi a1, a1, 16
-; CHECK-NEXT:    vs8r.v v16, (a1) # Unknown-size Folded Spill
+; CHECK-NEXT:    vs8r.v v8, (a1) # Unknown-size Folded Spill
 ; CHECK-NEXT:    addi a1, a4, -16
 ; CHECK-NEXT:    sltu a4, a4, a1
 ; CHECK-NEXT:    addi a4, a4, -1
 ; CHECK-NEXT:    and a1, a4, a1
 ; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v20
-; CHECK-NEXT:    vnsrl.wi v8, v24, 0, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v12
+; CHECK-NEXT:    vnsrl.wi v16, v24, 0, v0.t
 ; CHECK-NEXT:    bltu a7, a3, .LBB16_12
 ; CHECK-NEXT:  # %bb.11:
 ; CHECK-NEXT:    li a7, 32
@@ -384,45 +384,45 @@
 ; CHECK-NEXT:    mul a1, a1, a4
 ; CHECK-NEXT:    add a1, sp, a1
 ; CHECK-NEXT:    addi a1, a1, 16
-; CHECK-NEXT:    vl8r.v v16, (a1) # Unknown-size Folded Reload
+; CHECK-NEXT:    vl8r.v v8, (a1) # Unknown-size Folded Reload
 ; CHECK-NEXT:    csrr a1, vlenb
 ; CHECK-NEXT:    slli a1, a1, 3
 ; CHECK-NEXT:    add a1, sp, a1
 ; CHECK-NEXT:    addi a1, a1, 16
 ; CHECK-NEXT:    vl8r.v v24, (a1) # Unknown-size Folded Reload
-; CHECK-NEXT:    vslideup.vi v16, v24, 16
+; CHECK-NEXT:    vslideup.vi v8, v24, 16
 ; CHECK-NEXT:    csrr a1, vlenb
 ; CHECK-NEXT:    li a4, 48
 ; CHECK-NEXT:    mul a1, a1, a4
 ; CHECK-NEXT:    add a1, sp, a1
 ; CHECK-NEXT:    addi a1, a1, 16
-; CHECK-NEXT:    vs8r.v v16, (a1) # Unknown-size Folded Spill
+; CHECK-NEXT:    vs8r.v v8, (a1) # Unknown-size Folded Spill
 ; CHECK-NEXT:    csrr a1, vlenb
 ; CHECK-NEXT:    li a4, 40
 ; CHECK-NEXT:    mul a1, a1, a4
 ; CHECK-NEXT:    add a1, sp, a1
 ; CHECK-NEXT:    addi a1, a1, 16
-; CHECK-NEXT:    vl8r.v v16, (a1) # Unknown-size Folded Reload
+; CHECK-NEXT:    vl8r.v v8, (a1) # Unknown-size Folded Reload
 ; CHECK-NEXT:    addi a1, sp, 16
 ; CHECK-NEXT:    vl8r.v v24, (a1) # Unknown-size Folded Reload
-; CHECK-NEXT:    vslideup.vi v16, v24, 16
+; CHECK-NEXT:    vslideup.vi v8, v24, 16
 ; CHECK-NEXT:    csrr a1, vlenb
 ; CHECK-NEXT:    li a4, 40
 ; CHECK-NEXT:    mul a1, a1, a4
 ; CHECK-NEXT:    add a1, sp, a1
 ; CHECK-NEXT:    addi a1, a1, 16
-; CHECK-NEXT:    vs8r.v v16, (a1) # Unknown-size Folded Spill
+; CHECK-NEXT:    vs8r.v v8, (a1) # Unknown-size Folded Spill
 ; CHECK-NEXT:    csrr a1, vlenb
 ; CHECK-NEXT:    slli a1, a1, 5
 ; CHECK-NEXT:    add a1, sp, a1
 ; CHECK-NEXT:    addi a1, a1, 16
-; CHECK-NEXT:    vl8r.v v16, (a1) # Unknown-size Folded Reload
-; CHECK-NEXT:    vslideup.vi v16, v8, 16
+; CHECK-NEXT:    vl8r.v v8, (a1) # Unknown-size Folded Reload
+; CHECK-NEXT:    vslideup.vi v8, v16, 16
 ; CHECK-NEXT:    csrr a1, vlenb
 ; CHECK-NEXT:    slli a1, a1, 5
 ; CHECK-NEXT:    add a1, sp, a1
 ; CHECK-NEXT:    addi a1, a1, 16
-; CHECK-NEXT:    vs8r.v v16, (a1) # Unknown-size Folded Spill
+; CHECK-NEXT:    vs8r.v v8, (a1) # Unknown-size Folded Spill
 ; CHECK-NEXT:    addi a1, a7, -16
 ; CHECK-NEXT:    sltu a4, a7, a1
 ; CHECK-NEXT:    addi a4, a4, -1
@@ -433,8 +433,8 @@
 ; CHECK-NEXT:    slli a1, a1, 4
 ; CHECK-NEXT:    add a1, sp, a1
 ; CHECK-NEXT:    addi a1, a1, 16
-; CHECK-NEXT:    vl8r.v v16, (a1) # Unknown-size Folded Reload
-; CHECK-NEXT:    vnsrl.wi v8, v16, 0, v0.t
+; CHECK-NEXT:    vl8r.v v8, (a1) # Unknown-size Folded Reload
+; CHECK-NEXT:    vnsrl.wi v16, v8, 0, v0.t
 ; CHECK-NEXT:    bltu a7, a2, .LBB16_14
 ; CHECK-NEXT:  # %bb.13:
 ; CHECK-NEXT:    li a7, 16
@@ -447,10 +447,10 @@
 ; CHECK-NEXT:    add a1, sp, a1
 ; CHECK-NEXT:    addi a1, a1, 16
 ; CHECK-NEXT:    vl8r.v v24, (a1) # Unknown-size Folded Reload
-; CHECK-NEXT:    vnsrl.wi v16, v24, 0, v0.t
+; CHECK-NEXT:    vnsrl.wi v8, v24, 0, v0.t
 ; CHECK-NEXT:    vsetvli zero, a3, e32, m8, ta, ma
-; CHECK-NEXT:    vslideup.vi v16, v8, 16
-; CHECK-NEXT:    vse32.v v16, (a0)
+; CHECK-NEXT:    vslideup.vi v8, v16, 16
+; CHECK-NEXT:    vse32.v v8, (a0)
 ; CHECK-NEXT:    addi a1, a0, 256
 ; CHECK-NEXT:    csrr a2, vlenb
 ; CHECK-NEXT:    slli a2, a2, 5
diff --git a/llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll b/llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll
--- a/llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll
@@ -256,10 +256,10 @@
 ; RV32-NEXT:    addi a0, a0, %lo(.LCPI15_0)
 ; RV32-NEXT:    li a1, 32
 ; RV32-NEXT:    vsetvli zero, a1, e16, m4, ta, ma
-; RV32-NEXT:    vle16.v v20, (a0)
-; RV32-NEXT:    vmv2r.v v16, v10
+; RV32-NEXT:    vle16.v v16, (a0)
+; RV32-NEXT:    vmv2r.v v20, v10
 ; RV32-NEXT:    vmv2r.v v12, v8
-; RV32-NEXT:    vrgather.vv v8, v12, v20
+; RV32-NEXT:    vrgather.vv v8, v12, v16
 ; RV32-NEXT:    vid.v v12
 ; RV32-NEXT:    vrsub.vi v12, v12, 15
 ; RV32-NEXT:    lui a0, 16
@@ -267,7 +267,7 @@
 ; RV32-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
 ; RV32-NEXT:    vmv.v.x v0, a0
 ; RV32-NEXT:    vsetvli zero, a1, e16, m4, ta, mu
-; RV32-NEXT:    vrgather.vv v8, v16, v12, v0.t
+; RV32-NEXT:    vrgather.vv v8, v20, v12, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: v16i16_2:
@@ -276,10 +276,10 @@
 ; RV64-NEXT:    addi a0, a0, %lo(.LCPI15_0)
 ; RV64-NEXT:    li a1, 32
 ; RV64-NEXT:    vsetvli zero, a1, e16, m4, ta, ma
-; RV64-NEXT:    vle16.v v20, (a0)
-; RV64-NEXT:    vmv2r.v v16, v10
+; RV64-NEXT:    vle16.v v16, (a0)
+; RV64-NEXT:    vmv2r.v v20, v10
 ; RV64-NEXT:    vmv2r.v v12, v8
-; RV64-NEXT:    vrgather.vv v8, v12, v20
+; RV64-NEXT:    vrgather.vv v8, v12, v16
 ; RV64-NEXT:    vid.v v12
 ; RV64-NEXT:    vrsub.vi v12, v12, 15
 ; RV64-NEXT:    lui a0, 16
@@ -287,7 +287,7 @@
 ; RV64-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
 ; RV64-NEXT:    vmv.v.x v0, a0
 ; RV64-NEXT:    vsetvli zero, a1, e16, m4, ta, mu
-; RV64-NEXT:    vrgather.vv v8, v16, v12, v0.t
+; RV64-NEXT:    vrgather.vv v8, v20, v12, v0.t
 ; RV64-NEXT:    ret
   %v32i16 = shufflevector <16 x i16> %a, <16 x i16> %b,  <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
   ret <32 x i16> %v32i16
diff --git a/llvm/test/CodeGen/RISCV/rvv/subregister-subinit-undef.mir b/llvm/test/CodeGen/RISCV/rvv/subregister-subinit-undef.mir
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/subregister-subinit-undef.mir
@@ -0,0 +1,493 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc %s -mtriple=riscv64 -mattr=+v -riscv-enable-subreg-liveness -run-pass=riscv-sub-init-undef -o - | FileCheck %s
+
+...
+---
+name:            test_M4_sub_vrm1_0
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: test_M4_sub_vrm1_0
+    ; CHECK: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
+    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY [[DEF]]
+    ; CHECK-NEXT: [[COPY]].sub_vrm1_0:vrm4 = COPY [[DEF1]]
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY [[COPY]]
+    ; CHECK-NEXT: [[COPY1]].sub_vrm2_1:vrm4 = PseudoRVVInitUndefM2
+    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrm4 = COPY [[COPY1]]
+    ; CHECK-NEXT: [[COPY2]].sub_vrm1_1:vrm4 = PseudoRVVInitUndefM1
+    ; CHECK-NEXT: PseudoRET implicit [[COPY2]]
+    %0:vrm4 = IMPLICIT_DEF
+    %1:vr = IMPLICIT_DEF
+    %2:vrm4 = COPY %0
+    %2.sub_vrm1_0:vrm4 = COPY %1
+    %3:vrm4 = COPY %2
+    %3:vrm4 = PseudoRVVInitSubUndefM4 %3, 13
+    %4:vrm4 = COPY %3
+    %4:vrm4 = PseudoRVVInitSubUndefM4 %4, 5
+    PseudoRET implicit %4
+...
+---
+name:            test_M4_sub_vrm1_1
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: test_M4_sub_vrm1_1
+    ; CHECK: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
+    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY [[DEF]]
+    ; CHECK-NEXT: [[COPY]].sub_vrm1_1:vrm4 = COPY [[DEF1]]
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY [[COPY]]
+    ; CHECK-NEXT: [[COPY1]].sub_vrm2_1:vrm4 = PseudoRVVInitUndefM2
+    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrm4 = COPY [[COPY1]]
+    ; CHECK-NEXT: [[COPY2]].sub_vrm1_0:vrm4 = PseudoRVVInitUndefM1
+    ; CHECK-NEXT: PseudoRET implicit [[COPY2]]
+    %0:vrm4 = IMPLICIT_DEF
+    %1:vr = IMPLICIT_DEF
+    %2:vrm4 = COPY %0
+    %2.sub_vrm1_1:vrm4 = COPY %1
+    %3:vrm4 = COPY %2
+    %3:vrm4 = PseudoRVVInitSubUndefM4 %3, 13
+    %4:vrm4 = COPY %3
+    %4:vrm4 = PseudoRVVInitSubUndefM4 %4, 4
+    PseudoRET implicit %4
+...
+---
+name:            test_M4_sub_vrm1_2
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: test_M4_sub_vrm1_2
+    ; CHECK: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
+    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF
+    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm4 = INSERT_SUBREG [[DEF]], [[DEF1]], %subreg.sub_vrm1_2
+    ; CHECK-NEXT: [[INSERT_SUBREG]].sub_vrm2_0:vrm4 = PseudoRVVInitUndefM2
+    ; CHECK-NEXT: %3.sub_vrm1_3:vrm4 = PseudoRVVInitUndefM1
+    ; CHECK-NEXT: PseudoRET implicit %4:vrm4
+    %0:vrm4 = IMPLICIT_DEF
+    %3:vr = IMPLICIT_DEF
+    %4:vrm4 = INSERT_SUBREG %0, %3, %subreg.sub_vrm1_2
+    %8:vrm4 = PseudoRVVInitSubUndefM4 %4, 12
+    %9:vrm4 = PseudoRVVInitSubUndefM4 %8, 7
+    PseudoRET implicit %9:vrm4
+...
+---
+name:            test_M4_sub_vrm1_3
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: test_M4_sub_vrm1_3
+    ; CHECK: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
+    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY [[DEF]]
+    ; CHECK-NEXT: [[COPY]].sub_vrm1_3:vrm4 = COPY [[DEF1]]
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY [[COPY]]
+    ; CHECK-NEXT: [[COPY1]].sub_vrm2_0:vrm4 = PseudoRVVInitUndefM2
+    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrm4 = COPY [[COPY1]]
+    ; CHECK-NEXT: [[COPY2]].sub_vrm1_2:vrm4 = PseudoRVVInitUndefM1
+    ; CHECK-NEXT: PseudoRET implicit [[COPY2]]
+    %0:vrm4 = IMPLICIT_DEF
+    %1:vr = IMPLICIT_DEF
+    %2:vrm4 = COPY %0
+    %2.sub_vrm1_3:vrm4 = COPY %1
+    %3:vrm4 = COPY %2
+    %3:vrm4 = PseudoRVVInitSubUndefM4 %3, 12
+    %4:vrm4 = COPY %3
+    %4:vrm4 = PseudoRVVInitSubUndefM4 %4, 6
+    PseudoRET implicit %4
+...
+---
+name:            test_M4_sub_vrm2_0
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: test_M4_sub_vrm2_0
+    ; CHECK: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
+    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vrm2 = IMPLICIT_DEF
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY [[DEF]]
+    ; CHECK-NEXT: [[COPY]].sub_vrm2_0:vrm4 = COPY [[DEF1]]
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY [[COPY]]
+    ; CHECK-NEXT: [[COPY1]].sub_vrm2_1:vrm4 = PseudoRVVInitUndefM2
+    ; CHECK-NEXT: PseudoRET implicit [[COPY1]]
+    %0:vrm4 = IMPLICIT_DEF
+    %1:vrm2 = IMPLICIT_DEF
+    %2:vrm4 = COPY %0
+    %2.sub_vrm2_0:vrm4 = COPY %1
+    %3:vrm4 = COPY %2
+    %3:vrm4 = PseudoRVVInitSubUndefM4 %3, 13
+    PseudoRET implicit %3
+...
+---
+name:            test_M4_sub_vrm2_1
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: test_M4_sub_vrm2_1
+    ; CHECK: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
+    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vrm2 = IMPLICIT_DEF
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY [[DEF]]
+    ; CHECK-NEXT: [[COPY]].sub_vrm2_1:vrm4 = COPY [[DEF1]]
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY [[COPY]]
+    ; CHECK-NEXT: [[COPY1]].sub_vrm2_0:vrm4 = PseudoRVVInitUndefM2
+    ; CHECK-NEXT: PseudoRET implicit [[COPY1]]
+    %0:vrm4 = IMPLICIT_DEF
+    %1:vrm2 = IMPLICIT_DEF
+    %2:vrm4 = COPY %0
+    %2.sub_vrm2_1:vrm4 = COPY %1
+    %3:vrm4 = COPY %2
+    %3:vrm4 = PseudoRVVInitSubUndefM4 %3, 12
+    PseudoRET implicit %3
+...
+---
+name:            test_M8_sub_vrm1_0
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: test_M8_sub_vrm1_0
+    ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
+    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY [[DEF]]
+    ; CHECK-NEXT: [[COPY]].sub_vrm1_0:vrm8 = COPY [[DEF1]]
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY [[COPY]]
+    ; CHECK-NEXT: [[COPY1]].sub_vrm4_1:vrm8 = PseudoRVVInitUndefM4
+    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrm8 = COPY [[COPY1]]
+    ; CHECK-NEXT: [[COPY2]].sub_vrm2_1:vrm8 = PseudoRVVInitUndefM2
+    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vrm8 = COPY [[COPY2]]
+    ; CHECK-NEXT: [[COPY3]].sub_vrm1_1:vrm8 = PseudoRVVInitUndefM1
+    ; CHECK-NEXT: PseudoRET implicit [[COPY3]]
+    %0:vrm8 = IMPLICIT_DEF
+    %1:vr = IMPLICIT_DEF
+    %2:vrm8 = COPY %0
+    %2.sub_vrm1_0:vrm8 = COPY %1
+    %3:vrm8 = COPY %2
+    %3:vrm8 = PseudoRVVInitSubUndefM8 %3, 17
+    %4:vrm8 = COPY %3
+    %4:vrm8 = PseudoRVVInitSubUndefM8 %4, 13
+    %5:vrm8 = COPY %4
+    %5:vrm8 = PseudoRVVInitSubUndefM8 %5, 5
+    PseudoRET implicit %5
+...
+---
+name:            test_M8_sub_vrm1_1
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: test_M8_sub_vrm1_1
+    ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
+    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY [[DEF]]
+    ; CHECK-NEXT: [[COPY]].sub_vrm1_1:vrm8 = COPY [[DEF1]]
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY [[COPY]]
+    ; CHECK-NEXT: [[COPY1]].sub_vrm4_1:vrm8 = PseudoRVVInitUndefM4
+    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrm8 = COPY [[COPY1]]
+    ; CHECK-NEXT: [[COPY2]].sub_vrm2_1:vrm8 = PseudoRVVInitUndefM2
+    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vrm8 = COPY [[COPY2]]
+    ; CHECK-NEXT: [[COPY3]].sub_vrm1_0:vrm8 = PseudoRVVInitUndefM1
+    ; CHECK-NEXT: PseudoRET implicit [[COPY3]]
+    %0:vrm8 = IMPLICIT_DEF
+    %1:vr = IMPLICIT_DEF
+    %2:vrm8 = COPY %0
+    %2.sub_vrm1_1:vrm8 = COPY %1
+    %3:vrm8 = COPY %2
+    %3:vrm8 = PseudoRVVInitSubUndefM8 %3, 17
+    %4:vrm8 = COPY %3
+    %4:vrm8 = PseudoRVVInitSubUndefM8 %4, 13
+    %5:vrm8 = COPY %4
+    %5:vrm8 = PseudoRVVInitSubUndefM8 %5, 4
+    PseudoRET implicit %5
+...
+---
+name:            test_M8_sub_vrm1_2
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: test_M8_sub_vrm1_2
+    ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
+    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY [[DEF]]
+    ; CHECK-NEXT: [[COPY]].sub_vrm1_2:vrm8 = COPY [[DEF1]]
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY [[COPY]]
+    ; CHECK-NEXT: [[COPY1]].sub_vrm4_1:vrm8 = PseudoRVVInitUndefM4
+    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrm8 = COPY [[COPY1]]
+    ; CHECK-NEXT: [[COPY2]].sub_vrm2_0:vrm8 = PseudoRVVInitUndefM2
+    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vrm8 = COPY [[COPY2]]
+    ; CHECK-NEXT: [[COPY3]].sub_vrm1_3:vrm8 = PseudoRVVInitUndefM1
+    ; CHECK-NEXT: PseudoRET implicit [[COPY3]]
+    %0:vrm8 = IMPLICIT_DEF
+    %1:vr = IMPLICIT_DEF
+    %2:vrm8 = COPY %0
+    %2.sub_vrm1_2:vrm8 = COPY %1
+    %3:vrm8 = COPY %2
+    %3:vrm8 = PseudoRVVInitSubUndefM8 %3, 17
+    %4:vrm8 = COPY %3
+    %4:vrm8 = PseudoRVVInitSubUndefM8 %4, 12
+    %5:vrm8 = COPY %4
+    %5:vrm8 = PseudoRVVInitSubUndefM8 %5, 7
+    PseudoRET implicit %5
+...
+---
+name:            test_M8_sub_vrm1_3
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: test_M8_sub_vrm1_3
+    ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
+    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY [[DEF]]
+    ; CHECK-NEXT: [[COPY]].sub_vrm1_3:vrm8 = COPY [[DEF1]]
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY [[COPY]]
+    ; CHECK-NEXT: [[COPY1]].sub_vrm4_1:vrm8 = PseudoRVVInitUndefM4
+    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrm8 = COPY [[COPY1]]
+    ; CHECK-NEXT: [[COPY2]].sub_vrm2_0:vrm8 = PseudoRVVInitUndefM2
+    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vrm8 = COPY [[COPY2]]
+    ; CHECK-NEXT: [[COPY3]].sub_vrm1_2:vrm8 = PseudoRVVInitUndefM1
+    ; CHECK-NEXT: PseudoRET implicit [[COPY3]]
+    %0:vrm8 = IMPLICIT_DEF
+    %1:vr = IMPLICIT_DEF
+    %2:vrm8 = COPY %0
+    %2.sub_vrm1_3:vrm8 = COPY %1
+    %3:vrm8 = COPY %2
+    %3:vrm8 = PseudoRVVInitSubUndefM8 %3, 17
+    %4:vrm8 = COPY %3
+    %4:vrm8 = PseudoRVVInitSubUndefM8 %4, 12
+    %5:vrm8 = COPY %4
+    %5:vrm8 = PseudoRVVInitSubUndefM8 %5, 6
+    PseudoRET implicit %5
+...
+---
+name:            test_M8_sub_vrm1_4
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: test_M8_sub_vrm1_4
+    ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
+    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY [[DEF]]
+    ; CHECK-NEXT: [[COPY]].sub_vrm1_4:vrm8 = COPY [[DEF1]]
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY [[COPY]]
+    ; CHECK-NEXT: [[COPY1]].sub_vrm4_0:vrm8 = PseudoRVVInitUndefM4
+    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrm8 = COPY [[COPY1]]
+    ; CHECK-NEXT: [[COPY2]].sub_vrm2_3:vrm8 = PseudoRVVInitUndefM2
+    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vrm8 = COPY [[COPY2]]
+    ; CHECK-NEXT: [[COPY3]].sub_vrm1_5:vrm8 = PseudoRVVInitUndefM1
+    ; CHECK-NEXT: PseudoRET implicit [[COPY3]]
+    %0:vrm8 = IMPLICIT_DEF
+    %1:vr = IMPLICIT_DEF
+    %2:vrm8 = COPY %0
+    %2.sub_vrm1_4:vrm8 = COPY %1
+    %3:vrm8 = COPY %2
+    %3:vrm8 = PseudoRVVInitSubUndefM8 %3, 16
+    %4:vrm8 = COPY %3
+    %4:vrm8 = PseudoRVVInitSubUndefM8 %4, 15
+    %5:vrm8 = COPY %4
+    %5:vrm8 = PseudoRVVInitSubUndefM8 %5, 9
+    PseudoRET implicit %5
+...
+---
+name:            test_M8_sub_vrm1_5
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: test_M8_sub_vrm1_5
+    ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
+    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY [[DEF]]
+    ; CHECK-NEXT: [[COPY]].sub_vrm1_5:vrm8 = COPY [[DEF1]]
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY [[COPY]]
+    ; CHECK-NEXT: [[COPY1]].sub_vrm4_0:vrm8 = PseudoRVVInitUndefM4
+    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrm8 = COPY [[COPY1]]
+    ; CHECK-NEXT: [[COPY2]].sub_vrm2_3:vrm8 = PseudoRVVInitUndefM2
+    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vrm8 = COPY [[COPY2]]
+    ; CHECK-NEXT: [[COPY3]].sub_vrm1_4:vrm8 = PseudoRVVInitUndefM1
+    ; CHECK-NEXT: PseudoRET implicit [[COPY3]]
+    %0:vrm8 = IMPLICIT_DEF
+    %1:vr = IMPLICIT_DEF
+    %2:vrm8 = COPY %0
+    %2.sub_vrm1_5:vrm8 = COPY %1
+    %3:vrm8 = COPY %2
+    %3:vrm8 = PseudoRVVInitSubUndefM8 %3, 16
+    %4:vrm8 = COPY %3
+    %4:vrm8 = PseudoRVVInitSubUndefM8 %4, 15
+    %5:vrm8 = COPY %4
+    %5:vrm8 = PseudoRVVInitSubUndefM8 %5, 8
+    PseudoRET implicit %5
+...
+---
+name:            test_M8_sub_vrm1_6
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: test_M8_sub_vrm1_6
+    ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
+    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY [[DEF]]
+    ; CHECK-NEXT: [[COPY]].sub_vrm1_6:vrm8 = COPY [[DEF1]]
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY [[COPY]]
+    ; CHECK-NEXT: [[COPY1]].sub_vrm4_0:vrm8 = PseudoRVVInitUndefM4
+    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrm8 = COPY [[COPY1]]
+    ; CHECK-NEXT: [[COPY2]].sub_vrm2_2:vrm8 = PseudoRVVInitUndefM2
+    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vrm8 = COPY [[COPY2]]
+    ; CHECK-NEXT: [[COPY3]].sub_vrm1_7:vrm8 = PseudoRVVInitUndefM1
+    ; CHECK-NEXT: PseudoRET implicit [[COPY3]]
+    %0:vrm8 = IMPLICIT_DEF
+    %1:vr = IMPLICIT_DEF
+    %2:vrm8 = COPY %0
+    %2.sub_vrm1_6:vrm8 = COPY %1
+    %3:vrm8 = COPY %2
+    %3:vrm8 = PseudoRVVInitSubUndefM8 %3, 16
+    %4:vrm8 = COPY %3
+    %4:vrm8 = PseudoRVVInitSubUndefM8 %4, 14
+    %5:vrm8 = COPY %4
+    %5:vrm8 = PseudoRVVInitSubUndefM8 %5, 11
+    PseudoRET implicit %5
+...
+---
+name:            test_M8_sub_vrm1_7
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: test_M8_sub_vrm1_7
+    ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
+    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY [[DEF]]
+    ; CHECK-NEXT: [[COPY]].sub_vrm1_7:vrm8 = COPY [[DEF1]]
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY [[COPY]]
+    ; CHECK-NEXT: [[COPY1]].sub_vrm4_0:vrm8 = PseudoRVVInitUndefM4
+    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrm8 = COPY [[COPY1]]
+    ; CHECK-NEXT: [[COPY2]].sub_vrm2_2:vrm8 = PseudoRVVInitUndefM2
+    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vrm8 = COPY [[COPY2]]
+    ; CHECK-NEXT: [[COPY3]].sub_vrm1_6:vrm8 = PseudoRVVInitUndefM1
+    ; CHECK-NEXT: PseudoRET implicit [[COPY3]]
+    %0:vrm8 = IMPLICIT_DEF
+    %1:vr = IMPLICIT_DEF
+    %2:vrm8 = COPY %0
+    %2.sub_vrm1_7:vrm8 = COPY %1
+    %3:vrm8 = COPY %2
+    %3:vrm8 = PseudoRVVInitSubUndefM8 %3, 16
+    %4:vrm8 = COPY %3
+    %4:vrm8 = PseudoRVVInitSubUndefM8 %4, 14
+    %5:vrm8 = COPY %4
+    %5:vrm8 = PseudoRVVInitSubUndefM8 %5, 10
+    PseudoRET implicit %5
+...
+---
+name:            test_M8_sub_vrm2_0
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: test_M8_sub_vrm2_0
+    ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
+    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vrm2 = IMPLICIT_DEF
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY [[DEF]]
+    ; CHECK-NEXT: [[COPY]].sub_vrm2_0:vrm8 = COPY [[DEF1]]
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY [[COPY]]
+    ; CHECK-NEXT: [[COPY1]].sub_vrm4_1:vrm8 = PseudoRVVInitUndefM4
+    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrm8 = COPY [[COPY1]]
+    ; CHECK-NEXT: [[COPY2]].sub_vrm2_1:vrm8 = PseudoRVVInitUndefM2
+    ; CHECK-NEXT: PseudoRET implicit [[COPY2]]
+    %0:vrm8 = IMPLICIT_DEF
+    %1:vrm2 = IMPLICIT_DEF
+    %2:vrm8 = COPY %0
+    %2.sub_vrm2_0:vrm8 = COPY %1
+    %3:vrm8 = COPY %2
+    %3:vrm8 = PseudoRVVInitSubUndefM8 %3, 17
+    %4:vrm8 = COPY %3
+    %4:vrm8 = PseudoRVVInitSubUndefM8 %4, 13
+    PseudoRET implicit %4
+...
+---
+name:            test_M8_sub_vrm2_1
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: test_M8_sub_vrm2_1
+    ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
+    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vrm2 = IMPLICIT_DEF
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY [[DEF]]
+    ; CHECK-NEXT: [[COPY]].sub_vrm2_1:vrm8 = COPY [[DEF1]]
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY [[COPY]]
+    ; CHECK-NEXT: [[COPY1]].sub_vrm4_1:vrm8 = PseudoRVVInitUndefM4
+    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrm8 = COPY [[COPY1]]
+    ; CHECK-NEXT: [[COPY2]].sub_vrm2_0:vrm8 = PseudoRVVInitUndefM2
+    ; CHECK-NEXT: PseudoRET implicit [[COPY2]]
+    %0:vrm8 = IMPLICIT_DEF
+    %1:vrm2 = IMPLICIT_DEF
+    %2:vrm8 = COPY %0
+    %2.sub_vrm2_1:vrm8 = COPY %1
+    %3:vrm8 = COPY %2
+    %3:vrm8 = PseudoRVVInitSubUndefM8 %3, 17
+    %4:vrm8 = COPY %3
+    %4:vrm8 = PseudoRVVInitSubUndefM8 %4, 12
+    PseudoRET implicit %4
+...
+---
+name:            test_M8_sub_vrm2_2
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: test_M8_sub_vrm2_2
+    ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
+    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vrm2 = IMPLICIT_DEF
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY [[DEF]]
+    ; CHECK-NEXT: [[COPY]].sub_vrm2_2:vrm8 = COPY [[DEF1]]
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY [[COPY]]
+    ; CHECK-NEXT: [[COPY1]].sub_vrm4_0:vrm8 = PseudoRVVInitUndefM4
+    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrm8 = COPY [[COPY1]]
+    ; CHECK-NEXT: [[COPY2]].sub_vrm2_3:vrm8 = PseudoRVVInitUndefM2
+    ; CHECK-NEXT: PseudoRET implicit [[COPY2]]
+    %0:vrm8 = IMPLICIT_DEF
+    %1:vrm2 = IMPLICIT_DEF
+    %2:vrm8 = COPY %0
+    %2.sub_vrm2_2:vrm8 = COPY %1
+    %3:vrm8 = COPY %2
+    %3:vrm8 = PseudoRVVInitSubUndefM8 %3, 16
+    %4:vrm8 = COPY %3
+    %4:vrm8 = PseudoRVVInitSubUndefM8 %4, 15
+    PseudoRET implicit %4
+...
+---
+name:            test_M8_sub_vrm2_3
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: test_M8_sub_vrm2_3
+    ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
+    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vrm2 = IMPLICIT_DEF
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY [[DEF]]
+    ; CHECK-NEXT: [[COPY]].sub_vrm2_3:vrm8 = COPY [[DEF1]]
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY [[COPY]]
+    ; CHECK-NEXT: [[COPY1]].sub_vrm4_0:vrm8 = PseudoRVVInitUndefM4
+    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrm8 = COPY [[COPY1]]
+    ; CHECK-NEXT: [[COPY2]].sub_vrm2_2:vrm8 = PseudoRVVInitUndefM2
+    ; CHECK-NEXT: PseudoRET implicit [[COPY2]]
+    %0:vrm8 = IMPLICIT_DEF
+    %1:vrm2 = IMPLICIT_DEF
+    %2:vrm8 = COPY %0
+    %2.sub_vrm2_3:vrm8 = COPY %1
+    %3:vrm8 = COPY %2
+    %3:vrm8 = PseudoRVVInitSubUndefM8 %3, 16
+    %4:vrm8 = COPY %3
+    %4:vrm8 = PseudoRVVInitSubUndefM8 %4, 14
+    PseudoRET implicit %4
+...
+---
+name:            test_M8_sub_vrm4_0
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: test_M8_sub_vrm4_0
+    ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
+    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vrm4 = IMPLICIT_DEF
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY [[DEF]]
+    ; CHECK-NEXT: [[COPY]].sub_vrm4_0:vrm8 = COPY [[DEF1]]
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY [[COPY]]
+    ; CHECK-NEXT: [[COPY1]].sub_vrm4_1:vrm8 = PseudoRVVInitUndefM4
+    ; CHECK-NEXT: PseudoRET implicit [[COPY1]]
+    %0:vrm8 = IMPLICIT_DEF
+    %1:vrm4 = IMPLICIT_DEF
+    %2:vrm8 = COPY %0
+    %2.sub_vrm4_0:vrm8 = COPY %1
+    %3:vrm8 = COPY %2
+    %3:vrm8 = PseudoRVVInitSubUndefM8 %3, 17
+    PseudoRET implicit %3
+...
+---
+name:            test_M8_sub_vrm4_1
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: test_M8_sub_vrm4_1
+    ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
+    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vrm4 = IMPLICIT_DEF
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY [[DEF]]
+    ; CHECK-NEXT: [[COPY]].sub_vrm4_1:vrm8 = COPY [[DEF1]]
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY [[COPY]]
+    ; CHECK-NEXT: [[COPY1]].sub_vrm4_0:vrm8 = PseudoRVVInitUndefM4
+    ; CHECK-NEXT: PseudoRET implicit [[COPY1]]
+    %0:vrm8 = IMPLICIT_DEF
+    %1:vrm4 = IMPLICIT_DEF
+    %2:vrm8 = COPY %0
+    %2.sub_vrm4_1:vrm8 = COPY %1
+    %3:vrm8 = COPY %2
+    %3:vrm8 = PseudoRVVInitSubUndefM8 %3, 16
+    PseudoRET implicit %3
diff --git a/llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber.mir b/llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber.mir
--- a/llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber.mir
@@ -13,11 +13,9 @@
     ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */
     ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm4 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_0
     ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
-    ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2
-    ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_1
-    ; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1
-    ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM1_]], %subreg.sub_vrm1_1
-    ; CHECK-NEXT: early-clobber %5:vrm4 = PseudoVRGATHER_VI_M4 killed [[INSERT_SUBREG2]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype
+    ; CHECK-NEXT: [[PseudoRVVInitSubUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitSubUndefM4 [[INSERT_SUBREG]], 13
+    ; CHECK-NEXT: [[PseudoRVVInitSubUndefM4_1:%[0-9]+]]:vrm4 = PseudoRVVInitSubUndefM4 [[PseudoRVVInitSubUndefM4_]], 5
+    ; CHECK-NEXT: early-clobber %5:vrm4 = PseudoVRGATHER_VI_M4 killed [[PseudoRVVInitSubUndefM4_1]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype
     ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
     ; CHECK-NEXT: PseudoVSE32_V_M4 killed %5, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
@@ -49,11 +47,9 @@
     ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */
     ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm4 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_1
     ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
-    ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2
-    ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_1
-    ; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1
-    ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM1_]], %subreg.sub_vrm1_0
-    ; CHECK-NEXT: early-clobber %5:vrm4 = PseudoVRGATHER_VI_M4 killed [[INSERT_SUBREG2]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype
+    ; CHECK-NEXT: [[PseudoRVVInitSubUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitSubUndefM4 [[INSERT_SUBREG]], 13
+    ; CHECK-NEXT: [[PseudoRVVInitSubUndefM4_1:%[0-9]+]]:vrm4 = PseudoRVVInitSubUndefM4 [[PseudoRVVInitSubUndefM4_]], 4
+    ; CHECK-NEXT: early-clobber %5:vrm4 = PseudoVRGATHER_VI_M4 killed [[PseudoRVVInitSubUndefM4_1]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype
     ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
     ; CHECK-NEXT: PseudoVSE32_V_M4 killed %5, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
@@ -85,11 +81,9 @@
     ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */
     ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm4 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_2
     ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
-    ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2
-    ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_0
-    ; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1
-    ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM1_]], %subreg.sub_vrm1_3
-    ; CHECK-NEXT: early-clobber %5:vrm4 = PseudoVRGATHER_VI_M4 killed [[INSERT_SUBREG2]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype
+    ; CHECK-NEXT: [[PseudoRVVInitSubUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitSubUndefM4 [[INSERT_SUBREG]], 12
+    ; CHECK-NEXT: [[PseudoRVVInitSubUndefM4_1:%[0-9]+]]:vrm4 = PseudoRVVInitSubUndefM4 [[PseudoRVVInitSubUndefM4_]], 7
+    ; CHECK-NEXT: early-clobber %5:vrm4 = PseudoVRGATHER_VI_M4 killed [[PseudoRVVInitSubUndefM4_1]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype
     ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
     ; CHECK-NEXT: PseudoVSE32_V_M4 killed %5, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
@@ -121,11 +115,9 @@
     ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */
     ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm4 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_3
     ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
-    ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2
-    ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_0
-    ; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1
-    ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM1_]], %subreg.sub_vrm1_2
-    ; CHECK-NEXT: early-clobber %5:vrm4 = PseudoVRGATHER_VI_M4 killed [[INSERT_SUBREG2]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype
+    ; CHECK-NEXT: [[PseudoRVVInitSubUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitSubUndefM4 [[INSERT_SUBREG]], 12
+    ; CHECK-NEXT: [[PseudoRVVInitSubUndefM4_1:%[0-9]+]]:vrm4 = PseudoRVVInitSubUndefM4 [[PseudoRVVInitSubUndefM4_]], 6
+    ; CHECK-NEXT: early-clobber %5:vrm4 = PseudoVRGATHER_VI_M4 killed [[PseudoRVVInitSubUndefM4_1]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype
     ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
     ; CHECK-NEXT: PseudoVSE32_V_M4 killed %5, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
@@ -157,9 +149,8 @@
     ; CHECK-NEXT: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */
     ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm4 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M2_]], %subreg.sub_vrm2_0
     ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
-    ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2
-    ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_1
-    ; CHECK-NEXT: early-clobber %5:vrm4 = PseudoVRGATHER_VI_M4 killed [[INSERT_SUBREG1]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype
+    ; CHECK-NEXT: [[PseudoRVVInitSubUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitSubUndefM4 [[INSERT_SUBREG]], 13
+    ; CHECK-NEXT: early-clobber %5:vrm4 = PseudoVRGATHER_VI_M4 killed [[PseudoRVVInitSubUndefM4_]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype
     ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
     ; CHECK-NEXT: PseudoVSE32_V_M4 killed %5, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
@@ -191,9 +182,8 @@
     ; CHECK-NEXT: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */
     ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm4 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M2_]], %subreg.sub_vrm2_1
     ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
-    ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2
-    ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_0
-    ; CHECK-NEXT: early-clobber %5:vrm4 = PseudoVRGATHER_VI_M4 killed [[INSERT_SUBREG1]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype
+    ; CHECK-NEXT: [[PseudoRVVInitSubUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitSubUndefM4 [[INSERT_SUBREG]], 12
+    ; CHECK-NEXT: early-clobber %5:vrm4 = PseudoVRGATHER_VI_M4 killed [[PseudoRVVInitSubUndefM4_]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype
     ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
     ; CHECK-NEXT: PseudoVSE32_V_M4 killed %5, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
@@ -226,13 +216,10 @@
     ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */
     ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_0
     ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
-    ; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
-    ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_1
-    ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2
-    ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_1
-    ; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1
-    ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[PseudoRVVInitUndefM1_]], %subreg.sub_vrm1_1
-    ; CHECK-NEXT: early-clobber %5:vrm8 = PseudoVRGATHER_VI_M8 killed [[INSERT_SUBREG3]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype
+    ; CHECK-NEXT: [[PseudoRVVInitSubUndefM8_:%[0-9]+]]:vrm8 = PseudoRVVInitSubUndefM8 [[INSERT_SUBREG]], 17
+    ; CHECK-NEXT: [[PseudoRVVInitSubUndefM8_1:%[0-9]+]]:vrm8 = PseudoRVVInitSubUndefM8 [[PseudoRVVInitSubUndefM8_]], 13
+    ; CHECK-NEXT: [[PseudoRVVInitSubUndefM8_2:%[0-9]+]]:vrm8 = PseudoRVVInitSubUndefM8 [[PseudoRVVInitSubUndefM8_1]], 5
+    ; CHECK-NEXT: early-clobber %5:vrm8 = PseudoVRGATHER_VI_M8 killed [[PseudoRVVInitSubUndefM8_2]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype
     ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
     ; CHECK-NEXT: PseudoVSE32_V_M8 killed %5, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
@@ -264,13 +251,10 @@
     ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */
     ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_1
     ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
-    ; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
-    ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_1
-    ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2
-    ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_1
-    ; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1
-    ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[PseudoRVVInitUndefM1_]], %subreg.sub_vrm1_0
-    ; CHECK-NEXT: early-clobber %5:vrm8 = PseudoVRGATHER_VI_M8 killed [[INSERT_SUBREG3]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype
+    ; CHECK-NEXT: [[PseudoRVVInitSubUndefM8_:%[0-9]+]]:vrm8 = PseudoRVVInitSubUndefM8 [[INSERT_SUBREG]], 17
+    ; CHECK-NEXT: [[PseudoRVVInitSubUndefM8_1:%[0-9]+]]:vrm8 = PseudoRVVInitSubUndefM8 [[PseudoRVVInitSubUndefM8_]], 13
+    ; CHECK-NEXT: [[PseudoRVVInitSubUndefM8_2:%[0-9]+]]:vrm8 = PseudoRVVInitSubUndefM8 [[PseudoRVVInitSubUndefM8_1]], 4
+    ; CHECK-NEXT: early-clobber %5:vrm8 = PseudoVRGATHER_VI_M8 killed [[PseudoRVVInitSubUndefM8_2]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype
     ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
     ; CHECK-NEXT: PseudoVSE32_V_M8 killed %5, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
@@ -302,13 +286,10 @@
     ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */
     ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_2
     ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
-    ; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
-    ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_1
-    ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2
-    ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_0
-    ; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1
-    ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[PseudoRVVInitUndefM1_]], %subreg.sub_vrm1_3
-    ; CHECK-NEXT: early-clobber %5:vrm8 = PseudoVRGATHER_VI_M8 killed [[INSERT_SUBREG3]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype
+    ; CHECK-NEXT: [[PseudoRVVInitSubUndefM8_:%[0-9]+]]:vrm8 = PseudoRVVInitSubUndefM8 [[INSERT_SUBREG]], 17
+    ; CHECK-NEXT: [[PseudoRVVInitSubUndefM8_1:%[0-9]+]]:vrm8 = PseudoRVVInitSubUndefM8 [[PseudoRVVInitSubUndefM8_]], 12
+    ; CHECK-NEXT: [[PseudoRVVInitSubUndefM8_2:%[0-9]+]]:vrm8 = PseudoRVVInitSubUndefM8 [[PseudoRVVInitSubUndefM8_1]], 7
+    ; CHECK-NEXT: early-clobber %5:vrm8 = PseudoVRGATHER_VI_M8 killed [[PseudoRVVInitSubUndefM8_2]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype
     ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
     ; CHECK-NEXT: PseudoVSE32_V_M8 killed %5, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
@@ -340,13 +321,10 @@
     ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */
     ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_3
     ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
-    ; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
-    ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_1
-    ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2
-    ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_0
-    ; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1
-    ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[PseudoRVVInitUndefM1_]], %subreg.sub_vrm1_2
-    ; CHECK-NEXT: early-clobber %5:vrm8 = PseudoVRGATHER_VI_M8 killed [[INSERT_SUBREG3]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype
+    ; CHECK-NEXT: [[PseudoRVVInitSubUndefM8_:%[0-9]+]]:vrm8 = PseudoRVVInitSubUndefM8 [[INSERT_SUBREG]], 17
+    ; CHECK-NEXT: [[PseudoRVVInitSubUndefM8_1:%[0-9]+]]:vrm8 = PseudoRVVInitSubUndefM8 [[PseudoRVVInitSubUndefM8_]], 12
+    ; CHECK-NEXT: [[PseudoRVVInitSubUndefM8_2:%[0-9]+]]:vrm8 = PseudoRVVInitSubUndefM8 [[PseudoRVVInitSubUndefM8_1]], 6
+    ; CHECK-NEXT: early-clobber %5:vrm8 = PseudoVRGATHER_VI_M8 killed [[PseudoRVVInitSubUndefM8_2]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype
     ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
     ; CHECK-NEXT: PseudoVSE32_V_M8 killed %5, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
@@ -378,13 +356,10 @@
     ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */
     ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_4
     ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
-    ; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
-    ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_0
-    ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2
-    ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_3
-    ; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1
-    ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[PseudoRVVInitUndefM1_]], %subreg.sub_vrm1_5
-    ; CHECK-NEXT: early-clobber %5:vrm8 = PseudoVRGATHER_VI_M8 killed [[INSERT_SUBREG3]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype
+    ; CHECK-NEXT: [[PseudoRVVInitSubUndefM8_:%[0-9]+]]:vrm8 = PseudoRVVInitSubUndefM8 [[INSERT_SUBREG]], 16
+    ; CHECK-NEXT: [[PseudoRVVInitSubUndefM8_1:%[0-9]+]]:vrm8 = PseudoRVVInitSubUndefM8 [[PseudoRVVInitSubUndefM8_]], 15
+    ; CHECK-NEXT: [[PseudoRVVInitSubUndefM8_2:%[0-9]+]]:vrm8 = PseudoRVVInitSubUndefM8 [[PseudoRVVInitSubUndefM8_1]], 9
+    ; CHECK-NEXT: early-clobber %5:vrm8 = PseudoVRGATHER_VI_M8 killed [[PseudoRVVInitSubUndefM8_2]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype
     ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
     ; CHECK-NEXT: PseudoVSE32_V_M8 killed %5, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
@@ -416,13 +391,10 @@
     ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */
     ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_5
     ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
-    ; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
-    ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_0
-    ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2
-    ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_3
-    ; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1
-    ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[PseudoRVVInitUndefM1_]], %subreg.sub_vrm1_4
-    ; CHECK-NEXT: early-clobber %5:vrm8 = PseudoVRGATHER_VI_M8 killed [[INSERT_SUBREG3]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype
+    ; CHECK-NEXT: [[PseudoRVVInitSubUndefM8_:%[0-9]+]]:vrm8 = PseudoRVVInitSubUndefM8 [[INSERT_SUBREG]], 16
+    ; CHECK-NEXT: [[PseudoRVVInitSubUndefM8_1:%[0-9]+]]:vrm8 = PseudoRVVInitSubUndefM8 [[PseudoRVVInitSubUndefM8_]], 15
+    ; CHECK-NEXT: [[PseudoRVVInitSubUndefM8_2:%[0-9]+]]:vrm8 = PseudoRVVInitSubUndefM8 [[PseudoRVVInitSubUndefM8_1]], 8
+    ; CHECK-NEXT: early-clobber %5:vrm8 = PseudoVRGATHER_VI_M8 killed [[PseudoRVVInitSubUndefM8_2]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype
     ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
     ; CHECK-NEXT: PseudoVSE32_V_M8 killed %5, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
@@ -454,13 +426,10 @@
     ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */
     ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_6
     ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
-    ; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
-    ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_0
-    ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2
-    ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_2
-    ; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1
-    ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[PseudoRVVInitUndefM1_]], %subreg.sub_vrm1_7
-    ; CHECK-NEXT: early-clobber %5:vrm8 = PseudoVRGATHER_VI_M8 killed [[INSERT_SUBREG3]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype
+    ; CHECK-NEXT: [[PseudoRVVInitSubUndefM8_:%[0-9]+]]:vrm8 = PseudoRVVInitSubUndefM8 [[INSERT_SUBREG]], 16
+    ; CHECK-NEXT: [[PseudoRVVInitSubUndefM8_1:%[0-9]+]]:vrm8 = PseudoRVVInitSubUndefM8 [[PseudoRVVInitSubUndefM8_]], 14
+    ; CHECK-NEXT: [[PseudoRVVInitSubUndefM8_2:%[0-9]+]]:vrm8 = PseudoRVVInitSubUndefM8 [[PseudoRVVInitSubUndefM8_1]], 11
+    ; CHECK-NEXT: early-clobber %5:vrm8 = PseudoVRGATHER_VI_M8 killed [[PseudoRVVInitSubUndefM8_2]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype
     ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
     ; CHECK-NEXT: PseudoVSE32_V_M8 killed %5, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
@@ -492,13 +461,10 @@
     ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */
     ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_7
     ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
-    ; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
-    ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_0
-    ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2
-    ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_2
-    ; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1
-    ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[PseudoRVVInitUndefM1_]], %subreg.sub_vrm1_6
-    ; CHECK-NEXT: early-clobber %5:vrm8 = PseudoVRGATHER_VI_M8 killed [[INSERT_SUBREG3]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype
+    ; CHECK-NEXT: [[PseudoRVVInitSubUndefM8_:%[0-9]+]]:vrm8 = PseudoRVVInitSubUndefM8 [[INSERT_SUBREG]], 16
+    ; CHECK-NEXT: [[PseudoRVVInitSubUndefM8_1:%[0-9]+]]:vrm8 = PseudoRVVInitSubUndefM8 [[PseudoRVVInitSubUndefM8_]], 14
+    ; CHECK-NEXT: [[PseudoRVVInitSubUndefM8_2:%[0-9]+]]:vrm8 = PseudoRVVInitSubUndefM8 [[PseudoRVVInitSubUndefM8_1]], 10
+    ; CHECK-NEXT: early-clobber %5:vrm8 = PseudoVRGATHER_VI_M8 killed [[PseudoRVVInitSubUndefM8_2]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype
     ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
     ; CHECK-NEXT: PseudoVSE32_V_M8 killed %5, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
@@ -530,11 +496,9 @@
     ; CHECK-NEXT: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */
     ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M2_]], %subreg.sub_vrm2_0
     ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
-    ; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
-    ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_1
-    ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2
-    ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_1
-    ; CHECK-NEXT: early-clobber %5:vrm8 = PseudoVRGATHER_VI_M8 killed [[INSERT_SUBREG2]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype
+    ; CHECK-NEXT: [[PseudoRVVInitSubUndefM8_:%[0-9]+]]:vrm8 = PseudoRVVInitSubUndefM8 [[INSERT_SUBREG]], 17
+    ; CHECK-NEXT: [[PseudoRVVInitSubUndefM8_1:%[0-9]+]]:vrm8 = PseudoRVVInitSubUndefM8 [[PseudoRVVInitSubUndefM8_]], 13
+    ; CHECK-NEXT: early-clobber %5:vrm8 = PseudoVRGATHER_VI_M8 killed [[PseudoRVVInitSubUndefM8_1]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype
     ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
     ; CHECK-NEXT: PseudoVSE32_V_M8 killed %5, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
@@ -566,11 +530,9 @@
     ; CHECK-NEXT: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */
     ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M2_]], %subreg.sub_vrm2_1
     ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
-    ; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
-    ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_1
-    ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2
-    ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_0
-    ; CHECK-NEXT: early-clobber %5:vrm8 = PseudoVRGATHER_VI_M8 killed [[INSERT_SUBREG2]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype
+    ; CHECK-NEXT: [[PseudoRVVInitSubUndefM8_:%[0-9]+]]:vrm8 = PseudoRVVInitSubUndefM8 [[INSERT_SUBREG]], 17
+    ; CHECK-NEXT: [[PseudoRVVInitSubUndefM8_1:%[0-9]+]]:vrm8 = PseudoRVVInitSubUndefM8 [[PseudoRVVInitSubUndefM8_]], 12
+    ; CHECK-NEXT: early-clobber %5:vrm8 = PseudoVRGATHER_VI_M8 killed [[PseudoRVVInitSubUndefM8_1]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype
     ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
     ; CHECK-NEXT: PseudoVSE32_V_M8 killed %5, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
@@ -602,11 +564,9 @@
     ; CHECK-NEXT: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */
     ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M2_]], %subreg.sub_vrm2_2
     ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
-    ; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
-    ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_0
-    ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2
-    ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_3
-    ; CHECK-NEXT: early-clobber %5:vrm8 = PseudoVRGATHER_VI_M8 killed [[INSERT_SUBREG2]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype
+    ; CHECK-NEXT: [[PseudoRVVInitSubUndefM8_:%[0-9]+]]:vrm8 = PseudoRVVInitSubUndefM8 [[INSERT_SUBREG]], 16
+    ; CHECK-NEXT: [[PseudoRVVInitSubUndefM8_1:%[0-9]+]]:vrm8 = PseudoRVVInitSubUndefM8 [[PseudoRVVInitSubUndefM8_]], 15
+    ; CHECK-NEXT: early-clobber %5:vrm8 = PseudoVRGATHER_VI_M8 killed [[PseudoRVVInitSubUndefM8_1]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype
     ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
     ; CHECK-NEXT: PseudoVSE32_V_M8 killed %5, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
@@ -638,11 +598,9 @@
     ; CHECK-NEXT: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */
     ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M2_]], %subreg.sub_vrm2_3
     ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
-    ; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
-    ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_0
-    ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2
-    ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_2
-    ; CHECK-NEXT: early-clobber %5:vrm8 = PseudoVRGATHER_VI_M8 killed [[INSERT_SUBREG2]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype
+    ; CHECK-NEXT: [[PseudoRVVInitSubUndefM8_:%[0-9]+]]:vrm8 = PseudoRVVInitSubUndefM8 [[INSERT_SUBREG]], 16
+    ; CHECK-NEXT: [[PseudoRVVInitSubUndefM8_1:%[0-9]+]]:vrm8 = PseudoRVVInitSubUndefM8 [[PseudoRVVInitSubUndefM8_]], 14
+    ; CHECK-NEXT: early-clobber %5:vrm8 = PseudoVRGATHER_VI_M8 killed [[PseudoRVVInitSubUndefM8_1]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype
     ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
     ; CHECK-NEXT: PseudoVSE32_V_M8 killed %5, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
@@ -674,9 +632,8 @@
     ; CHECK-NEXT: [[PseudoVLE32_V_M4_:%[0-9]+]]:vrm4 = PseudoVLE32_V_M4 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */
     ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M4_]], %subreg.sub_vrm4_0
     ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
-    ; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
-    ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_1
-    ; CHECK-NEXT: early-clobber %5:vrm8 = PseudoVRGATHER_VI_M8 killed [[INSERT_SUBREG1]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype
+    ; CHECK-NEXT: [[PseudoRVVInitSubUndefM8_:%[0-9]+]]:vrm8 = PseudoRVVInitSubUndefM8 [[INSERT_SUBREG]], 17
+    ; CHECK-NEXT: early-clobber %5:vrm8 = PseudoVRGATHER_VI_M8 killed [[PseudoRVVInitSubUndefM8_]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype
     ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
     ; CHECK-NEXT: PseudoVSE32_V_M8 killed %5, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
@@ -708,9 +665,8 @@
     ; CHECK-NEXT: [[PseudoVLE32_V_M4_:%[0-9]+]]:vrm4 = PseudoVLE32_V_M4 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */
     ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M4_]], %subreg.sub_vrm4_1
     ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
-    ; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
-    ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_0
-    ; CHECK-NEXT: early-clobber %5:vrm8 = PseudoVRGATHER_VI_M8 killed [[INSERT_SUBREG1]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype
+    ; CHECK-NEXT: [[PseudoRVVInitSubUndefM8_:%[0-9]+]]:vrm8 = PseudoRVVInitSubUndefM8 [[INSERT_SUBREG]], 16
+    ; CHECK-NEXT: early-clobber %5:vrm8 = PseudoVRGATHER_VI_M8 killed [[PseudoRVVInitSubUndefM8_]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype
     ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
     ; CHECK-NEXT: PseudoVSE32_V_M8 killed %5, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
diff --git a/llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll b/llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll
--- a/llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll
@@ -150,10 +150,9 @@
 define void @repeat_shuffle(<2 x double> %v, ptr noalias %q) {
 ; CHECK-LABEL: repeat_shuffle:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv2r.v v12, v8
 ; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
-; CHECK-NEXT:    vmv1r.v v13, v10
-; CHECK-NEXT:    vslideup.vi v8, v12, 2
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vslideup.vi v8, v10, 2
 ; CHECK-NEXT:    vse64.v v8, (a0)
 ; CHECK-NEXT:    ret
   %w = shufflevector <2 x double> %v, <2 x double> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 1>