diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td @@ -820,99 +820,113 @@ } } -multiclass VPatIntegerSetCCVL_VV { - def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), - vti.RegClass:$rs2, cc, - VR:$merge, - (vti.Mask V0), - VLOpFrag)), - (!cast(instruction_name#"_VV_"#vti.LMul.MX#"_MASK") - VR:$merge, - vti.RegClass:$rs1, - vti.RegClass:$rs2, - (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; +multiclass VPatIntegerSetCCVL_VV { + foreach vti = AllIntegerVectors in + let Predicates = GetVTypePredicates.Predicates in + def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), + vti.RegClass:$rs2, cc, + VR:$merge, + (vti.Mask V0), + VLOpFrag)), + (!cast(instruction_name#"_VV_"#vti.LMul.MX#"_MASK") + VR:$merge, + vti.RegClass:$rs1, + vti.RegClass:$rs2, + (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; } // Inherits from VPatIntegerSetCCVL_VV and adds a pattern with operands swapped. -multiclass VPatIntegerSetCCVL_VV_Swappable - : VPatIntegerSetCCVL_VV { - def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs2), - vti.RegClass:$rs1, invcc, - VR:$merge, - (vti.Mask V0), - VLOpFrag)), - (!cast(instruction_name#"_VV_"#vti.LMul.MX#"_MASK") - VR:$merge, vti.RegClass:$rs1, - vti.RegClass:$rs2, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; + : VPatIntegerSetCCVL_VV { + foreach vti = AllIntegerVectors in + let Predicates = GetVTypePredicates.Predicates in + def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs2), + vti.RegClass:$rs1, invcc, + VR:$merge, + (vti.Mask V0), + VLOpFrag)), + (!cast(instruction_name#"_VV_"#vti.LMul.MX#"_MASK") + VR:$merge, vti.RegClass:$rs1, vti.RegClass:$rs2, + (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; } -multiclass VPatIntegerSetCCVL_VX_Swappable { - defvar instruction_masked = !cast(instruction_name#"_VX_"#vti.LMul.MX#"_MASK"); - def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), - (SplatPat (XLenVT GPR:$rs2)), cc, - VR:$merge, - (vti.Mask V0), - VLOpFrag)), - (instruction_masked VR:$merge, vti.RegClass:$rs1, - GPR:$rs2, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; - def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat (XLenVT GPR:$rs2)), - (vti.Vector vti.RegClass:$rs1), invcc, - VR:$merge, - (vti.Mask V0), - VLOpFrag)), - (instruction_masked VR:$merge, vti.RegClass:$rs1, - GPR:$rs2, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; + foreach vti = AllIntegerVectors in { + defvar instruction_masked = !cast(instruction_name#"_VX_"#vti.LMul.MX#"_MASK"); + let Predicates = GetVTypePredicates.Predicates in { + def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), + (SplatPat (XLenVT GPR:$rs2)), cc, + VR:$merge, + (vti.Mask V0), + VLOpFrag)), + (instruction_masked VR:$merge, vti.RegClass:$rs1, GPR:$rs2, + (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; + def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat (XLenVT GPR:$rs2)), + (vti.Vector vti.RegClass:$rs1), invcc, + VR:$merge, + (vti.Mask V0), + VLOpFrag)), + (instruction_masked VR:$merge, vti.RegClass:$rs1, GPR:$rs2, + (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; + } + } } -multiclass VPatIntegerSetCCVL_VI_Swappable { - defvar instruction_masked = !cast(instruction_name#"_VI_"#vti.LMul.MX#"_MASK"); - def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), - (SplatPat_simm5 simm5:$rs2), cc, - VR:$merge, - (vti.Mask V0), - VLOpFrag)), - (instruction_masked VR:$merge, vti.RegClass:$rs1, - XLenVT:$rs2, (vti.Mask V0), GPR:$vl, - vti.Log2SEW)>; - - // FIXME: Can do some canonicalization to remove these patterns. - def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat_simm5 simm5:$rs2), - (vti.Vector vti.RegClass:$rs1), invcc, - VR:$merge, - (vti.Mask V0), - VLOpFrag)), - (instruction_masked VR:$merge, vti.RegClass:$rs1, - simm5:$rs2, (vti.Mask V0), GPR:$vl, - vti.Log2SEW)>; + foreach vti = AllIntegerVectors in { + defvar instruction_masked = !cast(instruction_name#"_VI_"#vti.LMul.MX#"_MASK"); + let Predicates = GetVTypePredicates.Predicates in { + def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), + (SplatPat_simm5 simm5:$rs2), cc, + VR:$merge, + (vti.Mask V0), + VLOpFrag)), + (instruction_masked VR:$merge, vti.RegClass:$rs1, + XLenVT:$rs2, (vti.Mask V0), GPR:$vl, + vti.Log2SEW)>; + + // FIXME: Can do some canonicalization to remove these patterns. + def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat_simm5 simm5:$rs2), + (vti.Vector vti.RegClass:$rs1), invcc, + VR:$merge, + (vti.Mask V0), + VLOpFrag)), + (instruction_masked VR:$merge, vti.RegClass:$rs1, + simm5:$rs2, (vti.Mask V0), GPR:$vl, + vti.Log2SEW)>; + } + } } -multiclass VPatIntegerSetCCVL_VIPlus1_Swappable { - defvar instruction_masked = !cast(instruction_name#"_VI_"#vti.LMul.MX#"_MASK"); - def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), - (splatpat_kind simm5:$rs2), cc, - VR:$merge, - (vti.Mask V0), - VLOpFrag)), - (instruction_masked VR:$merge, vti.RegClass:$rs1, - (DecImm simm5:$rs2), (vti.Mask V0), GPR:$vl, - vti.Log2SEW)>; - - // FIXME: Can do some canonicalization to remove these patterns. - def : Pat<(vti.Mask (riscv_setcc_vl (splatpat_kind simm5:$rs2), - (vti.Vector vti.RegClass:$rs1), invcc, - VR:$merge, - (vti.Mask V0), - VLOpFrag)), - (instruction_masked VR:$merge, vti.RegClass:$rs1, - (DecImm simm5:$rs2), (vti.Mask V0), GPR:$vl, - vti.Log2SEW)>; + foreach vti = AllIntegerVectors in { + defvar instruction_masked = !cast(instruction_name#"_VI_"#vti.LMul.MX#"_MASK"); + let Predicates = GetVTypePredicates.Predicates in { + def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), + (splatpat_kind simm5:$rs2), cc, + VR:$merge, + (vti.Mask V0), + VLOpFrag)), + (instruction_masked VR:$merge, vti.RegClass:$rs1, + (DecImm simm5:$rs2), (vti.Mask V0), GPR:$vl, + vti.Log2SEW)>; + + // FIXME: Can do some canonicalization to remove these patterns. + def : Pat<(vti.Mask (riscv_setcc_vl (splatpat_kind simm5:$rs2), + (vti.Vector vti.RegClass:$rs1), invcc, + VR:$merge, + (vti.Mask V0), + VLOpFrag)), + (instruction_masked VR:$merge, vti.RegClass:$rs1, + (DecImm simm5:$rs2), (vti.Mask V0), GPR:$vl, + vti.Log2SEW)>; + } + } } multiclass VPatFPSetCCVL_VV_VF_FV.Predicates in { - defm : VPatIntegerSetCCVL_VV; - defm : VPatIntegerSetCCVL_VV; - - defm : VPatIntegerSetCCVL_VV_Swappable; - defm : VPatIntegerSetCCVL_VV_Swappable; - defm : VPatIntegerSetCCVL_VV_Swappable; - defm : VPatIntegerSetCCVL_VV_Swappable; - - defm : VPatIntegerSetCCVL_VX_Swappable; - defm : VPatIntegerSetCCVL_VX_Swappable; - defm : VPatIntegerSetCCVL_VX_Swappable; - defm : VPatIntegerSetCCVL_VX_Swappable; - defm : VPatIntegerSetCCVL_VX_Swappable; - defm : VPatIntegerSetCCVL_VX_Swappable; - defm : VPatIntegerSetCCVL_VX_Swappable; - defm : VPatIntegerSetCCVL_VX_Swappable; - // There is no VMSGE(U)_VX instruction - - defm : VPatIntegerSetCCVL_VI_Swappable; - defm : VPatIntegerSetCCVL_VI_Swappable; - defm : VPatIntegerSetCCVL_VI_Swappable; - defm : VPatIntegerSetCCVL_VI_Swappable; - defm : VPatIntegerSetCCVL_VI_Swappable; - defm : VPatIntegerSetCCVL_VI_Swappable; - - defm : VPatIntegerSetCCVL_VIPlus1_Swappable; - defm : VPatIntegerSetCCVL_VIPlus1_Swappable; - defm : VPatIntegerSetCCVL_VIPlus1_Swappable; - defm : VPatIntegerSetCCVL_VIPlus1_Swappable; - } -} // foreach vti = AllIntegerVectors +defm : VPatIntegerSetCCVL_VV<"PseudoVMSEQ", SETEQ>; +defm : VPatIntegerSetCCVL_VV<"PseudoVMSNE", SETNE>; + +defm : VPatIntegerSetCCVL_VV_Swappable<"PseudoVMSLT", SETLT, SETGT>; +defm : VPatIntegerSetCCVL_VV_Swappable<"PseudoVMSLTU", SETULT, SETUGT>; +defm : VPatIntegerSetCCVL_VV_Swappable<"PseudoVMSLE", SETLE, SETGE>; +defm : VPatIntegerSetCCVL_VV_Swappable<"PseudoVMSLEU", SETULE, SETUGE>; + +defm : VPatIntegerSetCCVL_VX_Swappable<"PseudoVMSEQ", SETEQ, SETEQ>; +defm : VPatIntegerSetCCVL_VX_Swappable<"PseudoVMSNE", SETNE, SETNE>; +defm : VPatIntegerSetCCVL_VX_Swappable<"PseudoVMSLT", SETLT, SETGT>; +defm : VPatIntegerSetCCVL_VX_Swappable<"PseudoVMSLTU", SETULT, SETUGT>; +defm : VPatIntegerSetCCVL_VX_Swappable<"PseudoVMSLE", SETLE, SETGE>; +defm : VPatIntegerSetCCVL_VX_Swappable<"PseudoVMSLEU", SETULE, SETUGE>; +defm : VPatIntegerSetCCVL_VX_Swappable<"PseudoVMSGT", SETGT, SETLT>; +defm : VPatIntegerSetCCVL_VX_Swappable<"PseudoVMSGTU", SETUGT, SETULT>; + +// There is no VMSGE(U)_VX instruction + +defm : VPatIntegerSetCCVL_VI_Swappable<"PseudoVMSEQ", SETEQ, SETEQ>; +defm : VPatIntegerSetCCVL_VI_Swappable<"PseudoVMSNE", SETNE, SETNE>; +defm : VPatIntegerSetCCVL_VI_Swappable<"PseudoVMSLE", SETLE, SETGE>; +defm : VPatIntegerSetCCVL_VI_Swappable<"PseudoVMSLEU", SETULE, SETUGE>; +defm : VPatIntegerSetCCVL_VI_Swappable<"PseudoVMSGT", SETGT, SETLT>; +defm : VPatIntegerSetCCVL_VI_Swappable<"PseudoVMSGTU", SETUGT, SETULT>; + +defm : VPatIntegerSetCCVL_VIPlus1_Swappable<"PseudoVMSLE", SETLT, SETGT, + SplatPat_simm5_plus1>; +defm : VPatIntegerSetCCVL_VIPlus1_Swappable<"PseudoVMSLEU", SETULT, SETUGT, + SplatPat_simm5_plus1_nonzero>; +defm : VPatIntegerSetCCVL_VIPlus1_Swappable<"PseudoVMSGT", SETGE, SETLE, + SplatPat_simm5_plus1>; +defm : VPatIntegerSetCCVL_VIPlus1_Swappable<"PseudoVMSGTU", SETUGE, SETULE, + SplatPat_simm5_plus1_nonzero>; // 11.9. Vector Integer Min/Max Instructions defm : VPatBinaryVL_VV_VX;