diff --git a/llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td --- a/llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td +++ b/llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td @@ -33,95 +33,91 @@ let Predicates = [HasBasicF] in { // Arithmetic Operation Instructions -def FADD_S : FP_ALU_3R<0b00000001000000001, "fadd.s", FPR32>; -def FSUB_S : FP_ALU_3R<0b00000001000000101, "fsub.s", FPR32>; -def FMUL_S : FP_ALU_3R<0b00000001000001001, "fmul.s", FPR32>; -def FDIV_S : FP_ALU_3R<0b00000001000001101, "fdiv.s", FPR32>; -def FMADD_S : FP_ALU_4R<0b000010000001, "fmadd.s", FPR32>; -def FMSUB_S : FP_ALU_4R<0b000010000101, "fmsub.s", FPR32>; -def FNMADD_S : FP_ALU_4R<0b000010001001, "fnmadd.s", FPR32>; -def FNMSUB_S : FP_ALU_4R<0b000010001101, "fnmsub.s", FPR32>; -def FMAX_S : FP_ALU_3R<0b00000001000010001, "fmax.s", FPR32>; -def FMIN_S : FP_ALU_3R<0b00000001000010101, "fmin.s", FPR32>; -def FMAXA_S : FP_ALU_3R<0b00000001000011001, "fmaxa.s", FPR32>; -def FMINA_S : FP_ALU_3R<0b00000001000011101, "fmina.s", FPR32>; -def FABS_S : FP_ALU_2R<0b0000000100010100000001, "fabs.s", FPR32>; -def FNEG_S : FP_ALU_2R<0b0000000100010100000101, "fneg.s", FPR32>; -def FSQRT_S : FP_ALU_2R<0b0000000100010100010001, "fsqrt.s", FPR32>; -def FRECIP_S : FP_ALU_2R<0b0000000100010100010101, "frecip.s", FPR32>; -def FRSQRT_S : FP_ALU_2R<0b0000000100010100011001, "frsqrt.s", FPR32>; -def FSCALEB_S : FP_ALU_3R<0b00000001000100001, "fscaleb.s", FPR32>; -def FLOGB_S : FP_ALU_2R<0b0000000100010100001001, "flogb.s", FPR32>; -def FCOPYSIGN_S : FP_ALU_3R<0b00000001000100101, "fcopysign.s", FPR32>; -def FCLASS_S : FP_ALU_2R<0b0000000100010100001101, "fclass.s", FPR32>; +def FADD_S : FP_ALU_3R<0b00000001000000001, FPR32>; +def FSUB_S : FP_ALU_3R<0b00000001000000101, FPR32>; +def FMUL_S : FP_ALU_3R<0b00000001000001001, FPR32>; +def FDIV_S : FP_ALU_3R<0b00000001000001101, FPR32>; +def FMADD_S : FP_ALU_4R<0b000010000001, FPR32>; +def FMSUB_S : FP_ALU_4R<0b000010000101, FPR32>; +def FNMADD_S : FP_ALU_4R<0b000010001001, FPR32>; +def FNMSUB_S : FP_ALU_4R<0b000010001101, FPR32>; +def FMAX_S : FP_ALU_3R<0b00000001000010001, FPR32>; +def FMIN_S : FP_ALU_3R<0b00000001000010101, FPR32>; +def FMAXA_S : FP_ALU_3R<0b00000001000011001, FPR32>; +def FMINA_S : FP_ALU_3R<0b00000001000011101, FPR32>; +def FABS_S : FP_ALU_2R<0b0000000100010100000001, FPR32>; +def FNEG_S : FP_ALU_2R<0b0000000100010100000101, FPR32>; +def FSQRT_S : FP_ALU_2R<0b0000000100010100010001, FPR32>; +def FRECIP_S : FP_ALU_2R<0b0000000100010100010101, FPR32>; +def FRSQRT_S : FP_ALU_2R<0b0000000100010100011001, FPR32>; +def FSCALEB_S : FP_ALU_3R<0b00000001000100001, FPR32>; +def FLOGB_S : FP_ALU_2R<0b0000000100010100001001, FPR32>; +def FCOPYSIGN_S : FP_ALU_3R<0b00000001000100101, FPR32>; +def FCLASS_S : FP_ALU_2R<0b0000000100010100001101, FPR32>; // Comparison Instructions -def FCMP_CAF_S : FP_CMP; -def FCMP_CUN_S : FP_CMP; -def FCMP_CEQ_S : FP_CMP; -def FCMP_CUEQ_S : FP_CMP; -def FCMP_CLT_S : FP_CMP; -def FCMP_CULT_S : FP_CMP; -def FCMP_CLE_S : FP_CMP; -def FCMP_CULE_S : FP_CMP; -def FCMP_CNE_S : FP_CMP; -def FCMP_COR_S : FP_CMP; -def FCMP_CUNE_S : FP_CMP; -def FCMP_SAF_S : FP_CMP; -def FCMP_SUN_S : FP_CMP; -def FCMP_SEQ_S : FP_CMP; -def FCMP_SUEQ_S : FP_CMP; -def FCMP_SLT_S : FP_CMP; -def FCMP_SULT_S : FP_CMP; -def FCMP_SLE_S : FP_CMP; -def FCMP_SULE_S : FP_CMP; -def FCMP_SNE_S : FP_CMP; -def FCMP_SOR_S : FP_CMP; -def FCMP_SUNE_S : FP_CMP; +def FCMP_CAF_S : FP_CMP; +def FCMP_CUN_S : FP_CMP; +def FCMP_CEQ_S : FP_CMP; +def FCMP_CUEQ_S : FP_CMP; +def FCMP_CLT_S : FP_CMP; +def FCMP_CULT_S : FP_CMP; +def FCMP_CLE_S : FP_CMP; +def FCMP_CULE_S : FP_CMP; +def FCMP_CNE_S : FP_CMP; +def FCMP_COR_S : FP_CMP; +def FCMP_CUNE_S : FP_CMP; +def FCMP_SAF_S : FP_CMP; +def FCMP_SUN_S : FP_CMP; +def FCMP_SEQ_S : FP_CMP; +def FCMP_SUEQ_S : FP_CMP; +def FCMP_SLT_S : FP_CMP; +def FCMP_SULT_S : FP_CMP; +def FCMP_SLE_S : FP_CMP; +def FCMP_SULE_S : FP_CMP; +def FCMP_SNE_S : FP_CMP; +def FCMP_SOR_S : FP_CMP; +def FCMP_SUNE_S : FP_CMP; // Conversion Instructions -def FFINT_S_W : FP_CONV<0b0000000100011101000100, "ffint.s.w", FPR32, FPR32>; -def FTINT_W_S : FP_CONV<0b0000000100011011000001, "ftint.w.s", FPR32, FPR32>; -def FTINTRM_W_S : FP_CONV<0b0000000100011010000001, "ftintrm.w.s", FPR32, - FPR32>; -def FTINTRP_W_S : FP_CONV<0b0000000100011010010001, "ftintrp.w.s", FPR32, - FPR32>; -def FTINTRZ_W_S : FP_CONV<0b0000000100011010100001, "ftintrz.w.s", FPR32, - FPR32>; -def FTINTRNE_W_S : FP_CONV<0b0000000100011010110001, "ftintrne.w.s", FPR32, - FPR32>; -def FRINT_S : FP_CONV<0b0000000100011110010001, "frint.s", FPR32, FPR32>; +def FFINT_S_W : FP_CONV<0b0000000100011101000100, FPR32, FPR32>; +def FTINT_W_S : FP_CONV<0b0000000100011011000001, FPR32, FPR32>; +def FTINTRM_W_S : FP_CONV<0b0000000100011010000001, FPR32, FPR32>; +def FTINTRP_W_S : FP_CONV<0b0000000100011010010001, FPR32, FPR32>; +def FTINTRZ_W_S : FP_CONV<0b0000000100011010100001, FPR32, FPR32>; +def FTINTRNE_W_S : FP_CONV<0b0000000100011010110001, FPR32, FPR32>; +def FRINT_S : FP_CONV<0b0000000100011110010001, FPR32, FPR32>; // Move Instructions -def FSEL_S : FP_SEL<0b00001101000000, "fsel", FPR32>; -def FMOV_S : FP_MOV<0b0000000100010100100101, "fmov.s", FPR32, FPR32>; -def MOVGR2FR_W : FP_MOV<0b0000000100010100101001, "movgr2fr.w", FPR32, GPR>; -def MOVFR2GR_S : FP_MOV<0b0000000100010100101101, "movfr2gr.s", GPR, FPR32>; +def FSEL_xS : FP_SEL<0b00001101000000, FPR32>; +def FMOV_S : FP_MOV<0b0000000100010100100101, FPR32, FPR32>; +def MOVGR2FR_W : FP_MOV<0b0000000100010100101001, FPR32, GPR>; +def MOVFR2GR_S : FP_MOV<0b0000000100010100101101, GPR, FPR32>; let hasSideEffects = 1 in { -def MOVGR2FCSR : FP_MOV<0b0000000100010100110000, "movgr2fcsr", FCSR, GPR>; -def MOVFCSR2GR : FP_MOV<0b0000000100010100110010, "movfcsr2gr", GPR, FCSR>; +def MOVGR2FCSR : FP_MOV<0b0000000100010100110000, FCSR, GPR>; +def MOVFCSR2GR : FP_MOV<0b0000000100010100110010, GPR, FCSR>; } // hasSideEffects = 1 -def MOVFR2CF_S : FP_MOV<0b0000000100010100110100, "movfr2cf", CFR, FPR32>; -def MOVCF2FR_S : FP_MOV<0b0000000100010100110101, "movcf2fr", FPR32, CFR>; -def MOVGR2CF : FP_MOV<0b0000000100010100110110, "movgr2cf", CFR, GPR>; -def MOVCF2GR : FP_MOV<0b0000000100010100110111, "movcf2gr", GPR, CFR>; +def MOVFR2CF_xS : FP_MOV<0b0000000100010100110100, CFR, FPR32>; +def MOVCF2FR_xS : FP_MOV<0b0000000100010100110101, FPR32, CFR>; +def MOVGR2CF : FP_MOV<0b0000000100010100110110, CFR, GPR>; +def MOVCF2GR : FP_MOV<0b0000000100010100110111, GPR, CFR>; // Branch Instructions -def BCEQZ : FP_BRANCH<0b01001000, "bceqz">; -def BCNEZ : FP_BRANCH<0b01001001, "bcnez">; +def BCEQZ : FP_BRANCH<0b01001000>; +def BCNEZ : FP_BRANCH<0b01001001>; // Common Memory Access Instructions -def FLD_S : FP_LOAD_2RI12<0b0010101100, "fld.s", FPR32>; -def FST_S : FP_STORE_2RI12<0b0010101101, "fst.s", FPR32>; -def FLDX_S : FP_LOAD_3R<0b00111000001100000, "fldx.s", FPR32>; -def FSTX_S : FP_STORE_3R<0b00111000001110000, "fstx.s", FPR32>; +def FLD_S : FP_LOAD_2RI12<0b0010101100, FPR32>; +def FST_S : FP_STORE_2RI12<0b0010101101, FPR32>; +def FLDX_S : FP_LOAD_3R<0b00111000001100000, FPR32>; +def FSTX_S : FP_STORE_3R<0b00111000001110000, FPR32>; // Bound Check Memory Access Instructions -def FLDGT_S : FP_LOAD_3R<0b00111000011101000, "fldgt.s", FPR32>; -def FLDLE_S : FP_LOAD_3R<0b00111000011101010, "fldle.s", FPR32>; -def FSTGT_S : FP_STORE_3R<0b00111000011101100, "fstgt.s", FPR32>; -def FSTLE_S : FP_STORE_3R<0b00111000011101110, "fstle.s", FPR32>; +def FLDGT_S : FP_LOAD_3R<0b00111000011101000, FPR32>; +def FLDLE_S : FP_LOAD_3R<0b00111000011101010, FPR32>; +def FSTGT_S : FP_STORE_3R<0b00111000011101100, FPR32>; +def FSTLE_S : FP_STORE_3R<0b00111000011101110, FPR32>; // Pseudo instructions for spill/reload CFRs. let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in @@ -225,7 +221,7 @@ /// Select def : Pat<(select CFR:$cc, FPR32:$fk, FPR32:$fj), - (FSEL_S FPR32:$fj, FPR32:$fk, CFR:$cc)>; + (FSEL_xS FPR32:$fj, FPR32:$fk, CFR:$cc)>; /// Selectcc @@ -233,16 +229,16 @@ RegisterClass RegTy> : Pat<(select (GRLenVT (setcc RegTy:$a, RegTy:$b, cc)), RegTy:$t, RegTy:$f), (SelInst RegTy:$f, RegTy:$t, (CmpInst RegTy:$a, RegTy:$b))>; -def : PatFPSelectcc; -def : PatFPSelectcc; -def : PatFPSelectcc; -def : PatFPSelectcc; -def : PatFPSelectcc; -def : PatFPSelectcc; -def : PatFPSelectcc; -def : PatFPSelectcc; -def : PatFPSelectcc; -def : PatFPSelectcc; +def : PatFPSelectcc; +def : PatFPSelectcc; +def : PatFPSelectcc; +def : PatFPSelectcc; +def : PatFPSelectcc; +def : PatFPSelectcc; +def : PatFPSelectcc; +def : PatFPSelectcc; +def : PatFPSelectcc; +def : PatFPSelectcc; /// Loads diff --git a/llvm/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td --- a/llvm/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td +++ b/llvm/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td @@ -17,123 +17,111 @@ let Predicates = [HasBasicD] in { // Arithmetic Operation Instructions -def FADD_D : FP_ALU_3R<0b00000001000000010, "fadd.d", FPR64>; -def FSUB_D : FP_ALU_3R<0b00000001000000110, "fsub.d", FPR64>; -def FMUL_D : FP_ALU_3R<0b00000001000001010, "fmul.d", FPR64>; -def FDIV_D : FP_ALU_3R<0b00000001000001110, "fdiv.d", FPR64>; -def FMADD_D : FP_ALU_4R<0b000010000010, "fmadd.d", FPR64>; -def FMSUB_D : FP_ALU_4R<0b000010000110, "fmsub.d", FPR64>; -def FNMADD_D : FP_ALU_4R<0b000010001010, "fnmadd.d", FPR64>; -def FNMSUB_D : FP_ALU_4R<0b000010001110, "fnmsub.d", FPR64>; -def FMAX_D : FP_ALU_3R<0b00000001000010010, "fmax.d", FPR64>; -def FMIN_D : FP_ALU_3R<0b00000001000010110, "fmin.d", FPR64>; -def FMAXA_D : FP_ALU_3R<0b00000001000011010, "fmaxa.d", FPR64>; -def FMINA_D : FP_ALU_3R<0b00000001000011110, "fmina.d", FPR64>; -def FABS_D : FP_ALU_2R<0b0000000100010100000010, "fabs.d", FPR64>; -def FNEG_D : FP_ALU_2R<0b0000000100010100000110, "fneg.d", FPR64>; -def FSQRT_D : FP_ALU_2R<0b0000000100010100010010, "fsqrt.d", FPR64>; -def FRECIP_D : FP_ALU_2R<0b0000000100010100010110, "frecip.d", FPR64>; -def FRSQRT_D : FP_ALU_2R<0b0000000100010100011010, "frsqrt.d", FPR64>; -def FSCALEB_D : FP_ALU_3R<0b00000001000100010, "fscaleb.d", FPR64>; -def FLOGB_D : FP_ALU_2R<0b0000000100010100001010, "flogb.d", FPR64>; -def FCOPYSIGN_D : FP_ALU_3R<0b00000001000100110, "fcopysign.d", FPR64>; -def FCLASS_D : FP_ALU_2R<0b0000000100010100001110, "fclass.d", FPR64>; +def FADD_D : FP_ALU_3R<0b00000001000000010, FPR64>; +def FSUB_D : FP_ALU_3R<0b00000001000000110, FPR64>; +def FMUL_D : FP_ALU_3R<0b00000001000001010, FPR64>; +def FDIV_D : FP_ALU_3R<0b00000001000001110, FPR64>; +def FMADD_D : FP_ALU_4R<0b000010000010, FPR64>; +def FMSUB_D : FP_ALU_4R<0b000010000110, FPR64>; +def FNMADD_D : FP_ALU_4R<0b000010001010, FPR64>; +def FNMSUB_D : FP_ALU_4R<0b000010001110, FPR64>; +def FMAX_D : FP_ALU_3R<0b00000001000010010, FPR64>; +def FMIN_D : FP_ALU_3R<0b00000001000010110, FPR64>; +def FMAXA_D : FP_ALU_3R<0b00000001000011010, FPR64>; +def FMINA_D : FP_ALU_3R<0b00000001000011110, FPR64>; +def FABS_D : FP_ALU_2R<0b0000000100010100000010, FPR64>; +def FNEG_D : FP_ALU_2R<0b0000000100010100000110, FPR64>; +def FSQRT_D : FP_ALU_2R<0b0000000100010100010010, FPR64>; +def FRECIP_D : FP_ALU_2R<0b0000000100010100010110, FPR64>; +def FRSQRT_D : FP_ALU_2R<0b0000000100010100011010, FPR64>; +def FSCALEB_D : FP_ALU_3R<0b00000001000100010, FPR64>; +def FLOGB_D : FP_ALU_2R<0b0000000100010100001010, FPR64>; +def FCOPYSIGN_D : FP_ALU_3R<0b00000001000100110, FPR64>; +def FCLASS_D : FP_ALU_2R<0b0000000100010100001110, FPR64>; // Comparison Instructions -def FCMP_CAF_D : FP_CMP; -def FCMP_CUN_D : FP_CMP; -def FCMP_CEQ_D : FP_CMP; -def FCMP_CUEQ_D : FP_CMP; -def FCMP_CLT_D : FP_CMP; -def FCMP_CULT_D : FP_CMP; -def FCMP_CLE_D : FP_CMP; -def FCMP_CULE_D : FP_CMP; -def FCMP_CNE_D : FP_CMP; -def FCMP_COR_D : FP_CMP; -def FCMP_CUNE_D : FP_CMP; -def FCMP_SAF_D : FP_CMP; -def FCMP_SUN_D : FP_CMP; -def FCMP_SEQ_D : FP_CMP; -def FCMP_SUEQ_D : FP_CMP; -def FCMP_SLT_D : FP_CMP; -def FCMP_SULT_D : FP_CMP; -def FCMP_SLE_D : FP_CMP; -def FCMP_SULE_D : FP_CMP; -def FCMP_SNE_D : FP_CMP; -def FCMP_SOR_D : FP_CMP; -def FCMP_SUNE_D : FP_CMP; +def FCMP_CAF_D : FP_CMP; +def FCMP_CUN_D : FP_CMP; +def FCMP_CEQ_D : FP_CMP; +def FCMP_CUEQ_D : FP_CMP; +def FCMP_CLT_D : FP_CMP; +def FCMP_CULT_D : FP_CMP; +def FCMP_CLE_D : FP_CMP; +def FCMP_CULE_D : FP_CMP; +def FCMP_CNE_D : FP_CMP; +def FCMP_COR_D : FP_CMP; +def FCMP_CUNE_D : FP_CMP; +def FCMP_SAF_D : FP_CMP; +def FCMP_SUN_D : FP_CMP; +def FCMP_SEQ_D : FP_CMP; +def FCMP_SUEQ_D : FP_CMP; +def FCMP_SLT_D : FP_CMP; +def FCMP_SULT_D : FP_CMP; +def FCMP_SLE_D : FP_CMP; +def FCMP_SULE_D : FP_CMP; +def FCMP_SNE_D : FP_CMP; +def FCMP_SOR_D : FP_CMP; +def FCMP_SUNE_D : FP_CMP; // Conversion Instructions -def FFINT_S_L : FP_CONV<0b0000000100011101000110, "ffint.s.l", FPR32, FPR64>; -def FTINT_L_S : FP_CONV<0b0000000100011011001001, "ftint.l.s", FPR64, FPR32>; -def FTINTRM_L_S : FP_CONV<0b0000000100011010001001, "ftintrm.l.s", FPR64, - FPR32>; -def FTINTRP_L_S : FP_CONV<0b0000000100011010011001, "ftintrp.l.s", FPR64, - FPR32>; -def FTINTRZ_L_S : FP_CONV<0b0000000100011010101001, "ftintrz.l.s", FPR64, - FPR32>; -def FTINTRNE_L_S : FP_CONV<0b0000000100011010111001, "ftintrne.l.s", FPR64, - FPR32>; -def FCVT_S_D : FP_CONV<0b0000000100011001000110, "fcvt.s.d", FPR32, FPR64>; -def FCVT_D_S : FP_CONV<0b0000000100011001001001, "fcvt.d.s", FPR64, FPR32>; -def FFINT_D_W : FP_CONV<0b0000000100011101001000, "ffint.d.w", FPR64, FPR32>; -def FFINT_D_L : FP_CONV<0b0000000100011101001010, "ffint.d.l", FPR64, FPR64>; -def FTINT_W_D : FP_CONV<0b0000000100011011000010, "ftint.w.d", FPR32, FPR64>; -def FTINT_L_D : FP_CONV<0b0000000100011011001010, "ftint.l.d", FPR64, FPR64>; -def FTINTRM_W_D : FP_CONV<0b0000000100011010000010, "ftintrm.w.d", FPR32, - FPR64>; -def FTINTRM_L_D : FP_CONV<0b0000000100011010001010, "ftintrm.l.d", FPR64, - FPR64>; -def FTINTRP_W_D : FP_CONV<0b0000000100011010010010, "ftintrp.w.d", FPR32, - FPR64>; -def FTINTRP_L_D : FP_CONV<0b0000000100011010011010, "ftintrp.l.d", FPR64, - FPR64>; -def FTINTRZ_W_D : FP_CONV<0b0000000100011010100010, "ftintrz.w.d", FPR32, - FPR64>; -def FTINTRZ_L_D : FP_CONV<0b0000000100011010101010, "ftintrz.l.d", FPR64, - FPR64>; -def FTINTRNE_W_D : FP_CONV<0b0000000100011010110010, "ftintrne.w.d", FPR32, - FPR64>; -def FTINTRNE_L_D : FP_CONV<0b0000000100011010111010, "ftintrne.l.d", FPR64, - FPR64>; -def FRINT_D : FP_CONV<0b0000000100011110010010, "frint.d", FPR64, FPR64>; +def FFINT_S_L : FP_CONV<0b0000000100011101000110, FPR32, FPR64>; +def FTINT_L_S : FP_CONV<0b0000000100011011001001, FPR64, FPR32>; +def FTINTRM_L_S : FP_CONV<0b0000000100011010001001, FPR64, FPR32>; +def FTINTRP_L_S : FP_CONV<0b0000000100011010011001, FPR64, FPR32>; +def FTINTRZ_L_S : FP_CONV<0b0000000100011010101001, FPR64, FPR32>; +def FTINTRNE_L_S : FP_CONV<0b0000000100011010111001, FPR64, FPR32>; +def FCVT_S_D : FP_CONV<0b0000000100011001000110, FPR32, FPR64>; +def FCVT_D_S : FP_CONV<0b0000000100011001001001, FPR64, FPR32>; +def FFINT_D_W : FP_CONV<0b0000000100011101001000, FPR64, FPR32>; +def FFINT_D_L : FP_CONV<0b0000000100011101001010, FPR64, FPR64>; +def FTINT_W_D : FP_CONV<0b0000000100011011000010, FPR32, FPR64>; +def FTINT_L_D : FP_CONV<0b0000000100011011001010, FPR64, FPR64>; +def FTINTRM_W_D : FP_CONV<0b0000000100011010000010, FPR32, FPR64>; +def FTINTRM_L_D : FP_CONV<0b0000000100011010001010, FPR64, FPR64>; +def FTINTRP_W_D : FP_CONV<0b0000000100011010010010, FPR32, FPR64>; +def FTINTRP_L_D : FP_CONV<0b0000000100011010011010, FPR64, FPR64>; +def FTINTRZ_W_D : FP_CONV<0b0000000100011010100010, FPR32, FPR64>; +def FTINTRZ_L_D : FP_CONV<0b0000000100011010101010, FPR64, FPR64>; +def FTINTRNE_W_D : FP_CONV<0b0000000100011010110010, FPR32, FPR64>; +def FTINTRNE_L_D : FP_CONV<0b0000000100011010111010, FPR64, FPR64>; +def FRINT_D : FP_CONV<0b0000000100011110010010, FPR64, FPR64>; // Move Instructions -def FMOV_D : FP_MOV<0b0000000100010100100110, "fmov.d", FPR64, FPR64>; -def MOVFRH2GR_S : FP_MOV<0b0000000100010100101111, "movfrh2gr.s", GPR, FPR64>; +def FMOV_D : FP_MOV<0b0000000100010100100110, FPR64, FPR64>; +def MOVFRH2GR_S : FP_MOV<0b0000000100010100101111, GPR, FPR64>; let isCodeGenOnly = 1 in { -def MOVFR2GR_S_64 : FP_MOV<0b0000000100010100101101, "movfr2gr.s", GPR, FPR64>; -def FSEL_D : FP_SEL<0b00001101000000, "fsel", FPR64>; +def MOVFR2GR_S_64 : FP_MOV<0b0000000100010100101101, GPR, FPR64>; +def FSEL_xD : FP_SEL<0b00001101000000, FPR64>; } // isCodeGenOnly = 1 let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Constraints = "$dst = $out" in { def MOVGR2FRH_W : FPFmtMOV<0b0000000100010100101011, (outs FPR64:$out), - (ins FPR64:$dst, GPR:$src), "movgr2frh.w", + (ins FPR64:$dst, GPR:$src), "$dst, $src">; } // hasSideEffects = 0, mayLoad = 0, mayStore = 0, Constraints = "$dst = $out" // Common Memory Access Instructions -def FLD_D : FP_LOAD_2RI12<0b0010101110, "fld.d", FPR64>; -def FST_D : FP_STORE_2RI12<0b0010101111, "fst.d", FPR64>; -def FLDX_D : FP_LOAD_3R<0b00111000001101000, "fldx.d", FPR64>; -def FSTX_D : FP_STORE_3R<0b00111000001111000, "fstx.d", FPR64>; +def FLD_D : FP_LOAD_2RI12<0b0010101110, FPR64>; +def FST_D : FP_STORE_2RI12<0b0010101111, FPR64>; +def FLDX_D : FP_LOAD_3R<0b00111000001101000, FPR64>; +def FSTX_D : FP_STORE_3R<0b00111000001111000, FPR64>; // Bound Check Memory Access Instructions -def FLDGT_D : FP_LOAD_3R<0b00111000011101001, "fldgt.d", FPR64>; -def FLDLE_D : FP_LOAD_3R<0b00111000011101011, "fldle.d", FPR64>; -def FSTGT_D : FP_STORE_3R<0b00111000011101101, "fstgt.d", FPR64>; -def FSTLE_D : FP_STORE_3R<0b00111000011101111, "fstle.d", FPR64>; +def FLDGT_D : FP_LOAD_3R<0b00111000011101001, FPR64>; +def FLDLE_D : FP_LOAD_3R<0b00111000011101011, FPR64>; +def FSTGT_D : FP_STORE_3R<0b00111000011101101, FPR64>; +def FSTLE_D : FP_STORE_3R<0b00111000011101111, FPR64>; } // Predicates = [HasBasicD] // Instructions only available on LA64 let Predicates = [HasBasicD, IsLA64] in { -def MOVGR2FR_D : FP_MOV<0b0000000100010100101010, "movgr2fr.d", FPR64, GPR>; -def MOVFR2GR_D : FP_MOV<0b0000000100010100101110, "movfr2gr.d", GPR, FPR64>; +def MOVGR2FR_D : FP_MOV<0b0000000100010100101010, FPR64, GPR>; +def MOVFR2GR_D : FP_MOV<0b0000000100010100101110, GPR, FPR64>; } // Predicates = [HasBasicD, IsLA64] // Instructions only available on LA32 let Predicates = [HasBasicD, IsLA32], isCodeGenOnly = 1 in { -def MOVGR2FR_W_64 : FP_MOV<0b0000000100010100101001, "movgr2fr.w", FPR64, GPR>; +def MOVGR2FR_W_64 : FP_MOV<0b0000000100010100101001, FPR64, GPR>; } // Predicates = [HasBasicD, IsLA32], isCodeGenOnly = 1 //===----------------------------------------------------------------------===// @@ -213,20 +201,20 @@ /// Select def : Pat<(select CFR:$cc, FPR64:$fk, FPR64:$fj), - (FSEL_D FPR64:$fj, FPR64:$fk, CFR:$cc)>; + (FSEL_xD FPR64:$fj, FPR64:$fk, CFR:$cc)>; /// Selectcc -def : PatFPSelectcc; -def : PatFPSelectcc; -def : PatFPSelectcc; -def : PatFPSelectcc; -def : PatFPSelectcc; -def : PatFPSelectcc; -def : PatFPSelectcc; -def : PatFPSelectcc; -def : PatFPSelectcc; -def : PatFPSelectcc; +def : PatFPSelectcc; +def : PatFPSelectcc; +def : PatFPSelectcc; +def : PatFPSelectcc; +def : PatFPSelectcc; +def : PatFPSelectcc; +def : PatFPSelectcc; +def : PatFPSelectcc; +def : PatFPSelectcc; +def : PatFPSelectcc; /// Loads diff --git a/llvm/lib/Target/LoongArch/LoongArchFloatInstrFormats.td b/llvm/lib/Target/LoongArch/LoongArchFloatInstrFormats.td --- a/llvm/lib/Target/LoongArch/LoongArchFloatInstrFormats.td +++ b/llvm/lib/Target/LoongArch/LoongArchFloatInstrFormats.td @@ -16,11 +16,24 @@ // //===----------------------------------------------------------------------===// +// Some FP instructions are defined twice, for accepting FPR32 and FPR64, but +// with the same mnemonic. Also some are codegen-only definitions that +// nevertheless require a "normal" mnemonic. +// +// In order to accommodate these needs, the instruction defs have names +// suffixed with `_x[SD]` or `_64`, that will get trimmed before the mnemonics +// are derived. +class deriveFPInsnMnemonic { + string ret = deriveInsnMnemonic.ret; +} + // 2R-type // -class FPFmt2R op, dag outs, dag ins, string opcstr, string opnstr, +class FPFmt2R op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<5> fj; bits<5> fd; @@ -31,9 +44,9 @@ // 3R-type // -class FPFmt3R op, dag outs, dag ins, string opcstr, string opnstr, +class FPFmt3R op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<5> fk; bits<5> fj; bits<5> fd; @@ -46,9 +59,9 @@ // 4R-type // -class FPFmt4R op, dag outs, dag ins, string opcstr, string opnstr, +class FPFmt4R op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<5> fa; bits<5> fk; bits<5> fj; @@ -63,9 +76,9 @@ // 2RI12-type // -class FPFmt2RI12 op, dag outs, dag ins, string opcstr, string opnstr, +class FPFmt2RI12 op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<12> imm12; bits<5> rj; bits<5> fd; @@ -78,9 +91,9 @@ // FmtFCMP // -class FPFmtFCMP op, bits<5> cond, dag outs, dag ins, string opcstr, - string opnstr, list pattern = []> - : LAInst { +class FPFmtFCMP op, bits<5> cond, dag outs, dag ins, string opnstr, + list pattern = []> + : LAInst.ret, opnstr, pattern> { bits<5> fk; bits<5> fj; bits<3> cd; @@ -95,9 +108,9 @@ // FPFmtBR // -class FPFmtBR opcode, dag outs, dag ins, string opcstr, - string opnstr, list pattern = []> - : LAInst { +class FPFmtBR opcode, dag outs, dag ins, string opnstr, + list pattern = []> + : LAInst.ret, opnstr, pattern> { bits<21> imm21; bits<3> cj; @@ -110,9 +123,9 @@ // FmtFSEL // -class FPFmtFSEL op, dag outs, dag ins, string opcstr, string opnstr, +class FPFmtFSEL op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<3> ca; bits<5> fk; bits<5> fj; @@ -127,9 +140,9 @@ // FPFmtMOV // -class FPFmtMOV op, dag outs, dag ins, string opcstr, string opnstr, +class FPFmtMOV op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<5> src; bits<5> dst; @@ -140,9 +153,9 @@ // FPFmtMEM // -class FPFmtMEM op, dag outs, dag ins, string opcstr, string opnstr, +class FPFmtMEM op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<5> rk; bits<5> rj; bits<5> fd; @@ -158,14 +171,14 @@ //===----------------------------------------------------------------------===// let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { -class FP_ALU_2R op, string opstr, RegisterClass rc> - : FPFmt2R; +class FP_ALU_2R op, RegisterClass rc> + : FPFmt2R; -class FP_ALU_3R op, string opstr, RegisterClass rc> - : FPFmt3R; +class FP_ALU_3R op, RegisterClass rc> + : FPFmt3R; -class FP_ALU_4R op, string opstr, RegisterClass rc> - : FPFmt4R op, RegisterClass rc> + : FPFmt4R; } // hasSideEffects = 0, mayLoad = 0, mayStore = 0 @@ -178,22 +191,22 @@ } let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { -class FP_CMP - : FPFmtFCMP + : FPFmtFCMP; -class FP_CONV op, string opstr, RegisterClass rcd, RegisterClass rcs> - : FPFmt2R; +class FP_CONV op, RegisterClass rcd, RegisterClass rcs> + : FPFmt2R; -class FP_MOV op, string opstr, RegisterClass rcd, RegisterClass rcs> - : FPFmtMOV; +class FP_MOV op, RegisterClass rcd, RegisterClass rcs> + : FPFmtMOV; -class FP_SEL op, string opstr, RegisterClass rc> - : FPFmtFSEL op, RegisterClass rc> + : FPFmtFSEL; -class FP_BRANCH opcode, string opstr> - : FPFmtBR opcode> + : FPFmtBR { let isBranch = 1; let isTerminator = 1; @@ -201,20 +214,20 @@ } // hasSideEffects = 0, mayLoad = 0, mayStore = 0 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in { -class FP_LOAD_3R op, string opstr, RegisterClass rc> - : FPFmtMEM op, RegisterClass rc> + : FPFmtMEM; -class FP_LOAD_2RI12 op, string opstr, RegisterClass rc> - : FPFmt2RI12 op, RegisterClass rc> + : FPFmt2RI12; } // hasSideEffects = 0, mayLoad = 1, mayStore = 0 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in { -class FP_STORE_3R op, string opstr, RegisterClass rc> - : FPFmtMEM op, RegisterClass rc> + : FPFmtMEM; -class FP_STORE_2RI12 op, string opstr, RegisterClass rc> - : FPFmt2RI12 op, RegisterClass rc> + : FPFmt2RI12; } // hasSideEffects = 0, mayLoad = 0, mayStore = 1 diff --git a/llvm/lib/Target/LoongArch/LoongArchInstrFormats.td b/llvm/lib/Target/LoongArch/LoongArchInstrFormats.td --- a/llvm/lib/Target/LoongArch/LoongArchInstrFormats.td +++ b/llvm/lib/Target/LoongArch/LoongArchInstrFormats.td @@ -42,11 +42,15 @@ let isCodeGenOnly = 1; } +class deriveInsnMnemonic { + string ret = !tolower(!subst("@", "_", !subst("_", ".", !subst("__", "@", name)))); +} + // 2R-type // -class Fmt2R op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2R op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<5> rj; bits<5> rd; @@ -57,9 +61,9 @@ // 3R-type // -class Fmt3R op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt3R op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<5> rk; bits<5> rj; bits<5> rd; @@ -72,9 +76,9 @@ // 3RI2-type // -class Fmt3RI2 op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt3RI2 op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<2> imm2; bits<5> rk; bits<5> rj; @@ -89,9 +93,9 @@ // 3RI3-type // -class Fmt3RI3 op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt3RI3 op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<3> imm3; bits<5> rk; bits<5> rj; @@ -106,9 +110,9 @@ // 2RI5-type // -class Fmt2RI5 op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI5 op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<5> imm5; bits<5> rj; bits<5> rd; @@ -121,9 +125,9 @@ // 2RI6-type // -class Fmt2RI6 op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI6 op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<6> imm6; bits<5> rj; bits<5> rd; @@ -136,9 +140,9 @@ // 2RI8-type // -class Fmt2RI8 op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI8 op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<8> imm8; bits<5> rj; bits<5> rd; @@ -151,9 +155,9 @@ // 2RI12-type // -class Fmt2RI12 op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI12 op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<12> imm12; bits<5> rj; bits<5> rd; @@ -166,9 +170,9 @@ // 2RI14-type // -class Fmt2RI14 op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI14 op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<14> imm14; bits<5> rj; bits<5> rd; @@ -181,9 +185,9 @@ // 2RI16-type // -class Fmt2RI16 op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI16 op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<16> imm16; bits<5> rj; bits<5> rd; @@ -196,9 +200,9 @@ // 1RI20-type // -class Fmt1RI20 op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt1RI20 op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<20> imm20; bits<5> rd; @@ -209,9 +213,9 @@ // 1RI21-type // -class Fmt1RI21 op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt1RI21 op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<21> imm21; bits<5> rj; @@ -223,9 +227,9 @@ // I15-type // -class FmtI15 op, dag outs, dag ins, string opcstr, string opnstr, +class FmtI15 op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<15> imm15; let Inst{31-15} = op; @@ -234,9 +238,9 @@ // I26-type // -class FmtI26 op, dag outs, dag ins, string opcstr, string opnstr, +class FmtI26 op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<26> imm26; let Inst{31-26} = op; @@ -246,9 +250,9 @@ // FmtBSTR_W // -class FmtBSTR_W op, dag outs, dag ins, string opcstr, string opnstr, +class FmtBSTR_W op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<5> msbw; bits<5> lsbw; bits<5> rj; @@ -264,9 +268,9 @@ // FmtBSTR_D // -class FmtBSTR_D op, dag outs, dag ins, string opcstr, string opnstr, +class FmtBSTR_D op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<6> msbd; bits<6> lsbd; bits<5> rj; @@ -281,9 +285,9 @@ // FmtASRT // -class FmtASRT op, dag outs, dag ins, string opcstr, string opnstr, +class FmtASRT op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<5> rk; bits<5> rj; @@ -295,9 +299,8 @@ // FmtPRELD // < 0b0010101011 | I12 | rj | I5> -class FmtPRELD pattern = []> - : LAInst { +class FmtPRELD pattern = []> + : LAInst.ret, opnstr, pattern> { bits<12> imm12; bits<5> rj; bits<5> imm5; @@ -310,9 +313,8 @@ // FmtPRELDX // < 0b00111000001011000 | rk | rj | I5> -class FmtPRELDX pattern = []> - : LAInst { +class FmtPRELDX pattern = []> + : LAInst.ret, opnstr, pattern> { bits<5> rk; bits<5> rj; bits<5> imm5; @@ -325,9 +327,9 @@ // FmtCSR // -class FmtCSR op, dag outs, dag ins, string opcstr, string opnstr, +class FmtCSR op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<14> csr_num; bits<5> rd; @@ -339,9 +341,9 @@ // FmtCSRXCHG // -class FmtCSRXCHG op, dag outs, dag ins, string opcstr, string opnstr, +class FmtCSRXCHG op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<14> csr_num; bits<5> rj; bits<5> rd; @@ -354,9 +356,8 @@ // FmtCACOP // <0b0000011000 | I12 | rj | I5> -class FmtCACOP pattern = []> - : LAInst { +class FmtCACOP pattern = []> + : LAInst.ret, opnstr, pattern> { bits<12> imm12; bits<5> rj; bits<5> op; @@ -369,16 +370,15 @@ // FmtIMM32 // -class FmtI32 op, string opstr, list pattern = []> - : LAInst<(outs), (ins), opstr, "", pattern> { +class FmtI32 op, list pattern = []> + : LAInst<(outs), (ins), deriveInsnMnemonic.ret, "", pattern> { let Inst{31-0} = op; } // FmtINVTLB // <0b00000110010010011 | rk | rj | I5> -class FmtINVTLB pattern = []> - : LAInst { +class FmtINVTLB pattern = []> + : LAInst.ret, opnstr, pattern> { bits<5> rk; bits<5> rj; bits<5> op; @@ -391,9 +391,8 @@ // FmtLDPTE // <0b00000110010001 | seq | rj | 00000> -class FmtLDPTE pattern = []> - : LAInst { +class FmtLDPTE pattern = []> + : LAInst.ret, opnstr, pattern> { bits<8> seq; bits<5> rj; diff --git a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td --- a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td +++ b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td @@ -533,224 +533,223 @@ //===----------------------------------------------------------------------===// let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { -class ALU_3R op, string opstr> - : Fmt3R; -class ALU_2R op, string opstr> - : Fmt2R; +class ALU_3R op> + : Fmt3R; +class ALU_2R op> + : Fmt2R; -class ALU_3RI2 op, string opstr, Operand ImmOpnd> - : Fmt3RI2 op, Operand ImmOpnd> + : Fmt3RI2; -class ALU_3RI3 op, string opstr, Operand ImmOpnd> - : Fmt3RI3 op, Operand ImmOpnd> + : Fmt3RI3; -class ALU_2RI5 op, string opstr, Operand ImmOpnd> - : Fmt2RI5 op, Operand ImmOpnd> + : Fmt2RI5; -class ALU_2RI6 op, string opstr, Operand ImmOpnd> - : Fmt2RI6 op, Operand ImmOpnd> + : Fmt2RI6; -class ALU_2RI12 op, string opstr, Operand ImmOpnd> - : Fmt2RI12 op, Operand ImmOpnd> + : Fmt2RI12; -class ALU_2RI16 op, string opstr, Operand ImmOpnd> - : Fmt2RI16 op, Operand ImmOpnd> + : Fmt2RI16; -class ALU_1RI20 op, string opstr, Operand ImmOpnd> - : Fmt1RI20; +class ALU_1RI20 op, Operand ImmOpnd> + : Fmt1RI20; } // hasSideEffects = 0, mayLoad = 0, mayStore = 0 let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in -class MISC_I15 op, string opstr> - : FmtI15; +class MISC_I15 op> + : FmtI15; let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in -class RDTIME_2R op, string opstr> - : Fmt2R; +class RDTIME_2R op> + : Fmt2R; let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { -class BrCC_2RI16 op, string opstr> - : Fmt2RI16 op> + : Fmt2RI16 { let isBranch = 1; let isTerminator = 1; } -class BrCCZ_1RI21 op, string opstr> - : Fmt1RI21 op> + : Fmt1RI21 { let isBranch = 1; let isTerminator = 1; } -class Br_I26 op, string opstr> - : FmtI26 { +class Br_I26 op> + : FmtI26 { let isBranch = 1; let isTerminator = 1; } } // hasSideEffects = 0, mayLoad = 0, mayStore = 0 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in { -class LOAD_3R op, string opstr> - : Fmt3R; -class LOAD_2RI12 op, string opstr> - : Fmt2RI12 op> + : Fmt3R; +class LOAD_2RI12 op> + : Fmt2RI12; -class LOAD_2RI14 op, string opstr> - : Fmt2RI14 op> + : Fmt2RI14; } // hasSideEffects = 0, mayLoad = 1, mayStore = 0 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in { -class STORE_3R op, string opstr> - : Fmt3R op> + : Fmt3R; -class STORE_2RI12 op, string opstr> - : Fmt2RI12 op> + : Fmt2RI12; -class STORE_2RI14 op, string opstr> - : Fmt2RI14 op> + : Fmt2RI14; } // hasSideEffects = 0, mayLoad = 0, mayStore = 1 let hasSideEffects = 0, mayLoad = 1, mayStore = 1, Constraints = "@earlyclobber $rd" in -class AM_3R op, string opstr> - : Fmt3R op> + : Fmt3R; let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in -class LLBase op, string opstr> - : Fmt2RI14 op> + : Fmt2RI14; let hasSideEffects = 0, mayLoad = 0, mayStore = 1, Constraints = "$rd = $dst" in -class SCBase op, string opstr> +class SCBase op> : Fmt2RI14; + "$rd, $rj, $imm14">; let hasSideEffects = 1 in -class IOCSRRD op, string opstr> - : Fmt2R; +class IOCSRRD op> + : Fmt2R; let hasSideEffects = 1 in -class IOCSRWR op, string opstr> - : Fmt2R; +class IOCSRWR op> + : Fmt2R; //===----------------------------------------------------------------------===// // Basic Integer Instructions //===----------------------------------------------------------------------===// // Arithmetic Operation Instructions -def ADD_W : ALU_3R<0b00000000000100000, "add.w">; -def SUB_W : ALU_3R<0b00000000000100010, "sub.w">; -def ADDI_W : ALU_2RI12<0b0000001010, "addi.w", simm12_addlike>; -def ALSL_W : ALU_3RI2<0b000000000000010, "alsl.w", uimm2_plus1>; -def LU12I_W : ALU_1RI20<0b0001010, "lu12i.w", simm20_lu12iw>; -def SLT : ALU_3R<0b00000000000100100, "slt">; -def SLTU : ALU_3R<0b00000000000100101, "sltu">; -def SLTI : ALU_2RI12<0b0000001000, "slti", simm12>; -def SLTUI : ALU_2RI12<0b0000001001, "sltui", simm12>; -def PCADDI : ALU_1RI20<0b0001100, "pcaddi", simm20>; -def PCADDU12I : ALU_1RI20<0b0001110, "pcaddu12i", simm20>; -def PCALAU12I : ALU_1RI20<0b0001101, "pcalau12i", simm20_pcalau12i>; -def AND : ALU_3R<0b00000000000101001, "and">; -def OR : ALU_3R<0b00000000000101010, "or">; -def NOR : ALU_3R<0b00000000000101000, "nor">; -def XOR : ALU_3R<0b00000000000101011, "xor">; -def ANDN : ALU_3R<0b00000000000101101, "andn">; -def ORN : ALU_3R<0b00000000000101100, "orn">; -def ANDI : ALU_2RI12<0b0000001101, "andi", uimm12>; -def ORI : ALU_2RI12<0b0000001110, "ori", uimm12_ori>; -def XORI : ALU_2RI12<0b0000001111, "xori", uimm12>; -def MUL_W : ALU_3R<0b00000000000111000, "mul.w">; -def MULH_W : ALU_3R<0b00000000000111001, "mulh.w">; -def MULH_WU : ALU_3R<0b00000000000111010, "mulh.wu">; +def ADD_W : ALU_3R<0b00000000000100000>; +def SUB_W : ALU_3R<0b00000000000100010>; +def ADDI_W : ALU_2RI12<0b0000001010, simm12_addlike>; +def ALSL_W : ALU_3RI2<0b000000000000010, uimm2_plus1>; +def LU12I_W : ALU_1RI20<0b0001010, simm20_lu12iw>; +def SLT : ALU_3R<0b00000000000100100>; +def SLTU : ALU_3R<0b00000000000100101>; +def SLTI : ALU_2RI12<0b0000001000, simm12>; +def SLTUI : ALU_2RI12<0b0000001001, simm12>; +def PCADDI : ALU_1RI20<0b0001100, simm20>; +def PCADDU12I : ALU_1RI20<0b0001110, simm20>; +def PCALAU12I : ALU_1RI20<0b0001101, simm20_pcalau12i>; +def AND : ALU_3R<0b00000000000101001>; +def OR : ALU_3R<0b00000000000101010>; +def NOR : ALU_3R<0b00000000000101000>; +def XOR : ALU_3R<0b00000000000101011>; +def ANDN : ALU_3R<0b00000000000101101>; +def ORN : ALU_3R<0b00000000000101100>; +def ANDI : ALU_2RI12<0b0000001101, uimm12>; +def ORI : ALU_2RI12<0b0000001110, uimm12_ori>; +def XORI : ALU_2RI12<0b0000001111, uimm12>; +def MUL_W : ALU_3R<0b00000000000111000>; +def MULH_W : ALU_3R<0b00000000000111001>; +def MULH_WU : ALU_3R<0b00000000000111010>; let usesCustomInserter = true in { -def DIV_W : ALU_3R<0b00000000001000000, "div.w">; -def MOD_W : ALU_3R<0b00000000001000001, "mod.w">; -def DIV_WU : ALU_3R<0b00000000001000010, "div.wu">; -def MOD_WU : ALU_3R<0b00000000001000011, "mod.wu">; +def DIV_W : ALU_3R<0b00000000001000000>; +def MOD_W : ALU_3R<0b00000000001000001>; +def DIV_WU : ALU_3R<0b00000000001000010>; +def MOD_WU : ALU_3R<0b00000000001000011>; } // usesCustomInserter = true // Bit-shift Instructions -def SLL_W : ALU_3R<0b00000000000101110, "sll.w">; -def SRL_W : ALU_3R<0b00000000000101111, "srl.w">; -def SRA_W : ALU_3R<0b00000000000110000, "sra.w">; -def ROTR_W : ALU_3R<0b00000000000110110, "rotr.w">; +def SLL_W : ALU_3R<0b00000000000101110>; +def SRL_W : ALU_3R<0b00000000000101111>; +def SRA_W : ALU_3R<0b00000000000110000>; +def ROTR_W : ALU_3R<0b00000000000110110>; -def SLLI_W : ALU_2RI5<0b00000000010000001, "slli.w", uimm5>; -def SRLI_W : ALU_2RI5<0b00000000010001001, "srli.w", uimm5>; -def SRAI_W : ALU_2RI5<0b00000000010010001, "srai.w", uimm5>; -def ROTRI_W : ALU_2RI5<0b00000000010011001, "rotri.w", uimm5>; +def SLLI_W : ALU_2RI5<0b00000000010000001, uimm5>; +def SRLI_W : ALU_2RI5<0b00000000010001001, uimm5>; +def SRAI_W : ALU_2RI5<0b00000000010010001, uimm5>; +def ROTRI_W : ALU_2RI5<0b00000000010011001, uimm5>; // Bit-manipulation Instructions -def EXT_W_B : ALU_2R<0b0000000000000000010111, "ext.w.b">; -def EXT_W_H : ALU_2R<0b0000000000000000010110, "ext.w.h">; -def CLO_W : ALU_2R<0b0000000000000000000100, "clo.w">; -def CLZ_W : ALU_2R<0b0000000000000000000101, "clz.w">; -def CTO_W : ALU_2R<0b0000000000000000000110, "cto.w">; -def CTZ_W : ALU_2R<0b0000000000000000000111, "ctz.w">; -def BYTEPICK_W : ALU_3RI2<0b000000000000100, "bytepick.w", uimm2>; -def REVB_2H : ALU_2R<0b0000000000000000001100, "revb.2h">; -def BITREV_4B : ALU_2R<0b0000000000000000010010, "bitrev.4b">; -def BITREV_W : ALU_2R<0b0000000000000000010100, "bitrev.w">; +def EXT_W_B : ALU_2R<0b0000000000000000010111>; +def EXT_W_H : ALU_2R<0b0000000000000000010110>; +def CLO_W : ALU_2R<0b0000000000000000000100>; +def CLZ_W : ALU_2R<0b0000000000000000000101>; +def CTO_W : ALU_2R<0b0000000000000000000110>; +def CTZ_W : ALU_2R<0b0000000000000000000111>; +def BYTEPICK_W : ALU_3RI2<0b000000000000100, uimm2>; +def REVB_2H : ALU_2R<0b0000000000000000001100>; +def BITREV_4B : ALU_2R<0b0000000000000000010010>; +def BITREV_W : ALU_2R<0b0000000000000000010100>; let Constraints = "$rd = $dst" in { def BSTRINS_W : FmtBSTR_W<0b000000000110, (outs GPR:$dst), (ins GPR:$rd, GPR:$rj, uimm5:$msbw, uimm5:$lsbw), - "bstrins.w", "$rd, $rj, $msbw, $lsbw">; + "$rd, $rj, $msbw, $lsbw">; } def BSTRPICK_W : FmtBSTR_W<0b000000000111, (outs GPR:$rd), (ins GPR:$rj, uimm5:$msbw, uimm5:$lsbw), - "bstrpick.w", "$rd, $rj, $msbw, $lsbw">; -def MASKEQZ : ALU_3R<0b00000000000100110, "maskeqz">; -def MASKNEZ : ALU_3R<0b00000000000100111, "masknez">; + "$rd, $rj, $msbw, $lsbw">; +def MASKEQZ : ALU_3R<0b00000000000100110>; +def MASKNEZ : ALU_3R<0b00000000000100111>; // Branch Instructions -def BEQ : BrCC_2RI16<0b010110, "beq">; -def BNE : BrCC_2RI16<0b010111, "bne">; -def BLT : BrCC_2RI16<0b011000, "blt">; -def BGE : BrCC_2RI16<0b011001, "bge">; -def BLTU : BrCC_2RI16<0b011010, "bltu">; -def BGEU : BrCC_2RI16<0b011011, "bgeu">; -def BEQZ : BrCCZ_1RI21<0b010000, "beqz">; -def BNEZ : BrCCZ_1RI21<0b010001, "bnez">; -def B : Br_I26<0b010100, "b">; +def BEQ : BrCC_2RI16<0b010110>; +def BNE : BrCC_2RI16<0b010111>; +def BLT : BrCC_2RI16<0b011000>; +def BGE : BrCC_2RI16<0b011001>; +def BLTU : BrCC_2RI16<0b011010>; +def BGEU : BrCC_2RI16<0b011011>; +def BEQZ : BrCCZ_1RI21<0b010000>; +def BNEZ : BrCCZ_1RI21<0b010001>; +def B : Br_I26<0b010100>; let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCall = 1, Defs=[R1] in -def BL : FmtI26<0b010101, (outs), (ins simm26_symbol:$imm26), "bl", "$imm26">; +def BL : FmtI26<0b010101, (outs), (ins simm26_symbol:$imm26), "$imm26">; let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in def JIRL : Fmt2RI16<0b010011, (outs GPR:$rd), - (ins GPR:$rj, simm16_lsl2:$imm16), "jirl", - "$rd, $rj, $imm16">; + (ins GPR:$rj, simm16_lsl2:$imm16), "$rd, $rj, $imm16">; // Common Memory Access Instructions -def LD_B : LOAD_2RI12<0b0010100000, "ld.b">; -def LD_H : LOAD_2RI12<0b0010100001, "ld.h">; -def LD_W : LOAD_2RI12<0b0010100010, "ld.w">; -def LD_BU : LOAD_2RI12<0b0010101000, "ld.bu">; -def LD_HU : LOAD_2RI12<0b0010101001, "ld.hu">; -def ST_B : STORE_2RI12<0b0010100100, "st.b">; -def ST_H : STORE_2RI12<0b0010100101, "st.h">; -def ST_W : STORE_2RI12<0b0010100110, "st.w">; +def LD_B : LOAD_2RI12<0b0010100000>; +def LD_H : LOAD_2RI12<0b0010100001>; +def LD_W : LOAD_2RI12<0b0010100010>; +def LD_BU : LOAD_2RI12<0b0010101000>; +def LD_HU : LOAD_2RI12<0b0010101001>; +def ST_B : STORE_2RI12<0b0010100100>; +def ST_H : STORE_2RI12<0b0010100101>; +def ST_W : STORE_2RI12<0b0010100110>; let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in -def PRELD : FmtPRELD<(outs), (ins uimm5:$imm5, GPR:$rj, simm12:$imm12), "preld", +def PRELD : FmtPRELD<(outs), (ins uimm5:$imm5, GPR:$rj, simm12:$imm12), "$imm5, $rj, $imm12">; // Atomic Memory Access Instructions -def LL_W : LLBase<0b00100000, "ll.w">; -def SC_W : SCBase<0b00100001, "sc.w">; +def LL_W : LLBase<0b00100000>; +def SC_W : SCBase<0b00100001>; // Barrier Instructions -def DBAR : MISC_I15<0b00111000011100100, "dbar">; -def IBAR : MISC_I15<0b00111000011100101, "ibar">; +def DBAR : MISC_I15<0b00111000011100100>; +def IBAR : MISC_I15<0b00111000011100101>; // Other Miscellaneous Instructions -def SYSCALL : MISC_I15<0b00000000001010110, "syscall">; -def BREAK : MISC_I15<0b00000000001010100, "break">; -def RDTIMEL_W : RDTIME_2R<0b0000000000000000011000, "rdtimel.w">; -def RDTIMEH_W : RDTIME_2R<0b0000000000000000011001, "rdtimeh.w">; -def CPUCFG : ALU_2R<0b0000000000000000011011, "cpucfg">; +def SYSCALL : MISC_I15<0b00000000001010110>; +def BREAK : MISC_I15<0b00000000001010100>; +def RDTIMEL_W : RDTIME_2R<0b0000000000000000011000>; +def RDTIMEH_W : RDTIME_2R<0b0000000000000000011001>; +def CPUCFG : ALU_2R<0b0000000000000000011011>; // Cache Maintenance Instructions -def CACOP : FmtCACOP<(outs), (ins uimm5:$op, GPR:$rj, simm12:$imm12), "cacop", +def CACOP : FmtCACOP<(outs), (ins uimm5:$op, GPR:$rj, simm12:$imm12), "$op, $rj, $imm12">; /// LA64 instructions @@ -758,161 +757,161 @@ let Predicates = [IsLA64] in { // Arithmetic Operation Instructions for 64-bits -def ADD_D : ALU_3R<0b00000000000100001, "add.d">; -def SUB_D : ALU_3R<0b00000000000100011, "sub.d">; -def ADDI_D : ALU_2RI12<0b0000001011, "addi.d", simm12_addlike>; -def ADDU16I_D : ALU_2RI16<0b000100, "addu16i.d", simm16>; -def ALSL_WU : ALU_3RI2<0b000000000000011, "alsl.wu", uimm2_plus1>; -def ALSL_D : ALU_3RI2<0b000000000010110, "alsl.d", uimm2_plus1>; +def ADD_D : ALU_3R<0b00000000000100001>; +def SUB_D : ALU_3R<0b00000000000100011>; +def ADDI_D : ALU_2RI12<0b0000001011, simm12_addlike>; +def ADDU16I_D : ALU_2RI16<0b000100, simm16>; +def ALSL_WU : ALU_3RI2<0b000000000000011, uimm2_plus1>; +def ALSL_D : ALU_3RI2<0b000000000010110, uimm2_plus1>; let Constraints = "$rd = $dst" in { let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in def LU32I_D : Fmt1RI20<0b0001011, (outs GPR:$dst), - (ins GPR:$rd, simm20_lu32id:$imm20), "lu32i.d", + (ins GPR:$rd, simm20_lu32id:$imm20), "$rd, $imm20">; } -def LU52I_D : ALU_2RI12<0b0000001100, "lu52i.d", simm12_lu52id>; -def PCADDU18I : ALU_1RI20<0b0001111, "pcaddu18i", simm20>; -def MUL_D : ALU_3R<0b00000000000111011, "mul.d">; -def MULH_D : ALU_3R<0b00000000000111100, "mulh.d">; -def MULH_DU : ALU_3R<0b00000000000111101, "mulh.du">; -def MULW_D_W : ALU_3R<0b00000000000111110, "mulw.d.w">; -def MULW_D_WU : ALU_3R<0b00000000000111111, "mulw.d.wu">; +def LU52I_D : ALU_2RI12<0b0000001100, simm12_lu52id>; +def PCADDU18I : ALU_1RI20<0b0001111, simm20>; +def MUL_D : ALU_3R<0b00000000000111011>; +def MULH_D : ALU_3R<0b00000000000111100>; +def MULH_DU : ALU_3R<0b00000000000111101>; +def MULW_D_W : ALU_3R<0b00000000000111110>; +def MULW_D_WU : ALU_3R<0b00000000000111111>; let usesCustomInserter = true in { -def DIV_D : ALU_3R<0b00000000001000100, "div.d">; -def MOD_D : ALU_3R<0b00000000001000101, "mod.d">; -def DIV_DU : ALU_3R<0b00000000001000110, "div.du">; -def MOD_DU : ALU_3R<0b00000000001000111, "mod.du">; +def DIV_D : ALU_3R<0b00000000001000100>; +def MOD_D : ALU_3R<0b00000000001000101>; +def DIV_DU : ALU_3R<0b00000000001000110>; +def MOD_DU : ALU_3R<0b00000000001000111>; } // usesCustomInserter = true // Bit-shift Instructions for 64-bits -def SLL_D : ALU_3R<0b00000000000110001, "sll.d">; -def SRL_D : ALU_3R<0b00000000000110010, "srl.d">; -def SRA_D : ALU_3R<0b00000000000110011, "sra.d">; -def ROTR_D : ALU_3R<0b00000000000110111, "rotr.d">; -def SLLI_D : ALU_2RI6<0b0000000001000001, "slli.d", uimm6>; -def SRLI_D : ALU_2RI6<0b0000000001000101, "srli.d", uimm6>; -def SRAI_D : ALU_2RI6<0b0000000001001001, "srai.d", uimm6>; -def ROTRI_D : ALU_2RI6<0b0000000001001101, "rotri.d", uimm6>; +def SLL_D : ALU_3R<0b00000000000110001>; +def SRL_D : ALU_3R<0b00000000000110010>; +def SRA_D : ALU_3R<0b00000000000110011>; +def ROTR_D : ALU_3R<0b00000000000110111>; +def SLLI_D : ALU_2RI6<0b0000000001000001, uimm6>; +def SRLI_D : ALU_2RI6<0b0000000001000101, uimm6>; +def SRAI_D : ALU_2RI6<0b0000000001001001, uimm6>; +def ROTRI_D : ALU_2RI6<0b0000000001001101, uimm6>; // Bit-manipulation Instructions for 64-bits -def CLO_D : ALU_2R<0b0000000000000000001000, "clo.d">; -def CLZ_D : ALU_2R<0b0000000000000000001001, "clz.d">; -def CTO_D : ALU_2R<0b0000000000000000001010, "cto.d">; -def CTZ_D : ALU_2R<0b0000000000000000001011, "ctz.d">; -def BYTEPICK_D : ALU_3RI3<0b00000000000011, "bytepick.d", uimm3>; -def REVB_4H : ALU_2R<0b0000000000000000001101, "revb.4h">; -def REVB_2W : ALU_2R<0b0000000000000000001110, "revb.2w">; -def REVB_D : ALU_2R<0b0000000000000000001111, "revb.d">; -def REVH_2W : ALU_2R<0b0000000000000000010000, "revh.2w">; -def REVH_D : ALU_2R<0b0000000000000000010001, "revh.d">; -def BITREV_8B : ALU_2R<0b0000000000000000010011, "bitrev.8b">; -def BITREV_D : ALU_2R<0b0000000000000000010101, "bitrev.d">; +def CLO_D : ALU_2R<0b0000000000000000001000>; +def CLZ_D : ALU_2R<0b0000000000000000001001>; +def CTO_D : ALU_2R<0b0000000000000000001010>; +def CTZ_D : ALU_2R<0b0000000000000000001011>; +def BYTEPICK_D : ALU_3RI3<0b00000000000011, uimm3>; +def REVB_4H : ALU_2R<0b0000000000000000001101>; +def REVB_2W : ALU_2R<0b0000000000000000001110>; +def REVB_D : ALU_2R<0b0000000000000000001111>; +def REVH_2W : ALU_2R<0b0000000000000000010000>; +def REVH_D : ALU_2R<0b0000000000000000010001>; +def BITREV_8B : ALU_2R<0b0000000000000000010011>; +def BITREV_D : ALU_2R<0b0000000000000000010101>; let Constraints = "$rd = $dst" in { def BSTRINS_D : FmtBSTR_D<0b0000000010, (outs GPR:$dst), (ins GPR:$rd, GPR:$rj, uimm6:$msbd, uimm6:$lsbd), - "bstrins.d", "$rd, $rj, $msbd, $lsbd">; + "$rd, $rj, $msbd, $lsbd">; } def BSTRPICK_D : FmtBSTR_D<0b0000000011, (outs GPR:$rd), (ins GPR:$rj, uimm6:$msbd, uimm6:$lsbd), - "bstrpick.d", "$rd, $rj, $msbd, $lsbd">; + "$rd, $rj, $msbd, $lsbd">; // Common Memory Access Instructions for 64-bits -def LD_WU : LOAD_2RI12<0b0010101010, "ld.wu">; -def LD_D : LOAD_2RI12<0b0010100011, "ld.d">; -def ST_D : STORE_2RI12<0b0010100111, "st.d">; -def LDX_B : LOAD_3R<0b00111000000000000, "ldx.b">; -def LDX_H : LOAD_3R<0b00111000000001000, "ldx.h">; -def LDX_W : LOAD_3R<0b00111000000010000, "ldx.w">; -def LDX_D : LOAD_3R<0b00111000000011000, "ldx.d">; -def LDX_BU : LOAD_3R<0b00111000001000000, "ldx.bu">; -def LDX_HU : LOAD_3R<0b00111000001001000, "ldx.hu">; -def LDX_WU : LOAD_3R<0b00111000001010000, "ldx.wu">; -def STX_B : STORE_3R<0b00111000000100000, "stx.b">; -def STX_H : STORE_3R<0b00111000000101000, "stx.h">; -def STX_W : STORE_3R<0b00111000000110000, "stx.w">; -def STX_D : STORE_3R<0b00111000000111000, "stx.d">; -def LDPTR_W : LOAD_2RI14<0b00100100, "ldptr.w">; -def LDPTR_D : LOAD_2RI14<0b00100110, "ldptr.d">; -def STPTR_W : STORE_2RI14<0b00100101, "stptr.w">; -def STPTR_D : STORE_2RI14<0b00100111, "stptr.d">; +def LD_WU : LOAD_2RI12<0b0010101010>; +def LD_D : LOAD_2RI12<0b0010100011>; +def ST_D : STORE_2RI12<0b0010100111>; +def LDX_B : LOAD_3R<0b00111000000000000>; +def LDX_H : LOAD_3R<0b00111000000001000>; +def LDX_W : LOAD_3R<0b00111000000010000>; +def LDX_D : LOAD_3R<0b00111000000011000>; +def LDX_BU : LOAD_3R<0b00111000001000000>; +def LDX_HU : LOAD_3R<0b00111000001001000>; +def LDX_WU : LOAD_3R<0b00111000001010000>; +def STX_B : STORE_3R<0b00111000000100000>; +def STX_H : STORE_3R<0b00111000000101000>; +def STX_W : STORE_3R<0b00111000000110000>; +def STX_D : STORE_3R<0b00111000000111000>; +def LDPTR_W : LOAD_2RI14<0b00100100>; +def LDPTR_D : LOAD_2RI14<0b00100110>; +def STPTR_W : STORE_2RI14<0b00100101>; +def STPTR_D : STORE_2RI14<0b00100111>; let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in -def PRELDX : FmtPRELDX<(outs), (ins uimm5:$imm5, GPR:$rj, GPR:$rk), "preldx", +def PRELDX : FmtPRELDX<(outs), (ins uimm5:$imm5, GPR:$rj, GPR:$rk), "$imm5, $rj, $rk">; // Bound Check Memory Access Instructions -def LDGT_B : LOAD_3R<0b00111000011110000, "ldgt.b">; -def LDGT_H : LOAD_3R<0b00111000011110001, "ldgt.h">; -def LDGT_W : LOAD_3R<0b00111000011110010, "ldgt.w">; -def LDGT_D : LOAD_3R<0b00111000011110011, "ldgt.d">; -def LDLE_B : LOAD_3R<0b00111000011110100, "ldle.b">; -def LDLE_H : LOAD_3R<0b00111000011110101, "ldle.h">; -def LDLE_W : LOAD_3R<0b00111000011110110, "ldle.w">; -def LDLE_D : LOAD_3R<0b00111000011110111, "ldle.d">; -def STGT_B : STORE_3R<0b00111000011111000, "stgt.b">; -def STGT_H : STORE_3R<0b00111000011111001, "stgt.h">; -def STGT_W : STORE_3R<0b00111000011111010, "stgt.w">; -def STGT_D : STORE_3R<0b00111000011111011, "stgt.d">; -def STLE_B : STORE_3R<0b00111000011111100, "stle.b">; -def STLE_H : STORE_3R<0b00111000011111101, "stle.h">; -def STLE_W : STORE_3R<0b00111000011111110, "stle.w">; -def STLE_D : STORE_3R<0b00111000011111111, "stle.d">; +def LDGT_B : LOAD_3R<0b00111000011110000>; +def LDGT_H : LOAD_3R<0b00111000011110001>; +def LDGT_W : LOAD_3R<0b00111000011110010>; +def LDGT_D : LOAD_3R<0b00111000011110011>; +def LDLE_B : LOAD_3R<0b00111000011110100>; +def LDLE_H : LOAD_3R<0b00111000011110101>; +def LDLE_W : LOAD_3R<0b00111000011110110>; +def LDLE_D : LOAD_3R<0b00111000011110111>; +def STGT_B : STORE_3R<0b00111000011111000>; +def STGT_H : STORE_3R<0b00111000011111001>; +def STGT_W : STORE_3R<0b00111000011111010>; +def STGT_D : STORE_3R<0b00111000011111011>; +def STLE_B : STORE_3R<0b00111000011111100>; +def STLE_H : STORE_3R<0b00111000011111101>; +def STLE_W : STORE_3R<0b00111000011111110>; +def STLE_D : STORE_3R<0b00111000011111111>; // Atomic Memory Access Instructions for 64-bits -def AMSWAP_W : AM_3R<0b00111000011000000, "amswap.w">; -def AMSWAP_D : AM_3R<0b00111000011000001, "amswap.d">; -def AMADD_W : AM_3R<0b00111000011000010, "amadd.w">; -def AMADD_D : AM_3R<0b00111000011000011, "amadd.d">; -def AMAND_W : AM_3R<0b00111000011000100, "amand.w">; -def AMAND_D : AM_3R<0b00111000011000101, "amand.d">; -def AMOR_W : AM_3R<0b00111000011000110, "amor.w">; -def AMOR_D : AM_3R<0b00111000011000111, "amor.d">; -def AMXOR_W : AM_3R<0b00111000011001000, "amxor.w">; -def AMXOR_D : AM_3R<0b00111000011001001, "amxor.d">; -def AMMAX_W : AM_3R<0b00111000011001010, "ammax.w">; -def AMMAX_D : AM_3R<0b00111000011001011, "ammax.d">; -def AMMIN_W : AM_3R<0b00111000011001100, "ammin.w">; -def AMMIN_D : AM_3R<0b00111000011001101, "ammin.d">; -def AMMAX_WU : AM_3R<0b00111000011001110, "ammax.wu">; -def AMMAX_DU : AM_3R<0b00111000011001111, "ammax.du">; -def AMMIN_WU : AM_3R<0b00111000011010000, "ammin.wu">; -def AMMIN_DU : AM_3R<0b00111000011010001, "ammin.du">; -def AMSWAP_DB_W : AM_3R<0b00111000011010010, "amswap_db.w">; -def AMSWAP_DB_D : AM_3R<0b00111000011010011, "amswap_db.d">; -def AMADD_DB_W : AM_3R<0b00111000011010100, "amadd_db.w">; -def AMADD_DB_D : AM_3R<0b00111000011010101, "amadd_db.d">; -def AMAND_DB_W : AM_3R<0b00111000011010110, "amand_db.w">; -def AMAND_DB_D : AM_3R<0b00111000011010111, "amand_db.d">; -def AMOR_DB_W : AM_3R<0b00111000011011000, "amor_db.w">; -def AMOR_DB_D : AM_3R<0b00111000011011001, "amor_db.d">; -def AMXOR_DB_W : AM_3R<0b00111000011011010, "amxor_db.w">; -def AMXOR_DB_D : AM_3R<0b00111000011011011, "amxor_db.d">; -def AMMAX_DB_W : AM_3R<0b00111000011011100, "ammax_db.w">; -def AMMAX_DB_D : AM_3R<0b00111000011011101, "ammax_db.d">; -def AMMIN_DB_W : AM_3R<0b00111000011011110, "ammin_db.w">; -def AMMIN_DB_D : AM_3R<0b00111000011011111, "ammin_db.d">; -def AMMAX_DB_WU : AM_3R<0b00111000011100000, "ammax_db.wu">; -def AMMAX_DB_DU : AM_3R<0b00111000011100001, "ammax_db.du">; -def AMMIN_DB_WU : AM_3R<0b00111000011100010, "ammin_db.wu">; -def AMMIN_DB_DU : AM_3R<0b00111000011100011, "ammin_db.du">; -def LL_D : LLBase<0b00100010, "ll.d">; -def SC_D : SCBase<0b00100011, "sc.d">; +def AMSWAP_W : AM_3R<0b00111000011000000>; +def AMSWAP_D : AM_3R<0b00111000011000001>; +def AMADD_W : AM_3R<0b00111000011000010>; +def AMADD_D : AM_3R<0b00111000011000011>; +def AMAND_W : AM_3R<0b00111000011000100>; +def AMAND_D : AM_3R<0b00111000011000101>; +def AMOR_W : AM_3R<0b00111000011000110>; +def AMOR_D : AM_3R<0b00111000011000111>; +def AMXOR_W : AM_3R<0b00111000011001000>; +def AMXOR_D : AM_3R<0b00111000011001001>; +def AMMAX_W : AM_3R<0b00111000011001010>; +def AMMAX_D : AM_3R<0b00111000011001011>; +def AMMIN_W : AM_3R<0b00111000011001100>; +def AMMIN_D : AM_3R<0b00111000011001101>; +def AMMAX_WU : AM_3R<0b00111000011001110>; +def AMMAX_DU : AM_3R<0b00111000011001111>; +def AMMIN_WU : AM_3R<0b00111000011010000>; +def AMMIN_DU : AM_3R<0b00111000011010001>; +def AMSWAP__DB_W : AM_3R<0b00111000011010010>; +def AMSWAP__DB_D : AM_3R<0b00111000011010011>; +def AMADD__DB_W : AM_3R<0b00111000011010100>; +def AMADD__DB_D : AM_3R<0b00111000011010101>; +def AMAND__DB_W : AM_3R<0b00111000011010110>; +def AMAND__DB_D : AM_3R<0b00111000011010111>; +def AMOR__DB_W : AM_3R<0b00111000011011000>; +def AMOR__DB_D : AM_3R<0b00111000011011001>; +def AMXOR__DB_W : AM_3R<0b00111000011011010>; +def AMXOR__DB_D : AM_3R<0b00111000011011011>; +def AMMAX__DB_W : AM_3R<0b00111000011011100>; +def AMMAX__DB_D : AM_3R<0b00111000011011101>; +def AMMIN__DB_W : AM_3R<0b00111000011011110>; +def AMMIN__DB_D : AM_3R<0b00111000011011111>; +def AMMAX__DB_WU : AM_3R<0b00111000011100000>; +def AMMAX__DB_DU : AM_3R<0b00111000011100001>; +def AMMIN__DB_WU : AM_3R<0b00111000011100010>; +def AMMIN__DB_DU : AM_3R<0b00111000011100011>; +def LL_D : LLBase<0b00100010>; +def SC_D : SCBase<0b00100011>; // CRC Check Instructions -def CRC_W_B_W : ALU_3R<0b00000000001001000, "crc.w.b.w">; -def CRC_W_H_W : ALU_3R<0b00000000001001001, "crc.w.h.w">; -def CRC_W_W_W : ALU_3R<0b00000000001001010, "crc.w.w.w">; -def CRC_W_D_W : ALU_3R<0b00000000001001011, "crc.w.d.w">; -def CRCC_W_B_W : ALU_3R<0b00000000001001100, "crcc.w.b.w">; -def CRCC_W_H_W : ALU_3R<0b00000000001001101, "crcc.w.h.w">; -def CRCC_W_W_W : ALU_3R<0b00000000001001110, "crcc.w.w.w">; -def CRCC_W_D_W : ALU_3R<0b00000000001001111, "crcc.w.d.w">; +def CRC_W_B_W : ALU_3R<0b00000000001001000>; +def CRC_W_H_W : ALU_3R<0b00000000001001001>; +def CRC_W_W_W : ALU_3R<0b00000000001001010>; +def CRC_W_D_W : ALU_3R<0b00000000001001011>; +def CRCC_W_B_W : ALU_3R<0b00000000001001100>; +def CRCC_W_H_W : ALU_3R<0b00000000001001101>; +def CRCC_W_W_W : ALU_3R<0b00000000001001110>; +def CRCC_W_D_W : ALU_3R<0b00000000001001111>; // Other Miscellaneous Instructions for 64-bits def ASRTLE_D : FmtASRT<0b00000000000000010, (outs), (ins GPR:$rj, GPR:$rk), - "asrtle.d", "$rj, $rk">; + "$rj, $rk">; def ASRTGT_D : FmtASRT<0b00000000000000011, (outs), (ins GPR:$rj, GPR:$rk), - "asrtgt.d", "$rj, $rk">; -def RDTIME_D : RDTIME_2R<0b0000000000000000011010, "rdtime.d">; + "$rj, $rk">; +def RDTIME_D : RDTIME_2R<0b0000000000000000011010>; } // Predicates = [IsLA64] //===----------------------------------------------------------------------===// @@ -1631,7 +1630,7 @@ def PseudoAtomicStoreW : Pseudo<(outs GPR:$dst), (ins GPR:$rj, GPR:$rk)>, - PseudoInstExpansion<(AMSWAP_DB_W R0, GPR:$rk, GPRMemAtomic:$rj)>; + PseudoInstExpansion<(AMSWAP__DB_W R0, GPR:$rk, GPRMemAtomic:$rj)>; def : Pat<(atomic_store_release_seqcst_32 GPR:$rj, GPR:$rk), (PseudoAtomicStoreW GPR:$rj, GPR:$rk)>; @@ -1639,7 +1638,7 @@ let Predicates = [IsLA64] in { def PseudoAtomicStoreD : Pseudo<(outs GPR:$dst), (ins GPR:$rj, GPR:$rk)>, - PseudoInstExpansion<(AMSWAP_DB_D R0, GPR:$rk, GPRMemAtomic:$rj)>; + PseudoInstExpansion<(AMSWAP__DB_D R0, GPR:$rk, GPRMemAtomic:$rj)>; def : Pat<(atomic_store_release_seqcst_64 GPR:$rj, GPR:$rk), (PseudoAtomicStoreD GPR:$rj, GPR:$rk)>; @@ -1766,54 +1765,54 @@ def : AtomicPat; def : Pat<(atomic_swap_32 GPR:$addr, GPR:$incr), - (AMSWAP_DB_W GPR:$incr, GPR:$addr)>; + (AMSWAP__DB_W GPR:$incr, GPR:$addr)>; def : Pat<(atomic_swap_64 GPR:$addr, GPR:$incr), - (AMSWAP_DB_D GPR:$incr, GPR:$addr)>; + (AMSWAP__DB_D GPR:$incr, GPR:$addr)>; def : Pat<(atomic_load_add_64 GPR:$rj, GPR:$rk), - (AMADD_DB_D GPR:$rk, GPR:$rj)>; + (AMADD__DB_D GPR:$rk, GPR:$rj)>; def : AtomicPat; def : Pat<(atomic_load_sub_32 GPR:$rj, GPR:$rk), - (AMADD_DB_W (SUB_W R0, GPR:$rk), GPR:$rj)>; + (AMADD__DB_W (SUB_W R0, GPR:$rk), GPR:$rj)>; def : Pat<(atomic_load_sub_64 GPR:$rj, GPR:$rk), - (AMADD_DB_D (SUB_D R0, GPR:$rk), GPR:$rj)>; + (AMADD__DB_D (SUB_D R0, GPR:$rk), GPR:$rj)>; def : AtomicPat; defm : PseudoBinPat<"atomic_load_nand_64", PseudoAtomicLoadNand64>; def : AtomicPat; def : Pat<(atomic_load_add_32 GPR:$rj, GPR:$rk), - (AMADD_DB_W GPR:$rk, GPR:$rj)>; + (AMADD__DB_W GPR:$rk, GPR:$rj)>; def : Pat<(atomic_load_and_32 GPR:$rj, GPR:$rk), - (AMAND_DB_W GPR:$rk, GPR:$rj)>; + (AMAND__DB_W GPR:$rk, GPR:$rj)>; def : Pat<(atomic_load_and_64 GPR:$rj, GPR:$rk), - (AMAND_DB_D GPR:$rk, GPR:$rj)>; + (AMAND__DB_D GPR:$rk, GPR:$rj)>; def : Pat<(atomic_load_or_32 GPR:$rj, GPR:$rk), - (AMOR_DB_W GPR:$rk, GPR:$rj)>; + (AMOR__DB_W GPR:$rk, GPR:$rj)>; def : Pat<(atomic_load_or_64 GPR:$rj, GPR:$rk), - (AMOR_DB_D GPR:$rk, GPR:$rj)>; + (AMOR__DB_D GPR:$rk, GPR:$rj)>; def : Pat<(atomic_load_xor_32 GPR:$rj, GPR:$rk), - (AMXOR_DB_W GPR:$rk, GPR:$rj)>; + (AMXOR__DB_W GPR:$rk, GPR:$rj)>; def : Pat<(atomic_load_xor_64 GPR:$rj, GPR:$rk), - (AMXOR_DB_D GPR:$rk, GPR:$rj)>; + (AMXOR__DB_D GPR:$rk, GPR:$rj)>; def : Pat<(atomic_load_umin_32 GPR:$rj, GPR:$rk), - (AMMIN_DB_WU GPR:$rk, GPR:$rj)>; + (AMMIN__DB_WU GPR:$rk, GPR:$rj)>; def : Pat<(atomic_load_umin_64 GPR:$rj, GPR:$rk), - (AMMIN_DB_DU GPR:$rk, GPR:$rj)>; + (AMMIN__DB_DU GPR:$rk, GPR:$rj)>; def : Pat<(atomic_load_umax_32 GPR:$rj, GPR:$rk), - (AMMAX_DB_WU GPR:$rk, GPR:$rj)>; + (AMMAX__DB_WU GPR:$rk, GPR:$rj)>; def : Pat<(atomic_load_umax_64 GPR:$rj, GPR:$rk), - (AMMAX_DB_DU GPR:$rk, GPR:$rj)>; + (AMMAX__DB_DU GPR:$rk, GPR:$rj)>; def : Pat<(atomic_load_min_32 GPR:$rj, GPR:$rk), - (AMMIN_DB_W GPR:$rk, GPR:$rj)>; + (AMMIN__DB_W GPR:$rk, GPR:$rj)>; def : Pat<(atomic_load_min_64 GPR:$rj, GPR:$rk), - (AMMIN_DB_D GPR:$rk, GPR:$rj)>; + (AMMIN__DB_D GPR:$rk, GPR:$rj)>; def : Pat<(atomic_load_max_32 GPR:$rj, GPR:$rk), - (AMMAX_DB_W GPR:$rk, GPR:$rj)>; + (AMMAX__DB_W GPR:$rk, GPR:$rj)>; def : Pat<(atomic_load_max_64 GPR:$rj, GPR:$rk), - (AMMAX_DB_D GPR:$rk, GPR:$rj)>; + (AMMAX__DB_D GPR:$rk, GPR:$rj)>; def : AtomicPat; @@ -1950,50 +1949,50 @@ // CSR Access Instructions let hasSideEffects = 1 in def CSRRD : FmtCSR<0b0000010000000, (outs GPR:$rd), (ins uimm14:$csr_num), - "csrrd", "$rd, $csr_num">; + "$rd, $csr_num">; let hasSideEffects = 1, Constraints = "$rd = $dst" in { def CSRWR : FmtCSR<0b0000010000001, (outs GPR:$dst), - (ins GPR:$rd, uimm14:$csr_num), "csrwr", "$rd, $csr_num">; + (ins GPR:$rd, uimm14:$csr_num), "$rd, $csr_num">; def CSRXCHG : FmtCSRXCHG<0b00000100, (outs GPR:$dst), (ins GPR:$rd, GPR:$rj, uimm14:$csr_num), - "csrxchg", "$rd, $rj, $csr_num">; + "$rd, $rj, $csr_num">; } // hasSideEffects = 1, Constraints = "$rd = $dst" // IOCSR Access Instructions -def IOCSRRD_B : IOCSRRD<0b0000011001001000000000, "iocsrrd.b">; -def IOCSRRD_H : IOCSRRD<0b0000011001001000000001, "iocsrrd.h">; -def IOCSRRD_W : IOCSRRD<0b0000011001001000000010, "iocsrrd.w">; -def IOCSRWR_B : IOCSRWR<0b0000011001001000000100, "iocsrwr.b">; -def IOCSRWR_H : IOCSRWR<0b0000011001001000000101, "iocsrwr.h">; -def IOCSRWR_W : IOCSRWR<0b0000011001001000000110, "iocsrwr.w">; +def IOCSRRD_B : IOCSRRD<0b0000011001001000000000>; +def IOCSRRD_H : IOCSRRD<0b0000011001001000000001>; +def IOCSRRD_W : IOCSRRD<0b0000011001001000000010>; +def IOCSRWR_B : IOCSRWR<0b0000011001001000000100>; +def IOCSRWR_H : IOCSRWR<0b0000011001001000000101>; +def IOCSRWR_W : IOCSRWR<0b0000011001001000000110>; let Predicates = [IsLA64] in { -def IOCSRRD_D : IOCSRRD<0b0000011001001000000011, "iocsrrd.d">; -def IOCSRWR_D : IOCSRWR<0b0000011001001000000111, "iocsrwr.d">; +def IOCSRRD_D : IOCSRRD<0b0000011001001000000011>; +def IOCSRWR_D : IOCSRWR<0b0000011001001000000111>; } // Predicates = [IsLA64] // TLB Maintenance Instructions let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in { -def TLBSRCH : FmtI32<0b00000110010010000010100000000000, "tlbsrch">; -def TLBRD : FmtI32<0b00000110010010000010110000000000, "tlbrd">; -def TLBWR : FmtI32<0b00000110010010000011000000000000, "tlbwr">; -def TLBFILL : FmtI32<0b00000110010010000011010000000000, "tlbfill">; -def TLBCLR : FmtI32<0b00000110010010000010000000000000, "tlbclr">; -def TLBFLUSH : FmtI32<0b00000110010010000010010000000000, "tlbflush">; -def INVTLB : FmtINVTLB<(outs), (ins GPR:$rk, GPR:$rj, uimm5:$op), "invtlb", +def TLBSRCH : FmtI32<0b00000110010010000010100000000000>; +def TLBRD : FmtI32<0b00000110010010000010110000000000>; +def TLBWR : FmtI32<0b00000110010010000011000000000000>; +def TLBFILL : FmtI32<0b00000110010010000011010000000000>; +def TLBCLR : FmtI32<0b00000110010010000010000000000000>; +def TLBFLUSH : FmtI32<0b00000110010010000010010000000000>; +def INVTLB : FmtINVTLB<(outs), (ins GPR:$rk, GPR:$rj, uimm5:$op), "$op, $rj, $rk">; } // hasSideEffects = 1, mayLoad = 0, mayStore = 0 // Software Page Walking Instructions def LDDIR : Fmt2RI8<0b00000110010000, (outs GPR:$rd), - (ins GPR:$rj, uimm8:$imm8), "lddir", "$rd, $rj, $imm8">; -def LDPTE : FmtLDPTE<(outs), (ins GPR:$rj, uimm8:$seq), "ldpte", "$rj, $seq">; + (ins GPR:$rj, uimm8:$imm8), "$rd, $rj, $imm8">; +def LDPTE : FmtLDPTE<(outs), (ins GPR:$rj, uimm8:$seq), "$rj, $seq">; // Other Miscellaneous Instructions let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in -def ERTN : FmtI32<0b00000110010010000011100000000000, "ertn">; -def DBCL : MISC_I15<0b00000000001010101, "dbcl">; -def IDLE : MISC_I15<0b00000110010010001, "idle">; +def ERTN : FmtI32<0b00000110010010000011100000000000>; +def DBCL : MISC_I15<0b00000000001010101>; +def IDLE : MISC_I15<0b00000110010010001>; //===----------------------------------------------------------------------===// // Privilege Intrinsics diff --git a/llvm/lib/Target/LoongArch/LoongArchLASXInstrFormats.td b/llvm/lib/Target/LoongArch/LoongArchLASXInstrFormats.td --- a/llvm/lib/Target/LoongArch/LoongArchLASXInstrFormats.td +++ b/llvm/lib/Target/LoongArch/LoongArchLASXInstrFormats.td @@ -18,9 +18,9 @@ // 1RI13-type // -class Fmt1RI13_XI op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt1RI13_XI op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<13> imm13; bits<5> xd; @@ -31,9 +31,9 @@ // 2R-type // -class Fmt2R_XX op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2R_XX op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<5> xj; bits<5> xd; @@ -43,9 +43,9 @@ } // -class Fmt2R_XR op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2R_XR op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<5> rj; bits<5> xd; @@ -55,9 +55,9 @@ } // -class Fmt2R_CX op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2R_CX op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<5> xj; bits<3> cd; @@ -68,9 +68,9 @@ // 2RI1-type // -class Fmt2RI1_XXI op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI1_XXI op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<1> imm1; bits<5> xj; bits<5> xd; @@ -83,9 +83,9 @@ // 2RI2-type // -class Fmt2RI2_XXI op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI2_XXI op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<2> imm2; bits<5> xj; bits<5> xd; @@ -97,9 +97,9 @@ } // -class Fmt2RI2_XRI op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI2_XRI op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<2> imm2; bits<5> rj; bits<5> xd; @@ -111,9 +111,9 @@ } // -class Fmt2RI2_RXI op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI2_RXI op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<2> imm2; bits<5> xj; bits<5> rd; @@ -126,9 +126,9 @@ // 2RI3-type // -class Fmt2RI3_XXI op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI3_XXI op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<3> imm3; bits<5> xj; bits<5> xd; @@ -140,9 +140,9 @@ } // -class Fmt2RI3_XRI op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI3_XRI op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<3> imm3; bits<5> rj; bits<5> xd; @@ -154,9 +154,9 @@ } // -class Fmt2RI3_RXI op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI3_RXI op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<3> imm3; bits<5> xj; bits<5> rd; @@ -169,9 +169,9 @@ // 2RI4-type // -class Fmt2RI4_XXI op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI4_XXI op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<4> imm4; bits<5> xj; bits<5> xd; @@ -183,9 +183,9 @@ } // -class Fmt2RI4_XRI op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI4_XRI op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<4> imm4; bits<5> rj; bits<5> xd; @@ -197,9 +197,9 @@ } // -class Fmt2RI4_RXI op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI4_RXI op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<4> imm4; bits<5> xj; bits<5> rd; @@ -212,9 +212,9 @@ // 2RI5-type // -class Fmt2RI5_XXI op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI5_XXI op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<5> imm5; bits<5> xj; bits<5> xd; @@ -227,9 +227,9 @@ // 2RI6-type // -class Fmt2RI6_XXI op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI6_XXI op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<6> imm6; bits<5> xj; bits<5> xd; @@ -242,9 +242,9 @@ // 2RI7-type // -class Fmt2RI7_XXI op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI7_XXI op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<7> imm7; bits<5> xj; bits<5> xd; @@ -257,9 +257,9 @@ // 2RI8-type // -class Fmt2RI8_XXI op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI8_XXI op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<8> imm8; bits<5> xj; bits<5> xd; @@ -272,9 +272,9 @@ // 2RI8I2-type // -class Fmt2RI8I2_XRII op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI8I2_XRII op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<2> imm2; bits<8> imm8; bits<5> rj; @@ -289,9 +289,9 @@ // 2RI8I3-type // -class Fmt2RI8I3_XRII op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI8I3_XRII op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<3> imm3; bits<8> imm8; bits<5> rj; @@ -306,9 +306,9 @@ // 2RI8I4-type // -class Fmt2RI8I4_XRII op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI8I4_XRII op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<4> imm4; bits<8> imm8; bits<5> rj; @@ -323,9 +323,9 @@ // 2RI8I5-type // -class Fmt2RI8I5_XRII op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI8I5_XRII op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<5> imm5; bits<8> imm8; bits<5> rj; @@ -340,9 +340,9 @@ // 2RI9-type // -class Fmt2RI9_XRI op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI9_XRI op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<9> imm9; bits<5> rj; bits<5> xd; @@ -355,9 +355,9 @@ // 2RI10-type // -class Fmt2RI10_XRI op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI10_XRI op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<10> imm10; bits<5> rj; bits<5> xd; @@ -370,9 +370,9 @@ // 2RI11-type // -class Fmt2RI11_XRI op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI11_XRI op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<11> imm11; bits<5> rj; bits<5> xd; @@ -385,9 +385,9 @@ // 2RI12-type // -class Fmt2RI12_XRI op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI12_XRI op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<12> imm12; bits<5> rj; bits<5> xd; @@ -400,9 +400,9 @@ // 3R-type // -class Fmt3R_XXX op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt3R_XXX op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<5> xk; bits<5> xj; bits<5> xd; @@ -414,9 +414,9 @@ } // -class Fmt3R_XXR op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt3R_XXR op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<5> rk; bits<5> xj; bits<5> xd; @@ -428,9 +428,9 @@ } // -class Fmt3R_XRR op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt3R_XRR op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<5> rk; bits<5> rj; bits<5> xd; @@ -443,9 +443,9 @@ // 4R-type // -class Fmt4R_XXXX op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt4R_XXXX op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<5> xa; bits<5> xk; bits<5> xj; diff --git a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td --- a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td +++ b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td @@ -15,159 +15,151 @@ //===----------------------------------------------------------------------===// class LASX1RI13_XI op, Operand ImmOpnd = simm13> - : Fmt1RI13_XI; + : Fmt1RI13_XI; class LASX2R_XX op> - : Fmt2R_XX; + : Fmt2R_XX; class LASX2R_XR op> - : Fmt2R_XR; + : Fmt2R_XR; class LASX2R_CX op> - : Fmt2R_CX; + : Fmt2R_CX; class LASX2RI1_XXI op, Operand ImmOpnd = uimm1> : Fmt2RI1_XXI; + "$xd, $xj, $imm1">; class LASX2RI2_XXI op, Operand ImmOpnd = uimm2> : Fmt2RI2_XXI; + "$xd, $xj, $imm2">; class LASX2RI2_RXI op, Operand ImmOpnd = uimm2> : Fmt2RI2_RXI; + "$rd, $xj, $imm2">; class LASX2RI3_XXI op, Operand ImmOpnd = uimm3> : Fmt2RI3_XXI; + "$xd, $xj, $imm3">; class LASX2RI3_RXI op, Operand ImmOpnd = uimm3> : Fmt2RI3_RXI; + "$rd, $xj, $imm3">; class LASX2RI4_XXI op, Operand ImmOpnd = uimm4> : Fmt2RI4_XXI; + "$xd, $xj, $imm4">; class LASX2RI4_XRI op, Operand ImmOpnd = uimm4> : Fmt2RI4_XRI; + "$xd, $rj, $imm4">; class LASX2RI4_RXI op, Operand ImmOpnd = uimm4> : Fmt2RI4_RXI; + "$rd, $xj, $imm4">; class LASX2RI5_XXI op, Operand ImmOpnd = uimm5> : Fmt2RI5_XXI; + "$xd, $xj, $imm5">; class LASX2RI6_XXI op, Operand ImmOpnd = uimm6> : Fmt2RI6_XXI; + "$xd, $xj, $imm6">; class LASX2RI8_XXI op, Operand ImmOpnd = uimm8> : Fmt2RI8_XXI; + "$xd, $xj, $imm8">; class LASX2RI8I2_XRII op, Operand ImmOpnd = simm8, Operand IdxOpnd = uimm2> : Fmt2RI8I2_XRII; class LASX2RI8I3_XRII op, Operand ImmOpnd = simm8, Operand IdxOpnd = uimm3> : Fmt2RI8I3_XRII; class LASX2RI8I4_XRII op, Operand ImmOpnd = simm8, Operand IdxOpnd = uimm4> : Fmt2RI8I4_XRII; class LASX2RI8I5_XRII op, Operand ImmOpnd = simm8, Operand IdxOpnd = uimm5> : Fmt2RI8I5_XRII; class LASX2RI9_XRI op, Operand ImmOpnd = simm9_lsl3> : Fmt2RI9_XRI; + "$xd, $rj, $imm9">; class LASX2RI10_XRI op, Operand ImmOpnd = simm10_lsl2> : Fmt2RI10_XRI; + "$xd, $rj, $imm10">; class LASX2RI11_XRI op, Operand ImmOpnd = simm11_lsl1> : Fmt2RI11_XRI; + "$xd, $rj, $imm11">; class LASX2RI12_XRI op, Operand ImmOpnd = simm12> : Fmt2RI12_XRI; + "$xd, $rj, $imm12">; class LASX3R_XXX op> : Fmt3R_XXX; + "$xd, $xj, $xk">; class LASX3R_XXR op> : Fmt3R_XXR; + "$xd, $xj, $rk">; class LASX3R_XRR op> : Fmt3R_XRR; + "$xd, $rj, $rk">; class LASX4R_XXXX op> : Fmt4R_XXXX; + "$xd, $xj, $xk, $xa">; let Constraints = "$xd = $dst" in { class LASX2RI2_XXXI op, Operand ImmOpnd = uimm2> : Fmt2RI2_XXI; + "$xd, $xj, $imm2">; class LASX2RI3_XXXI op, Operand ImmOpnd = uimm3> : Fmt2RI3_XXI; + "$xd, $xj, $imm3">; class LASX2RI2_XXRI op, Operand ImmOpnd = uimm2> : Fmt2RI2_XRI; + "$xd, $rj, $imm2">; class LASX2RI3_XXRI op, Operand ImmOpnd = uimm3> : Fmt2RI3_XRI; + "$xd, $rj, $imm3">; class LASX2RI4_XXXI op, Operand ImmOpnd = uimm4> : Fmt2RI4_XXI; + "$xd, $xj, $imm4">; class LASX2RI5_XXXI op, Operand ImmOpnd = uimm5> : Fmt2RI5_XXI; + "$xd, $xj, $imm5">; class LASX2RI6_XXXI op, Operand ImmOpnd = uimm6> : Fmt2RI6_XXI; + "$xd, $xj, $imm6">; class LASX2RI7_XXXI op, Operand ImmOpnd = uimm7> : Fmt2RI7_XXI; + "$xd, $xj, $imm7">; class LASX2RI8_XXXI op, Operand ImmOpnd = uimm8> : Fmt2RI8_XXI; + "$xd, $xj, $imm8">; class LASX3R_XXXX op> : Fmt3R_XXX; + "$xd, $xj, $xk">; } // Constraints = "$xd = $dst" diff --git a/llvm/lib/Target/LoongArch/LoongArchLSXInstrFormats.td b/llvm/lib/Target/LoongArch/LoongArchLSXInstrFormats.td --- a/llvm/lib/Target/LoongArch/LoongArchLSXInstrFormats.td +++ b/llvm/lib/Target/LoongArch/LoongArchLSXInstrFormats.td @@ -18,9 +18,9 @@ // 1RI13-type // -class Fmt1RI13_VI op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt1RI13_VI op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<13> imm13; bits<5> vd; @@ -31,9 +31,9 @@ // 2R-type // -class Fmt2R_VV op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2R_VV op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<5> vj; bits<5> vd; @@ -43,9 +43,9 @@ } // -class Fmt2R_VR op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2R_VR op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<5> rj; bits<5> vd; @@ -55,9 +55,9 @@ } // -class Fmt2R_CV op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2R_CV op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<5> vj; bits<3> cd; @@ -68,9 +68,9 @@ // 2RI1-type // -class Fmt2RI1_VVI op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI1_VVI op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<1> imm1; bits<5> vj; bits<5> vd; @@ -82,9 +82,9 @@ } // -class Fmt2RI1_VRI op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI1_VRI op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<1> imm1; bits<5> rj; bits<5> vd; @@ -96,9 +96,9 @@ } // -class Fmt2RI1_RVI op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI1_RVI op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<1> imm1; bits<5> vj; bits<5> rd; @@ -111,9 +111,9 @@ // 2RI2-type // -class Fmt2RI2_VVI op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI2_VVI op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<2> imm2; bits<5> vj; bits<5> vd; @@ -125,9 +125,9 @@ } // -class Fmt2RI2_VRI op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI2_VRI op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<2> imm2; bits<5> rj; bits<5> vd; @@ -139,9 +139,9 @@ } // -class Fmt2RI2_RVI op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI2_RVI op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<2> imm2; bits<5> vj; bits<5> rd; @@ -154,9 +154,9 @@ // 2RI3-type // -class Fmt2RI3_VVI op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI3_VVI op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<3> imm3; bits<5> vj; bits<5> vd; @@ -168,9 +168,9 @@ } // -class Fmt2RI3_VRI op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI3_VRI op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<3> imm3; bits<5> rj; bits<5> vd; @@ -182,9 +182,9 @@ } // -class Fmt2RI3_RVI op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI3_RVI op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<3> imm3; bits<5> vj; bits<5> rd; @@ -197,9 +197,9 @@ // 2RI4-type // -class Fmt2RI4_VVI op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI4_VVI op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<4> imm4; bits<5> vj; bits<5> vd; @@ -211,9 +211,9 @@ } // -class Fmt2RI4_VRI op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI4_VRI op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<4> imm4; bits<5> rj; bits<5> vd; @@ -225,9 +225,9 @@ } // -class Fmt2RI4_RVI op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI4_RVI op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<4> imm4; bits<5> vj; bits<5> rd; @@ -240,9 +240,9 @@ // 2RI5-type // -class Fmt2RI5_VVI op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI5_VVI op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<5> imm5; bits<5> vj; bits<5> vd; @@ -255,9 +255,9 @@ // 2RI6-type // -class Fmt2RI6_VVI op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI6_VVI op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<6> imm6; bits<5> vj; bits<5> vd; @@ -270,9 +270,9 @@ // 2RI7-type // -class Fmt2RI7_VVI op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI7_VVI op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<7> imm7; bits<5> vj; bits<5> vd; @@ -285,9 +285,9 @@ // 2RI8-type // -class Fmt2RI8_VVI op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI8_VVI op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<8> imm8; bits<5> vj; bits<5> vd; @@ -300,9 +300,9 @@ // 2RI8I1-type // -class Fmt2RI8I1_VRII op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI8I1_VRII op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<1> imm1; bits<8> imm8; bits<5> rj; @@ -317,9 +317,9 @@ // 2RI8I2-type // -class Fmt2RI8I2_VRII op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI8I2_VRII op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<2> imm2; bits<8> imm8; bits<5> rj; @@ -334,9 +334,9 @@ // 2RI8I3-type // -class Fmt2RI8I3_VRII op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI8I3_VRII op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<3> imm3; bits<8> imm8; bits<5> rj; @@ -351,9 +351,9 @@ // 2RI8I4-type // -class Fmt2RI8I4_VRII op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI8I4_VRII op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<4> imm4; bits<8> imm8; bits<5> rj; @@ -367,9 +367,9 @@ } // 2RI9-type // -class Fmt2RI9_VRI op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI9_VRI op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<9> imm9; bits<5> rj; bits<5> vd; @@ -382,9 +382,9 @@ // 2RI10-type // -class Fmt2RI10_VRI op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI10_VRI op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<10> imm10; bits<5> rj; bits<5> vd; @@ -397,9 +397,9 @@ // 2RI11-type // -class Fmt2RI11_VRI op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI11_VRI op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<11> imm11; bits<5> rj; bits<5> vd; @@ -412,9 +412,9 @@ // 2RI12-type // -class Fmt2RI12_VRI op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt2RI12_VRI op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<12> imm12; bits<5> rj; bits<5> vd; @@ -427,9 +427,9 @@ // 3R-type // -class Fmt3R_VVV op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt3R_VVV op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<5> vk; bits<5> vj; bits<5> vd; @@ -441,9 +441,9 @@ } // -class Fmt3R_VVR op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt3R_VVR op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<5> rk; bits<5> vj; bits<5> vd; @@ -455,9 +455,9 @@ } // -class Fmt3R_VRR op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt3R_VRR op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<5> rk; bits<5> rj; bits<5> vd; @@ -470,9 +470,9 @@ // 4R-type // -class Fmt4R_VVVV op, dag outs, dag ins, string opcstr, string opnstr, +class Fmt4R_VVVV op, dag outs, dag ins, string opnstr, list pattern = []> - : LAInst { + : LAInst.ret, opnstr, pattern> { bits<5> va; bits<5> vk; bits<5> vj; diff --git a/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td --- a/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td +++ b/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td @@ -15,158 +15,150 @@ //===----------------------------------------------------------------------===// class LSX1RI13_VI op, Operand ImmOpnd = simm13> - : Fmt1RI13_VI; + : Fmt1RI13_VI; class LSX2R_VV op> - : Fmt2R_VV; + : Fmt2R_VV; class LSX2R_VR op> - : Fmt2R_VR; + : Fmt2R_VR; class LSX2R_CV op> - : Fmt2R_CV; + : Fmt2R_CV; class LSX2RI1_VVI op, Operand ImmOpnd = uimm1> : Fmt2RI1_VVI; + "$vd, $vj, $imm1">; class LSX2RI1_RVI op, Operand ImmOpnd = uimm1> : Fmt2RI1_RVI; + "$rd, $vj, $imm1">; class LSX2RI2_VVI op, Operand ImmOpnd = uimm2> : Fmt2RI2_VVI; + "$vd, $vj, $imm2">; class LSX2RI2_RVI op, Operand ImmOpnd = uimm2> : Fmt2RI2_RVI; + "$rd, $vj, $imm2">; class LSX2RI3_VVI op, Operand ImmOpnd = uimm3> : Fmt2RI3_VVI; + "$vd, $vj, $imm3">; class LSX2RI3_RVI op, Operand ImmOpnd = uimm3> : Fmt2RI3_RVI; + "$rd, $vj, $imm3">; class LSX2RI4_VVI op, Operand ImmOpnd = uimm4> : Fmt2RI4_VVI; + "$vd, $vj, $imm4">; class LSX2RI4_RVI op, Operand ImmOpnd = uimm4> : Fmt2RI4_RVI; + "$rd, $vj, $imm4">; class LSX2RI5_VVI op, Operand ImmOpnd = uimm5> : Fmt2RI5_VVI; + "$vd, $vj, $imm5">; class LSX2RI6_VVI op, Operand ImmOpnd = uimm6> : Fmt2RI6_VVI; + "$vd, $vj, $imm6">; class LSX2RI8_VVI op, Operand ImmOpnd = uimm8> : Fmt2RI8_VVI; + "$vd, $vj, $imm8">; class LSX2RI8I1_VRII op, Operand ImmOpnd = simm8, Operand IdxOpnd = uimm1> : Fmt2RI8I1_VRII; class LSX2RI8I2_VRII op, Operand ImmOpnd = simm8, Operand IdxOpnd = uimm2> : Fmt2RI8I2_VRII; class LSX2RI8I3_VRII op, Operand ImmOpnd = simm8, Operand IdxOpnd = uimm3> : Fmt2RI8I3_VRII; class LSX2RI8I4_VRII op, Operand ImmOpnd = simm8, Operand IdxOpnd = uimm4> : Fmt2RI8I4_VRII; class LSX2RI9_VRI op, Operand ImmOpnd = simm9_lsl3> : Fmt2RI9_VRI; + "$vd, $rj, $imm9">; class LSX2RI10_VRI op, Operand ImmOpnd = simm10_lsl2> : Fmt2RI10_VRI; + "$vd, $rj, $imm10">; class LSX2RI11_VRI op, Operand ImmOpnd = simm11_lsl1> : Fmt2RI11_VRI; + "$vd, $rj, $imm11">; class LSX2RI12_VRI op, Operand ImmOpnd = simm12> : Fmt2RI12_VRI; + "$vd, $rj, $imm12">; class LSX3R_VVV op> : Fmt3R_VVV; + "$vd, $vj, $vk">; class LSX3R_VVR op> : Fmt3R_VVR; + "$vd, $vj, $rk">; class LSX3R_VRR op> : Fmt3R_VRR; + "$vd, $rj, $rk">; class LSX4R_VVVV op> : Fmt4R_VVVV; + "$vd, $vj, $vk, $va">; let Constraints = "$vd = $dst" in { class LSX2RI1_VVRI op, Operand ImmOpnd = uimm1> : Fmt2RI1_VRI; + "$vd, $rj, $imm1">; class LSX2RI2_VVRI op, Operand ImmOpnd = uimm2> : Fmt2RI2_VRI; + "$vd, $rj, $imm2">; class LSX2RI3_VVRI op, Operand ImmOpnd = uimm3> : Fmt2RI3_VRI; + "$vd, $rj, $imm3">; class LSX2RI4_VVRI op, Operand ImmOpnd = uimm4> : Fmt2RI4_VRI; + "$vd, $rj, $imm4">; class LSX2RI4_VVVI op, Operand ImmOpnd = uimm4> : Fmt2RI4_VVI; + "$vd, $vj, $imm4">; class LSX2RI5_VVVI op, Operand ImmOpnd = uimm5> : Fmt2RI5_VVI; + "$vd, $vj, $imm5">; class LSX2RI6_VVVI op, Operand ImmOpnd = uimm6> : Fmt2RI6_VVI; + "$vd, $vj, $imm6">; class LSX2RI7_VVVI op, Operand ImmOpnd = uimm7> : Fmt2RI7_VVI; + "$vd, $vj, $imm7">; class LSX2RI8_VVVI op, Operand ImmOpnd = uimm8> : Fmt2RI8_VVI; + "$vd, $vj, $imm8">; class LSX3R_VVVV op> : Fmt3R_VVV; + "$vd, $vj, $vk">; } // Constraints = "$vd = $dst"