diff --git a/llvm/test/CodeGen/LoongArch/zext-with-load-is-free.ll b/llvm/test/CodeGen/LoongArch/zext-with-load-is-free.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/zext-with-load-is-free.ll
@@ -0,0 +1,118 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+;; Adapted from the RISCV test case.
+; RUN: llc --mtriple=loongarch32 -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s --check-prefix=LA32
+; RUN: llc --mtriple=loongarch64 -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s --check-prefix=LA64
+
+@bytes = dso_local global [5 x i8] zeroinitializer, align 1
+
+define dso_local i32 @test_zext_i8() nounwind {
+; LA32-LABEL: test_zext_i8:
+; LA32:       # %bb.0: # %entry
+; LA32-NEXT:    pcalau12i $a0, %pc_hi20(bytes)
+; LA32-NEXT:    addi.w $a0, $a0, %pc_lo12(bytes)
+; LA32-NEXT:    ld.bu $a1, $a0, 0
+; LA32-NEXT:    ori $a2, $zero, 136
+; LA32-NEXT:    bne $a1, $a2, .LBB0_3
+; LA32-NEXT:  # %bb.1: # %entry
+; LA32-NEXT:    ld.b $a0, $a0, 1
+; LA32-NEXT:    andi $a0, $a0, 255
+; LA32-NEXT:    ori $a1, $zero, 7
+; LA32-NEXT:    bne $a0, $a1, .LBB0_3
+; LA32-NEXT:  # %bb.2: # %if.end
+; LA32-NEXT:    move $a0, $zero
+; LA32-NEXT:    ret
+; LA32-NEXT:  .LBB0_3: # %if.then
+; LA32-NEXT:    ori $a0, $zero, 1
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: test_zext_i8:
+; LA64:       # %bb.0: # %entry
+; LA64-NEXT:    pcalau12i $a0, %pc_hi20(bytes)
+; LA64-NEXT:    addi.d $a0, $a0, %pc_lo12(bytes)
+; LA64-NEXT:    ld.bu $a1, $a0, 0
+; LA64-NEXT:    ori $a2, $zero, 136
+; LA64-NEXT:    bne $a1, $a2, .LBB0_3
+; LA64-NEXT:  # %bb.1: # %entry
+; LA64-NEXT:    ld.b $a0, $a0, 1
+; LA64-NEXT:    andi $a0, $a0, 255
+; LA64-NEXT:    ori $a1, $zero, 7
+; LA64-NEXT:    bne $a0, $a1, .LBB0_3
+; LA64-NEXT:  # %bb.2: # %if.end
+; LA64-NEXT:    move $a0, $zero
+; LA64-NEXT:    ret
+; LA64-NEXT:  .LBB0_3: # %if.then
+; LA64-NEXT:    ori $a0, $zero, 1
+; LA64-NEXT:    ret
+entry:
+  %0 = load i8, ptr @bytes, align 1
+  %cmp = icmp eq i8 %0, -120
+  %1 = load i8, ptr getelementptr inbounds ([5 x i8], ptr @bytes, i32 0, i32 1), align 1
+  %cmp3 = icmp eq i8 %1, 7
+  %or.cond = and i1 %cmp, %cmp3
+  br i1 %or.cond, label %if.end, label %if.then
+
+if.then:
+  ret i32 1
+
+if.end:
+  ret i32 0
+}
+
+@shorts = dso_local global [5 x i16] zeroinitializer, align 2
+
+define dso_local i32 @test_zext_i16() nounwind {
+; LA32-LABEL: test_zext_i16:
+; LA32:       # %bb.0: # %entry
+; LA32-NEXT:    pcalau12i $a0, %pc_hi20(shorts)
+; LA32-NEXT:    addi.w $a0, $a0, %pc_lo12(shorts)
+; LA32-NEXT:    lu12i.w $a1, 15
+; LA32-NEXT:    ori $a1, $a1, 3976
+; LA32-NEXT:    ld.hu $a2, $a0, 0
+; LA32-NEXT:    bne $a2, $a1, .LBB1_3
+; LA32-NEXT:  # %bb.1: # %entry
+; LA32-NEXT:    ld.h $a0, $a0, 2
+; LA32-NEXT:    bstrpick.w $a0, $a0, 15, 0
+; LA32-NEXT:    ori $a1, $zero, 7
+; LA32-NEXT:    bne $a0, $a1, .LBB1_3
+; LA32-NEXT:  # %bb.2: # %if.end
+; LA32-NEXT:    move $a0, $zero
+; LA32-NEXT:    ret
+; LA32-NEXT:  .LBB1_3: # %if.then
+; LA32-NEXT:    ori $a0, $zero, 1
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: test_zext_i16:
+; LA64:       # %bb.0: # %entry
+; LA64-NEXT:    pcalau12i $a0, %pc_hi20(shorts)
+; LA64-NEXT:    addi.d $a0, $a0, %pc_lo12(shorts)
+; LA64-NEXT:    lu12i.w $a1, 15
+; LA64-NEXT:    ori $a1, $a1, 3976
+; LA64-NEXT:    ld.hu $a2, $a0, 0
+; LA64-NEXT:    bne $a2, $a1, .LBB1_3
+; LA64-NEXT:  # %bb.1: # %entry
+; LA64-NEXT:    ld.h $a0, $a0, 2
+; LA64-NEXT:    bstrpick.d $a0, $a0, 15, 0
+; LA64-NEXT:    ori $a1, $zero, 7
+; LA64-NEXT:    bne $a0, $a1, .LBB1_3
+; LA64-NEXT:  # %bb.2: # %if.end
+; LA64-NEXT:    move $a0, $zero
+; LA64-NEXT:    ret
+; LA64-NEXT:  .LBB1_3: # %if.then
+; LA64-NEXT:    ori $a0, $zero, 1
+; LA64-NEXT:    ret
+entry:
+  %0 = load i16, ptr @shorts, align 2
+  %cmp = icmp eq i16 %0, -120
+  %1 = load i16, ptr getelementptr inbounds ([5 x i16], ptr @shorts, i32 0, i32 1), align 2
+  %cmp3 = icmp eq i16 %1, 7
+  %or.cond = and i1 %cmp, %cmp3
+  br i1 %or.cond, label %if.end, label %if.then
+
+if.then:
+  ret i32 1
+
+if.end:
+  ret i32 0
+}