Index: llvm/test/Transforms/InstCombine/and-or-icmps.ll
===================================================================
--- llvm/test/Transforms/InstCombine/and-or-icmps.ll
+++ llvm/test/Transforms/InstCombine/and-or-icmps.ll
@@ -2666,7 +2666,6 @@
   %E = or <2 x i64> %C, %D
   ret <2 x i64> %E
 }
-
 define <2 x i64> @icmp_slt_0_or_icmp_sgt_0_i64x2_fail(<2 x i64> %x) {
 ; CHECK-LABEL: @icmp_slt_0_or_icmp_sgt_0_i64x2_fail(
 ; CHECK-NEXT:    [[B:%.*]] = icmp sgt <2 x i64> [[X:%.*]], <i64 1, i64 1>
@@ -2682,3 +2681,138 @@
   ret <2 x i64> %E
 
 }
+
+define i32 @icmps_slt_0_and_icmp_sge_neg1_i32(i32 %x) {
+; CHECK-LABEL: @icmps_slt_0_and_icmp_sge_neg1_i32(
+; CHECK-NEXT:    [[A:%.*]] = icmp sgt i32 [[X:%.*]], -1
+; CHECK-NEXT:    [[B:%.*]] = zext i1 [[A]] to i32
+; CHECK-NEXT:    [[C:%.*]] = lshr i32 [[X]], 31
+; CHECK-NEXT:    [[D:%.*]] = and i32 [[C]], [[B]]
+; CHECK-NEXT:    ret i32 [[D]]
+;
+  %A = icmp sgt i32 %x, -1
+  %B = zext i1 %A to i32
+  %C = lshr i32 %x, 31
+  %D = and i32 %C, %B
+  ret i32 %D
+}
+
+define i32 @icmps_slt_0_or_icmp_sge_neg1_i32(i32 %x) {
+; CHECK-LABEL: @icmps_slt_0_or_icmp_sge_neg1_i32(
+; CHECK-NEXT:    [[A:%.*]] = icmp sgt i32 [[X:%.*]], -2
+; CHECK-NEXT:    [[B:%.*]] = zext i1 [[A]] to i32
+; CHECK-NEXT:    [[C:%.*]] = lshr i32 [[X]], 31
+; CHECK-NEXT:    [[D:%.*]] = or i32 [[C]], [[B]]
+; CHECK-NEXT:    ret i32 [[D]]
+;
+  %A = icmp sge i32 %x, -1
+  %B = zext i1 %A to i32
+  %C = lshr i32 %x, 31
+  %D = or i32 %C, %B
+  ret i32 %D
+}
+
+define i64 @icmps_slt_0_and_icmp_sge_neg1_i64(i64 %x) {
+; CHECK-LABEL: @icmps_slt_0_and_icmp_sge_neg1_i64(
+; CHECK-NEXT:    [[A:%.*]] = icmp sgt i64 [[X:%.*]], -2
+; CHECK-NEXT:    [[B:%.*]] = zext i1 [[A]] to i64
+; CHECK-NEXT:    [[C:%.*]] = lshr i64 [[X]], 63
+; CHECK-NEXT:    [[D:%.*]] = and i64 [[C]], [[B]]
+; CHECK-NEXT:    ret i64 [[D]]
+;
+  %A = icmp sge i64 %x, -1
+  %B = zext i1 %A to i64
+  %C = lshr i64 %x, 63
+  %D = and i64 %C, %B
+  ret i64 %D
+}
+
+define i64 @icmps_slt_0_and_icmp_sge_neg1_i64_fail0(i64 %x) {
+; CHECK-LABEL: @icmps_slt_0_and_icmp_sge_neg1_i64_fail0(
+; CHECK-NEXT:    [[A:%.*]] = icmp sgt i64 [[X:%.*]], -2
+; CHECK-NEXT:    [[B:%.*]] = zext i1 [[A]] to i64
+; CHECK-NEXT:    [[C:%.*]] = lshr i64 [[X]], 63
+; CHECK-NEXT:    [[D:%.*]] = and i64 [[C]], [[B]]
+; CHECK-NEXT:    ret i64 [[D]]
+;
+  %A = icmp sge i64 %x, -1
+  %B = zext i1 %A to i64
+  %C = lshr i64 %x, 63
+  %D = and i64 %C, %B
+  ret i64 %D
+}
+
+define i64 @icmps_slt_0_and_icmp_sge_neg1_i64_fail1(i64 %x) {
+; CHECK-LABEL: @icmps_slt_0_and_icmp_sge_neg1_i64_fail1(
+; CHECK-NEXT:    [[A:%.*]] = icmp sgt i64 [[X:%.*]], -2
+; CHECK-NEXT:    [[B:%.*]] = zext i1 [[A]] to i64
+; CHECK-NEXT:    [[C1:%.*]] = lshr i64 [[X]], 63
+; CHECK-NEXT:    [[D:%.*]] = and i64 [[C1]], [[B]]
+; CHECK-NEXT:    ret i64 [[D]]
+;
+  %A = icmp sge i64 %x, -1
+  %B = zext i1 %A to i64
+  %C = ashr i64 %x, 63
+  %D = and i64 %C, %B
+  ret i64 %D
+}
+
+define i64 @icmps_slt_0_and_icmp_sge_neg1_i64_fail2(i64 %x) {
+; CHECK-LABEL: @icmps_slt_0_and_icmp_sge_neg1_i64_fail2(
+; CHECK-NEXT:    [[A:%.*]] = icmp sgt i64 [[X:%.*]], -2
+; CHECK-NEXT:    [[B:%.*]] = zext i1 [[A]] to i64
+; CHECK-NEXT:    [[C:%.*]] = lshr i64 [[X]], 62
+; CHECK-NEXT:    [[D:%.*]] = and i64 [[C]], [[B]]
+; CHECK-NEXT:    ret i64 [[D]]
+;
+  %A = icmp sge i64 %x, -1
+  %B = zext i1 %A to i64
+  %C = lshr i64 %x, 62
+  %D = and i64 %C, %B
+  ret i64 %D
+}
+
+define i64 @icmps_slt_0_and_icmp_sge_neg1_i64_fail3(i64 %x) {
+; CHECK-LABEL: @icmps_slt_0_and_icmp_sge_neg1_i64_fail3(
+; CHECK-NEXT:    [[A:%.*]] = icmp sgt i64 [[X:%.*]], -1
+; CHECK-NEXT:    [[B:%.*]] = zext i1 [[A]] to i64
+; CHECK-NEXT:    [[C:%.*]] = lshr i64 [[X]], 63
+; CHECK-NEXT:    [[D:%.*]] = and i64 [[C]], [[B]]
+; CHECK-NEXT:    ret i64 [[D]]
+;
+  %A = icmp sgt i64 %x, -1
+  %B = zext i1 %A to i64
+  %C = lshr i64 %x, 63
+  %D = and i64 %C, %B
+  ret i64 %D
+}
+
+define <2 x i32> @icmps_slt_0_and_icmp_sge_neg1_i32x2(<2 x i32> %x) {
+; CHECK-LABEL: @icmps_slt_0_and_icmp_sge_neg1_i32x2(
+; CHECK-NEXT:    [[A:%.*]] = icmp sgt <2 x i32> [[X:%.*]], <i32 -2, i32 -2>
+; CHECK-NEXT:    [[B:%.*]] = zext <2 x i1> [[A]] to <2 x i32>
+; CHECK-NEXT:    [[C:%.*]] = lshr <2 x i32> [[X]], <i32 31, i32 31>
+; CHECK-NEXT:    [[D:%.*]] = and <2 x i32> [[C]], [[B]]
+; CHECK-NEXT:    ret <2 x i32> [[D]]
+;
+  %A = icmp sge <2 x i32> %x, <i32 -1, i32 -1>
+  %B = zext <2 x i1> %A to <2 x i32>
+  %C = lshr <2 x i32> %x, <i32 31, i32 31>
+  %D = and <2 x i32> %C, %B
+  ret <2 x i32> %D
+}
+
+define <2 x i32> @icmps_slt_0_and_icmp_sge_neg2_i32x2(<2 x i32> %x) {
+; CHECK-LABEL: @icmps_slt_0_and_icmp_sge_neg2_i32x2(
+; CHECK-NEXT:    [[A:%.*]] = icmp sgt <2 x i32> [[X:%.*]], <i32 -3, i32 -3>
+; CHECK-NEXT:    [[B:%.*]] = zext <2 x i1> [[A]] to <2 x i32>
+; CHECK-NEXT:    [[C:%.*]] = lshr <2 x i32> [[X]], <i32 31, i32 31>
+; CHECK-NEXT:    [[D:%.*]] = and <2 x i32> [[C]], [[B]]
+; CHECK-NEXT:    ret <2 x i32> [[D]]
+;
+  %A = icmp sge <2 x i32> %x, <i32 -2, i32 -2>
+  %B = zext <2 x i1> %A to <2 x i32>
+  %C = lshr <2 x i32> %x, <i32 31, i32 31>
+  %D = and <2 x i32> %C, %B
+  ret <2 x i32> %D
+}