diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -41,6 +41,17 @@
             (store_instr reg_class:$rs2, GPR:$rs1, avl, log2sew)>;
 }
 
+defvar IsEEWAligned = [{
+  auto *MN = cast<MemSDNode>(N);
+  unsigned EEWSize =
+      MN->getMemoryVT().getVectorElementType().getSizeInBits() / 8;
+  return MN->getAlign() >= Align(EEWSize);
+}];
+
+def whole_reg_load : PatFrag<(ops node:$ptr), (load node:$ptr), IsEEWAligned>;
+def whole_reg_store : PatFrag<(ops node:$val, node:$ptr),
+                              (store node:$val, node:$ptr), IsEEWAligned>;
+
 multiclass VPatUSLoadStoreWholeVRSDNode<ValueType type,
                                         int log2sew,
                                         LMULInfo vlmul,
@@ -52,10 +63,10 @@
     !cast<Instruction>("VS"#!substr(vlmul.MX, 1)#"R_V");
 
   // Load
-  def : Pat<(type (load GPR:$rs1)),
+  def : Pat<(type (whole_reg_load GPR:$rs1)),
             (load_instr GPR:$rs1)>;
   // Store
-  def : Pat<(store type:$rs2, GPR:$rs1),
+  def : Pat<(whole_reg_store type:$rs2, GPR:$rs1),
             (store_instr reg_class:$rs2, GPR:$rs1)>;
 }
 
@@ -699,13 +710,19 @@
   defm : VPatUSLoadStoreSDNode<vti.Vector, vti.Log2SEW, vti.LMul,
                                vti.AVL, vti.RegClass>;
 foreach vti = [VI8M1, VI16M1, VI32M1, VI64M1, VF16M1, VF32M1, VF64M1] in
-  let Predicates = GetVTypePredicates<vti>.Predicates in
-  defm : VPatUSLoadStoreWholeVRSDNode<vti.Vector, vti.Log2SEW, vti.LMul,
-                                      vti.RegClass>;
+  let Predicates = GetVTypePredicates<vti>.Predicates in {
+    defm : VPatUSLoadStoreWholeVRSDNode<vti.Vector, vti.Log2SEW, vti.LMul,
+                                        vti.RegClass>;
+    defm : VPatUSLoadStoreSDNode<vti.Vector, vti.Log2SEW, vti.LMul, vti.AVL,
+                                 vti.RegClass>;
+  }
 foreach vti = !listconcat(GroupIntegerVectors, GroupFloatVectors) in
-  let Predicates = GetVTypePredicates<vti>.Predicates in 
-  defm : VPatUSLoadStoreWholeVRSDNode<vti.Vector, vti.Log2SEW, vti.LMul,
-                                      vti.RegClass>;
+  let Predicates = GetVTypePredicates<vti>.Predicates in {
+    defm : VPatUSLoadStoreWholeVRSDNode<vti.Vector, vti.Log2SEW, vti.LMul,
+                                        vti.RegClass>;
+    defm : VPatUSLoadStoreSDNode<vti.Vector, vti.Log2SEW, vti.LMul, vti.AVL,
+                                 vti.RegClass>;
+  }
 foreach mti = AllMasks in
   let Predicates = [HasVInstructions] in
   defm : VPatUSLoadStoreMaskSDNode<mti>;
diff --git a/llvm/test/CodeGen/RISCV/rvv/unaligned-loads-stores.ll b/llvm/test/CodeGen/RISCV/rvv/unaligned-loads-stores.ll
--- a/llvm/test/CodeGen/RISCV/rvv/unaligned-loads-stores.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/unaligned-loads-stores.ll
@@ -65,7 +65,8 @@
 ;
 ; UNALIGNED-LABEL: unaligned_load_nxv1i64_a1:
 ; UNALIGNED:       # %bb.0:
-; UNALIGNED-NEXT:    vl1re64.v v8, (a0)
+; UNALIGNED-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
+; UNALIGNED-NEXT:    vle64.v v8, (a0)
 ; UNALIGNED-NEXT:    ret
   %v = load <vscale x 1 x i64>, <vscale x 1 x i64>* %ptr, align 1
   ret <vscale x 1 x i64> %v
@@ -79,7 +80,8 @@
 ;
 ; UNALIGNED-LABEL: unaligned_load_nxv1i64_a4:
 ; UNALIGNED:       # %bb.0:
-; UNALIGNED-NEXT:    vl1re64.v v8, (a0)
+; UNALIGNED-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
+; UNALIGNED-NEXT:    vle64.v v8, (a0)
 ; UNALIGNED-NEXT:    ret
   %v = load <vscale x 1 x i64>, <vscale x 1 x i64>* %ptr, align 4
   ret <vscale x 1 x i64> %v
@@ -107,7 +109,8 @@
 ;
 ; UNALIGNED-LABEL: unaligned_load_nxv2i64_a1:
 ; UNALIGNED:       # %bb.0:
-; UNALIGNED-NEXT:    vl2re64.v v8, (a0)
+; UNALIGNED-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
+; UNALIGNED-NEXT:    vle64.v v8, (a0)
 ; UNALIGNED-NEXT:    ret
   %v = load <vscale x 2 x i64>, <vscale x 2 x i64>* %ptr, align 1
   ret <vscale x 2 x i64> %v
@@ -121,7 +124,8 @@
 ;
 ; UNALIGNED-LABEL: unaligned_load_nxv2i64_a4:
 ; UNALIGNED:       # %bb.0:
-; UNALIGNED-NEXT:    vl2re64.v v8, (a0)
+; UNALIGNED-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
+; UNALIGNED-NEXT:    vle64.v v8, (a0)
 ; UNALIGNED-NEXT:    ret
   %v = load <vscale x 2 x i64>, <vscale x 2 x i64>* %ptr, align 4
   ret <vscale x 2 x i64> %v
@@ -166,7 +170,8 @@
 ;
 ; UNALIGNED-LABEL: unaligned_load_nxv4f32_a1:
 ; UNALIGNED:       # %bb.0:
-; UNALIGNED-NEXT:    vl2re32.v v8, (a0)
+; UNALIGNED-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
+; UNALIGNED-NEXT:    vle32.v v8, (a0)
 ; UNALIGNED-NEXT:    ret
   %v = load <vscale x 4 x float>, <vscale x 4 x float>* %ptr, align 1
   ret <vscale x 4 x float> %v
@@ -180,7 +185,8 @@
 ;
 ; UNALIGNED-LABEL: unaligned_load_nxv4f32_a2:
 ; UNALIGNED:       # %bb.0:
-; UNALIGNED-NEXT:    vl2re32.v v8, (a0)
+; UNALIGNED-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
+; UNALIGNED-NEXT:    vle32.v v8, (a0)
 ; UNALIGNED-NEXT:    ret
   %v = load <vscale x 4 x float>, <vscale x 4 x float>* %ptr, align 2
   ret <vscale x 4 x float> %v
@@ -208,7 +214,8 @@
 ;
 ; UNALIGNED-LABEL: unaligned_load_nxv8f16_a1:
 ; UNALIGNED:       # %bb.0:
-; UNALIGNED-NEXT:    vl2re16.v v8, (a0)
+; UNALIGNED-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
+; UNALIGNED-NEXT:    vle16.v v8, (a0)
 ; UNALIGNED-NEXT:    ret
   %v = load <vscale x 8 x half>, <vscale x 8 x half>* %ptr, align 1
   ret <vscale x 8 x half> %v
@@ -236,7 +243,8 @@
 ;
 ; UNALIGNED-LABEL: unaligned_store_nxv4i32_a1:
 ; UNALIGNED:       # %bb.0:
-; UNALIGNED-NEXT:    vs2r.v v8, (a0)
+; UNALIGNED-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
+; UNALIGNED-NEXT:    vse32.v v8, (a0)
 ; UNALIGNED-NEXT:    ret
   store <vscale x 4 x i32> %x, <vscale x 4 x i32>* %ptr, align 1
   ret void
@@ -250,7 +258,8 @@
 ;
 ; UNALIGNED-LABEL: unaligned_store_nxv4i32_a2:
 ; UNALIGNED:       # %bb.0:
-; UNALIGNED-NEXT:    vs2r.v v8, (a0)
+; UNALIGNED-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
+; UNALIGNED-NEXT:    vse32.v v8, (a0)
 ; UNALIGNED-NEXT:    ret
   store <vscale x 4 x i32> %x, <vscale x 4 x i32>* %ptr, align 2
   ret void