Index: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -702,9 +702,14 @@
   defm FTMAD_ZZI : sve_fp_ftmad<"ftmad", int_aarch64_sve_ftmad_x>;
 } // End HasSVE
 
+class TriSVEOpFrag<dag res> : PatFrag<(ops node:$pg, node:$zn, node:$zm, node:$za), res>;
+
 let Predicates = [HasSVEorSME] in {
   defm FMLA_ZZZI : sve_fp_fma_by_indexed_elem<0b00, "fmla", int_aarch64_sve_fmla_lane>;
   defm FMLS_ZZZI : sve_fp_fma_by_indexed_elem<0b01, "fmls", int_aarch64_sve_fmls_lane>;
+  defm : SVEFPIndexedTiedPatterns<"FMLA_ZZZI", TriSVEOpFrag<(AArch64fma_p node:$pg, node:$zn, node:$zm, node:$za)>>;
+  defm : SVEFPIndexedTiedPatterns<"FMLS_ZZZI", TriSVEOpFrag<(AArch64fma_p node:$pg, (AArch64fneg_mt node:$pg, node:$zn, (undef)), node:$zm, node:$za)>>;
+  defm : SVEFPIndexedTiedPatterns<"FMLS_ZZZI", TriSVEOpFrag<(AArch64fma_p node:$pg, node:$zm, (AArch64fneg_mt node:$pg, node:$zn, (undef)), node:$za)>>;
 
   defm FCMLA_ZZZI : sve_fp_fcmla_by_indexed_elem<"fcmla", int_aarch64_sve_fcmla_lane>;
   defm FMUL_ZZZI   : sve_fp_fmul_by_indexed_elem<"fmul", int_aarch64_sve_fmul_lane>;
Index: llvm/lib/Target/AArch64/SVEInstrFormats.td
===================================================================
--- llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -2393,6 +2393,18 @@
             (!cast<Instruction>(NAME # _D) $Op1, $Op2, $Op3, VectorIndexD32b_timm:$idx)>;
 }
 
+class SVEFPIndexedTiedPattern<SDPatternOperator OpNode, ValueType vtd,
+  ValueType vtp, ValueType scalartp, Instruction inst, ZPRRegOp zprty, Operand imm_ty>
+  : Pat <(vtd (OpNode (vtp (SVEAnyPredicate)),
+                      (vtd (splat_vector (scalartp (vector_extract (vtd zprty:$Zda), imm_ty:$idx)))),
+                      (vtd zprty:$Zn), (vtd zprty:$Zm))),
+         (inst zprty:$Zda, zprty:$Zn, zprty:$Zm, (!cast<SDNodeXForm>("trunc_imm") $idx))>;
+
+multiclass SVEFPIndexedTiedPatterns<string INST, SDPatternOperator OpNode> {
+  def : SVEFPIndexedTiedPattern<OpNode, nxv8f16, nxv8i1, f16, !cast<Instruction>(INST # "_H"), ZPR16, VectorIndexH>;
+  def : SVEFPIndexedTiedPattern<OpNode, nxv4f32, nxv4i1, f32, !cast<Instruction>(INST # "_S"), ZPR32, VectorIndexS>;
+  def : SVEFPIndexedTiedPattern<OpNode, nxv2f64, nxv2i1, f64, !cast<Instruction>(INST # "_D"), ZPR64, VectorIndexD>;
+}
 
 //===----------------------------------------------------------------------===//
 // SVE Floating Point Multiply - Indexed Group
Index: llvm/test/CodeGen/AArch64/sve-fma.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/sve-fma.ll
@@ -0,0 +1,148 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
+
+define <vscale x 8 x half> @sve_fma_nxv8f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) {
+; CHECK-LABEL: sve_fma_nxv8f16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fmla z1.h, z0.h, z2.h[0]
+; CHECK-NEXT:    mov z0.d, z1.d
+; CHECK-NEXT:    ret
+  %b0splat = shufflevector <vscale x 8 x half> %b, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+  %mad = call <vscale x 8 x half> @llvm.fma.nxv8f16(<vscale x 8 x half> %b0splat, <vscale x 8 x half> %a, <vscale x 8 x half> %c)
+  ret <vscale x 8 x half> %mad
+}
+
+define <vscale x 4 x float> @sve_fma_nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c) {
+; CHECK-LABEL: sve_fma_nxv4f32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fmla z1.s, z0.s, z2.s[0]
+; CHECK-NEXT:    mov z0.d, z1.d
+; CHECK-NEXT:    ret
+  %b0splat = shufflevector <vscale x 4 x float> %b, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+  %mad = call <vscale x 4 x float> @llvm.fma.nxv4f32(<vscale x 4 x float> %b0splat, <vscale x 4 x float> %a, <vscale x 4 x float> %c)
+  ret <vscale x 4 x float> %mad
+}
+
+define <vscale x 2 x double> @sve_fma_nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b, <vscale x 2 x double> %c) {
+; CHECK-LABEL: sve_fma_nxv2f64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fmla z1.d, z0.d, z2.d[0]
+; CHECK-NEXT:    mov z0.d, z1.d
+; CHECK-NEXT:    ret
+  %b0splat = shufflevector <vscale x 2 x double> %b, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
+  %mad = call <vscale x 2 x double> @llvm.fma.nxv2f64(<vscale x 2 x double> %b0splat, <vscale x 2 x double> %a, <vscale x 2 x double> %c)
+  ret <vscale x 2 x double> %mad
+}
+
+define <vscale x 8 x half> @sve_fmuladd_nxv8f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) {
+; CHECK-LABEL: sve_fmuladd_nxv8f16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fmla z1.h, z0.h, z2.h[0]
+; CHECK-NEXT:    mov z0.d, z1.d
+; CHECK-NEXT:    ret
+  %b0splat = shufflevector <vscale x 8 x half> %b, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+  %mad = call <vscale x 8 x half> @llvm.fmuladd.nxv8f16(<vscale x 8 x half> %b0splat, <vscale x 8 x half> %a, <vscale x 8 x half> %c)
+  ret <vscale x 8 x half> %mad
+}
+
+define <vscale x 4 x float> @sve_fmuladd_nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c) {
+; CHECK-LABEL: sve_fmuladd_nxv4f32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fmla z1.s, z0.s, z2.s[0]
+; CHECK-NEXT:    mov z0.d, z1.d
+; CHECK-NEXT:    ret
+  %b0splat = shufflevector <vscale x 4 x float> %b, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+  %mad = call <vscale x 4 x float> @llvm.fmuladd.nxv4f32(<vscale x 4 x float> %b0splat, <vscale x 4 x float> %a, <vscale x 4 x float> %c)
+  ret <vscale x 4 x float> %mad
+}
+
+define <vscale x 2 x double> @sve_fmuladd_nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b, <vscale x 2 x double> %c) {
+; CHECK-LABEL: sve_fmuladd_nxv2f64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fmla z1.d, z0.d, z2.d[0]
+; CHECK-NEXT:    mov z0.d, z1.d
+; CHECK-NEXT:    ret
+  %b0splat = shufflevector <vscale x 2 x double> %b, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
+  %mad = call <vscale x 2 x double> @llvm.fmuladd.nxv2f64(<vscale x 2 x double> %b0splat, <vscale x 2 x double> %a, <vscale x 2 x double> %c)
+  ret <vscale x 2 x double> %mad
+}
+
+define <vscale x 8 x half> @sve_fmls_nxv8f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) {
+; CHECK-LABEL: sve_fmls_nxv8f16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fmls z1.h, z0.h, z2.h[0]
+; CHECK-NEXT:    mov z0.d, z1.d
+; CHECK-NEXT:    ret
+  %b0splat = shufflevector <vscale x 8 x half> %b, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+  %b0splat_neg = fneg <vscale x 8 x half> %b0splat
+  %mad = call <vscale x 8 x half> @llvm.fmuladd.nxv8f16(<vscale x 8 x half> %b0splat_neg, <vscale x 8 x half> %a, <vscale x 8 x half> %c)
+  ret <vscale x 8 x half> %mad
+}
+
+define <vscale x 4 x float> @sve_fmls_nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c) {
+; CHECK-LABEL: sve_fmls_nxv4f32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fmls z1.s, z0.s, z2.s[0]
+; CHECK-NEXT:    mov z0.d, z1.d
+; CHECK-NEXT:    ret
+  %b0splat = shufflevector <vscale x 4 x float> %b, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+  %b0splat_neg = fneg <vscale x 4 x float> %b0splat
+  %mad = call <vscale x 4 x float> @llvm.fmuladd.nxv4f32(<vscale x 4 x float> %b0splat_neg, <vscale x 4 x float> %a, <vscale x 4 x float> %c)
+  ret <vscale x 4 x float> %mad
+}
+
+define <vscale x 2 x double> @sve_fmls_nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b, <vscale x 2 x double> %c) {
+; CHECK-LABEL: sve_fmls_nxv2f64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fmls z1.d, z0.d, z2.d[0]
+; CHECK-NEXT:    mov z0.d, z1.d
+; CHECK-NEXT:    ret
+  %b0splat = shufflevector <vscale x 2 x double> %b, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
+  %b0splat_neg = fneg <vscale x 2 x double> %b0splat
+  %mad = call <vscale x 2 x double> @llvm.fmuladd.nxv2f64(<vscale x 2 x double> %b0splat_neg, <vscale x 2 x double> %a, <vscale x 2 x double> %c)
+  ret <vscale x 2 x double> %mad
+}
+
+define <vscale x 8 x half> @sve_fmls_nxv8f16_1(<vscale x 8 x half> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) {
+; CHECK-LABEL: sve_fmls_nxv8f16_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fmls z1.h, z0.h, z2.h[0]
+; CHECK-NEXT:    mov z0.d, z1.d
+; CHECK-NEXT:    ret
+  %b0splat = shufflevector <vscale x 8 x half> %b, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+  %b0splat_neg = fneg <vscale x 8 x half> %b0splat
+  %mad = call <vscale x 8 x half> @llvm.fmuladd.nxv8f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b0splat_neg, <vscale x 8 x half> %c)
+  ret <vscale x 8 x half> %mad
+}
+
+define <vscale x 4 x float> @sve_fmls_nxv4f32_1(<vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c) {
+; CHECK-LABEL: sve_fmls_nxv4f32_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fmls z1.s, z0.s, z2.s[0]
+; CHECK-NEXT:    mov z0.d, z1.d
+; CHECK-NEXT:    ret
+  %b0splat = shufflevector <vscale x 4 x float> %b, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+  %b0splat_neg = fneg <vscale x 4 x float> %b0splat
+  %mad = call <vscale x 4 x float> @llvm.fmuladd.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b0splat_neg, <vscale x 4 x float> %c)
+  ret <vscale x 4 x float> %mad
+}
+
+define <vscale x 2 x double> @sve_fmls_nxv2f64_1(<vscale x 2 x double> %a, <vscale x 2 x double> %b, <vscale x 2 x double> %c) {
+; CHECK-LABEL: sve_fmls_nxv2f64_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fmls z1.d, z0.d, z2.d[0]
+; CHECK-NEXT:    mov z0.d, z1.d
+; CHECK-NEXT:    ret
+  %b0splat = shufflevector <vscale x 2 x double> %b, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
+  %b0splat_neg = fneg <vscale x 2 x double> %b0splat
+  %mad = call <vscale x 2 x double> @llvm.fmuladd.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b0splat_neg, <vscale x 2 x double> %c)
+  ret <vscale x 2 x double> %mad
+}
+
+declare <vscale x 8 x half> @llvm.fma.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>)
+declare <vscale x 4 x float> @llvm.fma.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>)
+declare <vscale x 2 x double> @llvm.fma.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>)
+
+declare <vscale x 8 x half> @llvm.fmuladd.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>)
+declare <vscale x 4 x float> @llvm.fmuladd.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>)
+declare <vscale x 2 x double> @llvm.fmuladd.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>)