Index: lib/Target/Mips/AsmParser/MipsAsmParser.cpp =================================================================== --- lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -938,6 +938,15 @@ Inst.addOperand(MCOperand::createImm(Imm)); } + template + void addUImmOperands(MCInst &Inst, unsigned N) const { + if (isImm() && !isConstantImm()) { + addExpr(Inst, getImm()); + return; + } + addConstantUImmOperands(Inst, N); + } + void addImmOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); const MCExpr *Expr = getImm(); @@ -1003,6 +1012,14 @@ template bool isConstantUImm() const { return isConstantImm() && isUInt(getConstantImm() - Offset); } + template bool isUImm() const { + return isConstantImm() ? isUInt(getConstantImm()) : isImm(); + } + template bool isAnyImm() const { + return isConstantImm() ? (isInt(getConstantImm()) || + isUInt(getConstantImm())) + : isImm(); + } template bool isConstantSImm() const { return isConstantImm() && isInt(getConstantImm()); } @@ -1851,12 +1868,6 @@ if (Imm < -1 || Imm > 14) return Error(IDLoc, "immediate operand value out of range"); break; - case Mips::TEQ_MM: - case Mips::TGE_MM: - case Mips::TGEU_MM: - case Mips::TLT_MM: - case Mips::TLTU_MM: - case Mips::TNE_MM: case Mips::SB16_MM: case Mips::SB16_MMR6: Opnd = Inst.getOperand(2); @@ -3668,6 +3679,10 @@ case Match_UImm10_0: return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 10-bit unsigned immediate"); + case Match_UImm16: + case Match_UImm16_Relaxed: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), + "expected 16-bit unsigned immediate"); } llvm_unreachable("Implement any new match types added!"); Index: lib/Target/Mips/MicroMips32r6InstrInfo.td =================================================================== --- lib/Target/Mips/MicroMips32r6InstrInfo.td +++ lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -504,12 +504,12 @@ class MOD_MMR6_DESC : ArithLogicR<"mod", GPR32Opnd>; class MODU_MMR6_DESC : ArithLogicR<"modu", GPR32Opnd>; class AND_MMR6_DESC : ArithLogicR<"and", GPR32Opnd>; -class ANDI_MMR6_DESC : ArithLogicI<"andi", simm16, GPR32Opnd>; +class ANDI_MMR6_DESC : ArithLogicI<"andi", uimm16, GPR32Opnd>; class NOR_MMR6_DESC : ArithLogicR<"nor", GPR32Opnd>; class OR_MMR6_DESC : ArithLogicR<"or", GPR32Opnd>; -class ORI_MMR6_DESC : ArithLogicI<"ori", simm16, GPR32Opnd>; +class ORI_MMR6_DESC : ArithLogicI<"ori", uimm16, GPR32Opnd>; class XOR_MMR6_DESC : ArithLogicR<"xor", GPR32Opnd>; -class XORI_MMR6_DESC : ArithLogicI<"xori", simm16, GPR32Opnd>; +class XORI_MMR6_DESC : ArithLogicI<"xori", uimm16, GPR32Opnd>; class SWE_MMR6_DESC_BASE Pattern = [(set GPR32Opnd:$rt, (int_mips_rddsp immZExt10:$mask))]; + list Pattern = [(set GPR32Opnd:$rt, (int_mips_rddsp immZExt7:$mask))]; InstrItinClass Itinerary = NoItinerary; } class REPL_QB_MM_DESC { dag OutOperandList = (outs DSPROpnd:$rt); - dag InOperandList = (ins uimm16:$imm); + dag InOperandList = (ins uimm8:$imm); string AsmString = !strconcat("repl.qb", "\t$rt, $imm"); list Pattern = [(set DSPROpnd:$rt, (int_mips_repl_qb immZExt8:$imm))]; InstrItinClass Itinerary = NoItinerary; Index: lib/Target/Mips/MicroMipsInstrInfo.td =================================================================== --- lib/Target/Mips/MicroMipsInstrInfo.td +++ lib/Target/Mips/MicroMipsInstrInfo.td @@ -681,7 +681,7 @@ ADDI_FM_MM<0x14>; def XORi_MM : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd>, ADDI_FM_MM<0x1c>; - def LUi_MM : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM_MM; + def LUi_MM : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16_relaxed>, LUI_FM_MM; def LEA_ADDiu_MM : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM_MM<0xc>; @@ -901,12 +901,12 @@ ISA_MIPS32R2; /// Trap Instructions - def TEQ_MM : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM_MM<0x0>; - def TGE_MM : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM_MM<0x08>; - def TGEU_MM : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM_MM<0x10>; - def TLT_MM : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM_MM<0x20>; - def TLTU_MM : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM_MM<0x28>; - def TNE_MM : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM_MM<0x30>; + def TEQ_MM : MMRel, TEQ_FT<"teq", GPR32Opnd, uimm4>, TEQ_FM_MM<0x0>; + def TGE_MM : MMRel, TEQ_FT<"tge", GPR32Opnd, uimm4>, TEQ_FM_MM<0x08>; + def TGEU_MM : MMRel, TEQ_FT<"tgeu", GPR32Opnd, uimm4>, TEQ_FM_MM<0x10>; + def TLT_MM : MMRel, TEQ_FT<"tlt", GPR32Opnd, uimm4>, TEQ_FM_MM<0x20>; + def TLTU_MM : MMRel, TEQ_FT<"tltu", GPR32Opnd, uimm4>, TEQ_FM_MM<0x28>; + def TNE_MM : MMRel, TEQ_FT<"tne", GPR32Opnd, uimm4>, TEQ_FM_MM<0x30>; def TEQI_MM : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM_MM<0x0e>; def TGEI_MM : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM_MM<0x09>; Index: lib/Target/Mips/Mips64InstrInfo.td =================================================================== --- lib/Target/Mips/Mips64InstrInfo.td +++ lib/Target/Mips/Mips64InstrInfo.td @@ -15,11 +15,6 @@ // Mips Operand, Complex Patterns and Transformations Definitions. //===----------------------------------------------------------------------===// -// Unsigned Operand -def uimm16_64 : Operand { - let PrintMethod = "printUnsignedImm"; -} - // Signed Operand def simm10_64 : Operand; @@ -113,7 +108,7 @@ ADDI_FM<0xd>; def XORi64 : ArithLogicI<"xori", uimm16_64, GPR64Opnd, II_XOR, immZExt16, xor>, ADDI_FM<0xe>; -def LUi64 : LoadUpper<"lui", GPR64Opnd, uimm16_64>, LUI_FM; +def LUi64 : LoadUpper<"lui", GPR64Opnd, uimm16_64_relaxed>, LUI_FM; } /// Arithmetic Instructions (3-Operand, R-Type) Index: lib/Target/Mips/MipsDSPInstrInfo.td =================================================================== --- lib/Target/Mips/MipsDSPInstrInfo.td +++ lib/Target/Mips/MipsDSPInstrInfo.td @@ -16,7 +16,6 @@ def immZExt2 : ImmLeaf(Imm);}]>; def immZExt3 : ImmLeaf(Imm);}]>; def immZExt4 : ImmLeaf(Imm);}]>; -def immZExt7 : ImmLeaf(Imm);}]>; def immZExt8 : ImmLeaf(Imm);}]>; def immZExt10 : ImmLeaf(Imm);}]>; def immSExt6 : ImmLeaf(Imm);}]>; @@ -324,9 +323,10 @@ } class REPL_DESC_BASE { + Operand ImmOp, ImmLeaf immPat, InstrItinClass itin, + RegisterOperand RO> { dag OutOperandList = (outs RO:$rd); - dag InOperandList = (ins uimm16:$imm); + dag InOperandList = (ins ImmOp:$imm); string AsmString = !strconcat(instr_asm, "\t$rd, $imm"); list Pattern = [(set RO:$rd, (OpNode immPat:$imm))]; InstrItinClass Itinerary = itin; @@ -401,7 +401,7 @@ class EXTR_W_TY1_R1_DESC_BASE { dag OutOperandList = (outs GPR32Opnd:$rt); - dag InOperandList = (ins ACC64DSPOpnd:$ac, uimm16:$shift_rs); + dag InOperandList = (ins ACC64DSPOpnd:$ac, uimm5:$shift_rs); string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs"); InstrItinClass Itinerary = itin; string BaseOpcode = instr_asm; @@ -440,7 +440,7 @@ class RDDSP_DESC_BASE { dag OutOperandList = (outs GPR32Opnd:$rd); - dag InOperandList = (ins uimm16:$mask); + dag InOperandList = (ins uimm10:$mask); string AsmString = !strconcat(instr_asm, "\t$rd, $mask"); list Pattern = [(set GPR32Opnd:$rd, (OpNode immZExt10:$mask))]; InstrItinClass Itinerary = itin; @@ -845,11 +845,11 @@ class PACKRL_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"packrl.ph", int_mips_packrl_ph, NoItinerary, DSPROpnd, DSPROpnd>; -class REPL_QB_DESC : REPL_DESC_BASE<"repl.qb", int_mips_repl_qb, immZExt8, - NoItinerary, DSPROpnd>; +class REPL_QB_DESC : REPL_DESC_BASE<"repl.qb", int_mips_repl_qb, uimm8, + immZExt8, NoItinerary, DSPROpnd>; -class REPL_PH_DESC : REPL_DESC_BASE<"repl.ph", int_mips_repl_ph, immZExt10, - NoItinerary, DSPROpnd>; +class REPL_PH_DESC : REPL_DESC_BASE<"repl.ph", int_mips_repl_ph, uimm10, + immZExt10, NoItinerary, DSPROpnd>; class REPLV_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.qb", int_mips_repl_qb, NoItinerary, DSPROpnd, GPR32Opnd>; Index: lib/Target/Mips/MipsInstrInfo.td =================================================================== --- lib/Target/Mips/MipsInstrInfo.td +++ lib/Target/Mips/MipsInstrInfo.td @@ -403,8 +403,25 @@ let DiagnosticType = "UImm" # Bits # "_" # Offset; } +class UImmAsmOperandClass Supers = []> + : AsmOperandClass { + let Name = "UImm" # Bits; + let RenderMethod = "addUImmOperands<" # Bits # ">"; + let PredicateMethod = "isUImm<" # Bits # ">"; + let SuperClasses = Supers; + let DiagnosticType = "UImm" # Bits; +} + +def UImm16RelaxedAsmOperandClass + : UImmAsmOperandClass<16, []> { + let Name = "UImm16_Relaxed"; + let PredicateMethod = "isAnyImm<16>"; + let DiagnosticType = "UImm16_Relaxed"; +} +def UImm16AsmOperandClass + : UImmAsmOperandClass<16, [UImm16RelaxedAsmOperandClass]>; def ConstantUImm10AsmOperandClass - : ConstantUImmAsmOperandClass<10, []>; + : ConstantUImmAsmOperandClass<10, [UImm16AsmOperandClass]>; def ConstantUImm8AsmOperandClass : ConstantUImmAsmOperandClass<8, [ConstantUImm10AsmOperandClass]>; def ConstantUImm7AsmOperandClass @@ -575,6 +592,20 @@ let ParserMatchClass = ConstantUImm5Plus32NormalizeAsmOperandClass; } +foreach I = {16} in + def uimm # I : Operand { + let PrintMethod = "printUnsignedImm"; + let ParserMatchClass = + !cast("UImm" # I # "AsmOperandClass"); + } + +// Like uimm16_64 but coerces simm16 to uimm16. +def uimm16_relaxed : Operand { + let PrintMethod = "printUnsignedImm"; + let ParserMatchClass = + !cast("UImm16RelaxedAsmOperandClass"); +} + foreach I = {5} in def uimm # I # _64 : Operand { let PrintMethod = "printUnsignedImm"; @@ -582,6 +613,19 @@ !cast("ConstantUImm" # I # "AsmOperandClass"); } +def uimm16_64 : Operand { + let PrintMethod = "printUnsignedImm"; + let ParserMatchClass = + !cast("UImm16AsmOperandClass"); +} + +// Like uimm16_64 but coerces simm16 to uimm16. +def uimm16_64_relaxed : Operand { + let PrintMethod = "printUnsignedImm"; + let ParserMatchClass = + !cast("UImm16RelaxedAsmOperandClass"); +} + // Like uimm5_64 but reports a less confusing error for 32-63 when // an instruction alias permits that. def uimm5_64_report_uimm6 : Operand { @@ -589,10 +633,6 @@ let ParserMatchClass = ConstantUImm5ReportUImm6AsmOperandClass; } -def uimm16 : Operand { - let PrintMethod = "printUnsignedImm"; -} - def pcrel16 : Operand { } @@ -735,6 +775,9 @@ // e.g. addi, andi def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>; +// Node immediate fits as 7-bit zero extended on target immediate. +def immZExt7 : PatLeaf<(imm), [{ return isUInt<7>(N->getZExtValue()); }]>; + // Node immediate fits as 16-bit zero extended on target immediate. // The LO16 param means that only the lower 16 bits of the node // immediate are caught. @@ -1084,15 +1127,19 @@ let DecoderMethod = "DecodeSyncI"; } -let hasSideEffects = 1 in -class TEQ_FT : - InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_), +class TEQ_FT : + InstSE<(outs), (ins RO:$rs, RO:$rt, ImmOp:$code_), !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary, - FrmI, opstr>; + FrmI, opstr> { + let hasSideEffects = 1; +} class TEQI_FT : - InstSE<(outs), (ins RO:$rs, uimm16:$imm16), - !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>; + InstSE<(outs), (ins RO:$rs, simm16:$imm16), + !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr> { + let hasSideEffects = 1; +} + // Mul, Div class Mult DefRegs> : @@ -1350,7 +1397,7 @@ def XORi : MMRel, StdMMR6Rel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16, xor>, ADDI_FM<0xe>; -def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM; +def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16_relaxed>, LUI_FM; let AdditionalPredicates = [NotInMicroMips] in { /// Arithmetic Instructions (3-Operand, R-Type) def ADDu : MMRel, StdMMR6Rel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>, @@ -1456,12 +1503,12 @@ def SYNCI : MMRel, StdMMR6Rel, SYNCI_FT<"synci">, SYNCI_FM, ISA_MIPS32R2; let AdditionalPredicates = [NotInMicroMips] in { - def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>, ISA_MIPS2; - def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>, ISA_MIPS2; - def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>, ISA_MIPS2; - def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>, ISA_MIPS2; - def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>, ISA_MIPS2; - def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>, ISA_MIPS2; + def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd, uimm10>, TEQ_FM<0x34>, ISA_MIPS2; + def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd, uimm10>, TEQ_FM<0x30>, ISA_MIPS2; + def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd, uimm10>, TEQ_FM<0x31>, ISA_MIPS2; + def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd, uimm10>, TEQ_FM<0x32>, ISA_MIPS2; + def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd, uimm10>, TEQ_FM<0x33>, ISA_MIPS2; + def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd, uimm10>, TEQ_FM<0x36>, ISA_MIPS2; } def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>, @@ -1855,13 +1902,13 @@ def : MipsInstAlias<"sltu $rt, $rs, $imm", (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm16:$imm), 0>; def : MipsInstAlias<"xor $rs, $rt, $imm", - (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>; + (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32:$imm), 0>; def : MipsInstAlias<"xor $rs, $imm", - (XORi GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>; + (XORi GPR32Opnd:$rs, GPR32Opnd:$rs, simm32:$imm), 0>; def : MipsInstAlias<"or $rs, $rt, $imm", - (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>; + (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32:$imm), 0>; def : MipsInstAlias<"or $rs, $imm", - (ORi GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>; + (ORi GPR32Opnd:$rs, GPR32Opnd:$rs, simm32:$imm), 0>; let AdditionalPredicates = [NotInMicroMips] in { def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>; } Index: test/MC/Disassembler/Mips/mips2/valid-mips2-el.txt =================================================================== --- test/MC/Disassembler/Mips/mips2/valid-mips2-el.txt +++ test/MC/Disassembler/Mips/mips2/valid-mips2-el.txt @@ -136,11 +136,11 @@ 0x22 0x98 0xd1 0xb9 # CHECK: swr $17, -26590($14) 0x34 0x00 0x03 0x00 # CHECK: teq $zero, $3 0x34 0x9b 0xa7 0x00 # CHECK: teq $5, $7, 620 -0xa0 0xbb 0xac 0x06 # CHECK: teqi $21, 48032 +0xa0 0xbb 0xac 0x06 # CHECK: teqi $21, -17504 0x30 0x00 0xea 0x00 # CHECK: tge $7, $10 0x30 0x55 0xb3 0x00 # CHECK: tge $5, $19, 340 0xa1 0x13 0x28 0x06 # CHECK: tgei $17, 5025 -0x33 0x90 0xa9 0x07 # CHECK: tgeiu $sp, 36915 +0x33 0x90 0xa9 0x07 # CHECK: tgeiu $sp, -28621 0x31 0x00 0xdc 0x02 # CHECK: tgeu $22, $gp 0xf1 0x5e 0x8e 0x02 # CHECK: tgeu $20, $14, 379 0x08 0x00 0x00 0x42 # CHECK: tlbp @@ -149,13 +149,13 @@ 0x06 0x00 0x00 0x42 # CHECK: tlbwr 0x32 0x00 0xed 0x01 # CHECK: tlt $15, $13 0x72 0x21 0x53 0x00 # CHECK: tlt $2, $19, 133 -0xbd 0xad 0xca 0x05 # CHECK: tlti $14, 44477 -0x2c 0xec 0xeb 0x07 # CHECK: tltiu $ra, 60460 +0xbd 0xad 0xca 0x05 # CHECK: tlti $14, -21059 +0x2c 0xec 0xeb 0x07 # CHECK: tltiu $ra, -5076 0x33 0x00 0x70 0x01 # CHECK: tltu $11, $16 0x33 0xfe 0x1d 0x02 # CHECK: tltu $16, $sp, 1016 0x36 0x00 0xd1 0x00 # CHECK: tne $6, $17 0x76 0xdd 0xe8 0x00 # CHECK: tne $7, $8, 885 -0x31 0x8c 0x8e 0x05 # CHECK: tnei $12, 35889 +0x31 0x8c 0x8e 0x05 # CHECK: tnei $12, -29647 0x8d 0x75 0x20 0x46 # CHECK: trunc.w.d $f22, $f14 0x0d 0xf7 0x00 0x46 # CHECK: trunc.w.s $f28, $f30 0x26 0x90 0x9e 0x00 # CHECK: xor $18, $4, $fp Index: test/MC/Disassembler/Mips/mips2/valid-mips2.txt =================================================================== --- test/MC/Disassembler/Mips/mips2/valid-mips2.txt +++ test/MC/Disassembler/Mips/mips2/valid-mips2.txt @@ -72,14 +72,14 @@ 0x04 0xd0 0x14 0x9b # CHECK: bltzal $6, 21104 0x04 0xd1 0x14 0x9b # CHECK: bgezal $6, 21104 0x04 0xd2 0x00 0x7a # CHECK: bltzall $6, 492 -0x05 0x8e 0x8c 0x31 # CHECK: tnei $12, 35889 +0x05 0x8e 0x8c 0x31 # CHECK: tnei $12, -29647 0x05 0x93 0x07 0x1f # CHECK: bgezall $12, 7296 -0x05 0xca 0xad 0xbd # CHECK: tlti $14, 44477 +0x05 0xca 0xad 0xbd # CHECK: tlti $14, -21059 0x06 0x22 0xf6 0x45 # CHECK: bltzl $17, -9960 0x06 0x28 0x13 0xa1 # CHECK: tgei $17, 5025 -0x06 0xac 0xbb 0xa0 # CHECK: teqi $21, 48032 -0x07 0xa9 0x90 0x33 # CHECK: tgeiu $sp, 36915 -0x07 0xeb 0xec 0x2c # CHECK: tltiu $ra, 60460 +0x06 0xac 0xbb 0xa0 # CHECK: teqi $21, -17504 +0x07 0xa9 0x90 0x33 # CHECK: tgeiu $sp, -28621 +0x07 0xeb 0xec 0x2c # CHECK: tltiu $ra, -5076 0x08 0x00 0x00 0x01 # CHECK: j 4 0x09 0x33 0x00 0x2a # CHECK: j 80478376 0x0b 0x2a 0xd1 0x44 # CHECK: j 212550928 Index: test/MC/Disassembler/Mips/mips3/valid-mips3-el.txt =================================================================== --- test/MC/Disassembler/Mips/mips3/valid-mips3-el.txt +++ test/MC/Disassembler/Mips/mips3/valid-mips3-el.txt @@ -184,11 +184,11 @@ 0x22 0x98 0xd1 0xb9 # CHECK: swr $17, -26590($14) 0x34 0x00 0x03 0x00 # CHECK: teq $zero, $3 0x34 0x9b 0xa7 0x00 # CHECK: teq $5, $7, 620 -0xa0 0xbb 0xac 0x06 # CHECK: teqi $21, 48032 +0xa0 0xbb 0xac 0x06 # CHECK: teqi $21, -17504 0x30 0x00 0xea 0x00 # CHECK: tge $7, $10 0x30 0x55 0xb3 0x00 # CHECK: tge $5, $19, 340 0xa1 0x13 0x28 0x06 # CHECK: tgei $17, 5025 -0x33 0x90 0xa9 0x07 # CHECK: tgeiu $sp, 36915 +0x33 0x90 0xa9 0x07 # CHECK: tgeiu $sp, -28621 0x31 0x00 0xdc 0x02 # CHECK: tgeu $22, $gp 0xf1 0x5e 0x8e 0x02 # CHECK: tgeu $20, $14, 379 0x08 0x00 0x00 0x42 # CHECK: tlbp @@ -197,13 +197,13 @@ 0x06 0x00 0x00 0x42 # CHECK: tlbwr 0x32 0x00 0xed 0x01 # CHECK: tlt $15, $13 0x72 0x21 0x53 0x00 # CHECK: tlt $2, $19, 133 -0xbd 0xad 0xca 0x05 # CHECK: tlti $14, 44477 -0x2c 0xec 0xeb 0x07 # CHECK: tltiu $ra, 60460 +0xbd 0xad 0xca 0x05 # CHECK: tlti $14, -21059 +0x2c 0xec 0xeb 0x07 # CHECK: tltiu $ra, -5076 0x33 0x00 0x70 0x01 # CHECK: tltu $11, $16 0x33 0xfe 0x1d 0x02 # CHECK: tltu $16, $sp, 1016 0x36 0x00 0xd1 0x00 # CHECK: tne $6, $17 0x76 0xdd 0xe8 0x00 # CHECK: tne $7, $8, 885 -0x31 0x8c 0x8e 0x05 # CHECK: tnei $12, 35889 +0x31 0x8c 0x8e 0x05 # CHECK: tnei $12, -29647 0xc9 0xbd 0x20 0x46 # CHECK: trunc.l.d $f23, $f23 0x09 0xff 0x00 0x46 # CHECK: trunc.l.s $f28, $f31 0x8d 0x75 0x20 0x46 # CHECK: trunc.w.d $f22, $f14 Index: test/MC/Disassembler/Mips/mips3/valid-mips3.txt =================================================================== --- test/MC/Disassembler/Mips/mips3/valid-mips3.txt +++ test/MC/Disassembler/Mips/mips3/valid-mips3.txt @@ -103,14 +103,14 @@ 0x04 0xd0 0x14 0x9b # CHECK: bltzal $6, 21104 0x04 0xd1 0x14 0x9b # CHECK: bgezal $6, 21104 0x04 0xd2 0x00 0x7a # CHECK: bltzall $6, 492 -0x05 0x8e 0x8c 0x31 # CHECK: tnei $12, 35889 +0x05 0x8e 0x8c 0x31 # CHECK: tnei $12, -29647 0x05 0x93 0x07 0x1f # CHECK: bgezall $12, 7296 -0x05 0xca 0xad 0xbd # CHECK: tlti $14, 44477 +0x05 0xca 0xad 0xbd # CHECK: tlti $14, -21059 0x06 0x22 0xf6 0x45 # CHECK: bltzl $17, -9960 0x06 0x28 0x13 0xa1 # CHECK: tgei $17, 5025 -0x06 0xac 0xbb 0xa0 # CHECK: teqi $21, 48032 -0x07 0xa9 0x90 0x33 # CHECK: tgeiu $sp, 36915 -0x07 0xeb 0xec 0x2c # CHECK: tltiu $ra, 60460 +0x06 0xac 0xbb 0xa0 # CHECK: teqi $21, -17504 +0x07 0xa9 0x90 0x33 # CHECK: tgeiu $sp, -28621 +0x07 0xeb 0xec 0x2c # CHECK: tltiu $ra, -5076 0x08 0x00 0x00 0x01 # CHECK: j 4 0x09 0x33 0x00 0x2a # CHECK: j 80478376 0x0b 0x2a 0xd1 0x44 # CHECK: j 212550928 Index: test/MC/Disassembler/Mips/mips32/valid-mips32.txt =================================================================== --- test/MC/Disassembler/Mips/mips32/valid-mips32.txt +++ test/MC/Disassembler/Mips/mips32/valid-mips32.txt @@ -105,14 +105,14 @@ 0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332 0x04 0xd1 0x14 0x9b # CHECK: bgezal $6, 21104 0x04 0xd2 0x00 0x7a # CHECK: bltzall $6, 492 -0x05 0x8e 0x8c 0x31 # CHECK: tnei $12, 35889 +0x05 0x8e 0x8c 0x31 # CHECK: tnei $12, -29647 0x05 0x93 0x07 0x1f # CHECK: bgezall $12, 7296 -0x05 0xca 0xad 0xbd # CHECK: tlti $14, 44477 +0x05 0xca 0xad 0xbd # CHECK: tlti $14, -21059 0x06 0x22 0xf6 0x45 # CHECK: bltzl $17, -9960 0x06 0x28 0x13 0xa1 # CHECK: tgei $17, 5025 -0x06 0xac 0xbb 0xa0 # CHECK: teqi $21, 48032 -0x07 0xa9 0x90 0x33 # CHECK: tgeiu $sp, 36915 -0x07 0xeb 0xec 0x2c # CHECK: tltiu $ra, 60460 +0x06 0xac 0xbb 0xa0 # CHECK: teqi $21, -17504 +0x07 0xa9 0x90 0x33 # CHECK: tgeiu $sp, -28621 +0x07 0xeb 0xec 0x2c # CHECK: tltiu $ra, -5076 0x08 0x00 0x00 0x01 # CHECK: j 4 0x08 0x00 0x01 0x4c # CHECK: j 1328 0x09 0x33 0x00 0x2a # CHECK: j 80478376 Index: test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt =================================================================== --- test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt +++ test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt @@ -110,15 +110,15 @@ 0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332 0x04 0xd1 0x14 0x9b # CHECK: bgezal $6, 21104 0x04 0xd2 0x00 0x7a # CHECK: bltzall $6, 492 -0x05 0x8e 0x8c 0x31 # CHECK: tnei $12, 35889 +0x05 0x8e 0x8c 0x31 # CHECK: tnei $12, -29647 0x05 0x93 0x07 0x1f # CHECK: bgezall $12, 7296 -0x05 0xca 0xad 0xbd # CHECK: tlti $14, 44477 +0x05 0xca 0xad 0xbd # CHECK: tlti $14, -21059 0x06 0x22 0xf6 0x45 # CHECK: bltzl $17, -9960 0x06 0x28 0x13 0xa1 # CHECK: tgei $17, 5025 -0x06 0xac 0xbb 0xa0 # CHECK: teqi $21, 48032 -0x07 0xa9 0x90 0x33 # CHECK: tgeiu $sp, 36915 +0x06 0xac 0xbb 0xa0 # CHECK: teqi $21, -17504 +0x07 0xa9 0x90 0x33 # CHECK: tgeiu $sp, -28621 0x07 0xdf 0xe8 0x07 # CHECK: synci -6137($fp) -0x07 0xeb 0xec 0x2c # CHECK: tltiu $ra, 60460 +0x07 0xeb 0xec 0x2c # CHECK: tltiu $ra, -5076 0x08 0x00 0x00 0x01 # CHECK: j 4 0x08 0x00 0x01 0x4c # CHECK: j 1328 0x09 0x33 0x00 0x2a # CHECK: j 80478376 Index: test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt =================================================================== --- test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt +++ test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt @@ -107,15 +107,15 @@ 0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332 0x04 0xd1 0x14 0x9b # CHECK: bgezal $6, 21104 0x04 0xd2 0x00 0x7a # CHECK: bltzall $6, 492 -0x05 0x8e 0x8c 0x31 # CHECK: tnei $12, 35889 +0x05 0x8e 0x8c 0x31 # CHECK: tnei $12, -29647 0x05 0x93 0x07 0x1f # CHECK: bgezall $12, 7296 -0x05 0xca 0xad 0xbd # CHECK: tlti $14, 44477 +0x05 0xca 0xad 0xbd # CHECK: tlti $14, -21059 0x06 0x22 0xf6 0x45 # CHECK: bltzl $17, -9960 0x06 0x28 0x13 0xa1 # CHECK: tgei $17, 5025 -0x06 0xac 0xbb 0xa0 # CHECK: teqi $21, 48032 -0x07 0xa9 0x90 0x33 # CHECK: tgeiu $sp, 36915 +0x06 0xac 0xbb 0xa0 # CHECK: teqi $21, -17504 +0x07 0xa9 0x90 0x33 # CHECK: tgeiu $sp, -28621 0x07 0xdf 0xe8 0x07 # CHECK: synci -6137($fp) -0x07 0xeb 0xec 0x2c # CHECK: tltiu $ra, 60460 +0x07 0xeb 0xec 0x2c # CHECK: tltiu $ra, -5076 0x08 0x00 0x00 0x01 # CHECK: j 4 0x08 0x00 0x01 0x4c # CHECK: j 1328 0x09 0x33 0x00 0x2a # CHECK: j 80478376 Index: test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt =================================================================== --- test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt +++ test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt @@ -107,15 +107,15 @@ 0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332 0x04 0xd1 0x14 0x9b # CHECK: bgezal $6, 21104 0x04 0xd2 0x00 0x7a # CHECK: bltzall $6, 492 -0x05 0x8e 0x8c 0x31 # CHECK: tnei $12, 35889 +0x05 0x8e 0x8c 0x31 # CHECK: tnei $12, -29647 0x05 0x93 0x07 0x1f # CHECK: bgezall $12, 7296 -0x05 0xca 0xad 0xbd # CHECK: tlti $14, 44477 +0x05 0xca 0xad 0xbd # CHECK: tlti $14, -21059 0x06 0x22 0xf6 0x45 # CHECK: bltzl $17, -9960 0x06 0x28 0x13 0xa1 # CHECK: tgei $17, 5025 -0x06 0xac 0xbb 0xa0 # CHECK: teqi $21, 48032 -0x07 0xa9 0x90 0x33 # CHECK: tgeiu $sp, 36915 +0x06 0xac 0xbb 0xa0 # CHECK: teqi $21, -17504 +0x07 0xa9 0x90 0x33 # CHECK: tgeiu $sp, -28621 0x07 0xdf 0xe8 0x07 # CHECK: synci -6137($fp) -0x07 0xeb 0xec 0x2c # CHECK: tltiu $ra, 60460 +0x07 0xeb 0xec 0x2c # CHECK: tltiu $ra, -5076 0x08 0x00 0x00 0x01 # CHECK: j 4 0x08 0x00 0x01 0x4c # CHECK: j 1328 0x09 0x33 0x00 0x2a # CHECK: j 80478376 Index: test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt =================================================================== --- test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt +++ test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt @@ -204,11 +204,11 @@ 0x08 0x98 0x4c 0x4f # CHECK: swxc1 $f19, $12($26) 0x34 0x00 0x03 0x00 # CHECK: teq $zero, $3 0x34 0x9b 0xa7 0x00 # CHECK: teq $5, $7, 620 -0xa0 0xbb 0xac 0x06 # CHECK: teqi $21, 48032 +0xa0 0xbb 0xac 0x06 # CHECK: teqi $21, -17504 0x30 0x00 0xea 0x00 # CHECK: tge $7, $10 0x30 0x55 0xb3 0x00 # CHECK: tge $5, $19, 340 0xa1 0x13 0x28 0x06 # CHECK: tgei $17, 5025 -0x33 0x90 0xa9 0x07 # CHECK: tgeiu $sp, 36915 +0x33 0x90 0xa9 0x07 # CHECK: tgeiu $sp, -28621 0x31 0x00 0xdc 0x02 # CHECK: tgeu $22, $gp 0xf1 0x5e 0x8e 0x02 # CHECK: tgeu $20, $14, 379 0x08 0x00 0x00 0x42 # CHECK: tlbp @@ -217,13 +217,13 @@ 0x06 0x00 0x00 0x42 # CHECK: tlbwr 0x32 0x00 0xed 0x01 # CHECK: tlt $15, $13 0x72 0x21 0x53 0x00 # CHECK: tlt $2, $19, 133 -0xbd 0xad 0xca 0x05 # CHECK: tlti $14, 44477 -0x2c 0xec 0xeb 0x07 # CHECK: tltiu $ra, 60460 +0xbd 0xad 0xca 0x05 # CHECK: tlti $14, -21059 +0x2c 0xec 0xeb 0x07 # CHECK: tltiu $ra, -5076 0x33 0x00 0x70 0x01 # CHECK: tltu $11, $16 0x33 0xfe 0x1d 0x02 # CHECK: tltu $16, $sp, 1016 0x36 0x00 0xd1 0x00 # CHECK: tne $6, $17 0x76 0xdd 0xe8 0x00 # CHECK: tne $7, $8, 885 -0x31 0x8c 0x8e 0x05 # CHECK: tnei $12, 35889 +0x31 0x8c 0x8e 0x05 # CHECK: tnei $12, -29647 0xc9 0xbd 0x20 0x46 # CHECK: trunc.l.d $f23, $f23 0x09 0xff 0x00 0x46 # CHECK: trunc.l.s $f28, $f31 0x8d 0x75 0x20 0x46 # CHECK: trunc.w.d $f22, $f14 Index: test/MC/Disassembler/Mips/mips4/valid-mips4.txt =================================================================== --- test/MC/Disassembler/Mips/mips4/valid-mips4.txt +++ test/MC/Disassembler/Mips/mips4/valid-mips4.txt @@ -107,14 +107,14 @@ 0x04 0xd0 0x14 0x9b # CHECK: bltzal $6, 21104 0x04 0xd1 0x14 0x9b # CHECK: bgezal $6, 21104 0x04 0xd2 0x00 0x7a # CHECK: bltzall $6, 492 -0x05 0x8e 0x8c 0x31 # CHECK: tnei $12, 35889 +0x05 0x8e 0x8c 0x31 # CHECK: tnei $12, -29647 0x05 0x93 0x07 0x1f # CHECK: bgezall $12, 7296 -0x05 0xca 0xad 0xbd # CHECK: tlti $14, 44477 +0x05 0xca 0xad 0xbd # CHECK: tlti $14, -21059 0x06 0x22 0xf6 0x45 # CHECK: bltzl $17, -9960 0x06 0x28 0x13 0xa1 # CHECK: tgei $17, 5025 -0x06 0xac 0xbb 0xa0 # CHECK: teqi $21, 48032 -0x07 0xa9 0x90 0x33 # CHECK: tgeiu $sp, 36915 -0x07 0xeb 0xec 0x2c # CHECK: tltiu $ra, 60460 +0x06 0xac 0xbb 0xa0 # CHECK: teqi $21, -17504 +0x07 0xa9 0x90 0x33 # CHECK: tgeiu $sp, -28621 +0x07 0xeb 0xec 0x2c # CHECK: tltiu $ra, -5076 0x08 0x00 0x00 0x01 # CHECK: j 4 0x09 0x33 0x00 0x2a # CHECK: j 80478376 0x0b 0x2a 0xd1 0x44 # CHECK: j 212550928 Index: test/MC/Disassembler/Mips/mips64/valid-mips64.txt =================================================================== --- test/MC/Disassembler/Mips/mips64/valid-mips64.txt +++ test/MC/Disassembler/Mips/mips64/valid-mips64.txt @@ -147,14 +147,14 @@ 0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332 0x04 0xd1 0x14 0x9b # CHECK: bgezal $6, 21104 0x04 0xd2 0x00 0x7a # CHECK: bltzall $6, 492 -0x05 0x8e 0x8c 0x31 # CHECK: tnei $12, 35889 +0x05 0x8e 0x8c 0x31 # CHECK: tnei $12, -29647 0x05 0x93 0x07 0x1f # CHECK: bgezall $12, 7296 -0x05 0xca 0xad 0xbd # CHECK: tlti $14, 44477 +0x05 0xca 0xad 0xbd # CHECK: tlti $14, -21059 0x06 0x22 0xf6 0x45 # CHECK: bltzl $17, -9960 0x06 0x28 0x13 0xa1 # CHECK: tgei $17, 5025 -0x06 0xac 0xbb 0xa0 # CHECK: teqi $21, 48032 -0x07 0xa9 0x90 0x33 # CHECK: tgeiu $sp, 36915 -0x07 0xeb 0xec 0x2c # CHECK: tltiu $ra, 60460 +0x06 0xac 0xbb 0xa0 # CHECK: teqi $21, -17504 +0x07 0xa9 0x90 0x33 # CHECK: tgeiu $sp, -28621 +0x07 0xeb 0xec 0x2c # CHECK: tltiu $ra, -5076 0x08 0x00 0x00 0x01 # CHECK: j 4 0x08 0x00 0x01 0x4c # CHECK: j 1328 0x09 0x33 0x00 0x2a # CHECK: j 80478376 Index: test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt =================================================================== --- test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt +++ test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt @@ -161,14 +161,14 @@ 0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332 0x04 0xd1 0x14 0x9b # CHECK: bgezal $6, 21104 0x04 0xd2 0x00 0x7a # CHECK: bltzall $6, 492 -0x05 0x8e 0x8c 0x31 # CHECK: tnei $12, 35889 +0x05 0x8e 0x8c 0x31 # CHECK: tnei $12, -29647 0x05 0x93 0x07 0x1f # CHECK: bgezall $12, 7296 -0x05 0xca 0xad 0xbd # CHECK: tlti $14, 44477 +0x05 0xca 0xad 0xbd # CHECK: tlti $14, -21059 0x06 0x22 0xf6 0x45 # CHECK: bltzl $17, -9960 0x06 0x28 0x13 0xa1 # CHECK: tgei $17, 5025 -0x06 0xac 0xbb 0xa0 # CHECK: teqi $21, 48032 -0x07 0xa9 0x90 0x33 # CHECK: tgeiu $sp, 36915 -0x07 0xeb 0xec 0x2c # CHECK: tltiu $ra, 60460 +0x06 0xac 0xbb 0xa0 # CHECK: teqi $21, -17504 +0x07 0xa9 0x90 0x33 # CHECK: tgeiu $sp, -28621 +0x07 0xeb 0xec 0x2c # CHECK: tltiu $ra, -5076 0x08 0x00 0x00 0x01 # CHECK: j 4 0x08 0x00 0x01 0x4c # CHECK: j 1328 0x09 0x33 0x00 0x2a # CHECK: j 80478376 Index: test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt =================================================================== --- test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt +++ test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt @@ -158,14 +158,14 @@ 0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332 0x04 0xd1 0x14 0x9b # CHECK: bgezal $6, 21104 0x04 0xd2 0x00 0x7a # CHECK: bltzall $6, 492 -0x05 0x8e 0x8c 0x31 # CHECK: tnei $12, 35889 +0x05 0x8e 0x8c 0x31 # CHECK: tnei $12, -29647 0x05 0x93 0x07 0x1f # CHECK: bgezall $12, 7296 -0x05 0xca 0xad 0xbd # CHECK: tlti $14, 44477 +0x05 0xca 0xad 0xbd # CHECK: tlti $14, -21059 0x06 0x22 0xf6 0x45 # CHECK: bltzl $17, -9960 0x06 0x28 0x13 0xa1 # CHECK: tgei $17, 5025 -0x06 0xac 0xbb 0xa0 # CHECK: teqi $21, 48032 -0x07 0xa9 0x90 0x33 # CHECK: tgeiu $sp, 36915 -0x07 0xeb 0xec 0x2c # CHECK: tltiu $ra, 60460 +0x06 0xac 0xbb 0xa0 # CHECK: teqi $21, -17504 +0x07 0xa9 0x90 0x33 # CHECK: tgeiu $sp, -28621 +0x07 0xeb 0xec 0x2c # CHECK: tltiu $ra, -5076 0x08 0x00 0x00 0x01 # CHECK: j 4 0x08 0x00 0x01 0x4c # CHECK: j 1328 0x09 0x33 0x00 0x2a # CHECK: j 80478376 Index: test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt =================================================================== --- test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt +++ test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt @@ -158,14 +158,14 @@ 0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332 0x04 0xd1 0x14 0x9b # CHECK: bgezal $6, 21104 0x04 0xd2 0x00 0x7a # CHECK: bltzall $6, 492 -0x05 0x8e 0x8c 0x31 # CHECK: tnei $12, 35889 +0x05 0x8e 0x8c 0x31 # CHECK: tnei $12, -29647 0x05 0x93 0x07 0x1f # CHECK: bgezall $12, 7296 -0x05 0xca 0xad 0xbd # CHECK: tlti $14, 44477 +0x05 0xca 0xad 0xbd # CHECK: tlti $14, -21059 0x06 0x22 0xf6 0x45 # CHECK: bltzl $17, -9960 0x06 0x28 0x13 0xa1 # CHECK: tgei $17, 5025 -0x06 0xac 0xbb 0xa0 # CHECK: teqi $21, 48032 -0x07 0xa9 0x90 0x33 # CHECK: tgeiu $sp, 36915 -0x07 0xeb 0xec 0x2c # CHECK: tltiu $ra, 60460 +0x06 0xac 0xbb 0xa0 # CHECK: teqi $21, -17504 +0x07 0xa9 0x90 0x33 # CHECK: tgeiu $sp, -28621 +0x07 0xeb 0xec 0x2c # CHECK: tltiu $ra, -5076 0x08 0x00 0x00 0x01 # CHECK: j 4 0x08 0x00 0x01 0x4c # CHECK: j 1328 0x09 0x33 0x00 0x2a # CHECK: j 80478376 Index: test/MC/Mips/dsp/invalid.s =================================================================== --- test/MC/Mips/dsp/invalid.s +++ test/MC/Mips/dsp/invalid.s @@ -1,25 +1,39 @@ # RUN: not llvm-mc %s -triple=mips-unknown-unknown -show-encoding -mattr=dsp 2>%t1 # RUN: FileCheck %s < %t1 + extp $2, $ac1, -1 # CHECK: :[[@LINE]]:18: error: expected 5-bit unsigned immediate + extp $2, $ac1, 32 # CHECK: :[[@LINE]]:18: error: expected 5-bit unsigned immediate + extpdp $2, $ac1, -1 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate + extpdp $2, $ac1, 32 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate + extr.w $2, $ac1, -1 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate + extr.w $2, $ac1, 32 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate + extr_r.w $2, $ac1, -1 # CHECK: :[[@LINE]]:22: error: expected 5-bit unsigned immediate + extr_r.w $2, $ac1, 32 # CHECK: :[[@LINE]]:22: error: expected 5-bit unsigned immediate + extr_rs.w $2, $ac1, -1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate + extr_rs.w $2, $ac1, 32 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate shll.ph $3, $4, 16 # CHECK: :[[@LINE]]:19: error: expected 4-bit unsigned immediate shll.ph $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 4-bit unsigned immediate shll_s.ph $3, $4, 16 # CHECK: :[[@LINE]]:21: error: expected 4-bit unsigned immediate shll_s.ph $3, $4, -1 # CHECK: :[[@LINE]]:21: error: expected 4-bit unsigned immediate shll.qb $3, $4, 8 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate shll.qb $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate - // FIXME: Following invalid tests are temporarely disabled, until operand check for uimm5 is added - shll_s.w $3, $4, 32 # -CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate - shll_s.w $3, $4, -1 # -CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate + shll_s.w $3, $4, 32 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate + shll_s.w $3, $4, -1 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate shra.ph $3, $4, 16 # CHECK: :[[@LINE]]:19: error: expected 4-bit unsigned immediate shra.ph $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 4-bit unsigned immediate shra_r.ph $3, $4, 16 # CHECK: :[[@LINE]]:21: error: expected 4-bit unsigned immediate shra_r.ph $3, $4, -1 # CHECK: :[[@LINE]]:21: error: expected 4-bit unsigned immediate - // FIXME: Following invalid tests are temporarely disabled, until operand check for uimm5 is added - shra_r.w $3, $4, 32 # -CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate - shra_r.w $3, $4, -1 # -CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate + shra_r.w $3, $4, 32 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate + shra_r.w $3, $4, -1 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate shrl.qb $3, $4, 8 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate shrl.qb $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate shilo $ac1, 64 # CHECK: :[[@LINE]]:15: error: expected 6-bit signed immediate shilo $ac1, -64 # CHECK: :[[@LINE]]:15: error: expected 6-bit signed immediate - wrdsp $5, 1024 # CHECK: :[[@LINE]]:13: error: expected 10-bit unsigned immediate + repl.qb $2, -1 # CHECK: :[[@LINE]]:15: error: expected 8-bit unsigned immediate + repl.qb $2, 256 # CHECK: :[[@LINE]]:15: error: expected 8-bit unsigned immediate + repl.ph $2, -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + repl.ph $2, 1024 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + rddsp $2, -1 # CHECK: :[[@LINE]]:13: error: expected 10-bit unsigned immediate + rddsp $2, 1024 # CHECK: :[[@LINE]]:13: error: expected 10-bit unsigned immediate wrdsp $5, -1 # CHECK: :[[@LINE]]:13: error: expected 10-bit unsigned immediate + wrdsp $5, 1024 # CHECK: :[[@LINE]]:13: error: expected 10-bit unsigned immediate Index: test/MC/Mips/micromips32r6/invalid-wrong-error.s =================================================================== --- /dev/null +++ test/MC/Mips/micromips32r6/invalid-wrong-error.s @@ -0,0 +1,27 @@ +# Instructions that are correctly rejected but emit a wrong or misleading error. +# RUN: not llvm-mc %s -triple=mips -show-encoding -mcpu=mips32r6 -mattr=micromips 2>%t1 +# RUN: FileCheck %s < %t1 + + + # The 10-bit immediate supported by the standard encodings cause us to emit + # the diagnostic for the 10-bit form. This isn't exactly wrong but it is + # misleading. Ideally, we'd emit every way to achieve a valid match instead + # of picking only one. + teq $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + teq $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + teq $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled + tge $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + tge $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + tge $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled + tgeu $8, $9, $2 # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate + tgeu $8, $9, -1 # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate + tgeu $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled + tlt $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + tlt $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + tlt $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled + tltu $8, $9, $2 # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate + tltu $8, $9, -1 # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate + tltu $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled + tne $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + tne $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + tne $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled Index: test/MC/Mips/micromips32r6/invalid.s =================================================================== --- test/MC/Mips/micromips32r6/invalid.s +++ test/MC/Mips/micromips32r6/invalid.s @@ -54,28 +54,16 @@ pref 32, 255($7) # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate teq $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction teq $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - teq $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range tge $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction tge $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - tge $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range tgeu $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction tgeu $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - tgeu $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range tlt $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction tlt $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - tlt $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range tltu $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction tltu $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - tltu $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range tne $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction tne $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - tne $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range - teq $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - tge $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - tgeu $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - tlt $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - tltu $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - tne $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction wait -1 # CHECK: :[[@LINE]]:8: error: expected 10-bit unsigned immediate wait 1024 # CHECK: :[[@LINE]]:8: error: expected 10-bit unsigned immediate wrpgpr $34, $4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction Index: test/MC/Mips/micromips64r6/invalid-wrong-error.s =================================================================== --- /dev/null +++ test/MC/Mips/micromips64r6/invalid-wrong-error.s @@ -0,0 +1,27 @@ +# Instructions that are correctly rejected but emit a wrong or misleading error. +# RUN: not llvm-mc %s -triple=mips -show-encoding -mcpu=mips64r6 -mattr=micromips 2>%t1 +# RUN: FileCheck %s < %t1 + + + # The 10-bit immediate supported by the standard encodings cause us to emit + # the diagnostic for the 10-bit form. This isn't exactly wrong but it is + # misleading. Ideally, we'd emit every way to achieve a valid match instead + # of picking only one. + teq $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + teq $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + teq $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled + tge $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + tge $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + tge $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled + tgeu $8, $9, $2 # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate + tgeu $8, $9, -1 # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate + tgeu $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled + tlt $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + tlt $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + tlt $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled + tltu $8, $9, $2 # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate + tltu $8, $9, -1 # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate + tltu $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled + tne $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + tne $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + tne $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled Index: test/MC/Mips/micromips64r6/invalid.s =================================================================== --- test/MC/Mips/micromips64r6/invalid.s +++ test/MC/Mips/micromips64r6/invalid.s @@ -79,28 +79,16 @@ pref 32, 255($7) # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate teq $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction teq $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - teq $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range tge $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction tge $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - tge $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range tgeu $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction tgeu $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - tgeu $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range tlt $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction tlt $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - tlt $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range tltu $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction tltu $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - tltu $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range tne $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction tne $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - tne $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range - teq $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - tge $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - tgeu $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - tlt $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - tltu $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - tne $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction wrpgpr $34, $4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction wrpgpr $3, $33 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction wsbh $34, $4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction Index: test/MC/Mips/mips32r2/invalid-dsp.s =================================================================== --- test/MC/Mips/mips32r2/invalid-dsp.s +++ test/MC/Mips/mips32r2/invalid-dsp.s @@ -77,7 +77,7 @@ precrq_rs.ph.w $a1,$k0,$a3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled precrqu_s.qb.ph $zero,$gp,$s5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled raddu.w.qb $25,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - repl.ph $at,-307 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + repl.ph $at,307 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled replv.ph $v1,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled replv.qb $25,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled shilo $ac1,26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled Index: test/MC/Mips/mips32r2/invalid-dspr2.s =================================================================== --- test/MC/Mips/mips32r2/invalid-dspr2.s +++ test/MC/Mips/mips32r2/invalid-dspr2.s @@ -103,7 +103,7 @@ precrq_rs.ph.w $a1,$k0,$a3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled precrqu_s.qb.ph $zero,$gp,$s5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled raddu.w.qb $25,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - repl.ph $at,-307 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + repl.ph $at,307 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled replv.ph $v1,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled replv.qb $25,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled shilo $ac1,26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled Index: test/MC/Mips/mips32r2/invalid.s =================================================================== --- test/MC/Mips/mips32r2/invalid.s +++ test/MC/Mips/mips32r2/invalid.s @@ -6,6 +6,8 @@ .text .set noreorder + andi $2, $3, -1 # CHECK: :[[@LINE]]:22: error: expected 16-bit unsigned immediate + andi $2, $3, 65536 # CHECK: :[[@LINE]]:22: error: expected 16-bit unsigned immediate cache -1, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate cache 32, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate # FIXME: Check '0 < pos + size <= 32' constraint on ext @@ -18,6 +20,8 @@ ins $2, $3, 32, 1 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate jalr.hb $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different + ori $2, $3, -1 # CHECK: :[[@LINE]]:21: error: expected 16-bit unsigned immediate + ori $2, $3, 65536 # CHECK: :[[@LINE]]:21: error: expected 16-bit unsigned immediate pref -1, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate pref 32, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate sll $2, $3, -1 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate @@ -28,3 +32,5 @@ sra $2, $3, 32 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate rotr $2, $3, -1 # CHECK: :[[@LINE]]:22: error: expected 5-bit unsigned immediate rotr $2, $3, 32 # CHECK: :[[@LINE]]:22: error: expected 5-bit unsigned immediate + xori $2, $3, -1 # CHECK: :[[@LINE]]:22: error: expected 16-bit unsigned immediate + xori $2, $3, 65536 # CHECK: :[[@LINE]]:22: error: expected 16-bit unsigned immediate